[clang] [CIR] Upstream shift operators for VectorType (PR #139465)

[Amr Hesham via cfe-commits]

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@@ -1399,8 +1400,10 @@ mlir::LogicalResult CIRToLLVMShiftOpLowering::matchAndRewrite(
   if (op.getIsShiftleft()) {
     rewriter.replaceOpWithNewOp<mlir::LLVM::ShlOp>(op, llvmTy, val, amt);
   } else {
-    assert(!cir::MissingFeatures::vectorType());
-    bool isUnsigned = !cirValTy.isSigned();
+    const bool isUnsigned =
+        cirValTy
+            ? !cirValTy.isSigned()
+            : !mlir::cast<cir::IntType>(cirValVTy.getElementType()).isSigned();
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AmrDeveloper wrote:

I used your suggestion and assigned isUnsigned and getLLVMIntCast in the same branch

https://github.com/llvm/llvm-project/pull/139465