[clang] [CIR] Upstream shift operators for VectorType (PR #139465)

[Andy Kaylor via cfe-commits]

================
@@ -1399,8 +1400,10 @@ mlir::LogicalResult CIRToLLVMShiftOpLowering::matchAndRewrite(
   if (op.getIsShiftleft()) {
     rewriter.replaceOpWithNewOp<mlir::LLVM::ShlOp>(op, llvmTy, val, amt);
   } else {
-    assert(!cir::MissingFeatures::vectorType());
-    bool isUnsigned = !cirValTy.isSigned();
+    const bool isUnsigned =
+        cirValTy
+            ? !cirValTy.isSigned()
+            : !mlir::cast<cir::IntType>(cirValVTy.getElementType()).isSigned();
----------------
andykaylor wrote:

Would it make sense for the vector type to support `isSigned()`? The instead of having separate cirValTy and cirValVTy (one of which would always be null), we could do something like this above:

```
if (!cirValTy) {
  cirValTy = mlir::cast<cir::VectorType>(op.getValue().getType());
  assert(mlir::isa<cir::VectorType>(op.getAmount().getType());
}
```



https://github.com/llvm/llvm-project/pull/139465