[clang] [RISCV] Improve casting between i1 scalable vectors and i8 fixed vectors for -mrvv-vector-bits (PR #139190)
Paul Walker via cfe-commits
cfe-commits at lists.llvm.org
Mon May 12 06:25:49 PDT 2025
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@@ -2517,8 +2527,17 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) {
// If we are casting a scalable i1 predicate vector to a fixed i8
// vector, bitcast the source and use a vector extract.
if (ScalableSrcTy->getElementType()->isIntegerTy(1) &&
- ScalableSrcTy->getElementCount().isKnownMultipleOf(8) &&
FixedDstTy->getElementType()->isIntegerTy(8)) {
+ if (!ScalableSrcTy->getElementCount().isKnownMultipleOf(8)) {
+ ScalableSrcTy = llvm::ScalableVectorType::get(
+ ScalableSrcTy->getElementType(),
+ llvm::alignTo<8>(
+ ScalableSrcTy->getElementCount().getKnownMinValue()));
+ llvm::Value *ZeroVec = llvm::Constant::getNullValue(ScalableSrcTy);
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paulwalker-arm wrote:
Should this be poison instead of zero?
https://github.com/llvm/llvm-project/pull/139190
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