[clang] [llvm] [RISCV] Add processor definition for SiFive P870 (PR #137725)

[Min-Yih Hsu via cfe-commits]

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@@ -365,6 +365,32 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
                                        TuneVXRMPipelineFlush,
                                        TunePostRAScheduler]>;
 
+def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", NoSchedModel,
+                                      !listconcat(RVA23U64Features,
+                                      [FeatureStdExtZama16b,
+                                       FeatureStdExtZfh,
+                                       FeatureStdExtZifencei,
+                                       FeatureStdExtZihintntl,
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mshockwave wrote:

Zihintntl and Zvbb have been removed.

https://github.com/llvm/llvm-project/pull/137725