[clang] 9c2190e - [RISCV] Add support for Ziccamoc (#136694)
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Thu Apr 24 22:49:52 PDT 2025
Author: T-Tie
Date: 2025-04-25T13:49:48+08:00
New Revision: 9c2190eb5dacfb7991f616c83a9e87740c1c6d49
URL: https://github.com/llvm/llvm-project/commit/9c2190eb5dacfb7991f616c83a9e87740c1c6d49
DIFF: https://github.com/llvm/llvm-project/commit/9c2190eb5dacfb7991f616c83a9e87740c1c6d49.diff
LOG: [RISCV] Add support for Ziccamoc (#136694)
Support for Ziccamoc is added in this pr.
Specification link:
https://drive.google.com/file/d/12QKRm92cLcEk8-5J9NI91m0fAQOxqNAq/view
---------
Co-authored-by: Tie <Tie at llvm.com>
Added:
Modified:
clang/test/Driver/print-supported-extensions-riscv.c
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/docs/ReleaseNotes.md
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/CodeGen/RISCV/features-info.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Removed:
################################################################################
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 1f83910969221..6fb5825f83e1f 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -19,6 +19,7 @@
// CHECK-NEXT: zicbop 1.0 'Zicbop' (Cache-Block Prefetch Instructions)
// CHECK-NEXT: zicboz 1.0 'Zicboz' (Cache-Block Zero Instructions)
// CHECK-NEXT: ziccamoa 1.0 'Ziccamoa' (Main Memory Supports All Atomics in A)
+// CHECK-NEXT: ziccamoc 1.0 'Ziccamoc' (Main Memory Supports Atomics in Zacas)
// CHECK-NEXT: ziccif 1.0 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)
// CHECK-NEXT: zicclsm 1.0 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)
// CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 03c291afe19bd..25f15cc5283f9 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -125,6 +125,7 @@
// CHECK-NOT: __riscv_zicbop {{.*$}}
// CHECK-NOT: __riscv_zicboz {{.*$}}
// CHECK-NOT: __riscv_ziccamoa {{.*$}}
+// CHECK-NOT: __riscv_ziccamoc {{.*$}}
// CHECK-NOT: __riscv_ziccif {{.*$}}
// CHECK-NOT: __riscv_zicclsm {{.*$}}
// CHECK-NOT: __riscv_ziccrse {{.*$}}
@@ -1047,6 +1048,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCAMOA-EXT %s
// CHECK-ZICCAMOA-EXT: __riscv_ziccamoa 1000000{{$}}
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32iziccamoc -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCAMOC-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64iziccamoc -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCAMOC-EXT %s
+// CHECK-ZICCAMOC-EXT: __riscv_ziccamoc 1000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32iziccif -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICCIF-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 1ebe7b57abd7d..1aceb305d98af 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -197,6 +197,7 @@ on support follow.
``Zicbop`` Supported
``Zicboz`` Assembly Support
``Ziccamoa`` Supported (`See note <#riscv-profiles-extensions-note>`__)
+ ``Ziccamoc`` Supported (`See note <#riscv-profiles-extensions-note>`__)
``Ziccif`` Supported (`See note <#riscv-profiles-extensions-note>`__)
``Zicclsm`` Supported (`See note <#riscv-profiles-extensions-note>`__)
``Ziccrse`` Supported (`See note <#riscv-profiles-extensions-note>`__)
@@ -298,7 +299,7 @@ Supported
.. _riscv-profiles-extensions-note:
-``Za128rs``, ``Za64rs``, ``Zama16b``, ``Zic64b``, ``Ziccamoa``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``, ``Shcounterenvw``, ``Shgatpa``, ``Shtvala``, ``Shvsatpa``, ``Shvstvala``, ``Shvstvecd``, ``Ssccptr``, ``Sscounterenw``, ``Ssstateen``, ``Ssstrict``, ``Sstvala``, ``Sstvecd``, ``Ssu64xl``, ``Svade``, ``Svbare``
+``Za128rs``, ``Za64rs``, ``Zama16b``, ``Zic64b``, ``Ziccamoa``, ``Ziccamoc``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``, ``Shcounterenvw``, ``Shgatpa``, ``Shtvala``, ``Shvsatpa``, ``Shvstvala``, ``Shvstvecd``, ``Ssccptr``, ``Sscounterenw``, ``Ssstateen``, ``Ssstrict``, ``Sstvala``, ``Sstvecd``, ``Ssu64xl``, ``Svade``, ``Svbare``
These extensions are defined as part of the `RISC-V Profiles specification <https://github.com/riscv/riscv-profiles/releases/tag/v1.0>`__. They do not introduce any new features themselves, but instead describe existing hardware features.
.. _riscv-zacas-note:
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 298b716801da7..a3e65fb2091bc 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -167,9 +167,11 @@ Changes to the RISC-V Backend
* Adds assembler support for ``.option exact``, which disables automatic compression,
and branch and linker relaxation. This can be disabled with ``.option noexact``,
which is also the default.
+<<<<<<< HEAD
* `-mcpu=xiangshan-kunminghu` was added.
* `-mcpu=andes-n45` and `-mcpu=andes-nx45` were added.
* `-mcpu=andes-a45` and `-mcpu=andes-ax45` were added.
+* Adds support for the 'Ziccamoc` (Main Memory Supports Atomics in Zacas) extension, which was introduced as an optional extension of the RISC-V Profiles specification.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 87cab1dafc75b..188043b0c143c 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -102,6 +102,9 @@ def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
def FeatureStdExtZiccamoa
: RISCVExtension<1, 0, "Main Memory Supports All Atomics in A">;
+def FeatureStdExtZiccamoc
+ : RISCVExtension<1, 0, "Main Memory Supports Atomics in Zacas">;
+
def FeatureStdExtZiccif
: RISCVExtension<1, 0,
"Main Memory Supports Instruction Fetch with Atomicity Requirement">;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index b0dc65839559a..81bb1763966c1 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -265,6 +265,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zcmp %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCMP %s
; RUN: llc -mtriple=riscv64 -mattr=+zcmt %s -o - | FileCheck --check-prefixes=CHECK,RV64ZCMT %s
; RUN: llc -mtriple=riscv64 -mattr=+ziccamoa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCAMOA %s
+; RUN: llc -mtriple=riscv64 -mattr=+ziccamoc %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCAMOC %s
; RUN: llc -mtriple=riscv64 -mattr=+ziccif %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCIF %s
; RUN: llc -mtriple=riscv64 -mattr=+zicclsm %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCLSM %s
; RUN: llc -mtriple=riscv64 -mattr=+ziccrse %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICCRSE %s
@@ -602,6 +603,7 @@
; RV64ZCMP: .attribute 5, "rv64i2p1_zca1p0_zcmp1p0"
; RV64ZCMT: .attribute 5, "rv64i2p1_zicsr2p0_zca1p0_zcmt1p0"
; RV64ZICCAMOA: .attribute 5, "rv64i2p1_ziccamoa1p0"
+; RV64ZICCAMOC: .attribute 5, "rv64i2p1_ziccamoc1p0"
; RV64ZICCIF: .attribute 5, "rv64i2p1_ziccif1p0"
; RV64ZICCLSM: .attribute 5, "rv64i2p1_zicclsm1p0"
; RV64ZICCRSE: .attribute 5, "rv64i2p1_ziccrse1p0"
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index f7824ec10834c..75ee7d1f324c4 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -237,6 +237,7 @@
; CHECK-NEXT: zicbop - 'Zicbop' (Cache-Block Prefetch Instructions).
; CHECK-NEXT: zicboz - 'Zicboz' (Cache-Block Zero Instructions).
; CHECK-NEXT: ziccamoa - 'Ziccamoa' (Main Memory Supports All Atomics in A).
+; CHECK-NEXT: ziccamoc - 'Ziccamoc' (Main Memory Supports Atomics in Zacas).
; CHECK-NEXT: ziccif - 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement).
; CHECK-NEXT: zicclsm - 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores).
; CHECK-NEXT: ziccrse - 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences).
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 16acd403eb9af..d3b49d03279a2 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -106,6 +106,9 @@
.attribute arch, "rv32iziccamoa"
# CHECK: attribute 5, "rv32i2p1_ziccamoa1p0"
+.attribute arch, "rv32iziccamoc"
+# CHECK: attribute 5, "rv32i2p1_ziccamoc1p0"
+
.attribute arch, "rv32iziccif"
# CHECK: attribute 5, "rv32i2p1_ziccif1p0"
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 43896fede57d8..71c3b9635a8be 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -982,6 +982,7 @@ R"(All available -march extensions for RISC-V
zicbop 1.0
zicboz 1.0
ziccamoa 1.0
+ ziccamoc 1.0
ziccif 1.0
zicclsm 1.0
ziccrse 1.0
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