[clang] [NFC][Driver][HIP] Fix mixing `amdgcnspirv` and `gfxXXX` via `--offload-arch` (PR #133024)

[Alex Voicu via cfe-commits]

https://github.com/AlexVlx created https://github.com/llvm/llvm-project/pull/133024

Due to `amdgcnspirv` piggybacking on the HIPAMDToolchain, it loses its immediately apparent SPIR-Vness, which makes the Driver want to go all the way to Assembly emmission. This was problematic as we were trying to `llvm-link` SPIR-V, before trying to translate it. This patch ensures that we do the right thing and stop at bitcode emission if we are mixing `amdgcnspirv` and concrete targets.

>From 500f68f29c2f8d355955267cff5907b80ebc67e7 Mon Sep 17 00:00:00 2001
From: Alex Voicu <alexandru.voicu at amd.com>
Date: Wed, 26 Mar 2025 00:57:20 +0000
Subject: [PATCH] Ensure we stop at BC emission  when mixing `amdgcnspirv` and
 concrete, otherwise the toolchain gets confused.

---
 clang/lib/Driver/Driver.cpp | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 056bfcf1b739a..07e36ea2efba4 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -3750,9 +3750,12 @@ class OffloadingActionBuilder final {
             // compiler phases, including backend and assemble phases.
             ActionList AL;
             Action *BackendAction = nullptr;
-            if (ToolChains.front()->getTriple().isSPIRV()) {
+            if (ToolChains.front()->getTriple().isSPIRV() ||
+                (ToolChains.front()->getTriple().isAMDGCN() &&
+                 GpuArchList[I] == StringRef("amdgcnspirv"))) {
               // Emit LLVM bitcode for SPIR-V targets. SPIR-V device tool chain
-              // (HIPSPVToolChain) runs post-link LLVM IR passes.
+              // (HIPSPVToolChain or HIPAMDToolChain) runs post-link LLVM IR
+              // passes.
               types::ID Output = Args.hasArg(options::OPT_S)
                                      ? types::TY_LLVM_IR
                                      : types::TY_LLVM_BC;