[clang] [flang] [llvm] [mlir] [Transforms] Introduce BuildBuiltins.h atomic helpers (PR #101966)
Michael Kruse via cfe-commits
cfe-commits at lists.llvm.org
Tue Mar 11 10:50:03 PDT 2025
https://github.com/Meinersbur updated https://github.com/llvm/llvm-project/pull/101966
>From 945b7c8c592498c4a5fcb4fc2eeacd26a868c3ff Mon Sep 17 00:00:00 2001
From: Michael Kruse <llvm-project at meinersbur.de>
Date: Mon, 3 Mar 2025 16:03:44 +0100
Subject: [PATCH 1/4] Introduce BuildBuiltins.h
---
clang/lib/CodeGen/CGStmtOpenMP.cpp | 14 +-
clang/test/OpenMP/atomic_compare_codegen.cpp | 36250 ++++++++++------
flang/lib/Semantics/CMakeLists.txt | 65 +-
.../OpenMP/atomic-capture-complex.f90 | 68 +-
.../llvm/Analysis/TargetLibraryInfo.def | 80 +
.../llvm/Frontend/OpenMP/OMPIRBuilder.h | 41 +-
llvm/include/llvm/Support/AtomicOrdering.h | 22 +
.../llvm/Transforms/Utils/BuildBuiltins.h | 283 +
.../llvm/Transforms/Utils/BuildLibCalls.h | 47 +
llvm/lib/Analysis/TargetLibraryInfo.cpp | 21 +
llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 432 +-
llvm/lib/Transforms/Utils/BuildBuiltins.cpp | 826 +
llvm/lib/Transforms/Utils/BuildLibCalls.cpp | 212 +
llvm/lib/Transforms/Utils/CMakeLists.txt | 1 +
.../tools/llvm-tli-checker/ps4-tli-check.yaml | 4 +-
.../Analysis/TargetLibraryInfoTest.cpp | 18 +
.../Frontend/OpenMPIRBuilderTest.cpp | 1529 +-
.../OpenMP/OpenMPToLLVMIRTranslation.cpp | 14 +-
mlir/test/Target/LLVMIR/openmp-llvm.mlir | 473 +-
19 files changed, 26565 insertions(+), 13835 deletions(-)
create mode 100644 llvm/include/llvm/Transforms/Utils/BuildBuiltins.h
create mode 100644 llvm/lib/Transforms/Utils/BuildBuiltins.cpp
diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp
index e4d1db264aac9..a8ffe1edd1202 100644
--- a/clang/lib/CodeGen/CGStmtOpenMP.cpp
+++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp
@@ -6740,16 +6740,18 @@ static void emitOMPAtomicCompareExpr(
R->getType().isVolatileQualified()};
}
+ llvm::OpenMPIRBuilder::InsertPointTy AllocaIP(
+ CGF.AllocaInsertPt->getParent(), CGF.AllocaInsertPt->getIterator());
if (FailAO == llvm::AtomicOrdering::NotAtomic) {
// fail clause was not mentioned on the
// "#pragma omp atomic compare" construct.
- CGF.Builder.restoreIP(OMPBuilder.createAtomicCompare(
- CGF.Builder, XOpVal, VOpVal, ROpVal, EVal, DVal, AO, Op, IsXBinopExpr,
- IsPostfixUpdate, IsFailOnly));
+ CGF.Builder.restoreIP(cantFail(OMPBuilder.createAtomicCompare(
+ CGF.Builder, AllocaIP, XOpVal, VOpVal, ROpVal, EVal, DVal, AO, Op,
+ IsXBinopExpr, IsPostfixUpdate, IsFailOnly)));
} else
- CGF.Builder.restoreIP(OMPBuilder.createAtomicCompare(
- CGF.Builder, XOpVal, VOpVal, ROpVal, EVal, DVal, AO, Op, IsXBinopExpr,
- IsPostfixUpdate, IsFailOnly, FailAO));
+ CGF.Builder.restoreIP(cantFail(OMPBuilder.createAtomicCompare(
+ CGF.Builder, AllocaIP, XOpVal, VOpVal, ROpVal, EVal, DVal, AO, Op,
+ IsXBinopExpr, IsPostfixUpdate, IsFailOnly, FailAO)));
}
static void emitOMPAtomicExpr(CodeGenFunction &CGF, OpenMPClauseKind Kind,
diff --git a/clang/test/OpenMP/atomic_compare_codegen.cpp b/clang/test/OpenMP/atomic_compare_codegen.cpp
index 03e5081a5c1d8..ff6e8fe3afea8 100644
--- a/clang/test/OpenMP/atomic_compare_codegen.cpp
+++ b/clang/test/OpenMP/atomic_compare_codegen.cpp
@@ -13903,6 +13903,726 @@ double fail_dxevd() {
// CHECK-NEXT: [[DX:%.*]] = alloca double, align 8
// CHECK-NEXT: [[DE:%.*]] = alloca double, align 8
// CHECK-NEXT: [[DD:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR1:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR2:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR3:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR4:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR10:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR11:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR12:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR18:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR19:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR20:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR26:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR27:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR28:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR29:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR35:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR36:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR37:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR43:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR44:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR45:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR51:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR52:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR53:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR59:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR60:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR61:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR67:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR68:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR69:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR75:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR76:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR77:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR83:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR84:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR85:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR91:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR92:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR93:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR99:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR100:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR101:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR107:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR108:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR109:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR115:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR116:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR117:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR123:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR124:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR125:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR131:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR132:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR133:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR139:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR140:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR141:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR147:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR148:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR149:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR155:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR156:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR157:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR163:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR164:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR165:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR171:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR172:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR173:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR179:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR180:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR181:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR187:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR188:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR189:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR195:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR196:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR197:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR203:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR204:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR205:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR211:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR212:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR213:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR219:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR220:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR221:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR227:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR228:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR229:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR235:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR236:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR237:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR243:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR244:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR245:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR251:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR252:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR253:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR259:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR260:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR261:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR267:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR268:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR269:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR275:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR276:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR277:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR283:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR284:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR285:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR291:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR292:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR293:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR299:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR300:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR301:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR307:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR308:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR309:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR315:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR316:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR317:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR323:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR324:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR325:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR331:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR332:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR333:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR339:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR340:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR341:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR347:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR348:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR349:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR355:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR356:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR357:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR363:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR364:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR365:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR371:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR372:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR373:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR374:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR380:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR381:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR382:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR388:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR389:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR390:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR396:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR397:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR398:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR399:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR405:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR406:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR407:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR413:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR414:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR415:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR421:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR422:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR423:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR429:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR430:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR431:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR437:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR438:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR439:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR445:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR446:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR447:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR453:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR454:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR455:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR461:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR462:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR463:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR469:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR470:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR471:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR477:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR478:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR479:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR485:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR486:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR487:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR493:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR494:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR495:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR501:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR502:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR503:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR509:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR510:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR511:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR517:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR518:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR519:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR525:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR526:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR527:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR533:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR534:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR535:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR541:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR542:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR543:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR549:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR550:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR551:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR557:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR558:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR559:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR565:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR566:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR567:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR573:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR574:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR575:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR581:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR582:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR583:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR589:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR590:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR591:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR597:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR598:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR599:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR605:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR606:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR607:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR613:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR614:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR615:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR621:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR622:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR623:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR629:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR630:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR631:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR637:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR638:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR639:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR645:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR646:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR647:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR653:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR654:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR655:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR661:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR662:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR663:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR669:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR670:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR671:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR677:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR678:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR679:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR685:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR686:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR687:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR693:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR694:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR695:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR701:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR702:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR703:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR709:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR710:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR711:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR717:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR718:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR719:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR725:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR726:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR727:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR733:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR734:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR735:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR741:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR742:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR743:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR744:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR750:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR751:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR752:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR758:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR759:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR760:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR766:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR767:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR768:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR769:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR775:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR776:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR777:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR783:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR784:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR785:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR791:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR792:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR793:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR799:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR800:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR801:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR807:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR808:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR809:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR815:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR816:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR817:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR823:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR824:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR825:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR831:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR832:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR833:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR839:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR840:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR841:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR847:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR848:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR849:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR855:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR856:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR857:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR863:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR864:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR865:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR871:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR872:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR873:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR879:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR880:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR881:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR887:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR888:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR889:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR895:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR896:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR897:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR903:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR904:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR905:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR911:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR912:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR913:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR919:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR920:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR921:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR927:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR928:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR929:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR935:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR936:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR937:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR943:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR944:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR945:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR951:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR952:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR953:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR959:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR960:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR961:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR967:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR968:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR969:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR975:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR976:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR977:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR983:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR984:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR985:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR991:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR992:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR993:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR999:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR1000:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR1001:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR1007:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR1008:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR1009:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR1015:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR1016:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR1017:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR1023:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR1024:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR1025:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR1031:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR1032:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR1033:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR1039:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR1040:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR1041:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR1047:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR1048:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR1049:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR1055:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR1056:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR1057:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR1063:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR1064:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR1065:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR1071:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR1072:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR1073:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR1079:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR1080:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR1081:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR1087:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR1088:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR1089:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR1095:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR1096:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR1097:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR1103:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR1104:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR1105:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1111:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1112:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1113:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1114:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1120:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1121:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1122:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1128:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1129:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1130:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1136:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1137:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1138:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1139:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1145:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1146:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1147:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1153:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1154:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1155:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1161:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1162:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1163:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1169:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1170:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1171:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1177:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1178:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1179:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1185:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1186:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1187:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1193:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1194:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1195:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1201:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1202:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1203:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1209:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1210:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1211:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1217:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1218:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1219:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1225:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1226:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1227:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1233:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1234:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1235:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1241:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1242:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1243:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1249:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1250:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1251:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1257:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1258:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1259:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1265:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1266:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1267:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1273:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1274:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1275:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1281:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1282:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1283:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1289:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1290:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1291:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1297:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1298:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1299:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1305:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1306:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1307:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1313:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1314:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1315:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1321:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1322:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1323:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1329:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1330:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1331:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1337:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1338:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1339:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1345:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1346:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1347:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1353:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1354:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1355:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1361:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1362:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1363:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1369:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1370:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1371:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1377:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1378:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1379:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1385:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1386:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1387:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1393:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1394:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1395:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1401:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1402:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1403:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1409:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1410:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1411:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1417:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1418:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1419:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1425:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1426:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1427:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1433:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1434:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1435:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1441:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR1442:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1443:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1449:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1450:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1451:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1457:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1458:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1459:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1465:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1466:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1467:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1473:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR1474:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1475:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1481:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1482:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1483:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1484:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1490:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1491:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1492:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1498:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1499:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1500:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1506:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1507:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1508:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1509:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1515:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1516:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1517:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1523:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1524:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1525:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1531:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1532:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1533:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1539:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1540:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1541:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1547:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1548:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1549:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1555:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1556:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1557:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1563:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1564:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1565:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1571:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1572:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1573:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1579:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1580:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1581:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1587:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1588:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1589:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1595:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1596:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1597:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1603:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1604:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1605:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1611:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1612:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1613:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1619:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1620:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1621:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1627:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1628:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1629:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1635:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1636:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1637:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1643:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1644:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1645:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1651:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1652:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1653:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1659:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1660:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1661:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1667:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1668:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1669:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1675:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1676:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1677:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1683:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1684:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1685:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1691:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1692:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1693:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1699:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1700:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1701:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1707:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1708:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1709:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1715:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1716:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1717:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1723:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1724:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1725:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1731:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1732:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1733:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1739:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1740:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1741:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1747:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1748:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1749:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1755:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1756:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1757:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1763:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1764:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1765:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1771:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1772:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1773:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1779:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1780:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1781:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1787:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1788:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1789:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1795:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1796:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1797:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1803:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1804:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1805:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1811:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR1812:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1813:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1819:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1820:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1821:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1827:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1828:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1829:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1835:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1836:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1837:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1843:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR1844:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1845:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[CE]], align 1
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP0]] monotonic, align 1
// CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[CE]], align 1
@@ -13921,47 +14641,115 @@ double fail_dxevd() {
// CHECK-NEXT: [[TMP15:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP14]] monotonic, align 1
// CHECK-NEXT: [[TMP16:%.*]] = load i8, ptr [[CE]], align 1
// CHECK-NEXT: [[TMP17:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP16]], i8 [[TMP17]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP19:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP21:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP19]], i8 [[TMP20]] monotonic monotonic, align 1
+// CHECK-NEXT: store i8 [[TMP16]], ptr [[CX_ATOMIC_EXPECTED_PTR]], align 1
+// CHECK-NEXT: store i8 [[TMP17]], ptr [[CX_ATOMIC_DESIRED_PTR]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED]], i8 [[CX_CMPXCHG_DESIRED]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV]], ptr [[CX_ATOMIC_EXPECTED_PTR1]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[TMP18:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP19:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP18]], ptr [[CX_ATOMIC_EXPECTED_PTR2]], align 1
+// CHECK-NEXT: store i8 [[TMP19]], ptr [[CX_ATOMIC_DESIRED_PTR3]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED5:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR2]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED6:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR3]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR7:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED5]], i8 [[CX_CMPXCHG_DESIRED6]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV8:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR7]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV8]], ptr [[CX_ATOMIC_EXPECTED_PTR4]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS9:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR7]], 1
+// CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP21:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP20]], ptr [[CX_ATOMIC_EXPECTED_PTR10]], align 1
+// CHECK-NEXT: store i8 [[TMP21]], ptr [[CX_ATOMIC_DESIRED_PTR11]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED13:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR10]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED14:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR11]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR15:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED13]], i8 [[CX_CMPXCHG_DESIRED14]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV16:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR15]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV16]], ptr [[CX_ATOMIC_EXPECTED_PTR12]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS17:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR15]], 1
// CHECK-NEXT: [[TMP22:%.*]] = load i8, ptr [[CE]], align 1
// CHECK-NEXT: [[TMP23:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP24:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP22]], i8 [[TMP23]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP25:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP26:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP27:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP25]], i8 [[TMP26]] monotonic monotonic, align 1
+// CHECK-NEXT: store i8 [[TMP22]], ptr [[CX_ATOMIC_EXPECTED_PTR18]], align 1
+// CHECK-NEXT: store i8 [[TMP23]], ptr [[CX_ATOMIC_DESIRED_PTR19]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED21:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR18]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED22:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR19]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR23:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED21]], i8 [[CX_CMPXCHG_DESIRED22]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV24:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR23]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV24]], ptr [[CX_ATOMIC_EXPECTED_PTR20]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS25:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR23]], 1
+// CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP24]] monotonic, align 1
+// CHECK-NEXT: [[TMP26:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP27:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP26]] monotonic, align 1
// CHECK-NEXT: [[TMP28:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP29:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP28]] monotonic, align 1
+// CHECK-NEXT: [[TMP29:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP28]] monotonic, align 1
// CHECK-NEXT: [[TMP30:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP30]] monotonic, align 1
+// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP30]] monotonic, align 1
// CHECK-NEXT: [[TMP32:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP33:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP32]] monotonic, align 1
+// CHECK-NEXT: [[TMP33:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP32]] monotonic, align 1
// CHECK-NEXT: [[TMP34:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP34]] monotonic, align 1
+// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP34]] monotonic, align 1
// CHECK-NEXT: [[TMP36:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP37:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP36]] monotonic, align 1
+// CHECK-NEXT: [[TMP37:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP36]] monotonic, align 1
// CHECK-NEXT: [[TMP38:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP39:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP38]] monotonic, align 1
+// CHECK-NEXT: [[TMP39:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP38]] monotonic, align 1
// CHECK-NEXT: [[TMP40:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP41:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP40]] monotonic, align 1
+// CHECK-NEXT: [[TMP41:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP40]], ptr [[UCX_ATOMIC_EXPECTED_PTR]], align 1
+// CHECK-NEXT: store i8 [[TMP41]], ptr [[UCX_ATOMIC_DESIRED_PTR]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED]], i8 [[UCX_CMPXCHG_DESIRED]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV]], ptr [[UCX_ATOMIC_EXPECTED_PTR26]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR]], 1
// CHECK-NEXT: [[TMP42:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP43:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP42]] monotonic, align 1
+// CHECK-NEXT: [[TMP43:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP42]], ptr [[UCX_ATOMIC_EXPECTED_PTR27]], align 1
+// CHECK-NEXT: store i8 [[TMP43]], ptr [[UCX_ATOMIC_DESIRED_PTR28]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED30:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR27]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED31:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR28]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR32:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED30]], i8 [[UCX_CMPXCHG_DESIRED31]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV33:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR32]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV33]], ptr [[UCX_ATOMIC_EXPECTED_PTR29]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS34:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR32]], 1
// CHECK-NEXT: [[TMP44:%.*]] = load i8, ptr [[UCE]], align 1
// CHECK-NEXT: [[TMP45:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP46:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP44]], i8 [[TMP45]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP47:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP48:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP49:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP47]], i8 [[TMP48]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP50:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP51:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP52:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP50]], i8 [[TMP51]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP53:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP54:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP55:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP53]], i8 [[TMP54]] monotonic monotonic, align 1
+// CHECK-NEXT: store i8 [[TMP44]], ptr [[UCX_ATOMIC_EXPECTED_PTR35]], align 1
+// CHECK-NEXT: store i8 [[TMP45]], ptr [[UCX_ATOMIC_DESIRED_PTR36]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED38:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR35]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED39:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR36]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR40:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED38]], i8 [[UCX_CMPXCHG_DESIRED39]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV41:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR40]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV41]], ptr [[UCX_ATOMIC_EXPECTED_PTR37]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS42:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR40]], 1
+// CHECK-NEXT: [[TMP46:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP47:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP46]], ptr [[UCX_ATOMIC_EXPECTED_PTR43]], align 1
+// CHECK-NEXT: store i8 [[TMP47]], ptr [[UCX_ATOMIC_DESIRED_PTR44]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED46:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR43]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED47:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR44]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR48:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED46]], i8 [[UCX_CMPXCHG_DESIRED47]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV49:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR48]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV49]], ptr [[UCX_ATOMIC_EXPECTED_PTR45]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS50:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR48]], 1
+// CHECK-NEXT: [[TMP48:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP49:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP48]] acq_rel, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1:[0-9]+]])
+// CHECK-NEXT: [[TMP50:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP51:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP50]] acq_rel, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP52:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP52]] acq_rel, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP54:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP55:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP54]] acq_rel, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP56:%.*]] = load i8, ptr [[CE]], align 1
// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP56]] acq_rel, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1:[0-9]+]])
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP58:%.*]] = load i8, ptr [[CE]], align 1
// CHECK-NEXT: [[TMP59:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP58]] acq_rel, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
@@ -13972,1161 +14760,2461 @@ double fail_dxevd() {
// CHECK-NEXT: [[TMP63:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP62]] acq_rel, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP64:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP65:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP64]] acq_rel, align 1
+// CHECK-NEXT: [[TMP65:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP64]], ptr [[CX_ATOMIC_EXPECTED_PTR51]], align 1
+// CHECK-NEXT: store i8 [[TMP65]], ptr [[CX_ATOMIC_DESIRED_PTR52]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED54:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR51]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED55:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR52]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR56:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED54]], i8 [[CX_CMPXCHG_DESIRED55]] acq_rel acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV57:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR56]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV57]], ptr [[CX_ATOMIC_EXPECTED_PTR53]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS58:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR56]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP66:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP66]] acq_rel, align 1
+// CHECK-NEXT: [[TMP67:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP66]], ptr [[CX_ATOMIC_EXPECTED_PTR59]], align 1
+// CHECK-NEXT: store i8 [[TMP67]], ptr [[CX_ATOMIC_DESIRED_PTR60]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED62:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR59]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED63:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR60]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR64:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED62]], i8 [[CX_CMPXCHG_DESIRED63]] acq_rel acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV65:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR64]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV65]], ptr [[CX_ATOMIC_EXPECTED_PTR61]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS66:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR64]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP68:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP68]] acq_rel, align 1
+// CHECK-NEXT: [[TMP69:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP68]], ptr [[CX_ATOMIC_EXPECTED_PTR67]], align 1
+// CHECK-NEXT: store i8 [[TMP69]], ptr [[CX_ATOMIC_DESIRED_PTR68]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED70:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR67]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED71:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR68]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR72:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED70]], i8 [[CX_CMPXCHG_DESIRED71]] acq_rel acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV73:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR72]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV73]], ptr [[CX_ATOMIC_EXPECTED_PTR69]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS74:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR72]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP70:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP71:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP70]] acq_rel, align 1
+// CHECK-NEXT: [[TMP71:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP70]], ptr [[CX_ATOMIC_EXPECTED_PTR75]], align 1
+// CHECK-NEXT: store i8 [[TMP71]], ptr [[CX_ATOMIC_DESIRED_PTR76]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED78:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR75]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED79:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR76]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR80:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED78]], i8 [[CX_CMPXCHG_DESIRED79]] acq_rel acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV81:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR80]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV81]], ptr [[CX_ATOMIC_EXPECTED_PTR77]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS82:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR80]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP72:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP73:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP72]] acq_rel, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP72:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP73:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP74:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP72]], i8 [[TMP73]] acq_rel acquire, align 1
+// CHECK-NEXT: [[TMP74:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP74]] acq_rel, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP75:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP76:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP77:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP75]], i8 [[TMP76]] acq_rel acquire, align 1
+// CHECK-NEXT: [[TMP76:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP77:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP76]] acq_rel, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP78:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP79:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP80:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP78]], i8 [[TMP79]] acq_rel acquire, align 1
+// CHECK-NEXT: [[TMP78:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP78]] acq_rel, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP81:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP82:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP83:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP81]], i8 [[TMP82]] acq_rel acquire, align 1
+// CHECK-NEXT: [[TMP80:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP81:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP80]] acq_rel, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP82:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP83:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP82]] acq_rel, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP84:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP85:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP84]] acq_rel, align 1
+// CHECK-NEXT: [[TMP85:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP84]] acq_rel, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP86:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP86]] acq_rel, align 1
+// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP86]] acq_rel, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP88:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP88]] acq_rel, align 1
+// CHECK-NEXT: [[TMP89:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP88]], ptr [[UCX_ATOMIC_EXPECTED_PTR83]], align 1
+// CHECK-NEXT: store i8 [[TMP89]], ptr [[UCX_ATOMIC_DESIRED_PTR84]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED86:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR83]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED87:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR84]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR88:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED86]], i8 [[UCX_CMPXCHG_DESIRED87]] acq_rel acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV89:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR88]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV89]], ptr [[UCX_ATOMIC_EXPECTED_PTR85]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS90:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR88]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP90:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP90]] acq_rel, align 1
+// CHECK-NEXT: [[TMP91:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP90]], ptr [[UCX_ATOMIC_EXPECTED_PTR91]], align 1
+// CHECK-NEXT: store i8 [[TMP91]], ptr [[UCX_ATOMIC_DESIRED_PTR92]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED94:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR91]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED95:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR92]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR96:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED94]], i8 [[UCX_CMPXCHG_DESIRED95]] acq_rel acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV97:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR96]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV97]], ptr [[UCX_ATOMIC_EXPECTED_PTR93]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS98:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR96]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP92:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP93:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP92]] acq_rel, align 1
+// CHECK-NEXT: [[TMP93:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP92]], ptr [[UCX_ATOMIC_EXPECTED_PTR99]], align 1
+// CHECK-NEXT: store i8 [[TMP93]], ptr [[UCX_ATOMIC_DESIRED_PTR100]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED102:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR99]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED103:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR100]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR104:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED102]], i8 [[UCX_CMPXCHG_DESIRED103]] acq_rel acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV105:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR104]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV105]], ptr [[UCX_ATOMIC_EXPECTED_PTR101]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS106:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR104]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP94:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP95:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP94]] acq_rel, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP96:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP96]] acq_rel, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP98:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP99:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP98]] acq_rel, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP100:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP101:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP102:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP100]], i8 [[TMP101]] acq_rel acquire, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP103:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP104:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP105:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP103]], i8 [[TMP104]] acq_rel acquire, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP106:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP107:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP108:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP106]], i8 [[TMP107]] acq_rel acquire, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP109:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP110:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP111:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP109]], i8 [[TMP110]] acq_rel acquire, align 1
+// CHECK-NEXT: [[TMP95:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP94]], ptr [[UCX_ATOMIC_EXPECTED_PTR107]], align 1
+// CHECK-NEXT: store i8 [[TMP95]], ptr [[UCX_ATOMIC_DESIRED_PTR108]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED110:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR107]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED111:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR108]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR112:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED110]], i8 [[UCX_CMPXCHG_DESIRED111]] acq_rel acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV113:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR112]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV113]], ptr [[UCX_ATOMIC_EXPECTED_PTR109]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS114:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR112]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP96:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP96]] acquire, align 1
+// CHECK-NEXT: [[TMP98:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP99:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP98]] acquire, align 1
+// CHECK-NEXT: [[TMP100:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP100]] acquire, align 1
+// CHECK-NEXT: [[TMP102:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP103:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP102]] acquire, align 1
+// CHECK-NEXT: [[TMP104:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP105:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP104]] acquire, align 1
+// CHECK-NEXT: [[TMP106:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP107:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP106]] acquire, align 1
+// CHECK-NEXT: [[TMP108:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP109:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP108]] acquire, align 1
+// CHECK-NEXT: [[TMP110:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP110]] acquire, align 1
// CHECK-NEXT: [[TMP112:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP112]] acquire, align 1
+// CHECK-NEXT: [[TMP113:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP112]], ptr [[CX_ATOMIC_EXPECTED_PTR115]], align 1
+// CHECK-NEXT: store i8 [[TMP113]], ptr [[CX_ATOMIC_DESIRED_PTR116]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED118:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR115]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED119:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR116]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR120:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED118]], i8 [[CX_CMPXCHG_DESIRED119]] acquire acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV121:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR120]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV121]], ptr [[CX_ATOMIC_EXPECTED_PTR117]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS122:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR120]], 1
// CHECK-NEXT: [[TMP114:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP115:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP114]] acquire, align 1
+// CHECK-NEXT: [[TMP115:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP114]], ptr [[CX_ATOMIC_EXPECTED_PTR123]], align 1
+// CHECK-NEXT: store i8 [[TMP115]], ptr [[CX_ATOMIC_DESIRED_PTR124]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED126:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR123]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED127:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR124]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR128:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED126]], i8 [[CX_CMPXCHG_DESIRED127]] acquire acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV129:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR128]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV129]], ptr [[CX_ATOMIC_EXPECTED_PTR125]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS130:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR128]], 1
// CHECK-NEXT: [[TMP116:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP117:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP116]] acquire, align 1
+// CHECK-NEXT: [[TMP117:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP116]], ptr [[CX_ATOMIC_EXPECTED_PTR131]], align 1
+// CHECK-NEXT: store i8 [[TMP117]], ptr [[CX_ATOMIC_DESIRED_PTR132]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED134:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR131]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED135:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR132]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR136:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED134]], i8 [[CX_CMPXCHG_DESIRED135]] acquire acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV137:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR136]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV137]], ptr [[CX_ATOMIC_EXPECTED_PTR133]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS138:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR136]], 1
// CHECK-NEXT: [[TMP118:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP118]] acquire, align 1
-// CHECK-NEXT: [[TMP120:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP121:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP120]] acquire, align 1
-// CHECK-NEXT: [[TMP122:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP122]] acquire, align 1
-// CHECK-NEXT: [[TMP124:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP125:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP124]] acquire, align 1
-// CHECK-NEXT: [[TMP126:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP127:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP126]] acquire, align 1
-// CHECK-NEXT: [[TMP128:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP129:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP130:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP128]], i8 [[TMP129]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP131:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP132:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP133:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP131]], i8 [[TMP132]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP134:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP135:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP136:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP134]], i8 [[TMP135]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP137:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP138:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP139:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP137]], i8 [[TMP138]] acquire acquire, align 1
+// CHECK-NEXT: [[TMP119:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP118]], ptr [[CX_ATOMIC_EXPECTED_PTR139]], align 1
+// CHECK-NEXT: store i8 [[TMP119]], ptr [[CX_ATOMIC_DESIRED_PTR140]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED142:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR139]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED143:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR140]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR144:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED142]], i8 [[CX_CMPXCHG_DESIRED143]] acquire acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV145:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR144]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV145]], ptr [[CX_ATOMIC_EXPECTED_PTR141]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS146:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR144]], 1
+// CHECK-NEXT: [[TMP120:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP121:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP120]] acquire, align 1
+// CHECK-NEXT: [[TMP122:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP122]] acquire, align 1
+// CHECK-NEXT: [[TMP124:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP125:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP124]] acquire, align 1
+// CHECK-NEXT: [[TMP126:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP127:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP126]] acquire, align 1
+// CHECK-NEXT: [[TMP128:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP129:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP128]] acquire, align 1
+// CHECK-NEXT: [[TMP130:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP131:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP130]] acquire, align 1
+// CHECK-NEXT: [[TMP132:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP133:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP132]] acquire, align 1
+// CHECK-NEXT: [[TMP134:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP135:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP134]] acquire, align 1
+// CHECK-NEXT: [[TMP136:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP137:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP136]], ptr [[UCX_ATOMIC_EXPECTED_PTR147]], align 1
+// CHECK-NEXT: store i8 [[TMP137]], ptr [[UCX_ATOMIC_DESIRED_PTR148]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED150:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR147]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED151:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR148]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR152:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED150]], i8 [[UCX_CMPXCHG_DESIRED151]] acquire acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV153:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR152]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV153]], ptr [[UCX_ATOMIC_EXPECTED_PTR149]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS154:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR152]], 1
+// CHECK-NEXT: [[TMP138:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP139:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP138]], ptr [[UCX_ATOMIC_EXPECTED_PTR155]], align 1
+// CHECK-NEXT: store i8 [[TMP139]], ptr [[UCX_ATOMIC_DESIRED_PTR156]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED158:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR155]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED159:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR156]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR160:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED158]], i8 [[UCX_CMPXCHG_DESIRED159]] acquire acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV161:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR160]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV161]], ptr [[UCX_ATOMIC_EXPECTED_PTR157]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS162:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR160]], 1
// CHECK-NEXT: [[TMP140:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP141:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP140]] acquire, align 1
+// CHECK-NEXT: [[TMP141:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP140]], ptr [[UCX_ATOMIC_EXPECTED_PTR163]], align 1
+// CHECK-NEXT: store i8 [[TMP141]], ptr [[UCX_ATOMIC_DESIRED_PTR164]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED166:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR163]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED167:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR164]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR168:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED166]], i8 [[UCX_CMPXCHG_DESIRED167]] acquire acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV169:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR168]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV169]], ptr [[UCX_ATOMIC_EXPECTED_PTR165]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS170:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR168]], 1
// CHECK-NEXT: [[TMP142:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP143:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP142]] acquire, align 1
-// CHECK-NEXT: [[TMP144:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP145:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP144]] acquire, align 1
-// CHECK-NEXT: [[TMP146:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP147:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP146]] acquire, align 1
-// CHECK-NEXT: [[TMP148:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP149:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP148]] acquire, align 1
-// CHECK-NEXT: [[TMP150:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP151:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP150]] acquire, align 1
-// CHECK-NEXT: [[TMP152:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP153:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP152]] acquire, align 1
-// CHECK-NEXT: [[TMP154:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP155:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP154]] acquire, align 1
-// CHECK-NEXT: [[TMP156:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP157:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP158:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP156]], i8 [[TMP157]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP159:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP160:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP161:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP159]], i8 [[TMP160]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP162:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP163:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP164:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP162]], i8 [[TMP163]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP165:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP166:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP167:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP165]], i8 [[TMP166]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP168:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP169:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP168]] monotonic, align 1
-// CHECK-NEXT: [[TMP170:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP171:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP170]] monotonic, align 1
-// CHECK-NEXT: [[TMP172:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP173:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP172]] monotonic, align 1
-// CHECK-NEXT: [[TMP174:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP175:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP174]] monotonic, align 1
-// CHECK-NEXT: [[TMP176:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP177:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP176]] monotonic, align 1
-// CHECK-NEXT: [[TMP178:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP179:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP178]] monotonic, align 1
-// CHECK-NEXT: [[TMP180:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP181:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP180]] monotonic, align 1
-// CHECK-NEXT: [[TMP182:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP183:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP182]] monotonic, align 1
-// CHECK-NEXT: [[TMP184:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP185:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP186:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP184]], i8 [[TMP185]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP187:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP188:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP189:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP187]], i8 [[TMP188]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP190:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP191:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP192:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP190]], i8 [[TMP191]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP193:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP194:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP195:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP193]], i8 [[TMP194]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP196:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP197:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP196]] monotonic, align 1
-// CHECK-NEXT: [[TMP198:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP199:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP198]] monotonic, align 1
-// CHECK-NEXT: [[TMP200:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP201:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP200]] monotonic, align 1
-// CHECK-NEXT: [[TMP202:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP203:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP202]] monotonic, align 1
-// CHECK-NEXT: [[TMP204:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP205:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP204]] monotonic, align 1
-// CHECK-NEXT: [[TMP206:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP207:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP206]] monotonic, align 1
-// CHECK-NEXT: [[TMP208:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP209:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP208]] monotonic, align 1
-// CHECK-NEXT: [[TMP210:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP211:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP210]] monotonic, align 1
-// CHECK-NEXT: [[TMP212:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP213:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP214:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP212]], i8 [[TMP213]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP215:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP216:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP217:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP215]], i8 [[TMP216]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP218:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP219:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP220:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP218]], i8 [[TMP219]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP221:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP222:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP223:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP221]], i8 [[TMP222]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP224:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP225:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP224]] release, align 1
+// CHECK-NEXT: [[TMP143:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP142]], ptr [[UCX_ATOMIC_EXPECTED_PTR171]], align 1
+// CHECK-NEXT: store i8 [[TMP143]], ptr [[UCX_ATOMIC_DESIRED_PTR172]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED174:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR171]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED175:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR172]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR176:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED174]], i8 [[UCX_CMPXCHG_DESIRED175]] acquire acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV177:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR176]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV177]], ptr [[UCX_ATOMIC_EXPECTED_PTR173]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS178:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR176]], 1
+// CHECK-NEXT: [[TMP144:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP145:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP144]] monotonic, align 1
+// CHECK-NEXT: [[TMP146:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP147:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP146]] monotonic, align 1
+// CHECK-NEXT: [[TMP148:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP149:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP148]] monotonic, align 1
+// CHECK-NEXT: [[TMP150:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP151:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP150]] monotonic, align 1
+// CHECK-NEXT: [[TMP152:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP153:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP152]] monotonic, align 1
+// CHECK-NEXT: [[TMP154:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP155:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP154]] monotonic, align 1
+// CHECK-NEXT: [[TMP156:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP157:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP156]] monotonic, align 1
+// CHECK-NEXT: [[TMP158:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP159:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP158]] monotonic, align 1
+// CHECK-NEXT: [[TMP160:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP161:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP160]], ptr [[CX_ATOMIC_EXPECTED_PTR179]], align 1
+// CHECK-NEXT: store i8 [[TMP161]], ptr [[CX_ATOMIC_DESIRED_PTR180]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED182:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR179]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED183:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR180]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR184:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED182]], i8 [[CX_CMPXCHG_DESIRED183]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV185:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR184]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV185]], ptr [[CX_ATOMIC_EXPECTED_PTR181]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS186:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR184]], 1
+// CHECK-NEXT: [[TMP162:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP163:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP162]], ptr [[CX_ATOMIC_EXPECTED_PTR187]], align 1
+// CHECK-NEXT: store i8 [[TMP163]], ptr [[CX_ATOMIC_DESIRED_PTR188]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED190:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR187]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED191:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR188]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR192:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED190]], i8 [[CX_CMPXCHG_DESIRED191]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV193:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR192]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV193]], ptr [[CX_ATOMIC_EXPECTED_PTR189]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS194:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR192]], 1
+// CHECK-NEXT: [[TMP164:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP165:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP164]], ptr [[CX_ATOMIC_EXPECTED_PTR195]], align 1
+// CHECK-NEXT: store i8 [[TMP165]], ptr [[CX_ATOMIC_DESIRED_PTR196]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED198:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR195]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED199:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR196]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR200:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED198]], i8 [[CX_CMPXCHG_DESIRED199]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV201:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR200]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV201]], ptr [[CX_ATOMIC_EXPECTED_PTR197]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS202:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR200]], 1
+// CHECK-NEXT: [[TMP166:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP167:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP166]], ptr [[CX_ATOMIC_EXPECTED_PTR203]], align 1
+// CHECK-NEXT: store i8 [[TMP167]], ptr [[CX_ATOMIC_DESIRED_PTR204]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED206:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR203]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED207:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR204]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR208:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED206]], i8 [[CX_CMPXCHG_DESIRED207]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV209:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR208]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV209]], ptr [[CX_ATOMIC_EXPECTED_PTR205]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS210:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR208]], 1
+// CHECK-NEXT: [[TMP168:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP169:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP168]] monotonic, align 1
+// CHECK-NEXT: [[TMP170:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP171:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP170]] monotonic, align 1
+// CHECK-NEXT: [[TMP172:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP173:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP172]] monotonic, align 1
+// CHECK-NEXT: [[TMP174:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP175:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP174]] monotonic, align 1
+// CHECK-NEXT: [[TMP176:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP177:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP176]] monotonic, align 1
+// CHECK-NEXT: [[TMP178:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP179:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP178]] monotonic, align 1
+// CHECK-NEXT: [[TMP180:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP181:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP180]] monotonic, align 1
+// CHECK-NEXT: [[TMP182:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP183:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP182]] monotonic, align 1
+// CHECK-NEXT: [[TMP184:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP185:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP184]], ptr [[UCX_ATOMIC_EXPECTED_PTR211]], align 1
+// CHECK-NEXT: store i8 [[TMP185]], ptr [[UCX_ATOMIC_DESIRED_PTR212]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED214:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR211]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED215:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR212]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR216:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED214]], i8 [[UCX_CMPXCHG_DESIRED215]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV217:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR216]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV217]], ptr [[UCX_ATOMIC_EXPECTED_PTR213]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS218:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR216]], 1
+// CHECK-NEXT: [[TMP186:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP187:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP186]], ptr [[UCX_ATOMIC_EXPECTED_PTR219]], align 1
+// CHECK-NEXT: store i8 [[TMP187]], ptr [[UCX_ATOMIC_DESIRED_PTR220]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED222:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR219]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED223:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR220]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR224:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED222]], i8 [[UCX_CMPXCHG_DESIRED223]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV225:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR224]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV225]], ptr [[UCX_ATOMIC_EXPECTED_PTR221]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS226:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR224]], 1
+// CHECK-NEXT: [[TMP188:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP189:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP188]], ptr [[UCX_ATOMIC_EXPECTED_PTR227]], align 1
+// CHECK-NEXT: store i8 [[TMP189]], ptr [[UCX_ATOMIC_DESIRED_PTR228]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED230:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR227]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED231:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR228]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR232:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED230]], i8 [[UCX_CMPXCHG_DESIRED231]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV233:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR232]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV233]], ptr [[UCX_ATOMIC_EXPECTED_PTR229]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS234:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR232]], 1
+// CHECK-NEXT: [[TMP190:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP191:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP190]], ptr [[UCX_ATOMIC_EXPECTED_PTR235]], align 1
+// CHECK-NEXT: store i8 [[TMP191]], ptr [[UCX_ATOMIC_DESIRED_PTR236]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED238:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR235]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED239:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR236]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR240:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED238]], i8 [[UCX_CMPXCHG_DESIRED239]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV241:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR240]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV241]], ptr [[UCX_ATOMIC_EXPECTED_PTR237]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS242:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR240]], 1
+// CHECK-NEXT: [[TMP192:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP193:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP192]] release, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP226:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP227:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP226]] release, align 1
+// CHECK-NEXT: [[TMP194:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP195:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP194]] release, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP228:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP229:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP228]] release, align 1
+// CHECK-NEXT: [[TMP196:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP197:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP196]] release, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP198:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP199:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP198]] release, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP230:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP231:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP230]] release, align 1
+// CHECK-NEXT: [[TMP200:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP201:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP200]] release, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP232:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP233:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP232]] release, align 1
+// CHECK-NEXT: [[TMP202:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP203:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP202]] release, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP234:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP235:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP234]] release, align 1
+// CHECK-NEXT: [[TMP204:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP205:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP204]] release, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP206:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP207:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP206]] release, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP208:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP209:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP208]], ptr [[CX_ATOMIC_EXPECTED_PTR243]], align 1
+// CHECK-NEXT: store i8 [[TMP209]], ptr [[CX_ATOMIC_DESIRED_PTR244]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED246:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR243]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED247:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR244]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR248:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED246]], i8 [[CX_CMPXCHG_DESIRED247]] release monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV249:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR248]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV249]], ptr [[CX_ATOMIC_EXPECTED_PTR245]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS250:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR248]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP236:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP237:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP236]] release, align 1
+// CHECK-NEXT: [[TMP210:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP211:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP210]], ptr [[CX_ATOMIC_EXPECTED_PTR251]], align 1
+// CHECK-NEXT: store i8 [[TMP211]], ptr [[CX_ATOMIC_DESIRED_PTR252]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED254:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR251]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED255:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR252]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR256:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED254]], i8 [[CX_CMPXCHG_DESIRED255]] release monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV257:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR256]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV257]], ptr [[CX_ATOMIC_EXPECTED_PTR253]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS258:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR256]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP212:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP213:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP212]], ptr [[CX_ATOMIC_EXPECTED_PTR259]], align 1
+// CHECK-NEXT: store i8 [[TMP213]], ptr [[CX_ATOMIC_DESIRED_PTR260]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED262:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR259]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED263:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR260]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR264:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED262]], i8 [[CX_CMPXCHG_DESIRED263]] release monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV265:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR264]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV265]], ptr [[CX_ATOMIC_EXPECTED_PTR261]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS266:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR264]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP214:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP215:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP214]], ptr [[CX_ATOMIC_EXPECTED_PTR267]], align 1
+// CHECK-NEXT: store i8 [[TMP215]], ptr [[CX_ATOMIC_DESIRED_PTR268]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED270:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR267]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED271:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR268]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR272:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED270]], i8 [[CX_CMPXCHG_DESIRED271]] release monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV273:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR272]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV273]], ptr [[CX_ATOMIC_EXPECTED_PTR269]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS274:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR272]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP216:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP217:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP216]] release, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP238:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP239:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP238]] release, align 1
+// CHECK-NEXT: [[TMP218:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP219:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP218]] release, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP220:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP221:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP220]] release, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP222:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP223:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP222]] release, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP224:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP225:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP224]] release, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP226:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP227:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP226]] release, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP228:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP229:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP228]] release, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP230:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP231:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP230]] release, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP232:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP233:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP232]], ptr [[UCX_ATOMIC_EXPECTED_PTR275]], align 1
+// CHECK-NEXT: store i8 [[TMP233]], ptr [[UCX_ATOMIC_DESIRED_PTR276]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED278:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR275]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED279:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR276]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR280:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED278]], i8 [[UCX_CMPXCHG_DESIRED279]] release monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV281:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR280]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV281]], ptr [[UCX_ATOMIC_EXPECTED_PTR277]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS282:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR280]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP234:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP235:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP234]], ptr [[UCX_ATOMIC_EXPECTED_PTR283]], align 1
+// CHECK-NEXT: store i8 [[TMP235]], ptr [[UCX_ATOMIC_DESIRED_PTR284]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED286:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR283]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED287:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR284]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR288:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED286]], i8 [[UCX_CMPXCHG_DESIRED287]] release monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV289:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR288]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV289]], ptr [[UCX_ATOMIC_EXPECTED_PTR285]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS290:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR288]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP236:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP237:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP236]], ptr [[UCX_ATOMIC_EXPECTED_PTR291]], align 1
+// CHECK-NEXT: store i8 [[TMP237]], ptr [[UCX_ATOMIC_DESIRED_PTR292]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED294:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR291]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED295:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR292]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR296:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED294]], i8 [[UCX_CMPXCHG_DESIRED295]] release monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV297:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR296]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV297]], ptr [[UCX_ATOMIC_EXPECTED_PTR293]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS298:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR296]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP238:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP239:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP238]], ptr [[UCX_ATOMIC_EXPECTED_PTR299]], align 1
+// CHECK-NEXT: store i8 [[TMP239]], ptr [[UCX_ATOMIC_DESIRED_PTR300]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED302:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR299]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED303:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR300]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR304:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED302]], i8 [[UCX_CMPXCHG_DESIRED303]] release monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV305:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR304]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV305]], ptr [[UCX_ATOMIC_EXPECTED_PTR301]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS306:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR304]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP240:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP241:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP242:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP240]], i8 [[TMP241]] release monotonic, align 1
+// CHECK-NEXT: [[TMP241:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP240]] seq_cst, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP242:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP243:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP242]] seq_cst, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP243:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP244:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP245:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP243]], i8 [[TMP244]] release monotonic, align 1
+// CHECK-NEXT: [[TMP244:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP245:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP244]] seq_cst, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP246:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP247:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP248:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP246]], i8 [[TMP247]] release monotonic, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP249:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP250:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP251:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP249]], i8 [[TMP250]] release monotonic, align 1
+// CHECK-NEXT: [[TMP247:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP246]] seq_cst, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP252:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP253:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP252]] release, align 1
+// CHECK-NEXT: [[TMP248:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP249:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP248]] seq_cst, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP254:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP255:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP254]] release, align 1
+// CHECK-NEXT: [[TMP250:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP251:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP250]] seq_cst, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP256:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP257:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP256]] release, align 1
+// CHECK-NEXT: [[TMP252:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP253:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP252]] seq_cst, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP258:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP259:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP258]] release, align 1
+// CHECK-NEXT: [[TMP254:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP255:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP254]] seq_cst, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP256:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP257:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP256]], ptr [[CX_ATOMIC_EXPECTED_PTR307]], align 1
+// CHECK-NEXT: store i8 [[TMP257]], ptr [[CX_ATOMIC_DESIRED_PTR308]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED310:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR307]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED311:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR308]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR312:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED310]], i8 [[CX_CMPXCHG_DESIRED311]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV313:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR312]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV313]], ptr [[CX_ATOMIC_EXPECTED_PTR309]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS314:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR312]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP260:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP261:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP260]] release, align 1
+// CHECK-NEXT: [[TMP258:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP259:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP258]], ptr [[CX_ATOMIC_EXPECTED_PTR315]], align 1
+// CHECK-NEXT: store i8 [[TMP259]], ptr [[CX_ATOMIC_DESIRED_PTR316]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED318:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR315]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED319:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR316]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR320:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED318]], i8 [[CX_CMPXCHG_DESIRED319]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV321:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR320]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV321]], ptr [[CX_ATOMIC_EXPECTED_PTR317]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS322:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR320]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP260:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP261:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP260]], ptr [[CX_ATOMIC_EXPECTED_PTR323]], align 1
+// CHECK-NEXT: store i8 [[TMP261]], ptr [[CX_ATOMIC_DESIRED_PTR324]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED326:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR323]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED327:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR324]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR328:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED326]], i8 [[CX_CMPXCHG_DESIRED327]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV329:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR328]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV329]], ptr [[CX_ATOMIC_EXPECTED_PTR325]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS330:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR328]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP262:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP263:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP262]] release, align 1
+// CHECK-NEXT: [[TMP262:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP263:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP262]], ptr [[CX_ATOMIC_EXPECTED_PTR331]], align 1
+// CHECK-NEXT: store i8 [[TMP263]], ptr [[CX_ATOMIC_DESIRED_PTR332]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED334:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR331]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED335:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR332]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR336:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED334]], i8 [[CX_CMPXCHG_DESIRED335]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV337:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR336]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV337]], ptr [[CX_ATOMIC_EXPECTED_PTR333]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS338:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR336]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP264:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP265:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP264]] release, align 1
+// CHECK-NEXT: [[TMP265:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP264]] seq_cst, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP266:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP267:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP266]] release, align 1
+// CHECK-NEXT: [[TMP267:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP266]] seq_cst, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP268:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP269:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP270:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP268]], i8 [[TMP269]] release monotonic, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP271:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP272:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP273:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP271]], i8 [[TMP272]] release monotonic, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP274:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP275:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP276:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP274]], i8 [[TMP275]] release monotonic, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP277:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP278:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP279:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP277]], i8 [[TMP278]] release monotonic, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP280:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP281:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP280]] seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP282:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP283:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP282]] seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP284:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP285:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP284]] seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP286:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP287:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP286]] seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP288:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP289:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP288]] seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP290:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP291:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP290]] seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP292:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP293:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP292]] seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP294:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP295:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP294]] seq_cst, align 1
+// CHECK-NEXT: [[TMP269:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP268]] seq_cst, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP296:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP297:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP298:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP296]], i8 [[TMP297]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[TMP270:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP271:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP270]] seq_cst, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP299:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP300:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP301:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP299]], i8 [[TMP300]] seq_cst seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP302:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP303:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP304:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP302]], i8 [[TMP303]] seq_cst seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP305:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP306:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP307:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP305]], i8 [[TMP306]] seq_cst seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP308:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP309:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP308]] seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP310:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP311:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP310]] seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP312:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP313:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP312]] seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP314:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP315:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP314]] seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP316:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP317:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP316]] seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP318:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP319:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP318]] seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP320:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP321:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP320]] seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP322:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP323:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP322]] seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP324:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP325:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP326:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP324]], i8 [[TMP325]] seq_cst seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP327:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP328:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP329:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP327]], i8 [[TMP328]] seq_cst seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP330:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP331:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP332:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP330]], i8 [[TMP331]] seq_cst seq_cst, align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP333:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP334:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP335:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP333]], i8 [[TMP334]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[TMP272:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP273:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP272]] seq_cst, align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP274:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP275:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP274]] seq_cst, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP276:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP277:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP276]] seq_cst, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP278:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP279:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP278]] seq_cst, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP280:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP281:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP280]], ptr [[UCX_ATOMIC_EXPECTED_PTR339]], align 1
+// CHECK-NEXT: store i8 [[TMP281]], ptr [[UCX_ATOMIC_DESIRED_PTR340]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED342:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR339]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED343:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR340]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR344:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED342]], i8 [[UCX_CMPXCHG_DESIRED343]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV345:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR344]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV345]], ptr [[UCX_ATOMIC_EXPECTED_PTR341]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS346:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR344]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP282:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP283:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP282]], ptr [[UCX_ATOMIC_EXPECTED_PTR347]], align 1
+// CHECK-NEXT: store i8 [[TMP283]], ptr [[UCX_ATOMIC_DESIRED_PTR348]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED350:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR347]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED351:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR348]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR352:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED350]], i8 [[UCX_CMPXCHG_DESIRED351]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV353:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR352]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV353]], ptr [[UCX_ATOMIC_EXPECTED_PTR349]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS354:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR352]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP284:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP285:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP284]], ptr [[UCX_ATOMIC_EXPECTED_PTR355]], align 1
+// CHECK-NEXT: store i8 [[TMP285]], ptr [[UCX_ATOMIC_DESIRED_PTR356]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED358:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR355]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED359:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR356]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR360:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED358]], i8 [[UCX_CMPXCHG_DESIRED359]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV361:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR360]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV361]], ptr [[UCX_ATOMIC_EXPECTED_PTR357]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS362:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR360]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP286:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP287:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP286]], ptr [[UCX_ATOMIC_EXPECTED_PTR363]], align 1
+// CHECK-NEXT: store i8 [[TMP287]], ptr [[UCX_ATOMIC_DESIRED_PTR364]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED366:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR363]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED367:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR364]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR368:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED366]], i8 [[UCX_CMPXCHG_DESIRED367]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV369:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR368]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV369]], ptr [[UCX_ATOMIC_EXPECTED_PTR365]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS370:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR368]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP288:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP289:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP288]] monotonic, align 2
+// CHECK-NEXT: [[TMP290:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP291:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP290]] monotonic, align 2
+// CHECK-NEXT: [[TMP292:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP293:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP292]] monotonic, align 2
+// CHECK-NEXT: [[TMP294:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP295:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP294]] monotonic, align 2
+// CHECK-NEXT: [[TMP296:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP297:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP296]] monotonic, align 2
+// CHECK-NEXT: [[TMP298:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP299:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP298]] monotonic, align 2
+// CHECK-NEXT: [[TMP300:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP301:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP300]] monotonic, align 2
+// CHECK-NEXT: [[TMP302:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP303:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP302]] monotonic, align 2
+// CHECK-NEXT: [[TMP304:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP305:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP304]], ptr [[SX_ATOMIC_EXPECTED_PTR]], align 2
+// CHECK-NEXT: store i16 [[TMP305]], ptr [[SX_ATOMIC_DESIRED_PTR]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED]], i16 [[SX_CMPXCHG_DESIRED]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV]], ptr [[SX_ATOMIC_EXPECTED_PTR371]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[TMP306:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP307:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP306]], ptr [[SX_ATOMIC_EXPECTED_PTR372]], align 2
+// CHECK-NEXT: store i16 [[TMP307]], ptr [[SX_ATOMIC_DESIRED_PTR373]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED375:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR372]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED376:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR373]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR377:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED375]], i16 [[SX_CMPXCHG_DESIRED376]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV378:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR377]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV378]], ptr [[SX_ATOMIC_EXPECTED_PTR374]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS379:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR377]], 1
+// CHECK-NEXT: [[TMP308:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP309:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP308]], ptr [[SX_ATOMIC_EXPECTED_PTR380]], align 2
+// CHECK-NEXT: store i16 [[TMP309]], ptr [[SX_ATOMIC_DESIRED_PTR381]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED383:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR380]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED384:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR381]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR385:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED383]], i16 [[SX_CMPXCHG_DESIRED384]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV386:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR385]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV386]], ptr [[SX_ATOMIC_EXPECTED_PTR382]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS387:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR385]], 1
+// CHECK-NEXT: [[TMP310:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP311:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP310]], ptr [[SX_ATOMIC_EXPECTED_PTR388]], align 2
+// CHECK-NEXT: store i16 [[TMP311]], ptr [[SX_ATOMIC_DESIRED_PTR389]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED391:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR388]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED392:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR389]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR393:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED391]], i16 [[SX_CMPXCHG_DESIRED392]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV394:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR393]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV394]], ptr [[SX_ATOMIC_EXPECTED_PTR390]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS395:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR393]], 1
+// CHECK-NEXT: [[TMP312:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP313:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP312]] monotonic, align 2
+// CHECK-NEXT: [[TMP314:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP315:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP314]] monotonic, align 2
+// CHECK-NEXT: [[TMP316:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP317:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP316]] monotonic, align 2
+// CHECK-NEXT: [[TMP318:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP319:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP318]] monotonic, align 2
+// CHECK-NEXT: [[TMP320:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP321:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP320]] monotonic, align 2
+// CHECK-NEXT: [[TMP322:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP323:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP322]] monotonic, align 2
+// CHECK-NEXT: [[TMP324:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP325:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP324]] monotonic, align 2
+// CHECK-NEXT: [[TMP326:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP327:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP326]] monotonic, align 2
+// CHECK-NEXT: [[TMP328:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP329:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP328]], ptr [[USX_ATOMIC_EXPECTED_PTR]], align 2
+// CHECK-NEXT: store i16 [[TMP329]], ptr [[USX_ATOMIC_DESIRED_PTR]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED]], i16 [[USX_CMPXCHG_DESIRED]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV]], ptr [[USX_ATOMIC_EXPECTED_PTR396]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[TMP330:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP331:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP330]], ptr [[USX_ATOMIC_EXPECTED_PTR397]], align 2
+// CHECK-NEXT: store i16 [[TMP331]], ptr [[USX_ATOMIC_DESIRED_PTR398]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED400:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR397]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED401:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR398]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR402:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED400]], i16 [[USX_CMPXCHG_DESIRED401]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV403:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR402]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV403]], ptr [[USX_ATOMIC_EXPECTED_PTR399]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS404:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR402]], 1
+// CHECK-NEXT: [[TMP332:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP333:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP332]], ptr [[USX_ATOMIC_EXPECTED_PTR405]], align 2
+// CHECK-NEXT: store i16 [[TMP333]], ptr [[USX_ATOMIC_DESIRED_PTR406]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED408:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR405]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED409:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR406]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR410:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED408]], i16 [[USX_CMPXCHG_DESIRED409]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV411:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR410]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV411]], ptr [[USX_ATOMIC_EXPECTED_PTR407]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS412:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR410]], 1
+// CHECK-NEXT: [[TMP334:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP335:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP334]], ptr [[USX_ATOMIC_EXPECTED_PTR413]], align 2
+// CHECK-NEXT: store i16 [[TMP335]], ptr [[USX_ATOMIC_DESIRED_PTR414]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED416:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR413]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED417:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR414]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR418:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED416]], i16 [[USX_CMPXCHG_DESIRED417]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV419:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR418]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV419]], ptr [[USX_ATOMIC_EXPECTED_PTR415]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS420:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR418]], 1
// CHECK-NEXT: [[TMP336:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP337:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP336]] monotonic, align 2
+// CHECK-NEXT: [[TMP337:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP336]] acq_rel, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP338:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP339:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP338]] monotonic, align 2
+// CHECK-NEXT: [[TMP339:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP338]] acq_rel, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP340:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP341:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP340]] monotonic, align 2
+// CHECK-NEXT: [[TMP341:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP340]] acq_rel, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP342:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP343:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP342]] monotonic, align 2
+// CHECK-NEXT: [[TMP343:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP342]] acq_rel, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP344:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP345:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP344]] monotonic, align 2
+// CHECK-NEXT: [[TMP345:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP344]] acq_rel, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP346:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP347:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP346]] monotonic, align 2
+// CHECK-NEXT: [[TMP347:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP346]] acq_rel, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP348:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP349:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP348]] monotonic, align 2
+// CHECK-NEXT: [[TMP349:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP348]] acq_rel, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP350:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP351:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP350]] monotonic, align 2
+// CHECK-NEXT: [[TMP351:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP350]] acq_rel, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP352:%.*]] = load i16, ptr [[SE]], align 2
// CHECK-NEXT: [[TMP353:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP354:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP352]], i16 [[TMP353]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP355:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP356:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP357:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP355]], i16 [[TMP356]] monotonic monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP352]], ptr [[SX_ATOMIC_EXPECTED_PTR421]], align 2
+// CHECK-NEXT: store i16 [[TMP353]], ptr [[SX_ATOMIC_DESIRED_PTR422]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED424:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR421]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED425:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR422]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR426:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED424]], i16 [[SX_CMPXCHG_DESIRED425]] acq_rel acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV427:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR426]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV427]], ptr [[SX_ATOMIC_EXPECTED_PTR423]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS428:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR426]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP354:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP355:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP354]], ptr [[SX_ATOMIC_EXPECTED_PTR429]], align 2
+// CHECK-NEXT: store i16 [[TMP355]], ptr [[SX_ATOMIC_DESIRED_PTR430]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED432:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR429]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED433:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR430]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR434:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED432]], i16 [[SX_CMPXCHG_DESIRED433]] acq_rel acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV435:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR434]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV435]], ptr [[SX_ATOMIC_EXPECTED_PTR431]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS436:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR434]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP356:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP357:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP356]], ptr [[SX_ATOMIC_EXPECTED_PTR437]], align 2
+// CHECK-NEXT: store i16 [[TMP357]], ptr [[SX_ATOMIC_DESIRED_PTR438]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED440:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR437]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED441:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR438]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR442:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED440]], i16 [[SX_CMPXCHG_DESIRED441]] acq_rel acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV443:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR442]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV443]], ptr [[SX_ATOMIC_EXPECTED_PTR439]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS444:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR442]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP358:%.*]] = load i16, ptr [[SE]], align 2
// CHECK-NEXT: [[TMP359:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP360:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP358]], i16 [[TMP359]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP361:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP362:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP363:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP361]], i16 [[TMP362]] monotonic monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP358]], ptr [[SX_ATOMIC_EXPECTED_PTR445]], align 2
+// CHECK-NEXT: store i16 [[TMP359]], ptr [[SX_ATOMIC_DESIRED_PTR446]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED448:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR445]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED449:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR446]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR450:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED448]], i16 [[SX_CMPXCHG_DESIRED449]] acq_rel acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV451:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR450]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV451]], ptr [[SX_ATOMIC_EXPECTED_PTR447]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS452:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR450]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP360:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP361:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP360]] acq_rel, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP362:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP363:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP362]] acq_rel, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP364:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP365:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP364]] monotonic, align 2
+// CHECK-NEXT: [[TMP365:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP364]] acq_rel, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP366:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP367:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP366]] monotonic, align 2
+// CHECK-NEXT: [[TMP367:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP366]] acq_rel, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP368:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP369:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP368]] monotonic, align 2
+// CHECK-NEXT: [[TMP369:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP368]] acq_rel, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP370:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP371:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP370]] monotonic, align 2
+// CHECK-NEXT: [[TMP371:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP370]] acq_rel, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP372:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP373:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP372]] monotonic, align 2
+// CHECK-NEXT: [[TMP373:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP372]] acq_rel, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP374:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP375:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP374]] monotonic, align 2
+// CHECK-NEXT: [[TMP375:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP374]] acq_rel, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP376:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP377:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP376]] monotonic, align 2
+// CHECK-NEXT: [[TMP377:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP376]], ptr [[USX_ATOMIC_EXPECTED_PTR453]], align 2
+// CHECK-NEXT: store i16 [[TMP377]], ptr [[USX_ATOMIC_DESIRED_PTR454]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED456:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR453]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED457:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR454]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR458:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED456]], i16 [[USX_CMPXCHG_DESIRED457]] acq_rel acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV459:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR458]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV459]], ptr [[USX_ATOMIC_EXPECTED_PTR455]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS460:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR458]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP378:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP379:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP378]] monotonic, align 2
+// CHECK-NEXT: [[TMP379:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP378]], ptr [[USX_ATOMIC_EXPECTED_PTR461]], align 2
+// CHECK-NEXT: store i16 [[TMP379]], ptr [[USX_ATOMIC_DESIRED_PTR462]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED464:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR461]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED465:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR462]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR466:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED464]], i16 [[USX_CMPXCHG_DESIRED465]] acq_rel acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV467:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR466]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV467]], ptr [[USX_ATOMIC_EXPECTED_PTR463]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS468:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR466]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP380:%.*]] = load i16, ptr [[USE]], align 2
// CHECK-NEXT: [[TMP381:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP382:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP380]], i16 [[TMP381]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP383:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP384:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP385:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP383]], i16 [[TMP384]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP386:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP387:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP388:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP386]], i16 [[TMP387]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP389:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP390:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP391:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP389]], i16 [[TMP390]] monotonic monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP380]], ptr [[USX_ATOMIC_EXPECTED_PTR469]], align 2
+// CHECK-NEXT: store i16 [[TMP381]], ptr [[USX_ATOMIC_DESIRED_PTR470]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED472:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR469]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED473:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR470]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR474:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED472]], i16 [[USX_CMPXCHG_DESIRED473]] acq_rel acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV475:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR474]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV475]], ptr [[USX_ATOMIC_EXPECTED_PTR471]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS476:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR474]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP382:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP383:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP382]], ptr [[USX_ATOMIC_EXPECTED_PTR477]], align 2
+// CHECK-NEXT: store i16 [[TMP383]], ptr [[USX_ATOMIC_DESIRED_PTR478]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED480:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR477]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED481:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR478]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR482:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED480]], i16 [[USX_CMPXCHG_DESIRED481]] acq_rel acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV483:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR482]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV483]], ptr [[USX_ATOMIC_EXPECTED_PTR479]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS484:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR482]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP384:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP385:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP384]] acquire, align 2
+// CHECK-NEXT: [[TMP386:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP387:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP386]] acquire, align 2
+// CHECK-NEXT: [[TMP388:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP389:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP388]] acquire, align 2
+// CHECK-NEXT: [[TMP390:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP391:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP390]] acquire, align 2
// CHECK-NEXT: [[TMP392:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP393:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP392]] acq_rel, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP393:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP392]] acquire, align 2
// CHECK-NEXT: [[TMP394:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP395:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP394]] acq_rel, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP395:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP394]] acquire, align 2
// CHECK-NEXT: [[TMP396:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP397:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP396]] acq_rel, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP397:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP396]] acquire, align 2
// CHECK-NEXT: [[TMP398:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP399:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP398]] acq_rel, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP399:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP398]] acquire, align 2
// CHECK-NEXT: [[TMP400:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP401:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP400]] acq_rel, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP401:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP400]], ptr [[SX_ATOMIC_EXPECTED_PTR485]], align 2
+// CHECK-NEXT: store i16 [[TMP401]], ptr [[SX_ATOMIC_DESIRED_PTR486]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED488:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR485]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED489:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR486]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR490:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED488]], i16 [[SX_CMPXCHG_DESIRED489]] acquire acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV491:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR490]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV491]], ptr [[SX_ATOMIC_EXPECTED_PTR487]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS492:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR490]], 1
// CHECK-NEXT: [[TMP402:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP403:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP402]] acq_rel, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP403:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP402]], ptr [[SX_ATOMIC_EXPECTED_PTR493]], align 2
+// CHECK-NEXT: store i16 [[TMP403]], ptr [[SX_ATOMIC_DESIRED_PTR494]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED496:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR493]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED497:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR494]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR498:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED496]], i16 [[SX_CMPXCHG_DESIRED497]] acquire acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV499:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR498]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV499]], ptr [[SX_ATOMIC_EXPECTED_PTR495]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS500:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR498]], 1
// CHECK-NEXT: [[TMP404:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP405:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP404]] acq_rel, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP405:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP404]], ptr [[SX_ATOMIC_EXPECTED_PTR501]], align 2
+// CHECK-NEXT: store i16 [[TMP405]], ptr [[SX_ATOMIC_DESIRED_PTR502]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED504:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR501]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED505:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR502]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR506:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED504]], i16 [[SX_CMPXCHG_DESIRED505]] acquire acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV507:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR506]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV507]], ptr [[SX_ATOMIC_EXPECTED_PTR503]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS508:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR506]], 1
// CHECK-NEXT: [[TMP406:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP407:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP406]] acq_rel, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP408:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP409:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP410:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP408]], i16 [[TMP409]] acq_rel acquire, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP411:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP412:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP413:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP411]], i16 [[TMP412]] acq_rel acquire, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP414:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP415:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP416:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP414]], i16 [[TMP415]] acq_rel acquire, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP417:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP418:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP419:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP417]], i16 [[TMP418]] acq_rel acquire, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP407:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP406]], ptr [[SX_ATOMIC_EXPECTED_PTR509]], align 2
+// CHECK-NEXT: store i16 [[TMP407]], ptr [[SX_ATOMIC_DESIRED_PTR510]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED512:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR509]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED513:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR510]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR514:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED512]], i16 [[SX_CMPXCHG_DESIRED513]] acquire acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV515:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR514]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV515]], ptr [[SX_ATOMIC_EXPECTED_PTR511]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS516:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR514]], 1
+// CHECK-NEXT: [[TMP408:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP409:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP408]] acquire, align 2
+// CHECK-NEXT: [[TMP410:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP411:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP410]] acquire, align 2
+// CHECK-NEXT: [[TMP412:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP413:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP412]] acquire, align 2
+// CHECK-NEXT: [[TMP414:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP415:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP414]] acquire, align 2
+// CHECK-NEXT: [[TMP416:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP417:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP416]] acquire, align 2
+// CHECK-NEXT: [[TMP418:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP419:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP418]] acquire, align 2
// CHECK-NEXT: [[TMP420:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP421:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP420]] acq_rel, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP421:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP420]] acquire, align 2
// CHECK-NEXT: [[TMP422:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP423:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP422]] acq_rel, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP423:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP422]] acquire, align 2
// CHECK-NEXT: [[TMP424:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP425:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP424]] acq_rel, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP425:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP424]], ptr [[USX_ATOMIC_EXPECTED_PTR517]], align 2
+// CHECK-NEXT: store i16 [[TMP425]], ptr [[USX_ATOMIC_DESIRED_PTR518]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED520:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR517]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED521:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR518]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR522:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED520]], i16 [[USX_CMPXCHG_DESIRED521]] acquire acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV523:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR522]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV523]], ptr [[USX_ATOMIC_EXPECTED_PTR519]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS524:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR522]], 1
// CHECK-NEXT: [[TMP426:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP427:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP426]] acq_rel, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP427:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP426]], ptr [[USX_ATOMIC_EXPECTED_PTR525]], align 2
+// CHECK-NEXT: store i16 [[TMP427]], ptr [[USX_ATOMIC_DESIRED_PTR526]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED528:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR525]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED529:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR526]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR530:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED528]], i16 [[USX_CMPXCHG_DESIRED529]] acquire acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV531:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR530]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV531]], ptr [[USX_ATOMIC_EXPECTED_PTR527]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS532:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR530]], 1
// CHECK-NEXT: [[TMP428:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP429:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP428]] acq_rel, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP429:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP428]], ptr [[USX_ATOMIC_EXPECTED_PTR533]], align 2
+// CHECK-NEXT: store i16 [[TMP429]], ptr [[USX_ATOMIC_DESIRED_PTR534]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED536:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR533]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED537:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR534]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR538:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED536]], i16 [[USX_CMPXCHG_DESIRED537]] acquire acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV539:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR538]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV539]], ptr [[USX_ATOMIC_EXPECTED_PTR535]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS540:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR538]], 1
// CHECK-NEXT: [[TMP430:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP431:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP430]] acq_rel, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP432:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP433:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP432]] acq_rel, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP434:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP435:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP434]] acq_rel, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP436:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP437:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP438:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP436]], i16 [[TMP437]] acq_rel acquire, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP439:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP440:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP441:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP439]], i16 [[TMP440]] acq_rel acquire, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP442:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP443:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP444:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP442]], i16 [[TMP443]] acq_rel acquire, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP445:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP446:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP447:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP445]], i16 [[TMP446]] acq_rel acquire, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP431:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP430]], ptr [[USX_ATOMIC_EXPECTED_PTR541]], align 2
+// CHECK-NEXT: store i16 [[TMP431]], ptr [[USX_ATOMIC_DESIRED_PTR542]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED544:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR541]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED545:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR542]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR546:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED544]], i16 [[USX_CMPXCHG_DESIRED545]] acquire acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV547:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR546]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV547]], ptr [[USX_ATOMIC_EXPECTED_PTR543]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS548:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR546]], 1
+// CHECK-NEXT: [[TMP432:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP433:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP432]] monotonic, align 2
+// CHECK-NEXT: [[TMP434:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP435:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP434]] monotonic, align 2
+// CHECK-NEXT: [[TMP436:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP437:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP436]] monotonic, align 2
+// CHECK-NEXT: [[TMP438:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP439:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP438]] monotonic, align 2
+// CHECK-NEXT: [[TMP440:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP441:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP440]] monotonic, align 2
+// CHECK-NEXT: [[TMP442:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP443:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP442]] monotonic, align 2
+// CHECK-NEXT: [[TMP444:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP445:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP444]] monotonic, align 2
+// CHECK-NEXT: [[TMP446:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP447:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP446]] monotonic, align 2
// CHECK-NEXT: [[TMP448:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP449:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP448]] acquire, align 2
+// CHECK-NEXT: [[TMP449:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP448]], ptr [[SX_ATOMIC_EXPECTED_PTR549]], align 2
+// CHECK-NEXT: store i16 [[TMP449]], ptr [[SX_ATOMIC_DESIRED_PTR550]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED552:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR549]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED553:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR550]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR554:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED552]], i16 [[SX_CMPXCHG_DESIRED553]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV555:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR554]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV555]], ptr [[SX_ATOMIC_EXPECTED_PTR551]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS556:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR554]], 1
// CHECK-NEXT: [[TMP450:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP451:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP450]] acquire, align 2
+// CHECK-NEXT: [[TMP451:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP450]], ptr [[SX_ATOMIC_EXPECTED_PTR557]], align 2
+// CHECK-NEXT: store i16 [[TMP451]], ptr [[SX_ATOMIC_DESIRED_PTR558]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED560:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR557]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED561:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR558]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR562:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED560]], i16 [[SX_CMPXCHG_DESIRED561]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV563:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR562]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV563]], ptr [[SX_ATOMIC_EXPECTED_PTR559]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS564:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR562]], 1
// CHECK-NEXT: [[TMP452:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP453:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP452]] acquire, align 2
+// CHECK-NEXT: [[TMP453:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP452]], ptr [[SX_ATOMIC_EXPECTED_PTR565]], align 2
+// CHECK-NEXT: store i16 [[TMP453]], ptr [[SX_ATOMIC_DESIRED_PTR566]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED568:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR565]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED569:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR566]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR570:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED568]], i16 [[SX_CMPXCHG_DESIRED569]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV571:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR570]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV571]], ptr [[SX_ATOMIC_EXPECTED_PTR567]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS572:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR570]], 1
// CHECK-NEXT: [[TMP454:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP455:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP454]] acquire, align 2
-// CHECK-NEXT: [[TMP456:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP457:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP456]] acquire, align 2
-// CHECK-NEXT: [[TMP458:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP459:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP458]] acquire, align 2
-// CHECK-NEXT: [[TMP460:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP461:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP460]] acquire, align 2
-// CHECK-NEXT: [[TMP462:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP463:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP462]] acquire, align 2
-// CHECK-NEXT: [[TMP464:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP465:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP466:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP464]], i16 [[TMP465]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP467:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP468:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP469:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP467]], i16 [[TMP468]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP470:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP471:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP472:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP470]], i16 [[TMP471]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP473:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP474:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP475:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP473]], i16 [[TMP474]] acquire acquire, align 2
+// CHECK-NEXT: [[TMP455:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP454]], ptr [[SX_ATOMIC_EXPECTED_PTR573]], align 2
+// CHECK-NEXT: store i16 [[TMP455]], ptr [[SX_ATOMIC_DESIRED_PTR574]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED576:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR573]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED577:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR574]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR578:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED576]], i16 [[SX_CMPXCHG_DESIRED577]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV579:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR578]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV579]], ptr [[SX_ATOMIC_EXPECTED_PTR575]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS580:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR578]], 1
+// CHECK-NEXT: [[TMP456:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP457:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP456]] monotonic, align 2
+// CHECK-NEXT: [[TMP458:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP459:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP458]] monotonic, align 2
+// CHECK-NEXT: [[TMP460:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP461:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP460]] monotonic, align 2
+// CHECK-NEXT: [[TMP462:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP463:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP462]] monotonic, align 2
+// CHECK-NEXT: [[TMP464:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP465:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP464]] monotonic, align 2
+// CHECK-NEXT: [[TMP466:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP467:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP466]] monotonic, align 2
+// CHECK-NEXT: [[TMP468:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP469:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP468]] monotonic, align 2
+// CHECK-NEXT: [[TMP470:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP471:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP470]] monotonic, align 2
+// CHECK-NEXT: [[TMP472:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP473:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP472]], ptr [[USX_ATOMIC_EXPECTED_PTR581]], align 2
+// CHECK-NEXT: store i16 [[TMP473]], ptr [[USX_ATOMIC_DESIRED_PTR582]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED584:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR581]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED585:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR582]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR586:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED584]], i16 [[USX_CMPXCHG_DESIRED585]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV587:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR586]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV587]], ptr [[USX_ATOMIC_EXPECTED_PTR583]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS588:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR586]], 1
+// CHECK-NEXT: [[TMP474:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP475:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP474]], ptr [[USX_ATOMIC_EXPECTED_PTR589]], align 2
+// CHECK-NEXT: store i16 [[TMP475]], ptr [[USX_ATOMIC_DESIRED_PTR590]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED592:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR589]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED593:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR590]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR594:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED592]], i16 [[USX_CMPXCHG_DESIRED593]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV595:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR594]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV595]], ptr [[USX_ATOMIC_EXPECTED_PTR591]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS596:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR594]], 1
// CHECK-NEXT: [[TMP476:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP477:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP476]] acquire, align 2
+// CHECK-NEXT: [[TMP477:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP476]], ptr [[USX_ATOMIC_EXPECTED_PTR597]], align 2
+// CHECK-NEXT: store i16 [[TMP477]], ptr [[USX_ATOMIC_DESIRED_PTR598]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED600:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR597]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED601:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR598]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR602:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED600]], i16 [[USX_CMPXCHG_DESIRED601]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV603:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR602]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV603]], ptr [[USX_ATOMIC_EXPECTED_PTR599]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS604:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR602]], 1
// CHECK-NEXT: [[TMP478:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP479:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP478]] acquire, align 2
-// CHECK-NEXT: [[TMP480:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP481:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP480]] acquire, align 2
-// CHECK-NEXT: [[TMP482:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP483:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP482]] acquire, align 2
-// CHECK-NEXT: [[TMP484:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP485:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP484]] acquire, align 2
-// CHECK-NEXT: [[TMP486:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP487:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP486]] acquire, align 2
-// CHECK-NEXT: [[TMP488:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP489:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP488]] acquire, align 2
-// CHECK-NEXT: [[TMP490:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP491:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP490]] acquire, align 2
-// CHECK-NEXT: [[TMP492:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP493:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP494:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP492]], i16 [[TMP493]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP495:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP496:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP497:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP495]], i16 [[TMP496]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP498:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP499:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP500:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP498]], i16 [[TMP499]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP501:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP502:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP503:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP501]], i16 [[TMP502]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP504:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP505:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP504]] monotonic, align 2
-// CHECK-NEXT: [[TMP506:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP507:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP506]] monotonic, align 2
-// CHECK-NEXT: [[TMP508:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP509:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP508]] monotonic, align 2
-// CHECK-NEXT: [[TMP510:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP511:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP510]] monotonic, align 2
-// CHECK-NEXT: [[TMP512:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP513:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP512]] monotonic, align 2
-// CHECK-NEXT: [[TMP514:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP515:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP514]] monotonic, align 2
-// CHECK-NEXT: [[TMP516:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP517:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP516]] monotonic, align 2
-// CHECK-NEXT: [[TMP518:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP519:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP518]] monotonic, align 2
-// CHECK-NEXT: [[TMP520:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP521:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP522:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP520]], i16 [[TMP521]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP523:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP524:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP525:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP523]], i16 [[TMP524]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP526:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP527:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP528:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP526]], i16 [[TMP527]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP529:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP530:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP531:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP529]], i16 [[TMP530]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP532:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP533:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP532]] monotonic, align 2
-// CHECK-NEXT: [[TMP534:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP535:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP534]] monotonic, align 2
-// CHECK-NEXT: [[TMP536:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP537:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP536]] monotonic, align 2
-// CHECK-NEXT: [[TMP538:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP539:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP538]] monotonic, align 2
-// CHECK-NEXT: [[TMP540:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP541:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP540]] monotonic, align 2
-// CHECK-NEXT: [[TMP542:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP543:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP542]] monotonic, align 2
-// CHECK-NEXT: [[TMP544:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP545:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP544]] monotonic, align 2
-// CHECK-NEXT: [[TMP546:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP547:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP546]] monotonic, align 2
-// CHECK-NEXT: [[TMP548:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP549:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP550:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP548]], i16 [[TMP549]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP551:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP552:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP553:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP551]], i16 [[TMP552]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP554:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP555:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP556:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP554]], i16 [[TMP555]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP557:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP558:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP559:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP557]], i16 [[TMP558]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP560:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP561:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP560]] release, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP562:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP563:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP562]] release, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP564:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP565:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP564]] release, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP566:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP567:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP566]] release, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP568:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP569:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP568]] release, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP570:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP571:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP570]] release, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP572:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP573:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP572]] release, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP574:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP575:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP574]] release, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP576:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP577:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP578:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP576]], i16 [[TMP577]] release monotonic, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP579:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP580:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP581:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP579]], i16 [[TMP580]] release monotonic, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP582:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP583:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP584:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP582]], i16 [[TMP583]] release monotonic, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP585:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP586:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP587:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP585]], i16 [[TMP586]] release monotonic, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP588:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP589:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP588]] release, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP590:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP591:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP590]] release, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP592:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP593:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP592]] release, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP594:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP595:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP594]] release, align 2
+// CHECK-NEXT: [[TMP479:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP478]], ptr [[USX_ATOMIC_EXPECTED_PTR605]], align 2
+// CHECK-NEXT: store i16 [[TMP479]], ptr [[USX_ATOMIC_DESIRED_PTR606]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED608:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR605]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED609:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR606]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR610:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED608]], i16 [[USX_CMPXCHG_DESIRED609]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV611:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR610]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV611]], ptr [[USX_ATOMIC_EXPECTED_PTR607]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS612:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR610]], 1
+// CHECK-NEXT: [[TMP480:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP481:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP480]] release, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP482:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP483:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP482]] release, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP484:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP485:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP484]] release, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP486:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP487:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP486]] release, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP488:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP489:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP488]] release, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP490:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP491:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP490]] release, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP492:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP493:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP492]] release, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP494:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP495:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP494]] release, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP496:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP497:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP496]], ptr [[SX_ATOMIC_EXPECTED_PTR613]], align 2
+// CHECK-NEXT: store i16 [[TMP497]], ptr [[SX_ATOMIC_DESIRED_PTR614]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED616:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR613]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED617:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR614]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR618:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED616]], i16 [[SX_CMPXCHG_DESIRED617]] release monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV619:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR618]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV619]], ptr [[SX_ATOMIC_EXPECTED_PTR615]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS620:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR618]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP498:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP499:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP498]], ptr [[SX_ATOMIC_EXPECTED_PTR621]], align 2
+// CHECK-NEXT: store i16 [[TMP499]], ptr [[SX_ATOMIC_DESIRED_PTR622]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED624:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR621]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED625:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR622]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR626:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED624]], i16 [[SX_CMPXCHG_DESIRED625]] release monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV627:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR626]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV627]], ptr [[SX_ATOMIC_EXPECTED_PTR623]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS628:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR626]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP500:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP501:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP500]], ptr [[SX_ATOMIC_EXPECTED_PTR629]], align 2
+// CHECK-NEXT: store i16 [[TMP501]], ptr [[SX_ATOMIC_DESIRED_PTR630]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED632:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR629]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED633:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR630]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR634:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED632]], i16 [[SX_CMPXCHG_DESIRED633]] release monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV635:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR634]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV635]], ptr [[SX_ATOMIC_EXPECTED_PTR631]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS636:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR634]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP502:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP503:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP502]], ptr [[SX_ATOMIC_EXPECTED_PTR637]], align 2
+// CHECK-NEXT: store i16 [[TMP503]], ptr [[SX_ATOMIC_DESIRED_PTR638]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED640:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR637]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED641:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR638]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR642:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED640]], i16 [[SX_CMPXCHG_DESIRED641]] release monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV643:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR642]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV643]], ptr [[SX_ATOMIC_EXPECTED_PTR639]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS644:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR642]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP504:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP505:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP504]] release, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP506:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP507:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP506]] release, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP508:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP509:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP508]] release, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP510:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP511:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP510]] release, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP512:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP513:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP512]] release, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP514:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP515:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP514]] release, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP516:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP517:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP516]] release, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP518:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP519:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP518]] release, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP520:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP521:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP520]], ptr [[USX_ATOMIC_EXPECTED_PTR645]], align 2
+// CHECK-NEXT: store i16 [[TMP521]], ptr [[USX_ATOMIC_DESIRED_PTR646]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED648:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR645]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED649:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR646]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR650:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED648]], i16 [[USX_CMPXCHG_DESIRED649]] release monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV651:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR650]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV651]], ptr [[USX_ATOMIC_EXPECTED_PTR647]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS652:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR650]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP522:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP523:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP522]], ptr [[USX_ATOMIC_EXPECTED_PTR653]], align 2
+// CHECK-NEXT: store i16 [[TMP523]], ptr [[USX_ATOMIC_DESIRED_PTR654]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED656:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR653]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED657:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR654]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR658:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED656]], i16 [[USX_CMPXCHG_DESIRED657]] release monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV659:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR658]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV659]], ptr [[USX_ATOMIC_EXPECTED_PTR655]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS660:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR658]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP524:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP525:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP524]], ptr [[USX_ATOMIC_EXPECTED_PTR661]], align 2
+// CHECK-NEXT: store i16 [[TMP525]], ptr [[USX_ATOMIC_DESIRED_PTR662]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED664:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR661]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED665:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR662]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR666:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED664]], i16 [[USX_CMPXCHG_DESIRED665]] release monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV667:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR666]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV667]], ptr [[USX_ATOMIC_EXPECTED_PTR663]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS668:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR666]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP526:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP527:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP526]], ptr [[USX_ATOMIC_EXPECTED_PTR669]], align 2
+// CHECK-NEXT: store i16 [[TMP527]], ptr [[USX_ATOMIC_DESIRED_PTR670]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED672:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR669]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED673:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR670]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR674:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED672]], i16 [[USX_CMPXCHG_DESIRED673]] release monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV675:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR674]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV675]], ptr [[USX_ATOMIC_EXPECTED_PTR671]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS676:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR674]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP528:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP529:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP528]] seq_cst, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP530:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP531:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP530]] seq_cst, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP532:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP533:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP532]] seq_cst, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP534:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP535:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP534]] seq_cst, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP536:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP537:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP536]] seq_cst, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP538:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP539:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP538]] seq_cst, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP540:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP541:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP540]] seq_cst, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP542:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP543:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP542]] seq_cst, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP544:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP545:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP544]], ptr [[SX_ATOMIC_EXPECTED_PTR677]], align 2
+// CHECK-NEXT: store i16 [[TMP545]], ptr [[SX_ATOMIC_DESIRED_PTR678]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED680:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR677]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED681:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR678]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR682:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED680]], i16 [[SX_CMPXCHG_DESIRED681]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV683:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR682]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV683]], ptr [[SX_ATOMIC_EXPECTED_PTR679]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS684:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR682]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP546:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP547:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP546]], ptr [[SX_ATOMIC_EXPECTED_PTR685]], align 2
+// CHECK-NEXT: store i16 [[TMP547]], ptr [[SX_ATOMIC_DESIRED_PTR686]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED688:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR685]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED689:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR686]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR690:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED688]], i16 [[SX_CMPXCHG_DESIRED689]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV691:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR690]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV691]], ptr [[SX_ATOMIC_EXPECTED_PTR687]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS692:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR690]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP548:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP549:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP548]], ptr [[SX_ATOMIC_EXPECTED_PTR693]], align 2
+// CHECK-NEXT: store i16 [[TMP549]], ptr [[SX_ATOMIC_DESIRED_PTR694]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED696:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR693]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED697:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR694]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR698:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED696]], i16 [[SX_CMPXCHG_DESIRED697]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV699:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR698]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV699]], ptr [[SX_ATOMIC_EXPECTED_PTR695]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS700:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR698]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP550:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP551:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP550]], ptr [[SX_ATOMIC_EXPECTED_PTR701]], align 2
+// CHECK-NEXT: store i16 [[TMP551]], ptr [[SX_ATOMIC_DESIRED_PTR702]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED704:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR701]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED705:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR702]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR706:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED704]], i16 [[SX_CMPXCHG_DESIRED705]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV707:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR706]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV707]], ptr [[SX_ATOMIC_EXPECTED_PTR703]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS708:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR706]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP552:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP553:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP552]] seq_cst, align 2
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP596:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP597:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP596]] release, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP598:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP599:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP598]] release, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP600:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP601:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP600]] release, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP602:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP603:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP602]] release, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP604:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP605:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP606:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP604]], i16 [[TMP605]] release monotonic, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP607:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP608:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP609:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP607]], i16 [[TMP608]] release monotonic, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP610:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP611:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP612:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP610]], i16 [[TMP611]] release monotonic, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP613:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP614:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP615:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP613]], i16 [[TMP614]] release monotonic, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP616:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP617:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP616]] seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP618:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP619:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP618]] seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP620:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP621:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP620]] seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP622:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP623:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP622]] seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP624:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP625:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP624]] seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP626:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP627:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP626]] seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP628:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP629:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP628]] seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP630:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP631:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP630]] seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP632:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP633:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP634:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP632]], i16 [[TMP633]] seq_cst seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP635:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP636:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP637:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP635]], i16 [[TMP636]] seq_cst seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP638:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP639:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP640:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP638]], i16 [[TMP639]] seq_cst seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP641:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP642:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP643:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP641]], i16 [[TMP642]] seq_cst seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP644:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP645:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP644]] seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP646:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP647:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP646]] seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP648:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP649:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP648]] seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP650:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP651:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP650]] seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP652:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP653:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP652]] seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP654:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP655:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP654]] seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP656:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP657:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP656]] seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP658:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP659:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP658]] seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP660:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP661:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP662:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP660]], i16 [[TMP661]] seq_cst seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP663:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP664:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP665:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP663]], i16 [[TMP664]] seq_cst seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP666:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP667:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP668:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP666]], i16 [[TMP667]] seq_cst seq_cst, align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP669:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP670:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP671:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP669]], i16 [[TMP670]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[TMP554:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP555:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP554]] seq_cst, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP556:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP557:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP556]] seq_cst, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP558:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP559:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP558]] seq_cst, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP560:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP561:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP560]] seq_cst, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP562:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP563:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP562]] seq_cst, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP564:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP565:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP564]] seq_cst, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP566:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP567:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP566]] seq_cst, align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP568:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP569:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP568]], ptr [[USX_ATOMIC_EXPECTED_PTR709]], align 2
+// CHECK-NEXT: store i16 [[TMP569]], ptr [[USX_ATOMIC_DESIRED_PTR710]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED712:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR709]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED713:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR710]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR714:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED712]], i16 [[USX_CMPXCHG_DESIRED713]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV715:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR714]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV715]], ptr [[USX_ATOMIC_EXPECTED_PTR711]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS716:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR714]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP570:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP571:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP570]], ptr [[USX_ATOMIC_EXPECTED_PTR717]], align 2
+// CHECK-NEXT: store i16 [[TMP571]], ptr [[USX_ATOMIC_DESIRED_PTR718]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED720:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR717]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED721:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR718]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR722:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED720]], i16 [[USX_CMPXCHG_DESIRED721]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV723:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR722]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV723]], ptr [[USX_ATOMIC_EXPECTED_PTR719]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS724:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR722]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP572:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP573:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP572]], ptr [[USX_ATOMIC_EXPECTED_PTR725]], align 2
+// CHECK-NEXT: store i16 [[TMP573]], ptr [[USX_ATOMIC_DESIRED_PTR726]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED728:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR725]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED729:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR726]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR730:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED728]], i16 [[USX_CMPXCHG_DESIRED729]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV731:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR730]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV731]], ptr [[USX_ATOMIC_EXPECTED_PTR727]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS732:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR730]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP574:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP575:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP574]], ptr [[USX_ATOMIC_EXPECTED_PTR733]], align 2
+// CHECK-NEXT: store i16 [[TMP575]], ptr [[USX_ATOMIC_DESIRED_PTR734]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED736:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR733]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED737:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR734]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR738:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED736]], i16 [[USX_CMPXCHG_DESIRED737]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV739:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR738]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV739]], ptr [[USX_ATOMIC_EXPECTED_PTR735]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS740:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR738]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP576:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP577:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP576]] monotonic, align 4
+// CHECK-NEXT: [[TMP578:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP579:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP578]] monotonic, align 4
+// CHECK-NEXT: [[TMP580:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP581:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP580]] monotonic, align 4
+// CHECK-NEXT: [[TMP582:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP583:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP582]] monotonic, align 4
+// CHECK-NEXT: [[TMP584:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP585:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP584]] monotonic, align 4
+// CHECK-NEXT: [[TMP586:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP587:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP586]] monotonic, align 4
+// CHECK-NEXT: [[TMP588:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP589:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP588]] monotonic, align 4
+// CHECK-NEXT: [[TMP590:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP591:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP590]] monotonic, align 4
+// CHECK-NEXT: [[TMP592:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP593:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP592]], ptr [[IX_ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: store i32 [[TMP593]], ptr [[IX_ATOMIC_DESIRED_PTR]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED]], i32 [[IX_CMPXCHG_DESIRED]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV]], ptr [[IX_ATOMIC_EXPECTED_PTR741]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[TMP594:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP595:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP594]], ptr [[IX_ATOMIC_EXPECTED_PTR742]], align 4
+// CHECK-NEXT: store i32 [[TMP595]], ptr [[IX_ATOMIC_DESIRED_PTR743]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED745:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR742]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED746:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR743]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR747:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED745]], i32 [[IX_CMPXCHG_DESIRED746]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV748:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR747]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV748]], ptr [[IX_ATOMIC_EXPECTED_PTR744]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS749:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR747]], 1
+// CHECK-NEXT: [[TMP596:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP597:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP596]], ptr [[IX_ATOMIC_EXPECTED_PTR750]], align 4
+// CHECK-NEXT: store i32 [[TMP597]], ptr [[IX_ATOMIC_DESIRED_PTR751]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED753:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR750]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED754:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR751]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR755:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED753]], i32 [[IX_CMPXCHG_DESIRED754]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV756:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR755]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV756]], ptr [[IX_ATOMIC_EXPECTED_PTR752]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS757:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR755]], 1
+// CHECK-NEXT: [[TMP598:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP599:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP598]], ptr [[IX_ATOMIC_EXPECTED_PTR758]], align 4
+// CHECK-NEXT: store i32 [[TMP599]], ptr [[IX_ATOMIC_DESIRED_PTR759]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED761:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR758]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED762:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR759]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR763:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED761]], i32 [[IX_CMPXCHG_DESIRED762]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV764:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR763]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV764]], ptr [[IX_ATOMIC_EXPECTED_PTR760]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS765:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR763]], 1
+// CHECK-NEXT: [[TMP600:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP601:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP600]] monotonic, align 4
+// CHECK-NEXT: [[TMP602:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP603:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP602]] monotonic, align 4
+// CHECK-NEXT: [[TMP604:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP605:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP604]] monotonic, align 4
+// CHECK-NEXT: [[TMP606:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP607:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP606]] monotonic, align 4
+// CHECK-NEXT: [[TMP608:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP609:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP608]] monotonic, align 4
+// CHECK-NEXT: [[TMP610:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP611:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP610]] monotonic, align 4
+// CHECK-NEXT: [[TMP612:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP613:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP612]] monotonic, align 4
+// CHECK-NEXT: [[TMP614:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP615:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP614]] monotonic, align 4
+// CHECK-NEXT: [[TMP616:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP617:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP616]], ptr [[UIX_ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: store i32 [[TMP617]], ptr [[UIX_ATOMIC_DESIRED_PTR]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED]], i32 [[UIX_CMPXCHG_DESIRED]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV]], ptr [[UIX_ATOMIC_EXPECTED_PTR766]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[TMP618:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP619:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP618]], ptr [[UIX_ATOMIC_EXPECTED_PTR767]], align 4
+// CHECK-NEXT: store i32 [[TMP619]], ptr [[UIX_ATOMIC_DESIRED_PTR768]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED770:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR767]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED771:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR768]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR772:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED770]], i32 [[UIX_CMPXCHG_DESIRED771]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV773:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR772]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV773]], ptr [[UIX_ATOMIC_EXPECTED_PTR769]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS774:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR772]], 1
+// CHECK-NEXT: [[TMP620:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP621:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP620]], ptr [[UIX_ATOMIC_EXPECTED_PTR775]], align 4
+// CHECK-NEXT: store i32 [[TMP621]], ptr [[UIX_ATOMIC_DESIRED_PTR776]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED778:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR775]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED779:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR776]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR780:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED778]], i32 [[UIX_CMPXCHG_DESIRED779]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV781:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR780]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV781]], ptr [[UIX_ATOMIC_EXPECTED_PTR777]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS782:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR780]], 1
+// CHECK-NEXT: [[TMP622:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP623:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP622]], ptr [[UIX_ATOMIC_EXPECTED_PTR783]], align 4
+// CHECK-NEXT: store i32 [[TMP623]], ptr [[UIX_ATOMIC_DESIRED_PTR784]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED786:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR783]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED787:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR784]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR788:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED786]], i32 [[UIX_CMPXCHG_DESIRED787]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV789:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR788]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV789]], ptr [[UIX_ATOMIC_EXPECTED_PTR785]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS790:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR788]], 1
+// CHECK-NEXT: [[TMP624:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP625:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP624]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP626:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP627:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP626]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP628:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP629:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP628]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP630:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP631:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP630]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP632:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP633:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP632]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP634:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP635:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP634]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP636:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP637:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP636]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP638:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP639:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP638]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP640:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP641:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP640]], ptr [[IX_ATOMIC_EXPECTED_PTR791]], align 4
+// CHECK-NEXT: store i32 [[TMP641]], ptr [[IX_ATOMIC_DESIRED_PTR792]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED794:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR791]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED795:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR792]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR796:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED794]], i32 [[IX_CMPXCHG_DESIRED795]] acq_rel acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV797:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR796]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV797]], ptr [[IX_ATOMIC_EXPECTED_PTR793]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS798:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR796]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP642:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP643:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP642]], ptr [[IX_ATOMIC_EXPECTED_PTR799]], align 4
+// CHECK-NEXT: store i32 [[TMP643]], ptr [[IX_ATOMIC_DESIRED_PTR800]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED802:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR799]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED803:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR800]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR804:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED802]], i32 [[IX_CMPXCHG_DESIRED803]] acq_rel acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV805:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR804]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV805]], ptr [[IX_ATOMIC_EXPECTED_PTR801]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS806:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR804]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP644:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP645:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP644]], ptr [[IX_ATOMIC_EXPECTED_PTR807]], align 4
+// CHECK-NEXT: store i32 [[TMP645]], ptr [[IX_ATOMIC_DESIRED_PTR808]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED810:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR807]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED811:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR808]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR812:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED810]], i32 [[IX_CMPXCHG_DESIRED811]] acq_rel acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV813:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR812]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV813]], ptr [[IX_ATOMIC_EXPECTED_PTR809]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS814:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR812]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP646:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP647:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP646]], ptr [[IX_ATOMIC_EXPECTED_PTR815]], align 4
+// CHECK-NEXT: store i32 [[TMP647]], ptr [[IX_ATOMIC_DESIRED_PTR816]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED818:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR815]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED819:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR816]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR820:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED818]], i32 [[IX_CMPXCHG_DESIRED819]] acq_rel acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV821:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR820]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV821]], ptr [[IX_ATOMIC_EXPECTED_PTR817]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS822:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR820]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP648:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP649:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP648]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP650:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP651:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP650]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP652:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP653:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP652]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP654:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP655:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP654]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP656:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP657:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP656]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP658:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP659:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP658]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP660:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP661:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP660]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP662:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP663:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP662]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP664:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP665:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP664]], ptr [[UIX_ATOMIC_EXPECTED_PTR823]], align 4
+// CHECK-NEXT: store i32 [[TMP665]], ptr [[UIX_ATOMIC_DESIRED_PTR824]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED826:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR823]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED827:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR824]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR828:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED826]], i32 [[UIX_CMPXCHG_DESIRED827]] acq_rel acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV829:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR828]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV829]], ptr [[UIX_ATOMIC_EXPECTED_PTR825]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS830:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR828]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP666:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP667:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP666]], ptr [[UIX_ATOMIC_EXPECTED_PTR831]], align 4
+// CHECK-NEXT: store i32 [[TMP667]], ptr [[UIX_ATOMIC_DESIRED_PTR832]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED834:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR831]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED835:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR832]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR836:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED834]], i32 [[UIX_CMPXCHG_DESIRED835]] acq_rel acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV837:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR836]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV837]], ptr [[UIX_ATOMIC_EXPECTED_PTR833]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS838:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR836]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP668:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP669:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP668]], ptr [[UIX_ATOMIC_EXPECTED_PTR839]], align 4
+// CHECK-NEXT: store i32 [[TMP669]], ptr [[UIX_ATOMIC_DESIRED_PTR840]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED842:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR839]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED843:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR840]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR844:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED842]], i32 [[UIX_CMPXCHG_DESIRED843]] acq_rel acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV845:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR844]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV845]], ptr [[UIX_ATOMIC_EXPECTED_PTR841]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS846:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR844]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP670:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP671:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP670]], ptr [[UIX_ATOMIC_EXPECTED_PTR847]], align 4
+// CHECK-NEXT: store i32 [[TMP671]], ptr [[UIX_ATOMIC_DESIRED_PTR848]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED850:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR847]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED851:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR848]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR852:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED850]], i32 [[UIX_CMPXCHG_DESIRED851]] acq_rel acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV853:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR852]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV853]], ptr [[UIX_ATOMIC_EXPECTED_PTR849]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS854:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR852]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP672:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP673:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP672]] monotonic, align 4
+// CHECK-NEXT: [[TMP673:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP672]] acquire, align 4
// CHECK-NEXT: [[TMP674:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP675:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP674]] monotonic, align 4
+// CHECK-NEXT: [[TMP675:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP674]] acquire, align 4
// CHECK-NEXT: [[TMP676:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP677:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP676]] monotonic, align 4
+// CHECK-NEXT: [[TMP677:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP676]] acquire, align 4
// CHECK-NEXT: [[TMP678:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP679:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP678]] monotonic, align 4
+// CHECK-NEXT: [[TMP679:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP678]] acquire, align 4
// CHECK-NEXT: [[TMP680:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP681:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP680]] monotonic, align 4
+// CHECK-NEXT: [[TMP681:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP680]] acquire, align 4
// CHECK-NEXT: [[TMP682:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP683:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP682]] monotonic, align 4
+// CHECK-NEXT: [[TMP683:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP682]] acquire, align 4
// CHECK-NEXT: [[TMP684:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP685:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP684]] monotonic, align 4
+// CHECK-NEXT: [[TMP685:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP684]] acquire, align 4
// CHECK-NEXT: [[TMP686:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP687:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP686]] monotonic, align 4
+// CHECK-NEXT: [[TMP687:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP686]] acquire, align 4
// CHECK-NEXT: [[TMP688:%.*]] = load i32, ptr [[IE]], align 4
// CHECK-NEXT: [[TMP689:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP690:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP688]], i32 [[TMP689]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP691:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP692:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP693:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP691]], i32 [[TMP692]] monotonic monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP688]], ptr [[IX_ATOMIC_EXPECTED_PTR855]], align 4
+// CHECK-NEXT: store i32 [[TMP689]], ptr [[IX_ATOMIC_DESIRED_PTR856]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED858:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR855]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED859:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR856]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR860:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED858]], i32 [[IX_CMPXCHG_DESIRED859]] acquire acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV861:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR860]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV861]], ptr [[IX_ATOMIC_EXPECTED_PTR857]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS862:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR860]], 1
+// CHECK-NEXT: [[TMP690:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP691:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP690]], ptr [[IX_ATOMIC_EXPECTED_PTR863]], align 4
+// CHECK-NEXT: store i32 [[TMP691]], ptr [[IX_ATOMIC_DESIRED_PTR864]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED866:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR863]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED867:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR864]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR868:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED866]], i32 [[IX_CMPXCHG_DESIRED867]] acquire acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV869:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR868]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV869]], ptr [[IX_ATOMIC_EXPECTED_PTR865]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS870:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR868]], 1
+// CHECK-NEXT: [[TMP692:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP693:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP692]], ptr [[IX_ATOMIC_EXPECTED_PTR871]], align 4
+// CHECK-NEXT: store i32 [[TMP693]], ptr [[IX_ATOMIC_DESIRED_PTR872]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED874:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR871]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED875:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR872]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR876:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED874]], i32 [[IX_CMPXCHG_DESIRED875]] acquire acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV877:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR876]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV877]], ptr [[IX_ATOMIC_EXPECTED_PTR873]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS878:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR876]], 1
// CHECK-NEXT: [[TMP694:%.*]] = load i32, ptr [[IE]], align 4
// CHECK-NEXT: [[TMP695:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP696:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP694]], i32 [[TMP695]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP697:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP698:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP699:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP697]], i32 [[TMP698]] monotonic monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP694]], ptr [[IX_ATOMIC_EXPECTED_PTR879]], align 4
+// CHECK-NEXT: store i32 [[TMP695]], ptr [[IX_ATOMIC_DESIRED_PTR880]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED882:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR879]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED883:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR880]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR884:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED882]], i32 [[IX_CMPXCHG_DESIRED883]] acquire acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV885:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR884]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV885]], ptr [[IX_ATOMIC_EXPECTED_PTR881]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS886:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR884]], 1
+// CHECK-NEXT: [[TMP696:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP697:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP696]] acquire, align 4
+// CHECK-NEXT: [[TMP698:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP699:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP698]] acquire, align 4
// CHECK-NEXT: [[TMP700:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP701:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP700]] monotonic, align 4
+// CHECK-NEXT: [[TMP701:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP700]] acquire, align 4
// CHECK-NEXT: [[TMP702:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP703:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP702]] monotonic, align 4
+// CHECK-NEXT: [[TMP703:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP702]] acquire, align 4
// CHECK-NEXT: [[TMP704:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP705:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP704]] monotonic, align 4
+// CHECK-NEXT: [[TMP705:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP704]] acquire, align 4
// CHECK-NEXT: [[TMP706:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP707:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP706]] monotonic, align 4
+// CHECK-NEXT: [[TMP707:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP706]] acquire, align 4
// CHECK-NEXT: [[TMP708:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP709:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP708]] monotonic, align 4
+// CHECK-NEXT: [[TMP709:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP708]] acquire, align 4
// CHECK-NEXT: [[TMP710:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP711:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP710]] monotonic, align 4
+// CHECK-NEXT: [[TMP711:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP710]] acquire, align 4
// CHECK-NEXT: [[TMP712:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP713:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP712]] monotonic, align 4
+// CHECK-NEXT: [[TMP713:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP712]], ptr [[UIX_ATOMIC_EXPECTED_PTR887]], align 4
+// CHECK-NEXT: store i32 [[TMP713]], ptr [[UIX_ATOMIC_DESIRED_PTR888]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED890:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR887]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED891:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR888]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR892:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED890]], i32 [[UIX_CMPXCHG_DESIRED891]] acquire acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV893:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR892]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV893]], ptr [[UIX_ATOMIC_EXPECTED_PTR889]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS894:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR892]], 1
// CHECK-NEXT: [[TMP714:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP715:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP714]] monotonic, align 4
+// CHECK-NEXT: [[TMP715:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP714]], ptr [[UIX_ATOMIC_EXPECTED_PTR895]], align 4
+// CHECK-NEXT: store i32 [[TMP715]], ptr [[UIX_ATOMIC_DESIRED_PTR896]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED898:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR895]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED899:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR896]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR900:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED898]], i32 [[UIX_CMPXCHG_DESIRED899]] acquire acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV901:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR900]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV901]], ptr [[UIX_ATOMIC_EXPECTED_PTR897]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS902:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR900]], 1
// CHECK-NEXT: [[TMP716:%.*]] = load i32, ptr [[UIE]], align 4
// CHECK-NEXT: [[TMP717:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP718:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP716]], i32 [[TMP717]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP719:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP720:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP721:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP719]], i32 [[TMP720]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP722:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP723:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP724:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP722]], i32 [[TMP723]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP725:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP726:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP727:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP725]], i32 [[TMP726]] monotonic monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP716]], ptr [[UIX_ATOMIC_EXPECTED_PTR903]], align 4
+// CHECK-NEXT: store i32 [[TMP717]], ptr [[UIX_ATOMIC_DESIRED_PTR904]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED906:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR903]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED907:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR904]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR908:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED906]], i32 [[UIX_CMPXCHG_DESIRED907]] acquire acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV909:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR908]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV909]], ptr [[UIX_ATOMIC_EXPECTED_PTR905]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS910:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR908]], 1
+// CHECK-NEXT: [[TMP718:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP719:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP718]], ptr [[UIX_ATOMIC_EXPECTED_PTR911]], align 4
+// CHECK-NEXT: store i32 [[TMP719]], ptr [[UIX_ATOMIC_DESIRED_PTR912]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED914:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR911]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED915:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR912]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR916:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED914]], i32 [[UIX_CMPXCHG_DESIRED915]] acquire acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV917:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR916]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV917]], ptr [[UIX_ATOMIC_EXPECTED_PTR913]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS918:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR916]], 1
+// CHECK-NEXT: [[TMP720:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP721:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP720]] monotonic, align 4
+// CHECK-NEXT: [[TMP722:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP723:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP722]] monotonic, align 4
+// CHECK-NEXT: [[TMP724:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP725:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP724]] monotonic, align 4
+// CHECK-NEXT: [[TMP726:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP727:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP726]] monotonic, align 4
// CHECK-NEXT: [[TMP728:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP729:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP728]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP729:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP728]] monotonic, align 4
// CHECK-NEXT: [[TMP730:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP731:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP730]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP731:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP730]] monotonic, align 4
// CHECK-NEXT: [[TMP732:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP733:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP732]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP733:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP732]] monotonic, align 4
// CHECK-NEXT: [[TMP734:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP735:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP734]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP735:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP734]] monotonic, align 4
// CHECK-NEXT: [[TMP736:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP737:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP736]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP737:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP736]], ptr [[IX_ATOMIC_EXPECTED_PTR919]], align 4
+// CHECK-NEXT: store i32 [[TMP737]], ptr [[IX_ATOMIC_DESIRED_PTR920]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED922:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR919]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED923:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR920]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR924:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED922]], i32 [[IX_CMPXCHG_DESIRED923]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV925:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR924]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV925]], ptr [[IX_ATOMIC_EXPECTED_PTR921]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS926:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR924]], 1
// CHECK-NEXT: [[TMP738:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP739:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP738]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP739:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP738]], ptr [[IX_ATOMIC_EXPECTED_PTR927]], align 4
+// CHECK-NEXT: store i32 [[TMP739]], ptr [[IX_ATOMIC_DESIRED_PTR928]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED930:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR927]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED931:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR928]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR932:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED930]], i32 [[IX_CMPXCHG_DESIRED931]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV933:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR932]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV933]], ptr [[IX_ATOMIC_EXPECTED_PTR929]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS934:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR932]], 1
// CHECK-NEXT: [[TMP740:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP741:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP740]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP741:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP740]], ptr [[IX_ATOMIC_EXPECTED_PTR935]], align 4
+// CHECK-NEXT: store i32 [[TMP741]], ptr [[IX_ATOMIC_DESIRED_PTR936]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED938:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR935]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED939:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR936]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR940:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED938]], i32 [[IX_CMPXCHG_DESIRED939]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV941:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR940]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV941]], ptr [[IX_ATOMIC_EXPECTED_PTR937]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS942:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR940]], 1
// CHECK-NEXT: [[TMP742:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP743:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP742]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP744:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP745:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP746:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP744]], i32 [[TMP745]] acq_rel acquire, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP747:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP748:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP749:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP747]], i32 [[TMP748]] acq_rel acquire, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP750:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP751:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP752:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP750]], i32 [[TMP751]] acq_rel acquire, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP753:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP754:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP755:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP753]], i32 [[TMP754]] acq_rel acquire, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP743:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP742]], ptr [[IX_ATOMIC_EXPECTED_PTR943]], align 4
+// CHECK-NEXT: store i32 [[TMP743]], ptr [[IX_ATOMIC_DESIRED_PTR944]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED946:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR943]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED947:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR944]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR948:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED946]], i32 [[IX_CMPXCHG_DESIRED947]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV949:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR948]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV949]], ptr [[IX_ATOMIC_EXPECTED_PTR945]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS950:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR948]], 1
+// CHECK-NEXT: [[TMP744:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP745:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP744]] monotonic, align 4
+// CHECK-NEXT: [[TMP746:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP747:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP746]] monotonic, align 4
+// CHECK-NEXT: [[TMP748:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP749:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP748]] monotonic, align 4
+// CHECK-NEXT: [[TMP750:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP751:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP750]] monotonic, align 4
+// CHECK-NEXT: [[TMP752:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP753:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP752]] monotonic, align 4
+// CHECK-NEXT: [[TMP754:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP755:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP754]] monotonic, align 4
// CHECK-NEXT: [[TMP756:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP757:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP756]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP757:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP756]] monotonic, align 4
// CHECK-NEXT: [[TMP758:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP759:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP758]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP759:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP758]] monotonic, align 4
// CHECK-NEXT: [[TMP760:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP761:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP760]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP761:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP760]], ptr [[UIX_ATOMIC_EXPECTED_PTR951]], align 4
+// CHECK-NEXT: store i32 [[TMP761]], ptr [[UIX_ATOMIC_DESIRED_PTR952]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED954:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR951]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED955:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR952]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR956:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED954]], i32 [[UIX_CMPXCHG_DESIRED955]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV957:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR956]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV957]], ptr [[UIX_ATOMIC_EXPECTED_PTR953]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS958:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR956]], 1
// CHECK-NEXT: [[TMP762:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP763:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP762]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP763:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP762]], ptr [[UIX_ATOMIC_EXPECTED_PTR959]], align 4
+// CHECK-NEXT: store i32 [[TMP763]], ptr [[UIX_ATOMIC_DESIRED_PTR960]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED962:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR959]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED963:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR960]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR964:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED962]], i32 [[UIX_CMPXCHG_DESIRED963]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV965:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR964]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV965]], ptr [[UIX_ATOMIC_EXPECTED_PTR961]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS966:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR964]], 1
// CHECK-NEXT: [[TMP764:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP765:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP764]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP765:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP764]], ptr [[UIX_ATOMIC_EXPECTED_PTR967]], align 4
+// CHECK-NEXT: store i32 [[TMP765]], ptr [[UIX_ATOMIC_DESIRED_PTR968]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED970:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR967]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED971:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR968]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR972:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED970]], i32 [[UIX_CMPXCHG_DESIRED971]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV973:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR972]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV973]], ptr [[UIX_ATOMIC_EXPECTED_PTR969]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS974:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR972]], 1
// CHECK-NEXT: [[TMP766:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP767:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP766]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP768:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP769:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP768]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP770:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP771:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP770]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP772:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP773:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP774:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP772]], i32 [[TMP773]] acq_rel acquire, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP775:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP776:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP777:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP775]], i32 [[TMP776]] acq_rel acquire, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP778:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP779:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP780:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP778]], i32 [[TMP779]] acq_rel acquire, align 4
+// CHECK-NEXT: [[TMP767:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP766]], ptr [[UIX_ATOMIC_EXPECTED_PTR975]], align 4
+// CHECK-NEXT: store i32 [[TMP767]], ptr [[UIX_ATOMIC_DESIRED_PTR976]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED978:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR975]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED979:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR976]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR980:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED978]], i32 [[UIX_CMPXCHG_DESIRED979]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV981:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR980]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV981]], ptr [[UIX_ATOMIC_EXPECTED_PTR977]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS982:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR980]], 1
+// CHECK-NEXT: [[TMP768:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP769:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP768]] release, align 4
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP781:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP782:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP783:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP781]], i32 [[TMP782]] acq_rel acquire, align 4
+// CHECK-NEXT: [[TMP770:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP771:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP770]] release, align 4
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP784:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP785:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP784]] acquire, align 4
-// CHECK-NEXT: [[TMP786:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP787:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP786]] acquire, align 4
-// CHECK-NEXT: [[TMP788:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP789:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP788]] acquire, align 4
-// CHECK-NEXT: [[TMP790:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP791:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP790]] acquire, align 4
-// CHECK-NEXT: [[TMP792:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP793:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP792]] acquire, align 4
-// CHECK-NEXT: [[TMP794:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP795:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP794]] acquire, align 4
-// CHECK-NEXT: [[TMP796:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP797:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP796]] acquire, align 4
-// CHECK-NEXT: [[TMP798:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP799:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP798]] acquire, align 4
-// CHECK-NEXT: [[TMP800:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP801:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP802:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP800]], i32 [[TMP801]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP803:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP804:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP805:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP803]], i32 [[TMP804]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP806:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP807:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP808:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP806]], i32 [[TMP807]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP809:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP810:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP811:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP809]], i32 [[TMP810]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP812:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP813:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP812]] acquire, align 4
-// CHECK-NEXT: [[TMP814:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP815:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP814]] acquire, align 4
-// CHECK-NEXT: [[TMP816:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP817:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP816]] acquire, align 4
-// CHECK-NEXT: [[TMP818:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP819:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP818]] acquire, align 4
-// CHECK-NEXT: [[TMP820:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP821:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP820]] acquire, align 4
-// CHECK-NEXT: [[TMP822:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP823:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP822]] acquire, align 4
-// CHECK-NEXT: [[TMP824:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP825:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP824]] acquire, align 4
-// CHECK-NEXT: [[TMP826:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP827:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP826]] acquire, align 4
-// CHECK-NEXT: [[TMP828:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP829:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP830:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP828]], i32 [[TMP829]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP831:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP832:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP833:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP831]], i32 [[TMP832]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP834:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP835:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP836:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP834]], i32 [[TMP835]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP837:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP838:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP839:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP837]], i32 [[TMP838]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP840:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP841:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP840]] monotonic, align 4
-// CHECK-NEXT: [[TMP842:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP843:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP842]] monotonic, align 4
-// CHECK-NEXT: [[TMP844:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP845:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP844]] monotonic, align 4
-// CHECK-NEXT: [[TMP846:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP847:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP846]] monotonic, align 4
-// CHECK-NEXT: [[TMP848:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP849:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP848]] monotonic, align 4
-// CHECK-NEXT: [[TMP850:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP851:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP850]] monotonic, align 4
-// CHECK-NEXT: [[TMP852:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP853:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP852]] monotonic, align 4
-// CHECK-NEXT: [[TMP854:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP855:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP854]] monotonic, align 4
-// CHECK-NEXT: [[TMP856:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP857:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP858:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP856]], i32 [[TMP857]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP859:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP860:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP861:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP859]], i32 [[TMP860]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP862:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP863:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP864:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP862]], i32 [[TMP863]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP865:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP866:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP867:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP865]], i32 [[TMP866]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP868:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP869:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP868]] monotonic, align 4
-// CHECK-NEXT: [[TMP870:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP871:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP870]] monotonic, align 4
-// CHECK-NEXT: [[TMP872:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP873:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP872]] monotonic, align 4
-// CHECK-NEXT: [[TMP874:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP875:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP874]] monotonic, align 4
-// CHECK-NEXT: [[TMP876:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP877:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP876]] monotonic, align 4
-// CHECK-NEXT: [[TMP878:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP879:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP878]] monotonic, align 4
-// CHECK-NEXT: [[TMP880:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP881:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP880]] monotonic, align 4
-// CHECK-NEXT: [[TMP882:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP883:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP882]] monotonic, align 4
-// CHECK-NEXT: [[TMP884:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP885:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP886:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP884]], i32 [[TMP885]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP887:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP888:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP889:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP887]], i32 [[TMP888]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP890:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP891:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP892:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP890]], i32 [[TMP891]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP893:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP894:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP895:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP893]], i32 [[TMP894]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP896:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP897:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP896]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP898:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP899:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP898]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP900:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP901:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP900]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP902:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP903:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP902]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP904:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP905:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP904]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP906:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP907:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP906]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP908:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP909:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP908]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP910:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP911:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP910]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP912:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP913:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP914:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP912]], i32 [[TMP913]] release monotonic, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP915:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP916:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP917:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP915]], i32 [[TMP916]] release monotonic, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP918:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP919:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP920:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP918]], i32 [[TMP919]] release monotonic, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP921:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP922:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP923:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP921]], i32 [[TMP922]] release monotonic, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP924:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP925:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP924]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP926:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP927:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP926]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP928:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP929:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP928]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP930:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP931:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP930]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP932:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP933:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP932]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP934:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP935:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP934]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP936:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP937:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP936]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP938:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP939:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP938]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP940:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP941:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP942:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP940]], i32 [[TMP941]] release monotonic, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP943:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP944:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP945:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP943]], i32 [[TMP944]] release monotonic, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP946:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP947:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP948:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP946]], i32 [[TMP947]] release monotonic, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP949:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP950:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP951:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP949]], i32 [[TMP950]] release monotonic, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP952:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP953:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP952]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP954:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP955:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP954]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP956:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP957:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP956]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP958:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP959:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP958]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP960:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP961:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP960]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP962:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP963:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP962]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP964:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP965:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP964]] seq_cst, align 4
+// CHECK-NEXT: [[TMP772:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP773:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP772]] release, align 4
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP966:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP967:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP966]] seq_cst, align 4
+// CHECK-NEXT: [[TMP774:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP775:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP774]] release, align 4
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP968:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP969:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP970:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP968]], i32 [[TMP969]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[TMP776:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP777:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP776]] release, align 4
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP971:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP972:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP973:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP971]], i32 [[TMP972]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[TMP778:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP779:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP778]] release, align 4
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP974:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP975:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP976:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP974]], i32 [[TMP975]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[TMP780:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP781:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP780]] release, align 4
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP977:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP978:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP979:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP977]], i32 [[TMP978]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[TMP782:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP783:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP782]] release, align 4
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP980:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP981:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP980]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP982:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP983:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP982]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP984:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP985:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP984]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP986:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP987:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP986]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP988:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP989:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP988]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP990:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP991:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP990]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP992:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP993:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP992]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP994:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP995:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP994]] seq_cst, align 4
+// CHECK-NEXT: [[TMP784:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP785:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP784]], ptr [[IX_ATOMIC_EXPECTED_PTR983]], align 4
+// CHECK-NEXT: store i32 [[TMP785]], ptr [[IX_ATOMIC_DESIRED_PTR984]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED986:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR983]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED987:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR984]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR988:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED986]], i32 [[IX_CMPXCHG_DESIRED987]] release monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV989:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR988]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV989]], ptr [[IX_ATOMIC_EXPECTED_PTR985]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS990:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR988]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP996:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP997:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP998:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP996]], i32 [[TMP997]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[TMP786:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP787:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP786]], ptr [[IX_ATOMIC_EXPECTED_PTR991]], align 4
+// CHECK-NEXT: store i32 [[TMP787]], ptr [[IX_ATOMIC_DESIRED_PTR992]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED994:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR991]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED995:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR992]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR996:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED994]], i32 [[IX_CMPXCHG_DESIRED995]] release monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV997:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR996]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV997]], ptr [[IX_ATOMIC_EXPECTED_PTR993]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS998:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR996]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP999:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP1000:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP1001:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP999]], i32 [[TMP1000]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[TMP788:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP789:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP788]], ptr [[IX_ATOMIC_EXPECTED_PTR999]], align 4
+// CHECK-NEXT: store i32 [[TMP789]], ptr [[IX_ATOMIC_DESIRED_PTR1000]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED1002:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR999]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED1003:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR1000]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR1004:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED1002]], i32 [[IX_CMPXCHG_DESIRED1003]] release monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV1005:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR1004]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV1005]], ptr [[IX_ATOMIC_EXPECTED_PTR1001]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS1006:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR1004]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1002:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP1003:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP1004:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP1002]], i32 [[TMP1003]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[TMP790:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP791:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP790]], ptr [[IX_ATOMIC_EXPECTED_PTR1007]], align 4
+// CHECK-NEXT: store i32 [[TMP791]], ptr [[IX_ATOMIC_DESIRED_PTR1008]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED1010:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR1007]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED1011:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR1008]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR1012:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED1010]], i32 [[IX_CMPXCHG_DESIRED1011]] release monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV1013:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR1012]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV1013]], ptr [[IX_ATOMIC_EXPECTED_PTR1009]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS1014:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR1012]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP792:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP793:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP792]] release, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP794:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP795:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP794]] release, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP796:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP797:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP796]] release, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP798:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP799:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP798]] release, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP800:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP801:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP800]] release, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP802:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP803:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP802]] release, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP804:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP805:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP804]] release, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP806:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP807:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP806]] release, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP808:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP809:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP808]], ptr [[UIX_ATOMIC_EXPECTED_PTR1015]], align 4
+// CHECK-NEXT: store i32 [[TMP809]], ptr [[UIX_ATOMIC_DESIRED_PTR1016]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED1018:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR1015]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED1019:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR1016]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR1020:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED1018]], i32 [[UIX_CMPXCHG_DESIRED1019]] release monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV1021:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR1020]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV1021]], ptr [[UIX_ATOMIC_EXPECTED_PTR1017]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS1022:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR1020]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP810:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP811:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP810]], ptr [[UIX_ATOMIC_EXPECTED_PTR1023]], align 4
+// CHECK-NEXT: store i32 [[TMP811]], ptr [[UIX_ATOMIC_DESIRED_PTR1024]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED1026:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR1023]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED1027:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR1024]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR1028:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED1026]], i32 [[UIX_CMPXCHG_DESIRED1027]] release monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV1029:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR1028]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV1029]], ptr [[UIX_ATOMIC_EXPECTED_PTR1025]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS1030:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR1028]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1005:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP1006:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP1007:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP1005]], i32 [[TMP1006]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[TMP812:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP813:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP812]], ptr [[UIX_ATOMIC_EXPECTED_PTR1031]], align 4
+// CHECK-NEXT: store i32 [[TMP813]], ptr [[UIX_ATOMIC_DESIRED_PTR1032]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED1034:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR1031]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED1035:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR1032]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR1036:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED1034]], i32 [[UIX_CMPXCHG_DESIRED1035]] release monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV1037:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR1036]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV1037]], ptr [[UIX_ATOMIC_EXPECTED_PTR1033]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS1038:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR1036]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP814:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP815:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP814]], ptr [[UIX_ATOMIC_EXPECTED_PTR1039]], align 4
+// CHECK-NEXT: store i32 [[TMP815]], ptr [[UIX_ATOMIC_DESIRED_PTR1040]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED1042:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR1039]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED1043:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR1040]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR1044:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED1042]], i32 [[UIX_CMPXCHG_DESIRED1043]] release monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV1045:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR1044]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV1045]], ptr [[UIX_ATOMIC_EXPECTED_PTR1041]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS1046:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR1044]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP816:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP817:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP816]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP818:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP819:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP818]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP820:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP821:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP820]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP822:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP823:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP822]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP824:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP825:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP824]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP826:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP827:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP826]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP828:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP829:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP828]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP830:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP831:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP830]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP832:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP833:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP832]], ptr [[IX_ATOMIC_EXPECTED_PTR1047]], align 4
+// CHECK-NEXT: store i32 [[TMP833]], ptr [[IX_ATOMIC_DESIRED_PTR1048]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED1050:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR1047]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED1051:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR1048]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR1052:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED1050]], i32 [[IX_CMPXCHG_DESIRED1051]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV1053:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR1052]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV1053]], ptr [[IX_ATOMIC_EXPECTED_PTR1049]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS1054:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR1052]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP834:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP835:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP834]], ptr [[IX_ATOMIC_EXPECTED_PTR1055]], align 4
+// CHECK-NEXT: store i32 [[TMP835]], ptr [[IX_ATOMIC_DESIRED_PTR1056]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED1058:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR1055]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED1059:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR1056]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR1060:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED1058]], i32 [[IX_CMPXCHG_DESIRED1059]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV1061:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR1060]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV1061]], ptr [[IX_ATOMIC_EXPECTED_PTR1057]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS1062:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR1060]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP836:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP837:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP836]], ptr [[IX_ATOMIC_EXPECTED_PTR1063]], align 4
+// CHECK-NEXT: store i32 [[TMP837]], ptr [[IX_ATOMIC_DESIRED_PTR1064]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED1066:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR1063]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED1067:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR1064]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR1068:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED1066]], i32 [[IX_CMPXCHG_DESIRED1067]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV1069:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR1068]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV1069]], ptr [[IX_ATOMIC_EXPECTED_PTR1065]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS1070:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR1068]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP838:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP839:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP838]], ptr [[IX_ATOMIC_EXPECTED_PTR1071]], align 4
+// CHECK-NEXT: store i32 [[TMP839]], ptr [[IX_ATOMIC_DESIRED_PTR1072]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED1074:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR1071]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED1075:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR1072]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR1076:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED1074]], i32 [[IX_CMPXCHG_DESIRED1075]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV1077:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR1076]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV1077]], ptr [[IX_ATOMIC_EXPECTED_PTR1073]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS1078:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR1076]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP840:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP841:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP840]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP842:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP843:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP842]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP844:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP845:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP844]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP846:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP847:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP846]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP848:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP849:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP848]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP850:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP851:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP850]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP852:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP853:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP852]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP854:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP855:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP854]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP856:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP857:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP856]], ptr [[UIX_ATOMIC_EXPECTED_PTR1079]], align 4
+// CHECK-NEXT: store i32 [[TMP857]], ptr [[UIX_ATOMIC_DESIRED_PTR1080]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED1082:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR1079]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED1083:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR1080]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR1084:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED1082]], i32 [[UIX_CMPXCHG_DESIRED1083]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV1085:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR1084]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV1085]], ptr [[UIX_ATOMIC_EXPECTED_PTR1081]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS1086:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR1084]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP858:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP859:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP858]], ptr [[UIX_ATOMIC_EXPECTED_PTR1087]], align 4
+// CHECK-NEXT: store i32 [[TMP859]], ptr [[UIX_ATOMIC_DESIRED_PTR1088]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED1090:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR1087]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED1091:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR1088]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR1092:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED1090]], i32 [[UIX_CMPXCHG_DESIRED1091]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV1093:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR1092]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV1093]], ptr [[UIX_ATOMIC_EXPECTED_PTR1089]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS1094:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR1092]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP860:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP861:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP860]], ptr [[UIX_ATOMIC_EXPECTED_PTR1095]], align 4
+// CHECK-NEXT: store i32 [[TMP861]], ptr [[UIX_ATOMIC_DESIRED_PTR1096]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED1098:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR1095]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED1099:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR1096]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR1100:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED1098]], i32 [[UIX_CMPXCHG_DESIRED1099]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV1101:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR1100]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV1101]], ptr [[UIX_ATOMIC_EXPECTED_PTR1097]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS1102:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR1100]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP862:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP863:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP862]], ptr [[UIX_ATOMIC_EXPECTED_PTR1103]], align 4
+// CHECK-NEXT: store i32 [[TMP863]], ptr [[UIX_ATOMIC_DESIRED_PTR1104]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED1106:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR1103]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED1107:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR1104]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR1108:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED1106]], i32 [[UIX_CMPXCHG_DESIRED1107]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV1109:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR1108]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV1109]], ptr [[UIX_ATOMIC_EXPECTED_PTR1105]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS1110:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR1108]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP864:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP865:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP864]] monotonic, align 8
+// CHECK-NEXT: [[TMP866:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP867:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP866]] monotonic, align 8
+// CHECK-NEXT: [[TMP868:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP869:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP868]] monotonic, align 8
+// CHECK-NEXT: [[TMP870:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP871:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP870]] monotonic, align 8
+// CHECK-NEXT: [[TMP872:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP873:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP872]] monotonic, align 8
+// CHECK-NEXT: [[TMP874:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP875:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP874]] monotonic, align 8
+// CHECK-NEXT: [[TMP876:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP877:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP876]] monotonic, align 8
+// CHECK-NEXT: [[TMP878:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP879:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP878]] monotonic, align 8
+// CHECK-NEXT: [[TMP880:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP881:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP880]], ptr [[LX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: store i64 [[TMP881]], ptr [[LX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED]], i64 [[LX_CMPXCHG_DESIRED]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV]], ptr [[LX_ATOMIC_EXPECTED_PTR1111]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[TMP882:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP883:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP882]], ptr [[LX_ATOMIC_EXPECTED_PTR1112]], align 8
+// CHECK-NEXT: store i64 [[TMP883]], ptr [[LX_ATOMIC_DESIRED_PTR1113]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1115:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1112]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1116:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1113]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1117:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1115]], i64 [[LX_CMPXCHG_DESIRED1116]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1118:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1117]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1118]], ptr [[LX_ATOMIC_EXPECTED_PTR1114]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1119:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1117]], 1
+// CHECK-NEXT: [[TMP884:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP885:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP884]], ptr [[LX_ATOMIC_EXPECTED_PTR1120]], align 8
+// CHECK-NEXT: store i64 [[TMP885]], ptr [[LX_ATOMIC_DESIRED_PTR1121]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1123:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1120]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1124:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1121]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1125:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1123]], i64 [[LX_CMPXCHG_DESIRED1124]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1126:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1125]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1126]], ptr [[LX_ATOMIC_EXPECTED_PTR1122]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1127:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1125]], 1
+// CHECK-NEXT: [[TMP886:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP887:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP886]], ptr [[LX_ATOMIC_EXPECTED_PTR1128]], align 8
+// CHECK-NEXT: store i64 [[TMP887]], ptr [[LX_ATOMIC_DESIRED_PTR1129]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1131:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1128]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1132:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1129]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1133:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1131]], i64 [[LX_CMPXCHG_DESIRED1132]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1134:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1133]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1134]], ptr [[LX_ATOMIC_EXPECTED_PTR1130]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1135:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1133]], 1
+// CHECK-NEXT: [[TMP888:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP889:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP888]] monotonic, align 8
+// CHECK-NEXT: [[TMP890:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP891:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP890]] monotonic, align 8
+// CHECK-NEXT: [[TMP892:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP893:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP892]] monotonic, align 8
+// CHECK-NEXT: [[TMP894:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP895:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP894]] monotonic, align 8
+// CHECK-NEXT: [[TMP896:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP897:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP896]] monotonic, align 8
+// CHECK-NEXT: [[TMP898:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP899:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP898]] monotonic, align 8
+// CHECK-NEXT: [[TMP900:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP901:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP900]] monotonic, align 8
+// CHECK-NEXT: [[TMP902:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP903:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP902]] monotonic, align 8
+// CHECK-NEXT: [[TMP904:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP905:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP904]], ptr [[ULX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: store i64 [[TMP905]], ptr [[ULX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED]], i64 [[ULX_CMPXCHG_DESIRED]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV]], ptr [[ULX_ATOMIC_EXPECTED_PTR1136]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[TMP906:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP907:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP906]], ptr [[ULX_ATOMIC_EXPECTED_PTR1137]], align 8
+// CHECK-NEXT: store i64 [[TMP907]], ptr [[ULX_ATOMIC_DESIRED_PTR1138]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1140:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1137]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1141:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1138]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1142:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1140]], i64 [[ULX_CMPXCHG_DESIRED1141]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1143:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1142]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1143]], ptr [[ULX_ATOMIC_EXPECTED_PTR1139]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1144:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1142]], 1
+// CHECK-NEXT: [[TMP908:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP909:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP908]], ptr [[ULX_ATOMIC_EXPECTED_PTR1145]], align 8
+// CHECK-NEXT: store i64 [[TMP909]], ptr [[ULX_ATOMIC_DESIRED_PTR1146]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1148:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1145]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1149:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1146]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1150:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1148]], i64 [[ULX_CMPXCHG_DESIRED1149]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1151:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1150]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1151]], ptr [[ULX_ATOMIC_EXPECTED_PTR1147]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1152:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1150]], 1
+// CHECK-NEXT: [[TMP910:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP911:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP910]], ptr [[ULX_ATOMIC_EXPECTED_PTR1153]], align 8
+// CHECK-NEXT: store i64 [[TMP911]], ptr [[ULX_ATOMIC_DESIRED_PTR1154]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1156:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1153]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1157:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1154]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1158:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1156]], i64 [[ULX_CMPXCHG_DESIRED1157]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1159:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1158]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1159]], ptr [[ULX_ATOMIC_EXPECTED_PTR1155]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1160:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1158]], 1
+// CHECK-NEXT: [[TMP912:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP913:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP912]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP914:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP915:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP914]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP916:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP917:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP916]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP918:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP919:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP918]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP920:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP921:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP920]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP922:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP923:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP922]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP924:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP925:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP924]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP926:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP927:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP926]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP928:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP929:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP928]], ptr [[LX_ATOMIC_EXPECTED_PTR1161]], align 8
+// CHECK-NEXT: store i64 [[TMP929]], ptr [[LX_ATOMIC_DESIRED_PTR1162]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1164:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1161]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1165:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1162]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1166:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1164]], i64 [[LX_CMPXCHG_DESIRED1165]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1167:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1166]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1167]], ptr [[LX_ATOMIC_EXPECTED_PTR1163]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1168:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1166]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP930:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP931:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP930]], ptr [[LX_ATOMIC_EXPECTED_PTR1169]], align 8
+// CHECK-NEXT: store i64 [[TMP931]], ptr [[LX_ATOMIC_DESIRED_PTR1170]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1172:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1169]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1173:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1170]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1174:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1172]], i64 [[LX_CMPXCHG_DESIRED1173]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1175:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1174]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1175]], ptr [[LX_ATOMIC_EXPECTED_PTR1171]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1176:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1174]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP932:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP933:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP932]], ptr [[LX_ATOMIC_EXPECTED_PTR1177]], align 8
+// CHECK-NEXT: store i64 [[TMP933]], ptr [[LX_ATOMIC_DESIRED_PTR1178]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1180:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1177]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1181:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1178]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1182:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1180]], i64 [[LX_CMPXCHG_DESIRED1181]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1183:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1182]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1183]], ptr [[LX_ATOMIC_EXPECTED_PTR1179]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1184:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1182]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP934:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP935:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP934]], ptr [[LX_ATOMIC_EXPECTED_PTR1185]], align 8
+// CHECK-NEXT: store i64 [[TMP935]], ptr [[LX_ATOMIC_DESIRED_PTR1186]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1188:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1185]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1189:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1186]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1190:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1188]], i64 [[LX_CMPXCHG_DESIRED1189]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1191:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1190]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1191]], ptr [[LX_ATOMIC_EXPECTED_PTR1187]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1192:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1190]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP936:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP937:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP936]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP938:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP939:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP938]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP940:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP941:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP940]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP942:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP943:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP942]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP944:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP945:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP944]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP946:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP947:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP946]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP948:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP949:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP948]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP950:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP951:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP950]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP952:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP953:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP952]], ptr [[ULX_ATOMIC_EXPECTED_PTR1193]], align 8
+// CHECK-NEXT: store i64 [[TMP953]], ptr [[ULX_ATOMIC_DESIRED_PTR1194]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1196:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1193]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1197:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1194]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1198:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1196]], i64 [[ULX_CMPXCHG_DESIRED1197]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1199:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1198]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1199]], ptr [[ULX_ATOMIC_EXPECTED_PTR1195]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1200:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1198]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP954:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP955:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP954]], ptr [[ULX_ATOMIC_EXPECTED_PTR1201]], align 8
+// CHECK-NEXT: store i64 [[TMP955]], ptr [[ULX_ATOMIC_DESIRED_PTR1202]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1204:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1201]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1205:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1202]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1206:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1204]], i64 [[ULX_CMPXCHG_DESIRED1205]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1207:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1206]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1207]], ptr [[ULX_ATOMIC_EXPECTED_PTR1203]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1208:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1206]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP956:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP957:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP956]], ptr [[ULX_ATOMIC_EXPECTED_PTR1209]], align 8
+// CHECK-NEXT: store i64 [[TMP957]], ptr [[ULX_ATOMIC_DESIRED_PTR1210]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1212:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1209]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1213:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1210]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1214:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1212]], i64 [[ULX_CMPXCHG_DESIRED1213]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1215:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1214]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1215]], ptr [[ULX_ATOMIC_EXPECTED_PTR1211]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1216:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1214]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP958:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP959:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP958]], ptr [[ULX_ATOMIC_EXPECTED_PTR1217]], align 8
+// CHECK-NEXT: store i64 [[TMP959]], ptr [[ULX_ATOMIC_DESIRED_PTR1218]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1220:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1217]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1221:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1218]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1222:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1220]], i64 [[ULX_CMPXCHG_DESIRED1221]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1223:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1222]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1223]], ptr [[ULX_ATOMIC_EXPECTED_PTR1219]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1224:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1222]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP960:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP961:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP960]] acquire, align 8
+// CHECK-NEXT: [[TMP962:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP963:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP962]] acquire, align 8
+// CHECK-NEXT: [[TMP964:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP965:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP964]] acquire, align 8
+// CHECK-NEXT: [[TMP966:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP967:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP966]] acquire, align 8
+// CHECK-NEXT: [[TMP968:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP969:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP968]] acquire, align 8
+// CHECK-NEXT: [[TMP970:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP971:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP970]] acquire, align 8
+// CHECK-NEXT: [[TMP972:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP973:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP972]] acquire, align 8
+// CHECK-NEXT: [[TMP974:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP975:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP974]] acquire, align 8
+// CHECK-NEXT: [[TMP976:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP977:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP976]], ptr [[LX_ATOMIC_EXPECTED_PTR1225]], align 8
+// CHECK-NEXT: store i64 [[TMP977]], ptr [[LX_ATOMIC_DESIRED_PTR1226]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1228:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1225]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1229:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1226]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1230:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1228]], i64 [[LX_CMPXCHG_DESIRED1229]] acquire acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1231:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1230]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1231]], ptr [[LX_ATOMIC_EXPECTED_PTR1227]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1232:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1230]], 1
+// CHECK-NEXT: [[TMP978:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP979:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP978]], ptr [[LX_ATOMIC_EXPECTED_PTR1233]], align 8
+// CHECK-NEXT: store i64 [[TMP979]], ptr [[LX_ATOMIC_DESIRED_PTR1234]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1236:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1233]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1237:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1234]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1238:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1236]], i64 [[LX_CMPXCHG_DESIRED1237]] acquire acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1239:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1238]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1239]], ptr [[LX_ATOMIC_EXPECTED_PTR1235]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1240:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1238]], 1
+// CHECK-NEXT: [[TMP980:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP981:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP980]], ptr [[LX_ATOMIC_EXPECTED_PTR1241]], align 8
+// CHECK-NEXT: store i64 [[TMP981]], ptr [[LX_ATOMIC_DESIRED_PTR1242]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1244:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1241]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1245:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1242]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1246:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1244]], i64 [[LX_CMPXCHG_DESIRED1245]] acquire acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1247:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1246]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1247]], ptr [[LX_ATOMIC_EXPECTED_PTR1243]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1248:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1246]], 1
+// CHECK-NEXT: [[TMP982:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP983:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP982]], ptr [[LX_ATOMIC_EXPECTED_PTR1249]], align 8
+// CHECK-NEXT: store i64 [[TMP983]], ptr [[LX_ATOMIC_DESIRED_PTR1250]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1252:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1249]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1253:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1250]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1254:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1252]], i64 [[LX_CMPXCHG_DESIRED1253]] acquire acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1255:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1254]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1255]], ptr [[LX_ATOMIC_EXPECTED_PTR1251]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1256:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1254]], 1
+// CHECK-NEXT: [[TMP984:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP985:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP984]] acquire, align 8
+// CHECK-NEXT: [[TMP986:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP987:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP986]] acquire, align 8
+// CHECK-NEXT: [[TMP988:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP989:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP988]] acquire, align 8
+// CHECK-NEXT: [[TMP990:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP991:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP990]] acquire, align 8
+// CHECK-NEXT: [[TMP992:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP993:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP992]] acquire, align 8
+// CHECK-NEXT: [[TMP994:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP995:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP994]] acquire, align 8
+// CHECK-NEXT: [[TMP996:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP997:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP996]] acquire, align 8
+// CHECK-NEXT: [[TMP998:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP999:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP998]] acquire, align 8
+// CHECK-NEXT: [[TMP1000:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1001:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP1000]], ptr [[ULX_ATOMIC_EXPECTED_PTR1257]], align 8
+// CHECK-NEXT: store i64 [[TMP1001]], ptr [[ULX_ATOMIC_DESIRED_PTR1258]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1260:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1257]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1261:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1258]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1262:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1260]], i64 [[ULX_CMPXCHG_DESIRED1261]] acquire acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1263:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1262]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1263]], ptr [[ULX_ATOMIC_EXPECTED_PTR1259]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1264:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1262]], 1
+// CHECK-NEXT: [[TMP1002:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1003:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP1002]], ptr [[ULX_ATOMIC_EXPECTED_PTR1265]], align 8
+// CHECK-NEXT: store i64 [[TMP1003]], ptr [[ULX_ATOMIC_DESIRED_PTR1266]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1268:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1265]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1269:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1266]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1270:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1268]], i64 [[ULX_CMPXCHG_DESIRED1269]] acquire acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1271:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1270]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1271]], ptr [[ULX_ATOMIC_EXPECTED_PTR1267]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1272:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1270]], 1
+// CHECK-NEXT: [[TMP1004:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1005:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP1004]], ptr [[ULX_ATOMIC_EXPECTED_PTR1273]], align 8
+// CHECK-NEXT: store i64 [[TMP1005]], ptr [[ULX_ATOMIC_DESIRED_PTR1274]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1276:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1273]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1277:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1274]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1278:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1276]], i64 [[ULX_CMPXCHG_DESIRED1277]] acquire acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1279:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1278]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1279]], ptr [[ULX_ATOMIC_EXPECTED_PTR1275]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1280:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1278]], 1
+// CHECK-NEXT: [[TMP1006:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1007:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP1006]], ptr [[ULX_ATOMIC_EXPECTED_PTR1281]], align 8
+// CHECK-NEXT: store i64 [[TMP1007]], ptr [[ULX_ATOMIC_DESIRED_PTR1282]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1284:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1281]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1285:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1282]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1286:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1284]], i64 [[ULX_CMPXCHG_DESIRED1285]] acquire acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1287:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1286]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1287]], ptr [[ULX_ATOMIC_EXPECTED_PTR1283]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1288:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1286]], 1
// CHECK-NEXT: [[TMP1008:%.*]] = load i64, ptr [[LE]], align 8
// CHECK-NEXT: [[TMP1009:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1008]] monotonic, align 8
// CHECK-NEXT: [[TMP1010:%.*]] = load i64, ptr [[LE]], align 8
@@ -15145,1043 +17233,1355 @@ double fail_dxevd() {
// CHECK-NEXT: [[TMP1023:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1022]] monotonic, align 8
// CHECK-NEXT: [[TMP1024:%.*]] = load i64, ptr [[LE]], align 8
// CHECK-NEXT: [[TMP1025:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1026:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1024]], i64 [[TMP1025]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1027:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1028:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1029:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1027]], i64 [[TMP1028]] monotonic monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP1024]], ptr [[LX_ATOMIC_EXPECTED_PTR1289]], align 8
+// CHECK-NEXT: store i64 [[TMP1025]], ptr [[LX_ATOMIC_DESIRED_PTR1290]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1292:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1289]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1293:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1290]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1294:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1292]], i64 [[LX_CMPXCHG_DESIRED1293]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1295:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1294]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1295]], ptr [[LX_ATOMIC_EXPECTED_PTR1291]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1296:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1294]], 1
+// CHECK-NEXT: [[TMP1026:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1027:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1026]], ptr [[LX_ATOMIC_EXPECTED_PTR1297]], align 8
+// CHECK-NEXT: store i64 [[TMP1027]], ptr [[LX_ATOMIC_DESIRED_PTR1298]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1300:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1297]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1301:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1298]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1302:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1300]], i64 [[LX_CMPXCHG_DESIRED1301]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1303:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1302]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1303]], ptr [[LX_ATOMIC_EXPECTED_PTR1299]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1304:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1302]], 1
+// CHECK-NEXT: [[TMP1028:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1029:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1028]], ptr [[LX_ATOMIC_EXPECTED_PTR1305]], align 8
+// CHECK-NEXT: store i64 [[TMP1029]], ptr [[LX_ATOMIC_DESIRED_PTR1306]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1308:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1305]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1309:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1306]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1310:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1308]], i64 [[LX_CMPXCHG_DESIRED1309]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1311:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1310]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1311]], ptr [[LX_ATOMIC_EXPECTED_PTR1307]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1312:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1310]], 1
// CHECK-NEXT: [[TMP1030:%.*]] = load i64, ptr [[LE]], align 8
// CHECK-NEXT: [[TMP1031:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1032:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1030]], i64 [[TMP1031]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1033:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1034:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1035:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1033]], i64 [[TMP1034]] monotonic monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP1030]], ptr [[LX_ATOMIC_EXPECTED_PTR1313]], align 8
+// CHECK-NEXT: store i64 [[TMP1031]], ptr [[LX_ATOMIC_DESIRED_PTR1314]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1316:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1313]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1317:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1314]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1318:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1316]], i64 [[LX_CMPXCHG_DESIRED1317]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1319:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1318]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1319]], ptr [[LX_ATOMIC_EXPECTED_PTR1315]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1320:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1318]], 1
+// CHECK-NEXT: [[TMP1032:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1033:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1032]] monotonic, align 8
+// CHECK-NEXT: [[TMP1034:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1035:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1034]] monotonic, align 8
// CHECK-NEXT: [[TMP1036:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1037:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1036]] monotonic, align 8
+// CHECK-NEXT: [[TMP1037:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1036]] monotonic, align 8
// CHECK-NEXT: [[TMP1038:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1039:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1038]] monotonic, align 8
+// CHECK-NEXT: [[TMP1039:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1038]] monotonic, align 8
// CHECK-NEXT: [[TMP1040:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1041:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1040]] monotonic, align 8
+// CHECK-NEXT: [[TMP1041:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1040]] monotonic, align 8
// CHECK-NEXT: [[TMP1042:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1043:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1042]] monotonic, align 8
+// CHECK-NEXT: [[TMP1043:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1042]] monotonic, align 8
// CHECK-NEXT: [[TMP1044:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1045:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1044]] monotonic, align 8
+// CHECK-NEXT: [[TMP1045:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1044]] monotonic, align 8
// CHECK-NEXT: [[TMP1046:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1047:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1046]] monotonic, align 8
+// CHECK-NEXT: [[TMP1047:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1046]] monotonic, align 8
// CHECK-NEXT: [[TMP1048:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1049:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1048]] monotonic, align 8
+// CHECK-NEXT: [[TMP1049:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP1048]], ptr [[ULX_ATOMIC_EXPECTED_PTR1321]], align 8
+// CHECK-NEXT: store i64 [[TMP1049]], ptr [[ULX_ATOMIC_DESIRED_PTR1322]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1324:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1321]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1325:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1322]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1326:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1324]], i64 [[ULX_CMPXCHG_DESIRED1325]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1327:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1326]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1327]], ptr [[ULX_ATOMIC_EXPECTED_PTR1323]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1328:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1326]], 1
// CHECK-NEXT: [[TMP1050:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1051:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1050]] monotonic, align 8
+// CHECK-NEXT: [[TMP1051:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP1050]], ptr [[ULX_ATOMIC_EXPECTED_PTR1329]], align 8
+// CHECK-NEXT: store i64 [[TMP1051]], ptr [[ULX_ATOMIC_DESIRED_PTR1330]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1332:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1329]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1333:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1330]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1334:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1332]], i64 [[ULX_CMPXCHG_DESIRED1333]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1335:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1334]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1335]], ptr [[ULX_ATOMIC_EXPECTED_PTR1331]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1336:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1334]], 1
// CHECK-NEXT: [[TMP1052:%.*]] = load i64, ptr [[ULE]], align 8
// CHECK-NEXT: [[TMP1053:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1054:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1052]], i64 [[TMP1053]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1055:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1056:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1057:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1055]], i64 [[TMP1056]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1058:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1059:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1060:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1058]], i64 [[TMP1059]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1061:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1062:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1063:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1061]], i64 [[TMP1062]] monotonic monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP1052]], ptr [[ULX_ATOMIC_EXPECTED_PTR1337]], align 8
+// CHECK-NEXT: store i64 [[TMP1053]], ptr [[ULX_ATOMIC_DESIRED_PTR1338]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1340:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1337]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1341:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1338]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1342:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1340]], i64 [[ULX_CMPXCHG_DESIRED1341]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1343:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1342]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1343]], ptr [[ULX_ATOMIC_EXPECTED_PTR1339]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1344:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1342]], 1
+// CHECK-NEXT: [[TMP1054:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1055:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP1054]], ptr [[ULX_ATOMIC_EXPECTED_PTR1345]], align 8
+// CHECK-NEXT: store i64 [[TMP1055]], ptr [[ULX_ATOMIC_DESIRED_PTR1346]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1348:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1345]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1349:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1346]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1350:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1348]], i64 [[ULX_CMPXCHG_DESIRED1349]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1351:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1350]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1351]], ptr [[ULX_ATOMIC_EXPECTED_PTR1347]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1352:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1350]], 1
+// CHECK-NEXT: [[TMP1056:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1057:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1056]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1058:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1059:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1058]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1060:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1061:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1060]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1062:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1063:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1062]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1064:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1065:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1064]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1065:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1064]] release, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1066:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1067:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1066]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1067:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1066]] release, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1068:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1069:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1068]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1069:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1068]] release, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1070:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1071:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1070]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1071:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1070]] release, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1072:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1073:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1072]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1073:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1072]], ptr [[LX_ATOMIC_EXPECTED_PTR1353]], align 8
+// CHECK-NEXT: store i64 [[TMP1073]], ptr [[LX_ATOMIC_DESIRED_PTR1354]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1356:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1353]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1357:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1354]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1358:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1356]], i64 [[LX_CMPXCHG_DESIRED1357]] release monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1359:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1358]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1359]], ptr [[LX_ATOMIC_EXPECTED_PTR1355]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1360:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1358]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1074:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1075:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1074]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1075:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1074]], ptr [[LX_ATOMIC_EXPECTED_PTR1361]], align 8
+// CHECK-NEXT: store i64 [[TMP1075]], ptr [[LX_ATOMIC_DESIRED_PTR1362]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1364:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1361]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1365:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1362]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1366:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1364]], i64 [[LX_CMPXCHG_DESIRED1365]] release monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1367:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1366]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1367]], ptr [[LX_ATOMIC_EXPECTED_PTR1363]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1368:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1366]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1076:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1077:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1076]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1077:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1076]], ptr [[LX_ATOMIC_EXPECTED_PTR1369]], align 8
+// CHECK-NEXT: store i64 [[TMP1077]], ptr [[LX_ATOMIC_DESIRED_PTR1370]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1372:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1369]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1373:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1370]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1374:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1372]], i64 [[LX_CMPXCHG_DESIRED1373]] release monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1375:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1374]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1375]], ptr [[LX_ATOMIC_EXPECTED_PTR1371]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1376:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1374]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1078:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1079:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1078]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1079:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1078]], ptr [[LX_ATOMIC_EXPECTED_PTR1377]], align 8
+// CHECK-NEXT: store i64 [[TMP1079]], ptr [[LX_ATOMIC_DESIRED_PTR1378]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1380:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1377]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1381:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1378]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1382:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1380]], i64 [[LX_CMPXCHG_DESIRED1381]] release monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1383:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1382]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1383]], ptr [[LX_ATOMIC_EXPECTED_PTR1379]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1384:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1382]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1080:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1081:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1080]] release, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1080:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1081:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1082:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1080]], i64 [[TMP1081]] acq_rel acquire, align 8
+// CHECK-NEXT: [[TMP1082:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1083:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1082]] release, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1083:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1084:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1085:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1083]], i64 [[TMP1084]] acq_rel acquire, align 8
+// CHECK-NEXT: [[TMP1084:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1085:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1084]] release, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1086:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1087:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1088:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1086]], i64 [[TMP1087]] acq_rel acquire, align 8
+// CHECK-NEXT: [[TMP1086:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1087:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1086]] release, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1089:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1090:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1091:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1089]], i64 [[TMP1090]] acq_rel acquire, align 8
+// CHECK-NEXT: [[TMP1088:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1089:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1088]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1090:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1091:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1090]] release, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1092:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1093:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1092]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1093:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1092]] release, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1094:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1095:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1094]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1095:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1094]] release, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1096:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1097:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1096]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1097:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP1096]], ptr [[ULX_ATOMIC_EXPECTED_PTR1385]], align 8
+// CHECK-NEXT: store i64 [[TMP1097]], ptr [[ULX_ATOMIC_DESIRED_PTR1386]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1388:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1385]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1389:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1386]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1390:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1388]], i64 [[ULX_CMPXCHG_DESIRED1389]] release monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1391:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1390]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1391]], ptr [[ULX_ATOMIC_EXPECTED_PTR1387]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1392:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1390]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1098:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1099:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1098]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1099:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP1098]], ptr [[ULX_ATOMIC_EXPECTED_PTR1393]], align 8
+// CHECK-NEXT: store i64 [[TMP1099]], ptr [[ULX_ATOMIC_DESIRED_PTR1394]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1396:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1393]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1397:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1394]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1398:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1396]], i64 [[ULX_CMPXCHG_DESIRED1397]] release monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1399:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1398]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1399]], ptr [[ULX_ATOMIC_EXPECTED_PTR1395]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1400:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1398]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1100:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1101:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1100]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1101:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP1100]], ptr [[ULX_ATOMIC_EXPECTED_PTR1401]], align 8
+// CHECK-NEXT: store i64 [[TMP1101]], ptr [[ULX_ATOMIC_DESIRED_PTR1402]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1404:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1401]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1405:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1402]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1406:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1404]], i64 [[ULX_CMPXCHG_DESIRED1405]] release monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1407:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1406]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1407]], ptr [[ULX_ATOMIC_EXPECTED_PTR1403]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1408:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1406]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1102:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1103:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1102]] acq_rel, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1104:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1105:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1104]] acq_rel, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1106:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1107:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1106]] acq_rel, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1108:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1109:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1110:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1108]], i64 [[TMP1109]] acq_rel acquire, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1111:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1112:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1113:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1111]], i64 [[TMP1112]] acq_rel acquire, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1114:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1115:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1116:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1114]], i64 [[TMP1115]] acq_rel acquire, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1117:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1118:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1119:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1117]], i64 [[TMP1118]] acq_rel acquire, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1120:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1121:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1120]] acquire, align 8
-// CHECK-NEXT: [[TMP1122:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1123:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1122]] acquire, align 8
-// CHECK-NEXT: [[TMP1124:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1125:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1124]] acquire, align 8
-// CHECK-NEXT: [[TMP1126:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1127:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1126]] acquire, align 8
-// CHECK-NEXT: [[TMP1128:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1129:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1128]] acquire, align 8
-// CHECK-NEXT: [[TMP1130:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1131:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1130]] acquire, align 8
-// CHECK-NEXT: [[TMP1132:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1133:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1132]] acquire, align 8
-// CHECK-NEXT: [[TMP1134:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1135:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1134]] acquire, align 8
-// CHECK-NEXT: [[TMP1136:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1137:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1138:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1136]], i64 [[TMP1137]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP1139:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1140:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1141:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1139]], i64 [[TMP1140]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP1142:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1143:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1144:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1142]], i64 [[TMP1143]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP1145:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1146:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1147:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1145]], i64 [[TMP1146]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP1148:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1149:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1148]] acquire, align 8
-// CHECK-NEXT: [[TMP1150:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1151:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1150]] acquire, align 8
-// CHECK-NEXT: [[TMP1152:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1153:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1152]] acquire, align 8
-// CHECK-NEXT: [[TMP1154:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1155:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1154]] acquire, align 8
-// CHECK-NEXT: [[TMP1156:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1157:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1156]] acquire, align 8
-// CHECK-NEXT: [[TMP1158:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1159:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1158]] acquire, align 8
-// CHECK-NEXT: [[TMP1160:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1161:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1160]] acquire, align 8
-// CHECK-NEXT: [[TMP1162:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1163:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1162]] acquire, align 8
-// CHECK-NEXT: [[TMP1164:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1165:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1166:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1164]], i64 [[TMP1165]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP1167:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1168:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1169:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1167]], i64 [[TMP1168]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP1170:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1171:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1172:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1170]], i64 [[TMP1171]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP1173:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1174:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1175:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1173]], i64 [[TMP1174]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP1176:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1177:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1176]] monotonic, align 8
-// CHECK-NEXT: [[TMP1178:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1179:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1178]] monotonic, align 8
-// CHECK-NEXT: [[TMP1180:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1181:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1180]] monotonic, align 8
-// CHECK-NEXT: [[TMP1182:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1183:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1182]] monotonic, align 8
-// CHECK-NEXT: [[TMP1184:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1185:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1184]] monotonic, align 8
-// CHECK-NEXT: [[TMP1186:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1187:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1186]] monotonic, align 8
-// CHECK-NEXT: [[TMP1188:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1189:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1188]] monotonic, align 8
-// CHECK-NEXT: [[TMP1190:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1191:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1190]] monotonic, align 8
-// CHECK-NEXT: [[TMP1192:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1193:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1194:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1192]], i64 [[TMP1193]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1195:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1196:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1197:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1195]], i64 [[TMP1196]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1198:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1199:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1200:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1198]], i64 [[TMP1199]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1201:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1202:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1203:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1201]], i64 [[TMP1202]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1204:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1205:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1204]] monotonic, align 8
-// CHECK-NEXT: [[TMP1206:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1207:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1206]] monotonic, align 8
-// CHECK-NEXT: [[TMP1208:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1209:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1208]] monotonic, align 8
-// CHECK-NEXT: [[TMP1210:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1211:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1210]] monotonic, align 8
-// CHECK-NEXT: [[TMP1212:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1213:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1212]] monotonic, align 8
-// CHECK-NEXT: [[TMP1214:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1215:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1214]] monotonic, align 8
-// CHECK-NEXT: [[TMP1216:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1217:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1216]] monotonic, align 8
-// CHECK-NEXT: [[TMP1218:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1219:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1218]] monotonic, align 8
-// CHECK-NEXT: [[TMP1220:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1221:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1222:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1220]], i64 [[TMP1221]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1223:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1224:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1225:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1223]], i64 [[TMP1224]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1226:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1227:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1228:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1226]], i64 [[TMP1227]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1229:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1230:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1231:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1229]], i64 [[TMP1230]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1232:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1233:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1232]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1234:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1235:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1234]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1236:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1237:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1236]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1238:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1239:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1238]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1240:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1241:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1240]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1242:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1243:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1242]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1244:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1245:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1244]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1246:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1247:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1246]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1248:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1249:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1250:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1248]], i64 [[TMP1249]] release monotonic, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1251:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1252:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1253:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1251]], i64 [[TMP1252]] release monotonic, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1254:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1255:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1256:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1254]], i64 [[TMP1255]] release monotonic, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1257:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1258:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1259:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1257]], i64 [[TMP1258]] release monotonic, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1260:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1261:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1260]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1262:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1263:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1262]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1264:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1265:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1264]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1266:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1267:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1266]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1268:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1269:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1268]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1270:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1271:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1270]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1272:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1273:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1272]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1274:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1275:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1274]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1276:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1277:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1278:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1276]], i64 [[TMP1277]] release monotonic, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1279:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1280:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1281:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1279]], i64 [[TMP1280]] release monotonic, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1282:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1283:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1284:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1282]], i64 [[TMP1283]] release monotonic, align 8
+// CHECK-NEXT: [[TMP1103:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP1102]], ptr [[ULX_ATOMIC_EXPECTED_PTR1409]], align 8
+// CHECK-NEXT: store i64 [[TMP1103]], ptr [[ULX_ATOMIC_DESIRED_PTR1410]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1412:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1409]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1413:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1410]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1414:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1412]], i64 [[ULX_CMPXCHG_DESIRED1413]] release monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1415:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1414]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1415]], ptr [[ULX_ATOMIC_EXPECTED_PTR1411]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1416:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1414]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1285:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1286:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1287:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1285]], i64 [[TMP1286]] release monotonic, align 8
+// CHECK-NEXT: [[TMP1104:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1105:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1104]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1288:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1289:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1288]] seq_cst, align 8
+// CHECK-NEXT: [[TMP1106:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1107:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1106]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1290:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1291:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1290]] seq_cst, align 8
+// CHECK-NEXT: [[TMP1108:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1109:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1108]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1292:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1293:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1292]] seq_cst, align 8
+// CHECK-NEXT: [[TMP1110:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1111:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1110]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1294:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1295:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1294]] seq_cst, align 8
+// CHECK-NEXT: [[TMP1112:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1113:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1112]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1296:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1297:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1296]] seq_cst, align 8
+// CHECK-NEXT: [[TMP1114:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1115:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1114]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1298:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1299:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1298]] seq_cst, align 8
+// CHECK-NEXT: [[TMP1116:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1117:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1116]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1300:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1301:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1300]] seq_cst, align 8
+// CHECK-NEXT: [[TMP1118:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1119:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1118]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1302:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1303:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1302]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1304:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1305:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1306:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1304]], i64 [[TMP1305]] seq_cst seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1307:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1308:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1309:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1307]], i64 [[TMP1308]] seq_cst seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1310:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1311:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1312:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1310]], i64 [[TMP1311]] seq_cst seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1313:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP1314:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP1315:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP1313]], i64 [[TMP1314]] seq_cst seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1316:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1317:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1316]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1318:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1319:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1318]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1320:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1321:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1320]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1322:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1323:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1322]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1324:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1325:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1324]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1326:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1327:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1326]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1328:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1329:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1328]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1330:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1331:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1330]] seq_cst, align 8
+// CHECK-NEXT: [[TMP1120:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1121:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1120]], ptr [[LX_ATOMIC_EXPECTED_PTR1417]], align 8
+// CHECK-NEXT: store i64 [[TMP1121]], ptr [[LX_ATOMIC_DESIRED_PTR1418]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1420:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1417]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1421:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1418]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1422:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1420]], i64 [[LX_CMPXCHG_DESIRED1421]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1423:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1422]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1423]], ptr [[LX_ATOMIC_EXPECTED_PTR1419]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1424:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1422]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1332:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1333:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1334:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1332]], i64 [[TMP1333]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[TMP1122:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1123:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1122]], ptr [[LX_ATOMIC_EXPECTED_PTR1425]], align 8
+// CHECK-NEXT: store i64 [[TMP1123]], ptr [[LX_ATOMIC_DESIRED_PTR1426]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1428:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1425]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1429:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1426]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1430:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1428]], i64 [[LX_CMPXCHG_DESIRED1429]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1431:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1430]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1431]], ptr [[LX_ATOMIC_EXPECTED_PTR1427]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1432:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1430]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1335:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1336:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1337:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1335]], i64 [[TMP1336]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[TMP1124:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1125:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1124]], ptr [[LX_ATOMIC_EXPECTED_PTR1433]], align 8
+// CHECK-NEXT: store i64 [[TMP1125]], ptr [[LX_ATOMIC_DESIRED_PTR1434]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1436:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1433]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1437:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1434]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1438:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1436]], i64 [[LX_CMPXCHG_DESIRED1437]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1439:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1438]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1439]], ptr [[LX_ATOMIC_EXPECTED_PTR1435]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1440:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1438]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1338:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1339:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1340:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1338]], i64 [[TMP1339]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[TMP1126:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1127:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1126]], ptr [[LX_ATOMIC_EXPECTED_PTR1441]], align 8
+// CHECK-NEXT: store i64 [[TMP1127]], ptr [[LX_ATOMIC_DESIRED_PTR1442]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED1444:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1441]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED1445:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR1442]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR1446:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED1444]], i64 [[LX_CMPXCHG_DESIRED1445]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV1447:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1446]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV1447]], ptr [[LX_ATOMIC_EXPECTED_PTR1443]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS1448:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR1446]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1128:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1129:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1128]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1130:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1131:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1130]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1132:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1133:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1132]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1134:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1135:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1134]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1136:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1137:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1136]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1138:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1139:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1138]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1140:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1141:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP1140]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1142:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1143:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP1142]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1144:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1145:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP1144]], ptr [[ULX_ATOMIC_EXPECTED_PTR1449]], align 8
+// CHECK-NEXT: store i64 [[TMP1145]], ptr [[ULX_ATOMIC_DESIRED_PTR1450]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1452:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1449]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1453:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1450]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1454:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1452]], i64 [[ULX_CMPXCHG_DESIRED1453]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1455:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1454]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1455]], ptr [[ULX_ATOMIC_EXPECTED_PTR1451]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1456:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1454]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1146:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1147:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP1146]], ptr [[ULX_ATOMIC_EXPECTED_PTR1457]], align 8
+// CHECK-NEXT: store i64 [[TMP1147]], ptr [[ULX_ATOMIC_DESIRED_PTR1458]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1460:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1457]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1461:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1458]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1462:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1460]], i64 [[ULX_CMPXCHG_DESIRED1461]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1463:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1462]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1463]], ptr [[ULX_ATOMIC_EXPECTED_PTR1459]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1464:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1462]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1341:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP1342:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP1343:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP1341]], i64 [[TMP1342]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[TMP1148:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1149:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP1148]], ptr [[ULX_ATOMIC_EXPECTED_PTR1465]], align 8
+// CHECK-NEXT: store i64 [[TMP1149]], ptr [[ULX_ATOMIC_DESIRED_PTR1466]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1468:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1465]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1469:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1466]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1470:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1468]], i64 [[ULX_CMPXCHG_DESIRED1469]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1471:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1470]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1471]], ptr [[ULX_ATOMIC_EXPECTED_PTR1467]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1472:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1470]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1150:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP1151:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP1150]], ptr [[ULX_ATOMIC_EXPECTED_PTR1473]], align 8
+// CHECK-NEXT: store i64 [[TMP1151]], ptr [[ULX_ATOMIC_DESIRED_PTR1474]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED1476:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1473]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED1477:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR1474]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR1478:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED1476]], i64 [[ULX_CMPXCHG_DESIRED1477]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV1479:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1478]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV1479]], ptr [[ULX_ATOMIC_EXPECTED_PTR1475]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS1480:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR1478]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1152:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1153:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1152]] monotonic, align 8
+// CHECK-NEXT: [[TMP1154:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1155:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1154]] monotonic, align 8
+// CHECK-NEXT: [[TMP1156:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1157:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1156]] monotonic, align 8
+// CHECK-NEXT: [[TMP1158:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1159:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1158]] monotonic, align 8
+// CHECK-NEXT: [[TMP1160:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1161:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1160]] monotonic, align 8
+// CHECK-NEXT: [[TMP1162:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1163:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1162]] monotonic, align 8
+// CHECK-NEXT: [[TMP1164:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1165:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1164]] monotonic, align 8
+// CHECK-NEXT: [[TMP1166:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1167:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1166]] monotonic, align 8
+// CHECK-NEXT: [[TMP1168:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1169:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1168]], ptr [[LLX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: store i64 [[TMP1169]], ptr [[LLX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED]], i64 [[LLX_CMPXCHG_DESIRED]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV]], ptr [[LLX_ATOMIC_EXPECTED_PTR1481]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[TMP1170:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1171:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1170]], ptr [[LLX_ATOMIC_EXPECTED_PTR1482]], align 8
+// CHECK-NEXT: store i64 [[TMP1171]], ptr [[LLX_ATOMIC_DESIRED_PTR1483]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1485:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1482]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1486:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1483]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1487:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1485]], i64 [[LLX_CMPXCHG_DESIRED1486]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1488:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1487]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1488]], ptr [[LLX_ATOMIC_EXPECTED_PTR1484]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1489:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1487]], 1
+// CHECK-NEXT: [[TMP1172:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1173:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1172]], ptr [[LLX_ATOMIC_EXPECTED_PTR1490]], align 8
+// CHECK-NEXT: store i64 [[TMP1173]], ptr [[LLX_ATOMIC_DESIRED_PTR1491]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1493:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1490]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1494:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1491]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1495:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1493]], i64 [[LLX_CMPXCHG_DESIRED1494]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1496:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1495]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1496]], ptr [[LLX_ATOMIC_EXPECTED_PTR1492]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1497:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1495]], 1
+// CHECK-NEXT: [[TMP1174:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1175:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1174]], ptr [[LLX_ATOMIC_EXPECTED_PTR1498]], align 8
+// CHECK-NEXT: store i64 [[TMP1175]], ptr [[LLX_ATOMIC_DESIRED_PTR1499]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1501:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1498]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1502:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1499]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1503:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1501]], i64 [[LLX_CMPXCHG_DESIRED1502]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1504:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1503]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1504]], ptr [[LLX_ATOMIC_EXPECTED_PTR1500]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1505:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1503]], 1
+// CHECK-NEXT: [[TMP1176:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1177:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1176]] monotonic, align 8
+// CHECK-NEXT: [[TMP1178:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1179:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1178]] monotonic, align 8
+// CHECK-NEXT: [[TMP1180:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1181:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1180]] monotonic, align 8
+// CHECK-NEXT: [[TMP1182:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1183:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1182]] monotonic, align 8
+// CHECK-NEXT: [[TMP1184:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1185:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1184]] monotonic, align 8
+// CHECK-NEXT: [[TMP1186:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1187:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1186]] monotonic, align 8
+// CHECK-NEXT: [[TMP1188:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1189:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1188]] monotonic, align 8
+// CHECK-NEXT: [[TMP1190:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1191:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1190]] monotonic, align 8
+// CHECK-NEXT: [[TMP1192:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1193:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1192]], ptr [[ULLX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: store i64 [[TMP1193]], ptr [[ULLX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED]], i64 [[ULLX_CMPXCHG_DESIRED]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1506]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[TMP1194:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1195:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1194]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1507]], align 8
+// CHECK-NEXT: store i64 [[TMP1195]], ptr [[ULLX_ATOMIC_DESIRED_PTR1508]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1510:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1507]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1511:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1508]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1512:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1510]], i64 [[ULLX_CMPXCHG_DESIRED1511]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1513:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1512]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1513]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1509]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1514:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1512]], 1
+// CHECK-NEXT: [[TMP1196:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1197:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1196]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1515]], align 8
+// CHECK-NEXT: store i64 [[TMP1197]], ptr [[ULLX_ATOMIC_DESIRED_PTR1516]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1518:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1515]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1519:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1516]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1520:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1518]], i64 [[ULLX_CMPXCHG_DESIRED1519]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1521:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1520]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1521]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1517]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1522:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1520]], 1
+// CHECK-NEXT: [[TMP1198:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1199:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1198]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1523]], align 8
+// CHECK-NEXT: store i64 [[TMP1199]], ptr [[ULLX_ATOMIC_DESIRED_PTR1524]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1526:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1523]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1527:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1524]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1528:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1526]], i64 [[ULLX_CMPXCHG_DESIRED1527]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1529:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1528]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1529]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1525]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1530:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1528]], 1
+// CHECK-NEXT: [[TMP1200:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1201:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1200]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1202:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1203:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1202]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1204:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1205:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1204]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1206:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1207:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1206]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1208:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1209:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1208]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1210:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1211:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1210]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1212:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1213:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1212]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1214:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1215:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1214]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1216:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1217:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1216]], ptr [[LLX_ATOMIC_EXPECTED_PTR1531]], align 8
+// CHECK-NEXT: store i64 [[TMP1217]], ptr [[LLX_ATOMIC_DESIRED_PTR1532]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1534:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1531]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1535:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1532]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1536:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1534]], i64 [[LLX_CMPXCHG_DESIRED1535]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1537:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1536]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1537]], ptr [[LLX_ATOMIC_EXPECTED_PTR1533]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1538:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1536]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1218:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1219:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1218]], ptr [[LLX_ATOMIC_EXPECTED_PTR1539]], align 8
+// CHECK-NEXT: store i64 [[TMP1219]], ptr [[LLX_ATOMIC_DESIRED_PTR1540]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1542:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1539]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1543:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1540]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1544:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1542]], i64 [[LLX_CMPXCHG_DESIRED1543]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1545:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1544]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1545]], ptr [[LLX_ATOMIC_EXPECTED_PTR1541]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1546:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1544]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1220:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1221:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1220]], ptr [[LLX_ATOMIC_EXPECTED_PTR1547]], align 8
+// CHECK-NEXT: store i64 [[TMP1221]], ptr [[LLX_ATOMIC_DESIRED_PTR1548]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1550:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1547]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1551:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1548]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1552:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1550]], i64 [[LLX_CMPXCHG_DESIRED1551]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1553:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1552]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1553]], ptr [[LLX_ATOMIC_EXPECTED_PTR1549]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1554:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1552]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1222:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1223:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1222]], ptr [[LLX_ATOMIC_EXPECTED_PTR1555]], align 8
+// CHECK-NEXT: store i64 [[TMP1223]], ptr [[LLX_ATOMIC_DESIRED_PTR1556]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1558:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1555]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1559:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1556]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1560:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1558]], i64 [[LLX_CMPXCHG_DESIRED1559]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1561:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1560]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1561]], ptr [[LLX_ATOMIC_EXPECTED_PTR1557]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1562:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1560]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1224:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1225:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1224]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1226:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1227:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1226]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1228:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1229:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1228]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1230:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1231:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1230]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1232:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1233:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1232]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1234:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1235:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1234]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1236:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1237:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1236]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1238:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1239:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1238]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1240:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1241:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1240]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1563]], align 8
+// CHECK-NEXT: store i64 [[TMP1241]], ptr [[ULLX_ATOMIC_DESIRED_PTR1564]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1566:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1563]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1567:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1564]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1568:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1566]], i64 [[ULLX_CMPXCHG_DESIRED1567]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1569:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1568]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1569]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1565]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1570:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1568]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1242:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1243:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1242]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1571]], align 8
+// CHECK-NEXT: store i64 [[TMP1243]], ptr [[ULLX_ATOMIC_DESIRED_PTR1572]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1574:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1571]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1575:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1572]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1576:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1574]], i64 [[ULLX_CMPXCHG_DESIRED1575]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1577:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1576]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1577]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1573]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1578:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1576]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1244:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1245:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1244]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1579]], align 8
+// CHECK-NEXT: store i64 [[TMP1245]], ptr [[ULLX_ATOMIC_DESIRED_PTR1580]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1582:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1579]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1583:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1580]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1584:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1582]], i64 [[ULLX_CMPXCHG_DESIRED1583]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1585:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1584]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1585]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1581]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1586:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1584]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1246:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1247:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1246]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1587]], align 8
+// CHECK-NEXT: store i64 [[TMP1247]], ptr [[ULLX_ATOMIC_DESIRED_PTR1588]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1590:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1587]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1591:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1588]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1592:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1590]], i64 [[ULLX_CMPXCHG_DESIRED1591]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1593:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1592]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1593]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1589]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1594:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1592]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1248:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1249:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1248]] acquire, align 8
+// CHECK-NEXT: [[TMP1250:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1251:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1250]] acquire, align 8
+// CHECK-NEXT: [[TMP1252:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1253:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1252]] acquire, align 8
+// CHECK-NEXT: [[TMP1254:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1255:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1254]] acquire, align 8
+// CHECK-NEXT: [[TMP1256:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1257:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1256]] acquire, align 8
+// CHECK-NEXT: [[TMP1258:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1259:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1258]] acquire, align 8
+// CHECK-NEXT: [[TMP1260:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1261:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1260]] acquire, align 8
+// CHECK-NEXT: [[TMP1262:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1263:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1262]] acquire, align 8
+// CHECK-NEXT: [[TMP1264:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1265:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1264]], ptr [[LLX_ATOMIC_EXPECTED_PTR1595]], align 8
+// CHECK-NEXT: store i64 [[TMP1265]], ptr [[LLX_ATOMIC_DESIRED_PTR1596]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1598:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1595]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1599:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1596]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1600:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1598]], i64 [[LLX_CMPXCHG_DESIRED1599]] acquire acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1601:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1600]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1601]], ptr [[LLX_ATOMIC_EXPECTED_PTR1597]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1602:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1600]], 1
+// CHECK-NEXT: [[TMP1266:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1267:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1266]], ptr [[LLX_ATOMIC_EXPECTED_PTR1603]], align 8
+// CHECK-NEXT: store i64 [[TMP1267]], ptr [[LLX_ATOMIC_DESIRED_PTR1604]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1606:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1603]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1607:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1604]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1608:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1606]], i64 [[LLX_CMPXCHG_DESIRED1607]] acquire acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1609:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1608]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1609]], ptr [[LLX_ATOMIC_EXPECTED_PTR1605]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1610:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1608]], 1
+// CHECK-NEXT: [[TMP1268:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1269:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1268]], ptr [[LLX_ATOMIC_EXPECTED_PTR1611]], align 8
+// CHECK-NEXT: store i64 [[TMP1269]], ptr [[LLX_ATOMIC_DESIRED_PTR1612]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1614:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1611]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1615:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1612]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1616:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1614]], i64 [[LLX_CMPXCHG_DESIRED1615]] acquire acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1617:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1616]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1617]], ptr [[LLX_ATOMIC_EXPECTED_PTR1613]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1618:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1616]], 1
+// CHECK-NEXT: [[TMP1270:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1271:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1270]], ptr [[LLX_ATOMIC_EXPECTED_PTR1619]], align 8
+// CHECK-NEXT: store i64 [[TMP1271]], ptr [[LLX_ATOMIC_DESIRED_PTR1620]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1622:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1619]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1623:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1620]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1624:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1622]], i64 [[LLX_CMPXCHG_DESIRED1623]] acquire acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1625:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1624]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1625]], ptr [[LLX_ATOMIC_EXPECTED_PTR1621]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1626:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1624]], 1
+// CHECK-NEXT: [[TMP1272:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1273:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1272]] acquire, align 8
+// CHECK-NEXT: [[TMP1274:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1275:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1274]] acquire, align 8
+// CHECK-NEXT: [[TMP1276:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1277:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1276]] acquire, align 8
+// CHECK-NEXT: [[TMP1278:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1279:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1278]] acquire, align 8
+// CHECK-NEXT: [[TMP1280:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1281:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1280]] acquire, align 8
+// CHECK-NEXT: [[TMP1282:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1283:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1282]] acquire, align 8
+// CHECK-NEXT: [[TMP1284:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1285:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1284]] acquire, align 8
+// CHECK-NEXT: [[TMP1286:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1287:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1286]] acquire, align 8
+// CHECK-NEXT: [[TMP1288:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1289:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1288]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1627]], align 8
+// CHECK-NEXT: store i64 [[TMP1289]], ptr [[ULLX_ATOMIC_DESIRED_PTR1628]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1630:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1627]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1631:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1628]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1632:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1630]], i64 [[ULLX_CMPXCHG_DESIRED1631]] acquire acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1633:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1632]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1633]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1629]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1634:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1632]], 1
+// CHECK-NEXT: [[TMP1290:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1291:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1290]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1635]], align 8
+// CHECK-NEXT: store i64 [[TMP1291]], ptr [[ULLX_ATOMIC_DESIRED_PTR1636]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1638:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1635]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1639:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1636]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1640:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1638]], i64 [[ULLX_CMPXCHG_DESIRED1639]] acquire acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1641:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1640]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1641]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1637]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1642:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1640]], 1
+// CHECK-NEXT: [[TMP1292:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1293:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1292]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1643]], align 8
+// CHECK-NEXT: store i64 [[TMP1293]], ptr [[ULLX_ATOMIC_DESIRED_PTR1644]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1646:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1643]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1647:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1644]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1648:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1646]], i64 [[ULLX_CMPXCHG_DESIRED1647]] acquire acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1649:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1648]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1649]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1645]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1650:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1648]], 1
+// CHECK-NEXT: [[TMP1294:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1295:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1294]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1651]], align 8
+// CHECK-NEXT: store i64 [[TMP1295]], ptr [[ULLX_ATOMIC_DESIRED_PTR1652]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1654:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1651]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1655:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1652]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1656:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1654]], i64 [[ULLX_CMPXCHG_DESIRED1655]] acquire acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1657:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1656]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1657]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1653]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1658:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1656]], 1
+// CHECK-NEXT: [[TMP1296:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1297:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1296]] monotonic, align 8
+// CHECK-NEXT: [[TMP1298:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1299:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1298]] monotonic, align 8
+// CHECK-NEXT: [[TMP1300:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1301:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1300]] monotonic, align 8
+// CHECK-NEXT: [[TMP1302:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1303:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1302]] monotonic, align 8
+// CHECK-NEXT: [[TMP1304:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1305:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1304]] monotonic, align 8
+// CHECK-NEXT: [[TMP1306:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1307:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1306]] monotonic, align 8
+// CHECK-NEXT: [[TMP1308:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1309:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1308]] monotonic, align 8
+// CHECK-NEXT: [[TMP1310:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1311:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1310]] monotonic, align 8
+// CHECK-NEXT: [[TMP1312:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1313:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1312]], ptr [[LLX_ATOMIC_EXPECTED_PTR1659]], align 8
+// CHECK-NEXT: store i64 [[TMP1313]], ptr [[LLX_ATOMIC_DESIRED_PTR1660]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1662:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1659]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1663:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1660]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1664:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1662]], i64 [[LLX_CMPXCHG_DESIRED1663]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1665:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1664]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1665]], ptr [[LLX_ATOMIC_EXPECTED_PTR1661]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1666:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1664]], 1
+// CHECK-NEXT: [[TMP1314:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1315:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1314]], ptr [[LLX_ATOMIC_EXPECTED_PTR1667]], align 8
+// CHECK-NEXT: store i64 [[TMP1315]], ptr [[LLX_ATOMIC_DESIRED_PTR1668]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1670:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1667]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1671:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1668]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1672:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1670]], i64 [[LLX_CMPXCHG_DESIRED1671]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1673:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1672]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1673]], ptr [[LLX_ATOMIC_EXPECTED_PTR1669]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1674:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1672]], 1
+// CHECK-NEXT: [[TMP1316:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1317:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1316]], ptr [[LLX_ATOMIC_EXPECTED_PTR1675]], align 8
+// CHECK-NEXT: store i64 [[TMP1317]], ptr [[LLX_ATOMIC_DESIRED_PTR1676]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1678:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1675]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1679:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1676]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1680:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1678]], i64 [[LLX_CMPXCHG_DESIRED1679]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1681:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1680]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1681]], ptr [[LLX_ATOMIC_EXPECTED_PTR1677]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1682:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1680]], 1
+// CHECK-NEXT: [[TMP1318:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1319:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1318]], ptr [[LLX_ATOMIC_EXPECTED_PTR1683]], align 8
+// CHECK-NEXT: store i64 [[TMP1319]], ptr [[LLX_ATOMIC_DESIRED_PTR1684]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1686:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1683]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1687:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1684]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1688:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1686]], i64 [[LLX_CMPXCHG_DESIRED1687]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1689:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1688]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1689]], ptr [[LLX_ATOMIC_EXPECTED_PTR1685]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1690:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1688]], 1
+// CHECK-NEXT: [[TMP1320:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1321:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1320]] monotonic, align 8
+// CHECK-NEXT: [[TMP1322:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1323:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1322]] monotonic, align 8
+// CHECK-NEXT: [[TMP1324:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1325:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1324]] monotonic, align 8
+// CHECK-NEXT: [[TMP1326:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1327:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1326]] monotonic, align 8
+// CHECK-NEXT: [[TMP1328:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1329:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1328]] monotonic, align 8
+// CHECK-NEXT: [[TMP1330:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1331:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1330]] monotonic, align 8
+// CHECK-NEXT: [[TMP1332:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1333:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1332]] monotonic, align 8
+// CHECK-NEXT: [[TMP1334:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1335:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1334]] monotonic, align 8
+// CHECK-NEXT: [[TMP1336:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1337:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1336]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1691]], align 8
+// CHECK-NEXT: store i64 [[TMP1337]], ptr [[ULLX_ATOMIC_DESIRED_PTR1692]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1694:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1691]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1695:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1692]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1696:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1694]], i64 [[ULLX_CMPXCHG_DESIRED1695]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1697:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1696]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1697]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1693]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1698:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1696]], 1
+// CHECK-NEXT: [[TMP1338:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1339:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1338]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1699]], align 8
+// CHECK-NEXT: store i64 [[TMP1339]], ptr [[ULLX_ATOMIC_DESIRED_PTR1700]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1702:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1699]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1703:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1700]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1704:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1702]], i64 [[ULLX_CMPXCHG_DESIRED1703]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1705:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1704]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1705]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1701]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1706:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1704]], 1
+// CHECK-NEXT: [[TMP1340:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1341:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1340]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1707]], align 8
+// CHECK-NEXT: store i64 [[TMP1341]], ptr [[ULLX_ATOMIC_DESIRED_PTR1708]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1710:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1707]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1711:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1708]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1712:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1710]], i64 [[ULLX_CMPXCHG_DESIRED1711]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1713:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1712]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1713]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1709]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1714:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1712]], 1
+// CHECK-NEXT: [[TMP1342:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1343:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1342]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1715]], align 8
+// CHECK-NEXT: store i64 [[TMP1343]], ptr [[ULLX_ATOMIC_DESIRED_PTR1716]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1718:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1715]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1719:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1716]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1720:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1718]], i64 [[ULLX_CMPXCHG_DESIRED1719]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1721:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1720]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1721]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1717]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1722:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1720]], 1
// CHECK-NEXT: [[TMP1344:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1345:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1344]] monotonic, align 8
+// CHECK-NEXT: [[TMP1345:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1344]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1346:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1347:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1346]] monotonic, align 8
+// CHECK-NEXT: [[TMP1347:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1346]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1348:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1349:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1348]] monotonic, align 8
+// CHECK-NEXT: [[TMP1349:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1348]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1350:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1351:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1350]] monotonic, align 8
+// CHECK-NEXT: [[TMP1351:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1350]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1352:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1353:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1352]] monotonic, align 8
+// CHECK-NEXT: [[TMP1353:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1352]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1354:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1355:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1354]] monotonic, align 8
+// CHECK-NEXT: [[TMP1355:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1354]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1356:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1357:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1356]] monotonic, align 8
+// CHECK-NEXT: [[TMP1357:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1356]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1358:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1359:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1358]] monotonic, align 8
+// CHECK-NEXT: [[TMP1359:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1358]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1360:%.*]] = load i64, ptr [[LLE]], align 8
// CHECK-NEXT: [[TMP1361:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1362:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1360]], i64 [[TMP1361]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1363:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1364:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1365:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1363]], i64 [[TMP1364]] monotonic monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP1360]], ptr [[LLX_ATOMIC_EXPECTED_PTR1723]], align 8
+// CHECK-NEXT: store i64 [[TMP1361]], ptr [[LLX_ATOMIC_DESIRED_PTR1724]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1726:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1723]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1727:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1724]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1728:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1726]], i64 [[LLX_CMPXCHG_DESIRED1727]] release monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1729:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1728]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1729]], ptr [[LLX_ATOMIC_EXPECTED_PTR1725]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1730:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1728]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1362:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1363:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1362]], ptr [[LLX_ATOMIC_EXPECTED_PTR1731]], align 8
+// CHECK-NEXT: store i64 [[TMP1363]], ptr [[LLX_ATOMIC_DESIRED_PTR1732]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1734:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1731]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1735:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1732]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1736:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1734]], i64 [[LLX_CMPXCHG_DESIRED1735]] release monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1737:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1736]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1737]], ptr [[LLX_ATOMIC_EXPECTED_PTR1733]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1738:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1736]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1364:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1365:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1364]], ptr [[LLX_ATOMIC_EXPECTED_PTR1739]], align 8
+// CHECK-NEXT: store i64 [[TMP1365]], ptr [[LLX_ATOMIC_DESIRED_PTR1740]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1742:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1739]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1743:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1740]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1744:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1742]], i64 [[LLX_CMPXCHG_DESIRED1743]] release monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1745:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1744]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1745]], ptr [[LLX_ATOMIC_EXPECTED_PTR1741]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1746:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1744]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1366:%.*]] = load i64, ptr [[LLE]], align 8
// CHECK-NEXT: [[TMP1367:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1368:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1366]], i64 [[TMP1367]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1369:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1370:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1371:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1369]], i64 [[TMP1370]] monotonic monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP1366]], ptr [[LLX_ATOMIC_EXPECTED_PTR1747]], align 8
+// CHECK-NEXT: store i64 [[TMP1367]], ptr [[LLX_ATOMIC_DESIRED_PTR1748]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1750:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1747]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1751:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1748]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1752:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1750]], i64 [[LLX_CMPXCHG_DESIRED1751]] release monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1753:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1752]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1753]], ptr [[LLX_ATOMIC_EXPECTED_PTR1749]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1754:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1752]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1368:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1369:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1368]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1370:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1371:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1370]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1372:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1373:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1372]] monotonic, align 8
+// CHECK-NEXT: [[TMP1373:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1372]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1374:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1375:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1374]] monotonic, align 8
+// CHECK-NEXT: [[TMP1375:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1374]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1376:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1377:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1376]] monotonic, align 8
+// CHECK-NEXT: [[TMP1377:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1376]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1378:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1379:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1378]] monotonic, align 8
+// CHECK-NEXT: [[TMP1379:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1378]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1380:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1381:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1380]] monotonic, align 8
+// CHECK-NEXT: [[TMP1381:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1380]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1382:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1383:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1382]] monotonic, align 8
+// CHECK-NEXT: [[TMP1383:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1382]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1384:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1385:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1384]] monotonic, align 8
+// CHECK-NEXT: [[TMP1385:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1384]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1755]], align 8
+// CHECK-NEXT: store i64 [[TMP1385]], ptr [[ULLX_ATOMIC_DESIRED_PTR1756]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1758:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1755]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1759:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1756]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1760:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1758]], i64 [[ULLX_CMPXCHG_DESIRED1759]] release monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1761:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1760]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1761]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1757]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1762:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1760]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1386:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1387:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1386]] monotonic, align 8
+// CHECK-NEXT: [[TMP1387:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1386]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1763]], align 8
+// CHECK-NEXT: store i64 [[TMP1387]], ptr [[ULLX_ATOMIC_DESIRED_PTR1764]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1766:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1763]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1767:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1764]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1768:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1766]], i64 [[ULLX_CMPXCHG_DESIRED1767]] release monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1769:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1768]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1769]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1765]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1770:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1768]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1388:%.*]] = load i64, ptr [[ULLE]], align 8
// CHECK-NEXT: [[TMP1389:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1390:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1388]], i64 [[TMP1389]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1391:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1392:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1393:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1391]], i64 [[TMP1392]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1394:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1395:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1396:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1394]], i64 [[TMP1395]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1397:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1398:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1399:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1397]], i64 [[TMP1398]] monotonic monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP1388]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1771]], align 8
+// CHECK-NEXT: store i64 [[TMP1389]], ptr [[ULLX_ATOMIC_DESIRED_PTR1772]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1774:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1771]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1775:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1772]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1776:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1774]], i64 [[ULLX_CMPXCHG_DESIRED1775]] release monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1777:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1776]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1777]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1773]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1778:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1776]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1390:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1391:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1390]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1779]], align 8
+// CHECK-NEXT: store i64 [[TMP1391]], ptr [[ULLX_ATOMIC_DESIRED_PTR1780]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1782:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1779]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1783:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1780]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1784:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1782]], i64 [[ULLX_CMPXCHG_DESIRED1783]] release monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1785:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1784]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1785]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1781]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1786:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1784]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1392:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1393:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1392]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1394:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1395:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1394]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1396:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1397:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1396]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1398:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP1399:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1398]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1400:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1401:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1400]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1401:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1400]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1402:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1403:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1402]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1403:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1402]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1404:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1405:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1404]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1405:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1404]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1406:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1407:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1406]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1407:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1406]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1408:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1409:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1408]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1409:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1408]], ptr [[LLX_ATOMIC_EXPECTED_PTR1787]], align 8
+// CHECK-NEXT: store i64 [[TMP1409]], ptr [[LLX_ATOMIC_DESIRED_PTR1788]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1790:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1787]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1791:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1788]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1792:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1790]], i64 [[LLX_CMPXCHG_DESIRED1791]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1793:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1792]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1793]], ptr [[LLX_ATOMIC_EXPECTED_PTR1789]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1794:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1792]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1410:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1411:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1410]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1411:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1410]], ptr [[LLX_ATOMIC_EXPECTED_PTR1795]], align 8
+// CHECK-NEXT: store i64 [[TMP1411]], ptr [[LLX_ATOMIC_DESIRED_PTR1796]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1798:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1795]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1799:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1796]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1800:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1798]], i64 [[LLX_CMPXCHG_DESIRED1799]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1801:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1800]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1801]], ptr [[LLX_ATOMIC_EXPECTED_PTR1797]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1802:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1800]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1412:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1413:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1412]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1413:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1412]], ptr [[LLX_ATOMIC_EXPECTED_PTR1803]], align 8
+// CHECK-NEXT: store i64 [[TMP1413]], ptr [[LLX_ATOMIC_DESIRED_PTR1804]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1806:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1803]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1807:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1804]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1808:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1806]], i64 [[LLX_CMPXCHG_DESIRED1807]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1809:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1808]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1809]], ptr [[LLX_ATOMIC_EXPECTED_PTR1805]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1810:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1808]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1414:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1415:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1414]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1415:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1414]], ptr [[LLX_ATOMIC_EXPECTED_PTR1811]], align 8
+// CHECK-NEXT: store i64 [[TMP1415]], ptr [[LLX_ATOMIC_DESIRED_PTR1812]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED1814:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1811]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED1815:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR1812]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR1816:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED1814]], i64 [[LLX_CMPXCHG_DESIRED1815]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV1817:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1816]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV1817]], ptr [[LLX_ATOMIC_EXPECTED_PTR1813]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS1818:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR1816]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1416:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1417:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1418:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1416]], i64 [[TMP1417]] acq_rel acquire, align 8
+// CHECK-NEXT: [[TMP1416:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1417:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1416]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1419:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1420:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1421:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1419]], i64 [[TMP1420]] acq_rel acquire, align 8
+// CHECK-NEXT: [[TMP1418:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1419:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1418]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1422:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1423:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1424:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1422]], i64 [[TMP1423]] acq_rel acquire, align 8
+// CHECK-NEXT: [[TMP1420:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1421:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1420]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1425:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1426:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1427:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1425]], i64 [[TMP1426]] acq_rel acquire, align 8
+// CHECK-NEXT: [[TMP1422:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1423:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1422]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1424:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1425:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1424]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1426:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP1427:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1426]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1428:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1429:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1428]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1429:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1428]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1430:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1431:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1430]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1431:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1430]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1432:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1433:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1432]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1433:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1432]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1819]], align 8
+// CHECK-NEXT: store i64 [[TMP1433]], ptr [[ULLX_ATOMIC_DESIRED_PTR1820]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1822:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1819]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1823:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1820]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1824:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1822]], i64 [[ULLX_CMPXCHG_DESIRED1823]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1825:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1824]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1825]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1821]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1826:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1824]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1434:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1435:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1434]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1435:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1434]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1827]], align 8
+// CHECK-NEXT: store i64 [[TMP1435]], ptr [[ULLX_ATOMIC_DESIRED_PTR1828]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1830:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1827]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1831:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1828]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1832:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1830]], i64 [[ULLX_CMPXCHG_DESIRED1831]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1833:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1832]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1833]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1829]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1834:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1832]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1436:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1437:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1436]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1437:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1436]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1835]], align 8
+// CHECK-NEXT: store i64 [[TMP1437]], ptr [[ULLX_ATOMIC_DESIRED_PTR1836]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1838:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1835]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1839:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1836]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1840:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1838]], i64 [[ULLX_CMPXCHG_DESIRED1839]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1841:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1840]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1841]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1837]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1842:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1840]], 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP1438:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1439:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1438]] acq_rel, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1440:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1441:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1440]] acq_rel, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1442:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1443:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1442]] acq_rel, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1444:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1445:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1446:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1444]], i64 [[TMP1445]] acq_rel acquire, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1447:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1448:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1449:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1447]], i64 [[TMP1448]] acq_rel acquire, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1450:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1451:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1452:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1450]], i64 [[TMP1451]] acq_rel acquire, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1453:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1454:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1455:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1453]], i64 [[TMP1454]] acq_rel acquire, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1456:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1457:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1456]] acquire, align 8
-// CHECK-NEXT: [[TMP1458:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1459:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1458]] acquire, align 8
-// CHECK-NEXT: [[TMP1460:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1461:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1460]] acquire, align 8
-// CHECK-NEXT: [[TMP1462:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1463:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1462]] acquire, align 8
-// CHECK-NEXT: [[TMP1464:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1465:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1464]] acquire, align 8
-// CHECK-NEXT: [[TMP1466:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1467:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1466]] acquire, align 8
-// CHECK-NEXT: [[TMP1468:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1469:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1468]] acquire, align 8
-// CHECK-NEXT: [[TMP1470:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1471:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1470]] acquire, align 8
-// CHECK-NEXT: [[TMP1472:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1473:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1474:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1472]], i64 [[TMP1473]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP1475:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1476:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1477:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1475]], i64 [[TMP1476]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP1478:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1479:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1480:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1478]], i64 [[TMP1479]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP1481:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1482:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1483:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1481]], i64 [[TMP1482]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP1484:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1485:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1484]] acquire, align 8
-// CHECK-NEXT: [[TMP1486:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1487:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1486]] acquire, align 8
-// CHECK-NEXT: [[TMP1488:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1489:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1488]] acquire, align 8
-// CHECK-NEXT: [[TMP1490:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1491:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1490]] acquire, align 8
-// CHECK-NEXT: [[TMP1492:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1493:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1492]] acquire, align 8
-// CHECK-NEXT: [[TMP1494:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1495:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1494]] acquire, align 8
-// CHECK-NEXT: [[TMP1496:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1497:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1496]] acquire, align 8
-// CHECK-NEXT: [[TMP1498:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1499:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1498]] acquire, align 8
-// CHECK-NEXT: [[TMP1500:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1501:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1502:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1500]], i64 [[TMP1501]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP1503:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1504:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1505:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1503]], i64 [[TMP1504]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP1506:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1507:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1508:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1506]], i64 [[TMP1507]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP1509:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1510:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1511:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1509]], i64 [[TMP1510]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP1512:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1513:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1512]] monotonic, align 8
-// CHECK-NEXT: [[TMP1514:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1515:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1514]] monotonic, align 8
-// CHECK-NEXT: [[TMP1516:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1517:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1516]] monotonic, align 8
-// CHECK-NEXT: [[TMP1518:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1519:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1518]] monotonic, align 8
-// CHECK-NEXT: [[TMP1520:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1521:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1520]] monotonic, align 8
-// CHECK-NEXT: [[TMP1522:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1523:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1522]] monotonic, align 8
-// CHECK-NEXT: [[TMP1524:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1525:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1524]] monotonic, align 8
-// CHECK-NEXT: [[TMP1526:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1527:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1526]] monotonic, align 8
-// CHECK-NEXT: [[TMP1528:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1529:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1530:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1528]], i64 [[TMP1529]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1531:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1532:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1533:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1531]], i64 [[TMP1532]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1534:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1535:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1536:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1534]], i64 [[TMP1535]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1537:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1538:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1539:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1537]], i64 [[TMP1538]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1540:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1541:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1540]] monotonic, align 8
-// CHECK-NEXT: [[TMP1542:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1543:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1542]] monotonic, align 8
-// CHECK-NEXT: [[TMP1544:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1545:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1544]] monotonic, align 8
-// CHECK-NEXT: [[TMP1546:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1547:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1546]] monotonic, align 8
-// CHECK-NEXT: [[TMP1548:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1549:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1548]] monotonic, align 8
-// CHECK-NEXT: [[TMP1550:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1551:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1550]] monotonic, align 8
-// CHECK-NEXT: [[TMP1552:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1553:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1552]] monotonic, align 8
-// CHECK-NEXT: [[TMP1554:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1555:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1554]] monotonic, align 8
-// CHECK-NEXT: [[TMP1556:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1557:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1558:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1556]], i64 [[TMP1557]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1559:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1560:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1561:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1559]], i64 [[TMP1560]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1562:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1563:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1564:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1562]], i64 [[TMP1563]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1565:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1566:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1567:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1565]], i64 [[TMP1566]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP1568:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1569:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1568]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1570:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1571:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1570]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1572:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1573:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1572]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1574:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1575:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1574]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1576:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1577:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1576]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1578:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1579:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1578]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1580:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1581:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1580]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1582:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1583:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1582]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1584:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1585:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1586:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1584]], i64 [[TMP1585]] release monotonic, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1587:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1588:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1589:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1587]], i64 [[TMP1588]] release monotonic, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1590:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1591:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1592:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1590]], i64 [[TMP1591]] release monotonic, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1593:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1594:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1595:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1593]], i64 [[TMP1594]] release monotonic, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1596:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1597:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1596]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1598:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1599:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1598]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1600:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1601:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1600]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1602:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1603:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1602]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1604:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1605:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1604]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1606:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1607:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1606]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1608:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1609:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1608]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1610:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1611:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1610]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1612:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1613:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1614:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1612]], i64 [[TMP1613]] release monotonic, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1615:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1616:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1617:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1615]], i64 [[TMP1616]] release monotonic, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1618:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1619:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1620:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1618]], i64 [[TMP1619]] release monotonic, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1621:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1622:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1623:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1621]], i64 [[TMP1622]] release monotonic, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1624:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1625:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1624]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1626:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1627:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1626]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1628:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1629:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1628]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1630:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1631:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1630]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1632:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1633:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1632]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1634:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1635:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1634]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1636:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1637:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP1636]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1638:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1639:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP1638]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1640:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1641:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1642:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1640]], i64 [[TMP1641]] seq_cst seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1643:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1644:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1645:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1643]], i64 [[TMP1644]] seq_cst seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1646:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1647:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1648:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1646]], i64 [[TMP1647]] seq_cst seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1649:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP1650:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP1651:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP1649]], i64 [[TMP1650]] seq_cst seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1652:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1653:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1652]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1654:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1655:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1654]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1656:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1657:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1656]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1658:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1659:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1658]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1660:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1661:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1660]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1662:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1663:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1662]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1664:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1665:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP1664]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1666:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1667:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP1666]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1668:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1669:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1670:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1668]], i64 [[TMP1669]] seq_cst seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1671:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1672:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1673:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1671]], i64 [[TMP1672]] seq_cst seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1674:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1675:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1676:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1674]], i64 [[TMP1675]] seq_cst seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1677:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP1678:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP1679:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP1677]], i64 [[TMP1678]] seq_cst seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1680:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1681:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1680]] monotonic, align 4
-// CHECK-NEXT: [[TMP1682:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1683:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1682]] monotonic, align 4
-// CHECK-NEXT: [[TMP1684:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1685:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1684]] monotonic, align 4
-// CHECK-NEXT: [[TMP1686:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1687:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1686]] monotonic, align 4
-// CHECK-NEXT: [[TMP1688:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1689:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1688]] monotonic, align 4
-// CHECK-NEXT: [[TMP1690:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1691:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1690]] monotonic, align 4
-// CHECK-NEXT: [[TMP1692:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1693:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1692]] monotonic, align 4
-// CHECK-NEXT: [[TMP1694:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1695:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1694]] monotonic, align 4
-// CHECK-NEXT: [[TMP1696:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1697:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1696]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1698:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1699:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1698]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1700:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1701:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1700]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1702:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1703:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1702]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1704:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1705:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1704]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1706:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1707:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1706]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1708:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1709:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1708]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1710:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1711:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1710]] acq_rel, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1712:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1713:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1712]] acquire, align 4
-// CHECK-NEXT: [[TMP1714:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1715:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1714]] acquire, align 4
-// CHECK-NEXT: [[TMP1716:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1717:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1716]] acquire, align 4
-// CHECK-NEXT: [[TMP1718:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1719:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1718]] acquire, align 4
-// CHECK-NEXT: [[TMP1720:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1721:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1720]] acquire, align 4
-// CHECK-NEXT: [[TMP1722:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1723:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1722]] acquire, align 4
-// CHECK-NEXT: [[TMP1724:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1725:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1724]] acquire, align 4
-// CHECK-NEXT: [[TMP1726:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1727:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1726]] acquire, align 4
-// CHECK-NEXT: [[TMP1728:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1729:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1728]] monotonic, align 4
-// CHECK-NEXT: [[TMP1730:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1731:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1730]] monotonic, align 4
-// CHECK-NEXT: [[TMP1732:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1733:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1732]] monotonic, align 4
-// CHECK-NEXT: [[TMP1734:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1735:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1734]] monotonic, align 4
-// CHECK-NEXT: [[TMP1736:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1737:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1736]] monotonic, align 4
-// CHECK-NEXT: [[TMP1738:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1739:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1738]] monotonic, align 4
-// CHECK-NEXT: [[TMP1740:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1741:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1740]] monotonic, align 4
-// CHECK-NEXT: [[TMP1742:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1743:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1742]] monotonic, align 4
-// CHECK-NEXT: [[TMP1744:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1745:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1744]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1746:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1747:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1746]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1748:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1749:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1748]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1750:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1751:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1750]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1752:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1753:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1752]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1754:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1755:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1754]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1756:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1757:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1756]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1758:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1759:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1758]] release, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1760:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1761:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1760]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1762:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1763:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1762]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1764:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1765:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1764]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1766:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1767:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1766]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1768:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1769:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1768]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1770:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1771:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1770]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1772:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1773:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1772]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1774:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP1775:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1774]] seq_cst, align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1776:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1777:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1776]] monotonic, align 8
-// CHECK-NEXT: [[TMP1778:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1779:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1778]] monotonic, align 8
-// CHECK-NEXT: [[TMP1780:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1781:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1780]] monotonic, align 8
-// CHECK-NEXT: [[TMP1782:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1783:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1782]] monotonic, align 8
-// CHECK-NEXT: [[TMP1784:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1785:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1784]] monotonic, align 8
-// CHECK-NEXT: [[TMP1786:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1787:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1786]] monotonic, align 8
-// CHECK-NEXT: [[TMP1788:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1789:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1788]] monotonic, align 8
-// CHECK-NEXT: [[TMP1790:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1791:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1790]] monotonic, align 8
-// CHECK-NEXT: [[TMP1792:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1793:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1792]] acq_rel, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1794:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1795:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1794]] acq_rel, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1796:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1797:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1796]] acq_rel, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1798:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1799:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1798]] acq_rel, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1800:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1801:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1800]] acq_rel, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1802:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1803:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1802]] acq_rel, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1804:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1805:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1804]] acq_rel, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1806:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1807:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1806]] acq_rel, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1808:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1809:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1808]] acquire, align 8
-// CHECK-NEXT: [[TMP1810:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1811:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1810]] acquire, align 8
-// CHECK-NEXT: [[TMP1812:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1813:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1812]] acquire, align 8
-// CHECK-NEXT: [[TMP1814:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1815:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1814]] acquire, align 8
-// CHECK-NEXT: [[TMP1816:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1817:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1816]] acquire, align 8
-// CHECK-NEXT: [[TMP1818:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1819:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1818]] acquire, align 8
-// CHECK-NEXT: [[TMP1820:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1821:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1820]] acquire, align 8
-// CHECK-NEXT: [[TMP1822:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1823:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1822]] acquire, align 8
-// CHECK-NEXT: [[TMP1824:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1825:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1824]] monotonic, align 8
-// CHECK-NEXT: [[TMP1826:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1827:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1826]] monotonic, align 8
-// CHECK-NEXT: [[TMP1828:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1829:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1828]] monotonic, align 8
-// CHECK-NEXT: [[TMP1830:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1831:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1830]] monotonic, align 8
-// CHECK-NEXT: [[TMP1832:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1833:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1832]] monotonic, align 8
-// CHECK-NEXT: [[TMP1834:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1835:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1834]] monotonic, align 8
-// CHECK-NEXT: [[TMP1836:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1837:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1836]] monotonic, align 8
-// CHECK-NEXT: [[TMP1838:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1839:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1838]] monotonic, align 8
-// CHECK-NEXT: [[TMP1840:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1841:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1840]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1842:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1843:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1842]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1844:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1845:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1844]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1846:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1847:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1846]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1848:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1849:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1848]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1850:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1851:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1850]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1852:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1853:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1852]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1854:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1855:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1854]] release, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1856:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1857:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1856]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1858:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1859:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1858]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1860:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1861:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1860]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1862:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1863:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1862]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1864:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1865:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1864]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1866:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1867:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1866]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1868:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1869:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1868]] seq_cst, align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1870:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP1871:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1870]] seq_cst, align 8
+// CHECK-NEXT: [[TMP1439:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP1438]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1843]], align 8
+// CHECK-NEXT: store i64 [[TMP1439]], ptr [[ULLX_ATOMIC_DESIRED_PTR1844]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED1846:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1843]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED1847:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR1844]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR1848:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED1846]], i64 [[ULLX_CMPXCHG_DESIRED1847]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV1849:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1848]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV1849]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1845]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS1850:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR1848]], 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1440:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1441:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1440]] monotonic, align 4
+// CHECK-NEXT: [[TMP1442:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1443:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1442]] monotonic, align 4
+// CHECK-NEXT: [[TMP1444:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1445:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1444]] monotonic, align 4
+// CHECK-NEXT: [[TMP1446:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1447:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1446]] monotonic, align 4
+// CHECK-NEXT: [[TMP1448:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1449:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1448]] monotonic, align 4
+// CHECK-NEXT: [[TMP1450:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1451:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1450]] monotonic, align 4
+// CHECK-NEXT: [[TMP1452:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1453:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1452]] monotonic, align 4
+// CHECK-NEXT: [[TMP1454:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1455:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1454]] monotonic, align 4
+// CHECK-NEXT: [[TMP1456:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1457:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1456]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1458:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1459:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1458]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1460:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1461:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1460]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1462:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1463:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1462]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1464:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1465:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1464]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1466:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1467:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1466]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1468:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1469:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1468]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1470:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1471:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1470]] acq_rel, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1472:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1473:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1472]] acquire, align 4
+// CHECK-NEXT: [[TMP1474:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1475:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1474]] acquire, align 4
+// CHECK-NEXT: [[TMP1476:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1477:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1476]] acquire, align 4
+// CHECK-NEXT: [[TMP1478:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1479:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1478]] acquire, align 4
+// CHECK-NEXT: [[TMP1480:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1481:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1480]] acquire, align 4
+// CHECK-NEXT: [[TMP1482:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1483:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1482]] acquire, align 4
+// CHECK-NEXT: [[TMP1484:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1485:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1484]] acquire, align 4
+// CHECK-NEXT: [[TMP1486:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1487:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1486]] acquire, align 4
+// CHECK-NEXT: [[TMP1488:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1489:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1488]] monotonic, align 4
+// CHECK-NEXT: [[TMP1490:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1491:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1490]] monotonic, align 4
+// CHECK-NEXT: [[TMP1492:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1493:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1492]] monotonic, align 4
+// CHECK-NEXT: [[TMP1494:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1495:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1494]] monotonic, align 4
+// CHECK-NEXT: [[TMP1496:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1497:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1496]] monotonic, align 4
+// CHECK-NEXT: [[TMP1498:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1499:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1498]] monotonic, align 4
+// CHECK-NEXT: [[TMP1500:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1501:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1500]] monotonic, align 4
+// CHECK-NEXT: [[TMP1502:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1503:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1502]] monotonic, align 4
+// CHECK-NEXT: [[TMP1504:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1505:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1504]] release, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1506:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1507:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1506]] release, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1508:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1509:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1508]] release, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1510:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1511:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1510]] release, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1512:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1513:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1512]] release, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1514:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1515:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1514]] release, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1516:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1517:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1516]] release, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1518:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1519:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1518]] release, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1520:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1521:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1520]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1522:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1523:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1522]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1524:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1525:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1524]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1526:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1527:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1526]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1528:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1529:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1528]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1530:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1531:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1530]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1532:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1533:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP1532]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1534:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP1535:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP1534]] seq_cst, align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1536:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1537:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1536]] monotonic, align 8
+// CHECK-NEXT: [[TMP1538:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1539:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1538]] monotonic, align 8
+// CHECK-NEXT: [[TMP1540:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1541:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1540]] monotonic, align 8
+// CHECK-NEXT: [[TMP1542:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1543:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1542]] monotonic, align 8
+// CHECK-NEXT: [[TMP1544:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1545:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1544]] monotonic, align 8
+// CHECK-NEXT: [[TMP1546:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1547:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1546]] monotonic, align 8
+// CHECK-NEXT: [[TMP1548:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1549:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1548]] monotonic, align 8
+// CHECK-NEXT: [[TMP1550:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1551:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1550]] monotonic, align 8
+// CHECK-NEXT: [[TMP1552:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1553:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1552]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1554:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1555:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1554]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1556:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1557:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1556]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1558:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1559:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1558]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1560:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1561:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1560]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1562:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1563:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1562]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1564:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1565:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1564]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1566:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1567:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1566]] acq_rel, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1568:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1569:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1568]] acquire, align 8
+// CHECK-NEXT: [[TMP1570:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1571:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1570]] acquire, align 8
+// CHECK-NEXT: [[TMP1572:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1573:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1572]] acquire, align 8
+// CHECK-NEXT: [[TMP1574:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1575:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1574]] acquire, align 8
+// CHECK-NEXT: [[TMP1576:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1577:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1576]] acquire, align 8
+// CHECK-NEXT: [[TMP1578:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1579:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1578]] acquire, align 8
+// CHECK-NEXT: [[TMP1580:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1581:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1580]] acquire, align 8
+// CHECK-NEXT: [[TMP1582:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1583:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1582]] acquire, align 8
+// CHECK-NEXT: [[TMP1584:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1585:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1584]] monotonic, align 8
+// CHECK-NEXT: [[TMP1586:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1587:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1586]] monotonic, align 8
+// CHECK-NEXT: [[TMP1588:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1589:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1588]] monotonic, align 8
+// CHECK-NEXT: [[TMP1590:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1591:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1590]] monotonic, align 8
+// CHECK-NEXT: [[TMP1592:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1593:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1592]] monotonic, align 8
+// CHECK-NEXT: [[TMP1594:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1595:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1594]] monotonic, align 8
+// CHECK-NEXT: [[TMP1596:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1597:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1596]] monotonic, align 8
+// CHECK-NEXT: [[TMP1598:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1599:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1598]] monotonic, align 8
+// CHECK-NEXT: [[TMP1600:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1601:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1600]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1602:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1603:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1602]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1604:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1605:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1604]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1606:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1607:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1606]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1608:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1609:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1608]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1610:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1611:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1610]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1612:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1613:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1612]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1614:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1615:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1614]] release, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1616:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1617:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1616]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1618:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1619:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1618]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1620:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1621:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1620]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1622:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1623:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1622]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1624:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1625:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1624]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1626:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1627:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1626]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1628:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1629:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP1628]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1630:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1631:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP1630]] seq_cst, align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: ret void
//
@@ -16246,6 +18646,2166 @@ double fail_dxevd() {
// CHECK-NEXT: [[DV:%.*]] = alloca double, align 8
// CHECK-NEXT: [[DE:%.*]] = alloca double, align 8
// CHECK-NEXT: [[DD:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR1:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR2:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR3:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR4:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR11:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR12:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR13:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR20:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR21:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR22:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR30:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR31:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR32:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR39:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR40:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR41:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR50:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR51:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR52:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR58:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR59:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR60:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR66:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR67:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR68:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR77:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR78:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR79:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR88:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR89:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR90:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR97:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR98:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR99:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR106:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR107:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR108:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR116:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR117:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR118:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR126:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR127:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR128:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR137:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR138:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR139:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR148:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR149:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR150:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR156:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR157:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR158:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR164:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR165:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR166:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR175:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR176:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR177:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR186:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR187:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR188:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR195:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR196:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR197:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR204:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR205:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR206:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR214:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR215:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR216:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR224:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR225:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR226:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR235:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR236:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR237:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR246:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR247:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR248:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR254:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR255:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR256:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR262:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR263:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR264:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR273:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR274:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR275:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR284:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR285:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR286:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR293:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR294:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR295:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR302:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR303:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR304:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR312:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR313:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR314:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR322:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR323:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR324:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR333:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR334:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR335:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR344:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR345:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR346:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR352:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR353:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR354:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR360:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR361:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR362:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR371:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR372:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR373:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR382:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR383:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR384:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR391:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR392:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR393:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR400:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR401:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR402:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR410:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR411:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR412:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR420:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR421:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR422:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR431:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR432:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR433:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR442:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR443:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR444:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR450:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR451:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR452:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR458:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR459:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR460:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR469:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR470:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR471:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR480:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR481:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR482:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR489:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR490:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR491:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR498:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR499:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR500:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR508:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR509:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR510:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR518:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR519:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR520:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR529:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR530:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR531:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR540:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR541:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR542:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR548:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR549:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR550:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR556:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR557:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR558:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR567:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR568:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR569:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR578:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR579:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR580:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR581:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR588:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR589:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR590:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR597:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR598:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR599:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR607:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR608:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR609:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR616:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR617:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR618:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR627:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR628:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR629:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR635:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR636:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR637:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR643:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR644:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR645:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR654:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR655:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR656:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR665:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR666:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR667:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR674:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR675:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR676:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR683:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR684:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR685:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR693:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR694:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR695:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR703:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR704:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR705:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR714:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR715:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR716:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR725:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR726:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR727:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR733:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR734:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR735:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR741:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR742:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR743:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR752:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR753:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR754:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR763:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR764:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR765:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR772:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR773:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR774:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR781:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR782:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR783:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR791:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR792:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR793:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR801:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR802:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR803:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR812:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR813:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR814:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR823:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR824:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR825:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR831:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR832:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR833:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR839:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR840:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR841:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR850:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR851:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR852:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR861:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR862:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR863:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR870:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR871:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR872:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR879:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR880:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR881:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR889:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR890:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR891:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR899:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR900:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR901:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR910:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR911:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR912:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR921:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR922:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR923:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR929:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR930:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR931:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR937:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR938:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR939:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR948:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR949:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR950:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR959:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR960:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR961:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR968:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR969:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR970:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR977:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR978:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR979:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR987:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR988:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR989:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR997:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR998:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR999:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1008:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR1009:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1010:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1019:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR1020:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1021:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1027:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR1028:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1029:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1035:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR1036:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1037:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1046:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR1047:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1048:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1057:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR1058:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1059:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1066:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR1067:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1068:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1075:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR1076:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1077:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1085:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR1086:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1087:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1095:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR1096:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1097:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1106:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR1107:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1108:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1117:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR1118:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1119:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1125:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR1126:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1127:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1133:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR1134:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1135:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1144:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR1145:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1146:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1155:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1156:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1157:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1158:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1165:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1166:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1167:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1174:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1175:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1176:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1184:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1185:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1186:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1193:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1194:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1195:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1204:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1205:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1206:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1212:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1213:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1214:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1220:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1221:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1222:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1231:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1232:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1233:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1242:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1243:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1244:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1251:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1252:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1253:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1260:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1261:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1262:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1270:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1271:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1272:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1280:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1281:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1282:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1291:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1292:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1293:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1302:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1303:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1304:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1310:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1311:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1312:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1318:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1319:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1320:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1329:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1330:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1331:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1340:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1341:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1342:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1349:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1350:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1351:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1358:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1359:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1360:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1368:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1369:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1370:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1378:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1379:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1380:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1389:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1390:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1391:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1400:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1401:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1402:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1408:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1409:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1410:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1416:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1417:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1418:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1427:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1428:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1429:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1438:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1439:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1440:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1447:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1448:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1449:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1456:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1457:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1458:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1466:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1467:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1468:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1476:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1477:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1478:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1487:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1488:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1489:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1498:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1499:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1500:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1506:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1507:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1508:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1514:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1515:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1516:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1525:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1526:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1527:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1536:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1537:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1538:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1545:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1546:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1547:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1554:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1555:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1556:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1564:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1565:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1566:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1574:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1575:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1576:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1585:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1586:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1587:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1596:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1597:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1598:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1604:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1605:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1606:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1612:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1613:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1614:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1623:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1624:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1625:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1634:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1635:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1636:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1643:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1644:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1645:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1652:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1653:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1654:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1662:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1663:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1664:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1672:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1673:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1674:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1683:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1684:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1685:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1694:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1695:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1696:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1702:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1703:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1704:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1710:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1711:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1712:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1721:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR1722:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1723:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1732:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1733:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1734:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1735:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1742:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1743:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1744:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1751:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1752:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1753:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1761:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1762:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1763:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1770:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1771:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1772:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1781:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1782:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1783:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1789:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1790:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1791:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1797:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1798:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1799:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1808:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1809:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1810:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1819:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1820:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1821:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1828:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1829:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1830:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1837:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1838:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1839:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1847:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1848:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1849:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1857:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1858:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1859:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1868:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1869:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1870:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1879:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1880:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1881:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1887:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1888:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1889:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1895:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1896:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1897:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1906:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1907:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1908:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1917:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1918:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1919:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1926:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1927:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1928:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1935:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1936:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1937:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1945:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1946:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1947:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1955:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1956:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1957:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1966:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1967:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1968:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1977:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1978:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1979:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1985:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1986:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1987:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1993:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR1994:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1995:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2004:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2005:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2006:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2015:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2016:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2017:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2024:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2025:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2026:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2033:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2034:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2035:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2043:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2044:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2045:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2053:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2054:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2055:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2064:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2065:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2066:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2075:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2076:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2077:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2083:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2084:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2085:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2091:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2092:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2093:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2102:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2103:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2104:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2113:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2114:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2115:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2122:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2123:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2124:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2131:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2132:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2133:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2141:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2142:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2143:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2151:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2152:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2153:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2162:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2163:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2164:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2173:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2174:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2175:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2181:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2182:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2183:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2189:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2190:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2191:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2200:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2201:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2202:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2211:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2212:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2213:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2220:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2221:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2222:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2229:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2230:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2231:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2239:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2240:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2241:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2249:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2250:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2251:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2260:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2261:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2262:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2271:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2272:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2273:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2279:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2280:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2281:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2287:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2288:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2289:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2298:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR2299:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2300:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2309:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2310:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2311:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2312:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2319:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2320:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2321:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2328:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2329:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2330:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2338:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2339:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2340:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2347:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2348:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2349:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2358:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2359:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2360:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2366:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2367:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2368:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2374:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2375:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2376:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2385:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2386:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2387:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2396:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2397:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2398:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2405:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2406:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2407:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2414:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2415:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2416:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2424:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2425:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2426:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2434:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2435:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2436:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2445:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2446:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2447:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2456:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2457:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2458:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2464:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2465:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2466:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2472:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2473:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2474:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2483:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2484:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2485:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2494:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2495:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2496:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2503:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2504:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2505:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2512:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2513:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2514:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2522:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2523:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2524:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2532:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2533:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2534:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2543:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2544:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2545:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2554:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2555:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2556:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2562:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2563:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2564:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2570:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2571:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2572:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2581:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2582:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2583:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2592:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2593:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2594:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2601:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2602:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2603:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2610:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2611:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2612:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2620:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2621:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2622:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2630:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2631:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2632:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2641:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2642:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2643:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2652:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2653:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2654:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2660:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2661:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2662:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2668:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2669:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2670:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2679:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2680:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2681:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2690:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2691:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2692:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2699:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2700:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2701:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2708:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2709:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2710:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2718:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2719:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2720:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2728:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2729:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2730:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2739:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2740:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2741:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2750:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2751:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2752:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2758:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2759:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2760:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2766:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2767:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2768:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2777:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2778:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2779:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2788:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2789:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2790:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2797:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2798:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2799:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2806:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2807:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2808:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2816:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2817:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2818:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2826:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2827:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2828:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2837:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2838:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2839:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2848:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2849:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2850:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2856:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2857:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2858:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2864:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2865:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2866:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2875:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR2876:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2877:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2886:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2887:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR2888:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2889:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2896:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR2897:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2898:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2905:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR2906:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2907:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2915:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR2916:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2917:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2924:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR2925:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2926:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2935:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR2936:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2937:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2943:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR2944:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2945:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2951:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR2952:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2953:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2962:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR2963:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2964:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2973:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR2974:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2975:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2982:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR2983:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2984:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2991:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR2992:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2993:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3001:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3002:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3003:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3011:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3012:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3013:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3022:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3023:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3024:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3033:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3034:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3035:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3041:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3042:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3043:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3049:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3050:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3051:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3060:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3061:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3062:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3071:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3072:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3073:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3080:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3081:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3082:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3089:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3090:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3091:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3099:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3100:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3101:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3109:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3110:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3111:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3120:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3121:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3122:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3131:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3132:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3133:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3139:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3140:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3141:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3147:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3148:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3149:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3158:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3159:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3160:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3169:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3170:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3171:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3178:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3179:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3180:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3187:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3188:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3189:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3197:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3198:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3199:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3207:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3208:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3209:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3218:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3219:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3220:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3229:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3230:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3231:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3237:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3238:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3239:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3245:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3246:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3247:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3256:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3257:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3258:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3267:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3268:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3269:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3276:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3277:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3278:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3285:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3286:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3287:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3295:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3296:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3297:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3305:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3306:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3307:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3316:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3317:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3318:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3327:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3328:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3329:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3335:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3336:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3337:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3343:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3344:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3345:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3354:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3355:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3356:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3365:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3366:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3367:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3374:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3375:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3376:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3383:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3384:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3385:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3393:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3394:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3395:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3403:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3404:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3405:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3414:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3415:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3416:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3425:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3426:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3427:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3433:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3434:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3435:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3441:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3442:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3443:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3452:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3453:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR3454:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3463:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3464:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3465:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3466:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3473:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3474:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3475:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3482:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3483:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3484:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3492:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3493:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3494:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3501:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3502:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3503:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3512:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3513:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3514:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3520:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3521:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3522:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3528:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3529:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3530:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3539:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3540:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3541:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3550:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3551:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3552:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3559:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3560:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3561:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3568:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3569:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3570:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3578:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3579:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3580:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3588:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3589:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3590:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3599:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3600:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3601:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3610:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3611:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3612:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3618:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3619:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3620:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3626:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3627:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3628:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3637:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3638:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3639:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3648:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3649:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3650:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3657:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3658:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3659:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3666:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3667:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3668:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3676:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3677:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3678:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3686:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3687:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3688:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3697:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3698:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3699:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3708:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3709:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3710:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3716:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3717:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3718:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3724:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3725:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3726:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3735:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3736:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3737:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3746:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3747:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3748:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3755:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3756:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3757:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3764:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3765:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3766:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3774:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3775:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3776:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3784:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3785:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3786:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3795:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3796:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3797:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3806:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3807:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3808:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3814:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3815:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3816:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3822:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3823:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3824:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3833:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3834:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3835:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3844:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3845:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3846:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3853:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3854:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3855:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3862:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3863:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3864:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3872:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3873:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3874:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3882:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3883:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3884:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3893:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3894:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3895:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3904:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3905:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3906:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3912:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3913:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3914:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3920:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3921:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3922:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3931:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3932:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3933:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3942:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3943:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3944:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3951:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3952:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3953:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3960:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3961:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3962:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3970:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3971:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3972:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3980:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3981:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3982:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3991:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3992:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR3993:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR4002:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR4003:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR4004:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR4010:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR4011:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR4012:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR4018:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR4019:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR4020:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR4029:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR4030:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR4031:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4040:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4041:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4042:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4043:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4050:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4051:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4052:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4059:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4060:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4061:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4069:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4070:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4071:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4078:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4079:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4080:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4089:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4090:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4091:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4097:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4098:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4099:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4105:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4106:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4107:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4116:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4117:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4118:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4127:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4128:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4129:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4136:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4137:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4138:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4145:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4146:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4147:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4155:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4156:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4157:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4165:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4166:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4167:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4176:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4177:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4178:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4187:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4188:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4189:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4195:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4196:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4197:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4203:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4204:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4205:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4214:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4215:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4216:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4225:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4226:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4227:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4234:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4235:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4236:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4243:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4244:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4245:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4253:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4254:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4255:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4263:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4264:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4265:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4274:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4275:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4276:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4285:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4286:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4287:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4293:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4294:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4295:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4301:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4302:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4303:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4312:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4313:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4314:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4323:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4324:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4325:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4332:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4333:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4334:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4341:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4342:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4343:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4351:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4352:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4353:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4361:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4362:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4363:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4372:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4373:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4374:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4383:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4384:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4385:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4391:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4392:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4393:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4399:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4400:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4401:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4410:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4411:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4412:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4421:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4422:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4423:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4430:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4431:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4432:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4439:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4440:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4441:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4449:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4450:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4451:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4459:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4460:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4461:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4470:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4471:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4472:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4481:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4482:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4483:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4489:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4490:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4491:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4497:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4498:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4499:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4508:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4509:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4510:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4519:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4520:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4521:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4528:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4529:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4530:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4537:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4538:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4539:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4547:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4548:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4549:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4557:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4558:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4559:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4568:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4569:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4570:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4579:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4580:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4581:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4587:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4588:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4589:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4595:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4596:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4597:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4606:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR4607:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4608:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4617:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4618:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4619:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4620:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4627:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4628:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4629:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4636:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4637:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4638:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4646:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4647:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4648:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4655:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4656:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4657:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4666:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4667:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4668:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4674:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4675:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4676:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4682:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4683:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4684:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4693:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4694:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4695:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4704:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4705:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4706:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4713:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4714:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4715:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4722:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4723:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4724:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4732:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4733:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4734:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4742:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4743:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4744:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4753:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4754:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4755:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4764:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4765:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4766:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4772:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4773:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4774:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4780:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4781:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4782:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4791:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4792:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4793:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4802:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4803:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4804:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4811:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4812:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4813:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4820:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4821:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4822:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4830:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4831:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4832:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4840:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4841:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4842:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4851:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4852:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4853:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4862:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4863:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4864:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4870:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4871:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4872:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4878:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4879:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4880:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4889:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4890:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4891:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4900:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4901:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4902:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4909:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4910:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4911:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4918:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4919:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4920:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4928:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4929:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4930:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4938:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4939:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4940:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4949:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4950:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4951:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4960:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4961:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4962:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4968:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4969:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4970:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4976:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4977:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4978:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4987:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4988:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4989:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4998:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR4999:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5000:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5007:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5008:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5009:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5016:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5017:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5018:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5026:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5027:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5028:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5036:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5037:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5038:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5047:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5048:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5049:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5058:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5059:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5060:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5066:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5067:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5068:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5074:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5075:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5076:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5085:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5086:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5087:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5096:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5097:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5098:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5105:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5106:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5107:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5114:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5115:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5116:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5124:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5125:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5126:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5134:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5135:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5136:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5145:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5146:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5147:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5156:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5157:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5158:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5164:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5165:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5166:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5172:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5173:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5174:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5183:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR5184:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR5185:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5194:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5195:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5196:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5197:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5204:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5205:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5206:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5213:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5214:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5215:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5223:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5224:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5225:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5232:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5233:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5234:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5243:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5244:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5245:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5251:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5252:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5253:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5259:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5260:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5261:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5270:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5271:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5272:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5281:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5282:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5283:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5290:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5291:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5292:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5299:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5300:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5301:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5309:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5310:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5311:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5319:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5320:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5321:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5330:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5331:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5332:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5341:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5342:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5343:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5349:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5350:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5351:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5357:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5358:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5359:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5368:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5369:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5370:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5379:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5380:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5381:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5388:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5389:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5390:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5397:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5398:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5399:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5407:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5408:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5409:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5417:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5418:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5419:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5428:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5429:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5430:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5439:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5440:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5441:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5447:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5448:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5449:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5455:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5456:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5457:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5466:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5467:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5468:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5477:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5478:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5479:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5486:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5487:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5488:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5495:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5496:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5497:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5505:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5506:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5507:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5515:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5516:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5517:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5526:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5527:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5528:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5537:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5538:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5539:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5545:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5546:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5547:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5553:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5554:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5555:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5564:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5565:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5566:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5575:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5576:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5577:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5584:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5585:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5586:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5593:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5594:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5595:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5603:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5604:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5605:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5613:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5614:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5615:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5624:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5625:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5626:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5635:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5636:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5637:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5643:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5644:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5645:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5651:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5652:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5653:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5662:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5663:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5664:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5673:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5674:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5675:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5682:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5683:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5684:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5691:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5692:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5693:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5701:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5702:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5703:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5711:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5712:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5713:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5722:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5723:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5724:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5733:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5734:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5735:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5741:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5742:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5743:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5749:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5750:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5751:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5760:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR5761:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR5762:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5771:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5772:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5773:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5774:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5781:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5782:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5783:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5790:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5791:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5792:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5800:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5801:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5802:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5809:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5810:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5811:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5820:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5821:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5822:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5828:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5829:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5830:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5836:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5837:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5838:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5847:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5848:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5849:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5858:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5859:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5860:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5867:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5868:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5869:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5876:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5877:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5878:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5886:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5887:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5888:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5896:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5897:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5898:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5907:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5908:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5909:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5918:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5919:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5920:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5926:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5927:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5928:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5934:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5935:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5936:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5945:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5946:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5947:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5956:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5957:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5958:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5965:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5966:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5967:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5974:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5975:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5976:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5984:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5985:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5986:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5994:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR5995:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR5996:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6005:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6006:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6007:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6016:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6017:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6018:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6024:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6025:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6026:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6032:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6033:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6034:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6043:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6044:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6045:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6054:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6055:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6056:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6063:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6064:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6065:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6072:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6073:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6074:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6082:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6083:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6084:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6092:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6093:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6094:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6103:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6104:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6105:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6114:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6115:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6116:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6122:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6123:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6124:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6130:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6131:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6132:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6141:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6142:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6143:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6152:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6153:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6154:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6161:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6162:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6163:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6170:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6171:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6172:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6180:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6181:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6182:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6190:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6191:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6192:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6201:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6202:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6203:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6212:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6213:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6214:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6220:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6221:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6222:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6228:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6229:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6230:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6239:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6240:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6241:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6250:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6251:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6252:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6259:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6260:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6261:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6268:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6269:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6270:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6278:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6279:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6280:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6288:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6289:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6290:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6299:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6300:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6301:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6310:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6311:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6312:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6318:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6319:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6320:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6326:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6327:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6328:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6337:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR6338:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR6339:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6348:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6349:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6350:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6351:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6358:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6359:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6360:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6367:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6368:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6369:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6377:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6378:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6379:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6386:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6387:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6388:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6397:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6398:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6399:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6405:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6406:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6407:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6413:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6414:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6415:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6424:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6425:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6426:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6435:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6436:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6437:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6444:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6445:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6446:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6453:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6454:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6455:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6463:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6464:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6465:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6473:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6474:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6475:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6484:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6485:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6486:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6495:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6496:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6497:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6503:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6504:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6505:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6511:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6512:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6513:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6522:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6523:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6524:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6533:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6534:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6535:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6542:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6543:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6544:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6551:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6552:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6553:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6561:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6562:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6563:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6571:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6572:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6573:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6582:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6583:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6584:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6593:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6594:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6595:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6601:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6602:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6603:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6609:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6610:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6611:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6620:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6621:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6622:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6631:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6632:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6633:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6640:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6641:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6642:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6649:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6650:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6651:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6659:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6660:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6661:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6669:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6670:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6671:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6680:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6681:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6682:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6691:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6692:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6693:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6699:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6700:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6701:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6707:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6708:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6709:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6718:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6719:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6720:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6729:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6730:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6731:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6738:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6739:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6740:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6747:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6748:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6749:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6757:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6758:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6759:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6767:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6768:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6769:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6778:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6779:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6780:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6789:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6790:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6791:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6797:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6798:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6799:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6805:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6806:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6807:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6816:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6817:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6818:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6827:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6828:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6829:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6836:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6837:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6838:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6845:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6846:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6847:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6855:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6856:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6857:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6865:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6866:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6867:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6876:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6877:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6878:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6887:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6888:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6889:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6895:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6896:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6897:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6903:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6904:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6905:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6914:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR6915:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR6916:%.*]] = alloca double, align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[CE]], align 1
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP0]] monotonic, align 1
// CHECK-NEXT: store i8 [[TMP1]], ptr [[CV]], align 1
@@ -16260,17 +20820,36 @@ double fail_dxevd() {
// CHECK-NEXT: store i8 [[TMP7]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[CE]], align 1
// CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP10:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP8]], i8 [[TMP9]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP11:%.*]] = extractvalue { i8, i1 } [[TMP10]], 0
-// CHECK-NEXT: store i8 [[TMP11]], ptr [[CV]], align 1
+// CHECK-NEXT: store i8 [[TMP8]], ptr [[CX_ATOMIC_EXPECTED_PTR]], align 1
+// CHECK-NEXT: store i8 [[TMP9]], ptr [[CX_ATOMIC_DESIRED_PTR]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED]], i8 [[CX_CMPXCHG_DESIRED]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV]], ptr [[CX_ATOMIC_EXPECTED_PTR1]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR1]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP11:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP10]], ptr [[CX_ATOMIC_EXPECTED_PTR2]], align 1
+// CHECK-NEXT: store i8 [[TMP11]], ptr [[CX_ATOMIC_DESIRED_PTR3]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED5:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR2]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED6:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR3]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR7:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED5]], i8 [[CX_CMPXCHG_DESIRED6]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV8:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR7]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV8]], ptr [[CX_ATOMIC_EXPECTED_PTR4]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS9:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR7]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL10:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR4]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL10]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP13:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP14:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP12]], i8 [[TMP13]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP15:%.*]] = extractvalue { i8, i1 } [[TMP14]], 0
+// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP12]] monotonic, align 1
+// CHECK-NEXT: [[TMP14:%.*]] = icmp sgt i8 [[TMP13]], [[TMP12]]
+// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i8 [[TMP12]], i8 [[TMP13]]
// CHECK-NEXT: store i8 [[TMP15]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP16:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP17:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP16]] monotonic, align 1
-// CHECK-NEXT: [[TMP18:%.*]] = icmp sgt i8 [[TMP17]], [[TMP16]]
+// CHECK-NEXT: [[TMP17:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP16]] monotonic, align 1
+// CHECK-NEXT: [[TMP18:%.*]] = icmp slt i8 [[TMP17]], [[TMP16]]
// CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i8 [[TMP16]], i8 [[TMP17]]
// CHECK-NEXT: store i8 [[TMP19]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[CE]], align 1
@@ -16279,9164 +20858,13129 @@ double fail_dxevd() {
// CHECK-NEXT: [[TMP23:%.*]] = select i1 [[TMP22]], i8 [[TMP20]], i8 [[TMP21]]
// CHECK-NEXT: store i8 [[TMP23]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP24]] monotonic, align 1
-// CHECK-NEXT: [[TMP26:%.*]] = icmp slt i8 [[TMP25]], [[TMP24]]
+// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP24]] monotonic, align 1
+// CHECK-NEXT: [[TMP26:%.*]] = icmp sgt i8 [[TMP25]], [[TMP24]]
// CHECK-NEXT: [[TMP27:%.*]] = select i1 [[TMP26]], i8 [[TMP24]], i8 [[TMP25]]
// CHECK-NEXT: store i8 [[TMP27]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP28:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP29:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP28]] monotonic, align 1
-// CHECK-NEXT: [[TMP30:%.*]] = icmp sgt i8 [[TMP29]], [[TMP28]]
-// CHECK-NEXT: [[TMP31:%.*]] = select i1 [[TMP30]], i8 [[TMP28]], i8 [[TMP29]]
-// CHECK-NEXT: store i8 [[TMP31]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP29:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP28]], ptr [[CX_ATOMIC_EXPECTED_PTR11]], align 1
+// CHECK-NEXT: store i8 [[TMP29]], ptr [[CX_ATOMIC_DESIRED_PTR12]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED14:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR11]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED15:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR12]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR16:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED14]], i8 [[CX_CMPXCHG_DESIRED15]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV17:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR16]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV17]], ptr [[CX_ATOMIC_EXPECTED_PTR13]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS18:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR16]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL19:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR13]], align 1
+// CHECK-NEXT: [[CX_CAPTURE_CAPTURED:%.*]] = select i1 [[CX_CMPXCHG_SUCCESS18]], i8 [[TMP28]], i8 [[CX_CAPTURE_ACTUAL19]]
+// CHECK-NEXT: store i8 [[CX_CAPTURE_CAPTURED]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP30:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP31:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP30]], ptr [[CX_ATOMIC_EXPECTED_PTR20]], align 1
+// CHECK-NEXT: store i8 [[TMP31]], ptr [[CX_ATOMIC_DESIRED_PTR21]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED23:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR20]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED24:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR21]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR25:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED23]], i8 [[CX_CMPXCHG_DESIRED24]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV26:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR25]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV26]], ptr [[CX_ATOMIC_EXPECTED_PTR22]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS27:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR25]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL28:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR22]], align 1
+// CHECK-NEXT: [[CX_CAPTURE_CAPTURED29:%.*]] = select i1 [[CX_CMPXCHG_SUCCESS27]], i8 [[TMP30]], i8 [[CX_CAPTURE_ACTUAL28]]
+// CHECK-NEXT: store i8 [[CX_CAPTURE_CAPTURED29]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP32:%.*]] = load i8, ptr [[CE]], align 1
// CHECK-NEXT: [[TMP33:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP34:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP32]], i8 [[TMP33]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP35:%.*]] = extractvalue { i8, i1 } [[TMP34]], 0
-// CHECK-NEXT: [[TMP36:%.*]] = extractvalue { i8, i1 } [[TMP34]], 1
-// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i8 [[TMP32]], i8 [[TMP35]]
-// CHECK-NEXT: store i8 [[TMP37]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP38:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP39:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP38]], i8 [[TMP39]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i8, i1 } [[TMP40]], 0
-// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i8, i1 } [[TMP40]], 1
-// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i8 [[TMP38]], i8 [[TMP41]]
-// CHECK-NEXT: store i8 [[TMP43]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP44:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP45:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP46:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP44]], i8 [[TMP45]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP47:%.*]] = extractvalue { i8, i1 } [[TMP46]], 0
-// CHECK-NEXT: [[TMP48:%.*]] = extractvalue { i8, i1 } [[TMP46]], 1
-// CHECK-NEXT: br i1 [[TMP48]], label [[CX_ATOMIC_EXIT:%.*]], label [[CX_ATOMIC_CONT:%.*]]
+// CHECK-NEXT: store i8 [[TMP32]], ptr [[CX_ATOMIC_EXPECTED_PTR30]], align 1
+// CHECK-NEXT: store i8 [[TMP33]], ptr [[CX_ATOMIC_DESIRED_PTR31]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED33:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR30]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED34:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR31]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR35:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED33]], i8 [[CX_CMPXCHG_DESIRED34]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV36:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR35]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV36]], ptr [[CX_ATOMIC_EXPECTED_PTR32]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS37:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR35]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL38:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR32]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS37]], label [[CX_ATOMIC_EXIT:%.*]], label [[CX_ATOMIC_CONT:%.*]]
// CHECK: cx.atomic.cont:
-// CHECK-NEXT: store i8 [[TMP47]], ptr [[CV]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL38]], ptr [[CV]], align 1
// CHECK-NEXT: br label [[CX_ATOMIC_EXIT]]
// CHECK: cx.atomic.exit:
-// CHECK-NEXT: [[TMP49:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP50:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP51:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP49]], i8 [[TMP50]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP52:%.*]] = extractvalue { i8, i1 } [[TMP51]], 0
-// CHECK-NEXT: [[TMP53:%.*]] = extractvalue { i8, i1 } [[TMP51]], 1
-// CHECK-NEXT: br i1 [[TMP53]], label [[CX_ATOMIC_EXIT1:%.*]], label [[CX_ATOMIC_CONT2:%.*]]
-// CHECK: cx.atomic.cont2:
-// CHECK-NEXT: store i8 [[TMP52]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT1]]
-// CHECK: cx.atomic.exit1:
+// CHECK-NEXT: [[TMP34:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP35:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP34]], ptr [[CX_ATOMIC_EXPECTED_PTR39]], align 1
+// CHECK-NEXT: store i8 [[TMP35]], ptr [[CX_ATOMIC_DESIRED_PTR40]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED42:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR39]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED43:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR40]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR44:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED42]], i8 [[CX_CMPXCHG_DESIRED43]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV45:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR44]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV45]], ptr [[CX_ATOMIC_EXPECTED_PTR41]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS46:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR44]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL47:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR41]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS46]], label [[CX_ATOMIC_EXIT48:%.*]], label [[CX_ATOMIC_CONT49:%.*]]
+// CHECK: cx.atomic.cont49:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL47]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT48]]
+// CHECK: cx.atomic.exit48:
+// CHECK-NEXT: [[TMP36:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP37:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP36]], ptr [[CX_ATOMIC_EXPECTED_PTR50]], align 1
+// CHECK-NEXT: store i8 [[TMP37]], ptr [[CX_ATOMIC_DESIRED_PTR51]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED53:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR50]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED54:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR51]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR55:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED53]], i8 [[CX_CMPXCHG_DESIRED54]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV56:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR55]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV56]], ptr [[CX_ATOMIC_EXPECTED_PTR52]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS57:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR55]], 1
+// CHECK-NEXT: [[TMP38:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS57]] to i8
+// CHECK-NEXT: store i8 [[TMP38]], ptr [[CR]], align 1
+// CHECK-NEXT: [[TMP39:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP40:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP39]], ptr [[CX_ATOMIC_EXPECTED_PTR58]], align 1
+// CHECK-NEXT: store i8 [[TMP40]], ptr [[CX_ATOMIC_DESIRED_PTR59]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED61:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR58]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED62:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR59]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR63:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED61]], i8 [[CX_CMPXCHG_DESIRED62]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV64:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR63]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV64]], ptr [[CX_ATOMIC_EXPECTED_PTR60]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS65:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR63]], 1
+// CHECK-NEXT: [[TMP41:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS65]] to i8
+// CHECK-NEXT: store i8 [[TMP41]], ptr [[CR]], align 1
+// CHECK-NEXT: [[TMP42:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP43:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP42]], ptr [[CX_ATOMIC_EXPECTED_PTR66]], align 1
+// CHECK-NEXT: store i8 [[TMP43]], ptr [[CX_ATOMIC_DESIRED_PTR67]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED69:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR66]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED70:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR67]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR71:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED69]], i8 [[CX_CMPXCHG_DESIRED70]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV72:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR71]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV72]], ptr [[CX_ATOMIC_EXPECTED_PTR68]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS73:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR71]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL74:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR68]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS73]], label [[CX_ATOMIC_EXIT75:%.*]], label [[CX_ATOMIC_CONT76:%.*]]
+// CHECK: cx.atomic.cont76:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL74]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT75]]
+// CHECK: cx.atomic.exit75:
+// CHECK-NEXT: [[TMP44:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS73]] to i8
+// CHECK-NEXT: store i8 [[TMP44]], ptr [[CR]], align 1
+// CHECK-NEXT: [[TMP45:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP46:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP45]], ptr [[CX_ATOMIC_EXPECTED_PTR77]], align 1
+// CHECK-NEXT: store i8 [[TMP46]], ptr [[CX_ATOMIC_DESIRED_PTR78]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED80:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR77]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED81:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR78]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR82:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED80]], i8 [[CX_CMPXCHG_DESIRED81]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV83:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR82]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV83]], ptr [[CX_ATOMIC_EXPECTED_PTR79]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS84:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR82]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL85:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR79]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS84]], label [[CX_ATOMIC_EXIT86:%.*]], label [[CX_ATOMIC_CONT87:%.*]]
+// CHECK: cx.atomic.cont87:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL85]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT86]]
+// CHECK: cx.atomic.exit86:
+// CHECK-NEXT: [[TMP47:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS84]] to i8
+// CHECK-NEXT: store i8 [[TMP47]], ptr [[CR]], align 1
+// CHECK-NEXT: [[TMP48:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP49:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP48]] acq_rel, align 1
+// CHECK-NEXT: store i8 [[TMP49]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP50:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP51:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP50]] acq_rel, align 1
+// CHECK-NEXT: store i8 [[TMP51]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP52:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP52]] acq_rel, align 1
+// CHECK-NEXT: store i8 [[TMP53]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP54:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP55:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP56:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP54]], i8 [[TMP55]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP57:%.*]] = extractvalue { i8, i1 } [[TMP56]], 1
-// CHECK-NEXT: [[TMP58:%.*]] = sext i1 [[TMP57]] to i8
-// CHECK-NEXT: store i8 [[TMP58]], ptr [[CR]], align 1
-// CHECK-NEXT: [[TMP59:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP60:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP61:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP59]], i8 [[TMP60]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP62:%.*]] = extractvalue { i8, i1 } [[TMP61]], 1
-// CHECK-NEXT: [[TMP63:%.*]] = sext i1 [[TMP62]] to i8
-// CHECK-NEXT: store i8 [[TMP63]], ptr [[CR]], align 1
+// CHECK-NEXT: [[TMP55:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP54]] acq_rel, align 1
+// CHECK-NEXT: store i8 [[TMP55]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP56:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP57:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP56]], ptr [[CX_ATOMIC_EXPECTED_PTR88]], align 1
+// CHECK-NEXT: store i8 [[TMP57]], ptr [[CX_ATOMIC_DESIRED_PTR89]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED91:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR88]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED92:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR89]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR93:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED91]], i8 [[CX_CMPXCHG_DESIRED92]] acq_rel acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV94:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR93]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV94]], ptr [[CX_ATOMIC_EXPECTED_PTR90]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS95:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR93]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL96:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR90]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL96]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP58:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP59:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP58]], ptr [[CX_ATOMIC_EXPECTED_PTR97]], align 1
+// CHECK-NEXT: store i8 [[TMP59]], ptr [[CX_ATOMIC_DESIRED_PTR98]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED100:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR97]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED101:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR98]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR102:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED100]], i8 [[CX_CMPXCHG_DESIRED101]] acq_rel acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV103:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR102]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV103]], ptr [[CX_ATOMIC_EXPECTED_PTR99]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS104:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR102]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL105:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR99]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL105]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP60:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP61:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP60]] acq_rel, align 1
+// CHECK-NEXT: [[TMP62:%.*]] = icmp sgt i8 [[TMP61]], [[TMP60]]
+// CHECK-NEXT: [[TMP63:%.*]] = select i1 [[TMP62]], i8 [[TMP60]], i8 [[TMP61]]
+// CHECK-NEXT: store i8 [[TMP63]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP64:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP65:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP66:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP64]], i8 [[TMP65]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP67:%.*]] = extractvalue { i8, i1 } [[TMP66]], 0
-// CHECK-NEXT: [[TMP68:%.*]] = extractvalue { i8, i1 } [[TMP66]], 1
-// CHECK-NEXT: br i1 [[TMP68]], label [[CX_ATOMIC_EXIT3:%.*]], label [[CX_ATOMIC_CONT4:%.*]]
-// CHECK: cx.atomic.cont4:
+// CHECK-NEXT: [[TMP65:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP64]] acq_rel, align 1
+// CHECK-NEXT: [[TMP66:%.*]] = icmp slt i8 [[TMP65]], [[TMP64]]
+// CHECK-NEXT: [[TMP67:%.*]] = select i1 [[TMP66]], i8 [[TMP64]], i8 [[TMP65]]
// CHECK-NEXT: store i8 [[TMP67]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT3]]
-// CHECK: cx.atomic.exit3:
-// CHECK-NEXT: [[TMP69:%.*]] = extractvalue { i8, i1 } [[TMP66]], 1
-// CHECK-NEXT: [[TMP70:%.*]] = sext i1 [[TMP69]] to i8
-// CHECK-NEXT: store i8 [[TMP70]], ptr [[CR]], align 1
-// CHECK-NEXT: [[TMP71:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP72:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP73:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP71]], i8 [[TMP72]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP74:%.*]] = extractvalue { i8, i1 } [[TMP73]], 0
-// CHECK-NEXT: [[TMP75:%.*]] = extractvalue { i8, i1 } [[TMP73]], 1
-// CHECK-NEXT: br i1 [[TMP75]], label [[CX_ATOMIC_EXIT5:%.*]], label [[CX_ATOMIC_CONT6:%.*]]
-// CHECK: cx.atomic.cont6:
-// CHECK-NEXT: store i8 [[TMP74]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT5]]
-// CHECK: cx.atomic.exit5:
-// CHECK-NEXT: [[TMP76:%.*]] = extractvalue { i8, i1 } [[TMP73]], 1
-// CHECK-NEXT: [[TMP77:%.*]] = sext i1 [[TMP76]] to i8
-// CHECK-NEXT: store i8 [[TMP77]], ptr [[CR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP68:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP68]] acq_rel, align 1
+// CHECK-NEXT: [[TMP70:%.*]] = icmp slt i8 [[TMP69]], [[TMP68]]
+// CHECK-NEXT: [[TMP71:%.*]] = select i1 [[TMP70]], i8 [[TMP68]], i8 [[TMP69]]
+// CHECK-NEXT: store i8 [[TMP71]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP72:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP73:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP72]] acq_rel, align 1
+// CHECK-NEXT: [[TMP74:%.*]] = icmp sgt i8 [[TMP73]], [[TMP72]]
+// CHECK-NEXT: [[TMP75:%.*]] = select i1 [[TMP74]], i8 [[TMP72]], i8 [[TMP73]]
+// CHECK-NEXT: store i8 [[TMP75]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP76:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP77:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP76]], ptr [[CX_ATOMIC_EXPECTED_PTR106]], align 1
+// CHECK-NEXT: store i8 [[TMP77]], ptr [[CX_ATOMIC_DESIRED_PTR107]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED109:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR106]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED110:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR107]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR111:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED109]], i8 [[CX_CMPXCHG_DESIRED110]] acq_rel acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV112:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR111]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV112]], ptr [[CX_ATOMIC_EXPECTED_PTR108]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS113:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR111]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL114:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR108]], align 1
+// CHECK-NEXT: [[CX_CAPTURE_CAPTURED115:%.*]] = select i1 [[CX_CMPXCHG_SUCCESS113]], i8 [[TMP76]], i8 [[CX_CAPTURE_ACTUAL114]]
+// CHECK-NEXT: store i8 [[CX_CAPTURE_CAPTURED115]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP78:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP78]] acq_rel, align 1
-// CHECK-NEXT: store i8 [[TMP79]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP79:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP78]], ptr [[CX_ATOMIC_EXPECTED_PTR116]], align 1
+// CHECK-NEXT: store i8 [[TMP79]], ptr [[CX_ATOMIC_DESIRED_PTR117]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED119:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR116]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED120:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR117]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR121:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED119]], i8 [[CX_CMPXCHG_DESIRED120]] acq_rel acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV122:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR121]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV122]], ptr [[CX_ATOMIC_EXPECTED_PTR118]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS123:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR121]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL124:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR118]], align 1
+// CHECK-NEXT: [[CX_CAPTURE_CAPTURED125:%.*]] = select i1 [[CX_CMPXCHG_SUCCESS123]], i8 [[TMP78]], i8 [[CX_CAPTURE_ACTUAL124]]
+// CHECK-NEXT: store i8 [[CX_CAPTURE_CAPTURED125]], ptr [[CV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP80:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP81:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP80]] acq_rel, align 1
-// CHECK-NEXT: store i8 [[TMP81]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP81:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP80]], ptr [[CX_ATOMIC_EXPECTED_PTR126]], align 1
+// CHECK-NEXT: store i8 [[TMP81]], ptr [[CX_ATOMIC_DESIRED_PTR127]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED129:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR126]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED130:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR127]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR131:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED129]], i8 [[CX_CMPXCHG_DESIRED130]] acq_rel acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV132:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR131]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV132]], ptr [[CX_ATOMIC_EXPECTED_PTR128]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS133:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR131]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL134:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR128]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS133]], label [[CX_ATOMIC_EXIT135:%.*]], label [[CX_ATOMIC_CONT136:%.*]]
+// CHECK: cx.atomic.cont136:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL134]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT135]]
+// CHECK: cx.atomic.exit135:
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP82:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP83:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP82]] acq_rel, align 1
-// CHECK-NEXT: store i8 [[TMP83]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP83:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP82]], ptr [[CX_ATOMIC_EXPECTED_PTR137]], align 1
+// CHECK-NEXT: store i8 [[TMP83]], ptr [[CX_ATOMIC_DESIRED_PTR138]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED140:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR137]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED141:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR138]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR142:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED140]], i8 [[CX_CMPXCHG_DESIRED141]] acq_rel acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV143:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR142]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV143]], ptr [[CX_ATOMIC_EXPECTED_PTR139]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS144:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR142]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL145:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR139]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS144]], label [[CX_ATOMIC_EXIT146:%.*]], label [[CX_ATOMIC_CONT147:%.*]]
+// CHECK: cx.atomic.cont147:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL145]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT146]]
+// CHECK: cx.atomic.exit146:
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP84:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP85:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP84]] acq_rel, align 1
-// CHECK-NEXT: store i8 [[TMP85]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP86:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP87:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP88:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP86]], i8 [[TMP87]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP89:%.*]] = extractvalue { i8, i1 } [[TMP88]], 0
-// CHECK-NEXT: store i8 [[TMP89]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP85:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP84]], ptr [[CX_ATOMIC_EXPECTED_PTR148]], align 1
+// CHECK-NEXT: store i8 [[TMP85]], ptr [[CX_ATOMIC_DESIRED_PTR149]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED151:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR148]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED152:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR149]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR153:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED151]], i8 [[CX_CMPXCHG_DESIRED152]] acq_rel acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV154:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR153]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV154]], ptr [[CX_ATOMIC_EXPECTED_PTR150]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS155:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR153]], 1
+// CHECK-NEXT: [[TMP86:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS155]] to i8
+// CHECK-NEXT: store i8 [[TMP86]], ptr [[CR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP87:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP88:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP87]], ptr [[CX_ATOMIC_EXPECTED_PTR156]], align 1
+// CHECK-NEXT: store i8 [[TMP88]], ptr [[CX_ATOMIC_DESIRED_PTR157]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED159:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR156]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED160:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR157]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR161:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED159]], i8 [[CX_CMPXCHG_DESIRED160]] acq_rel acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV162:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR161]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV162]], ptr [[CX_ATOMIC_EXPECTED_PTR158]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS163:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR161]], 1
+// CHECK-NEXT: [[TMP89:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS163]] to i8
+// CHECK-NEXT: store i8 [[TMP89]], ptr [[CR]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP90:%.*]] = load i8, ptr [[CE]], align 1
// CHECK-NEXT: [[TMP91:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP92:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP90]], i8 [[TMP91]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP93:%.*]] = extractvalue { i8, i1 } [[TMP92]], 0
-// CHECK-NEXT: store i8 [[TMP93]], ptr [[CV]], align 1
+// CHECK-NEXT: store i8 [[TMP90]], ptr [[CX_ATOMIC_EXPECTED_PTR164]], align 1
+// CHECK-NEXT: store i8 [[TMP91]], ptr [[CX_ATOMIC_DESIRED_PTR165]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED167:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR164]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED168:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR165]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR169:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED167]], i8 [[CX_CMPXCHG_DESIRED168]] acq_rel acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV170:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR169]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV170]], ptr [[CX_ATOMIC_EXPECTED_PTR166]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS171:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR169]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL172:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR166]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS171]], label [[CX_ATOMIC_EXIT173:%.*]], label [[CX_ATOMIC_CONT174:%.*]]
+// CHECK: cx.atomic.cont174:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL172]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT173]]
+// CHECK: cx.atomic.exit173:
+// CHECK-NEXT: [[TMP92:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS171]] to i8
+// CHECK-NEXT: store i8 [[TMP92]], ptr [[CR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP93:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP94:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP93]], ptr [[CX_ATOMIC_EXPECTED_PTR175]], align 1
+// CHECK-NEXT: store i8 [[TMP94]], ptr [[CX_ATOMIC_DESIRED_PTR176]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED178:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR175]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED179:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR176]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR180:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED178]], i8 [[CX_CMPXCHG_DESIRED179]] acq_rel acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV181:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR180]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV181]], ptr [[CX_ATOMIC_EXPECTED_PTR177]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS182:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR180]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL183:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR177]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS182]], label [[CX_ATOMIC_EXIT184:%.*]], label [[CX_ATOMIC_CONT185:%.*]]
+// CHECK: cx.atomic.cont185:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL183]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT184]]
+// CHECK: cx.atomic.exit184:
+// CHECK-NEXT: [[TMP95:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS182]] to i8
+// CHECK-NEXT: store i8 [[TMP95]], ptr [[CR]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP94:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP95:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP94]] acq_rel, align 1
-// CHECK-NEXT: [[TMP96:%.*]] = icmp sgt i8 [[TMP95]], [[TMP94]]
-// CHECK-NEXT: [[TMP97:%.*]] = select i1 [[TMP96]], i8 [[TMP94]], i8 [[TMP95]]
+// CHECK-NEXT: [[TMP96:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP96]] acquire, align 1
// CHECK-NEXT: store i8 [[TMP97]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP98:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP99:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP98]] acq_rel, align 1
-// CHECK-NEXT: [[TMP100:%.*]] = icmp slt i8 [[TMP99]], [[TMP98]]
-// CHECK-NEXT: [[TMP101:%.*]] = select i1 [[TMP100]], i8 [[TMP98]], i8 [[TMP99]]
+// CHECK-NEXT: [[TMP99:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP98]] acquire, align 1
+// CHECK-NEXT: store i8 [[TMP99]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP100:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP100]] acquire, align 1
// CHECK-NEXT: store i8 [[TMP101]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP102:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP103:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP102]] acq_rel, align 1
-// CHECK-NEXT: [[TMP104:%.*]] = icmp slt i8 [[TMP103]], [[TMP102]]
-// CHECK-NEXT: [[TMP105:%.*]] = select i1 [[TMP104]], i8 [[TMP102]], i8 [[TMP103]]
-// CHECK-NEXT: store i8 [[TMP105]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP103:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP102]] acquire, align 1
+// CHECK-NEXT: store i8 [[TMP103]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP104:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP105:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP104]], ptr [[CX_ATOMIC_EXPECTED_PTR186]], align 1
+// CHECK-NEXT: store i8 [[TMP105]], ptr [[CX_ATOMIC_DESIRED_PTR187]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED189:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR186]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED190:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR187]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR191:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED189]], i8 [[CX_CMPXCHG_DESIRED190]] acquire acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV192:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR191]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV192]], ptr [[CX_ATOMIC_EXPECTED_PTR188]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS193:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR191]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL194:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR188]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL194]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP106:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP107:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP106]] acq_rel, align 1
-// CHECK-NEXT: [[TMP108:%.*]] = icmp sgt i8 [[TMP107]], [[TMP106]]
-// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i8 [[TMP106]], i8 [[TMP107]]
-// CHECK-NEXT: store i8 [[TMP109]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP110:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP111:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP112:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP110]], i8 [[TMP111]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP113:%.*]] = extractvalue { i8, i1 } [[TMP112]], 0
-// CHECK-NEXT: [[TMP114:%.*]] = extractvalue { i8, i1 } [[TMP112]], 1
-// CHECK-NEXT: [[TMP115:%.*]] = select i1 [[TMP114]], i8 [[TMP110]], i8 [[TMP113]]
+// CHECK-NEXT: [[TMP107:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP106]], ptr [[CX_ATOMIC_EXPECTED_PTR195]], align 1
+// CHECK-NEXT: store i8 [[TMP107]], ptr [[CX_ATOMIC_DESIRED_PTR196]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED198:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR195]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED199:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR196]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR200:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED198]], i8 [[CX_CMPXCHG_DESIRED199]] acquire acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV201:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR200]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV201]], ptr [[CX_ATOMIC_EXPECTED_PTR197]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS202:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR200]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL203:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR197]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL203]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP108:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP109:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP108]] acquire, align 1
+// CHECK-NEXT: [[TMP110:%.*]] = icmp sgt i8 [[TMP109]], [[TMP108]]
+// CHECK-NEXT: [[TMP111:%.*]] = select i1 [[TMP110]], i8 [[TMP108]], i8 [[TMP109]]
+// CHECK-NEXT: store i8 [[TMP111]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP112:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP112]] acquire, align 1
+// CHECK-NEXT: [[TMP114:%.*]] = icmp slt i8 [[TMP113]], [[TMP112]]
+// CHECK-NEXT: [[TMP115:%.*]] = select i1 [[TMP114]], i8 [[TMP112]], i8 [[TMP113]]
// CHECK-NEXT: store i8 [[TMP115]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP116:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP117:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP118:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP116]], i8 [[TMP117]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP119:%.*]] = extractvalue { i8, i1 } [[TMP118]], 0
-// CHECK-NEXT: [[TMP120:%.*]] = extractvalue { i8, i1 } [[TMP118]], 1
-// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i8 [[TMP116]], i8 [[TMP119]]
-// CHECK-NEXT: store i8 [[TMP121]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP122:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP123:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP124:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP122]], i8 [[TMP123]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP125:%.*]] = extractvalue { i8, i1 } [[TMP124]], 0
-// CHECK-NEXT: [[TMP126:%.*]] = extractvalue { i8, i1 } [[TMP124]], 1
-// CHECK-NEXT: br i1 [[TMP126]], label [[CX_ATOMIC_EXIT7:%.*]], label [[CX_ATOMIC_CONT8:%.*]]
-// CHECK: cx.atomic.cont8:
-// CHECK-NEXT: store i8 [[TMP125]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT7]]
-// CHECK: cx.atomic.exit7:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP127:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP128:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP129:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP127]], i8 [[TMP128]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i8, i1 } [[TMP129]], 0
-// CHECK-NEXT: [[TMP131:%.*]] = extractvalue { i8, i1 } [[TMP129]], 1
-// CHECK-NEXT: br i1 [[TMP131]], label [[CX_ATOMIC_EXIT9:%.*]], label [[CX_ATOMIC_CONT10:%.*]]
-// CHECK: cx.atomic.cont10:
-// CHECK-NEXT: store i8 [[TMP130]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT9]]
-// CHECK: cx.atomic.exit9:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP117:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP116]] acquire, align 1
+// CHECK-NEXT: [[TMP118:%.*]] = icmp slt i8 [[TMP117]], [[TMP116]]
+// CHECK-NEXT: [[TMP119:%.*]] = select i1 [[TMP118]], i8 [[TMP116]], i8 [[TMP117]]
+// CHECK-NEXT: store i8 [[TMP119]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP120:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP121:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP120]] acquire, align 1
+// CHECK-NEXT: [[TMP122:%.*]] = icmp sgt i8 [[TMP121]], [[TMP120]]
+// CHECK-NEXT: [[TMP123:%.*]] = select i1 [[TMP122]], i8 [[TMP120]], i8 [[TMP121]]
+// CHECK-NEXT: store i8 [[TMP123]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP124:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP125:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP124]], ptr [[CX_ATOMIC_EXPECTED_PTR204]], align 1
+// CHECK-NEXT: store i8 [[TMP125]], ptr [[CX_ATOMIC_DESIRED_PTR205]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED207:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR204]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED208:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR205]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR209:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED207]], i8 [[CX_CMPXCHG_DESIRED208]] acquire acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV210:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR209]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV210]], ptr [[CX_ATOMIC_EXPECTED_PTR206]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS211:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR209]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL212:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR206]], align 1
+// CHECK-NEXT: [[CX_CAPTURE_CAPTURED213:%.*]] = select i1 [[CX_CMPXCHG_SUCCESS211]], i8 [[TMP124]], i8 [[CX_CAPTURE_ACTUAL212]]
+// CHECK-NEXT: store i8 [[CX_CAPTURE_CAPTURED213]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP126:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP127:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP126]], ptr [[CX_ATOMIC_EXPECTED_PTR214]], align 1
+// CHECK-NEXT: store i8 [[TMP127]], ptr [[CX_ATOMIC_DESIRED_PTR215]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED217:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR214]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED218:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR215]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR219:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED217]], i8 [[CX_CMPXCHG_DESIRED218]] acquire acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV220:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR219]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV220]], ptr [[CX_ATOMIC_EXPECTED_PTR216]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS221:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR219]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL222:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR216]], align 1
+// CHECK-NEXT: [[CX_CAPTURE_CAPTURED223:%.*]] = select i1 [[CX_CMPXCHG_SUCCESS221]], i8 [[TMP126]], i8 [[CX_CAPTURE_ACTUAL222]]
+// CHECK-NEXT: store i8 [[CX_CAPTURE_CAPTURED223]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP128:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP129:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP128]], ptr [[CX_ATOMIC_EXPECTED_PTR224]], align 1
+// CHECK-NEXT: store i8 [[TMP129]], ptr [[CX_ATOMIC_DESIRED_PTR225]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED227:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR224]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED228:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR225]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR229:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED227]], i8 [[CX_CMPXCHG_DESIRED228]] acquire acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV230:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR229]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV230]], ptr [[CX_ATOMIC_EXPECTED_PTR226]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS231:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR229]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL232:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR226]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS231]], label [[CX_ATOMIC_EXIT233:%.*]], label [[CX_ATOMIC_CONT234:%.*]]
+// CHECK: cx.atomic.cont234:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL232]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT233]]
+// CHECK: cx.atomic.exit233:
+// CHECK-NEXT: [[TMP130:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP131:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP130]], ptr [[CX_ATOMIC_EXPECTED_PTR235]], align 1
+// CHECK-NEXT: store i8 [[TMP131]], ptr [[CX_ATOMIC_DESIRED_PTR236]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED238:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR235]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED239:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR236]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR240:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED238]], i8 [[CX_CMPXCHG_DESIRED239]] acquire acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV241:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR240]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV241]], ptr [[CX_ATOMIC_EXPECTED_PTR237]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS242:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR240]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL243:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR237]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS242]], label [[CX_ATOMIC_EXIT244:%.*]], label [[CX_ATOMIC_CONT245:%.*]]
+// CHECK: cx.atomic.cont245:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL243]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT244]]
+// CHECK: cx.atomic.exit244:
// CHECK-NEXT: [[TMP132:%.*]] = load i8, ptr [[CE]], align 1
// CHECK-NEXT: [[TMP133:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP134:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP132]], i8 [[TMP133]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP135:%.*]] = extractvalue { i8, i1 } [[TMP134]], 1
-// CHECK-NEXT: [[TMP136:%.*]] = sext i1 [[TMP135]] to i8
-// CHECK-NEXT: store i8 [[TMP136]], ptr [[CR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP137:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP138:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP139:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP137]], i8 [[TMP138]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP140:%.*]] = extractvalue { i8, i1 } [[TMP139]], 1
-// CHECK-NEXT: [[TMP141:%.*]] = sext i1 [[TMP140]] to i8
-// CHECK-NEXT: store i8 [[TMP141]], ptr [[CR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP142:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP143:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP144:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP142]], i8 [[TMP143]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP145:%.*]] = extractvalue { i8, i1 } [[TMP144]], 0
-// CHECK-NEXT: [[TMP146:%.*]] = extractvalue { i8, i1 } [[TMP144]], 1
-// CHECK-NEXT: br i1 [[TMP146]], label [[CX_ATOMIC_EXIT11:%.*]], label [[CX_ATOMIC_CONT12:%.*]]
-// CHECK: cx.atomic.cont12:
+// CHECK-NEXT: store i8 [[TMP132]], ptr [[CX_ATOMIC_EXPECTED_PTR246]], align 1
+// CHECK-NEXT: store i8 [[TMP133]], ptr [[CX_ATOMIC_DESIRED_PTR247]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED249:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR246]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED250:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR247]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR251:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED249]], i8 [[CX_CMPXCHG_DESIRED250]] acquire acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV252:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR251]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV252]], ptr [[CX_ATOMIC_EXPECTED_PTR248]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS253:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR251]], 1
+// CHECK-NEXT: [[TMP134:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS253]] to i8
+// CHECK-NEXT: store i8 [[TMP134]], ptr [[CR]], align 1
+// CHECK-NEXT: [[TMP135:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP136:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP135]], ptr [[CX_ATOMIC_EXPECTED_PTR254]], align 1
+// CHECK-NEXT: store i8 [[TMP136]], ptr [[CX_ATOMIC_DESIRED_PTR255]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED257:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR254]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED258:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR255]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR259:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED257]], i8 [[CX_CMPXCHG_DESIRED258]] acquire acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV260:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR259]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV260]], ptr [[CX_ATOMIC_EXPECTED_PTR256]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS261:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR259]], 1
+// CHECK-NEXT: [[TMP137:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS261]] to i8
+// CHECK-NEXT: store i8 [[TMP137]], ptr [[CR]], align 1
+// CHECK-NEXT: [[TMP138:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP139:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP138]], ptr [[CX_ATOMIC_EXPECTED_PTR262]], align 1
+// CHECK-NEXT: store i8 [[TMP139]], ptr [[CX_ATOMIC_DESIRED_PTR263]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED265:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR262]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED266:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR263]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR267:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED265]], i8 [[CX_CMPXCHG_DESIRED266]] acquire acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV268:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR267]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV268]], ptr [[CX_ATOMIC_EXPECTED_PTR264]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS269:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR267]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL270:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR264]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS269]], label [[CX_ATOMIC_EXIT271:%.*]], label [[CX_ATOMIC_CONT272:%.*]]
+// CHECK: cx.atomic.cont272:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL270]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT271]]
+// CHECK: cx.atomic.exit271:
+// CHECK-NEXT: [[TMP140:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS269]] to i8
+// CHECK-NEXT: store i8 [[TMP140]], ptr [[CR]], align 1
+// CHECK-NEXT: [[TMP141:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP142:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP141]], ptr [[CX_ATOMIC_EXPECTED_PTR273]], align 1
+// CHECK-NEXT: store i8 [[TMP142]], ptr [[CX_ATOMIC_DESIRED_PTR274]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED276:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR273]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED277:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR274]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR278:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED276]], i8 [[CX_CMPXCHG_DESIRED277]] acquire acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV279:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR278]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV279]], ptr [[CX_ATOMIC_EXPECTED_PTR275]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS280:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR278]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL281:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR275]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS280]], label [[CX_ATOMIC_EXIT282:%.*]], label [[CX_ATOMIC_CONT283:%.*]]
+// CHECK: cx.atomic.cont283:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL281]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT282]]
+// CHECK: cx.atomic.exit282:
+// CHECK-NEXT: [[TMP143:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS280]] to i8
+// CHECK-NEXT: store i8 [[TMP143]], ptr [[CR]], align 1
+// CHECK-NEXT: [[TMP144:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP145:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP144]] monotonic, align 1
// CHECK-NEXT: store i8 [[TMP145]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT11]]
-// CHECK: cx.atomic.exit11:
-// CHECK-NEXT: [[TMP147:%.*]] = extractvalue { i8, i1 } [[TMP144]], 1
-// CHECK-NEXT: [[TMP148:%.*]] = sext i1 [[TMP147]] to i8
-// CHECK-NEXT: store i8 [[TMP148]], ptr [[CR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP149:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP150:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP151:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP149]], i8 [[TMP150]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP152:%.*]] = extractvalue { i8, i1 } [[TMP151]], 0
-// CHECK-NEXT: [[TMP153:%.*]] = extractvalue { i8, i1 } [[TMP151]], 1
-// CHECK-NEXT: br i1 [[TMP153]], label [[CX_ATOMIC_EXIT13:%.*]], label [[CX_ATOMIC_CONT14:%.*]]
-// CHECK: cx.atomic.cont14:
-// CHECK-NEXT: store i8 [[TMP152]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT13]]
-// CHECK: cx.atomic.exit13:
-// CHECK-NEXT: [[TMP154:%.*]] = extractvalue { i8, i1 } [[TMP151]], 1
-// CHECK-NEXT: [[TMP155:%.*]] = sext i1 [[TMP154]] to i8
-// CHECK-NEXT: store i8 [[TMP155]], ptr [[CR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP146:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP147:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP146]] monotonic, align 1
+// CHECK-NEXT: store i8 [[TMP147]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP148:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP149:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP148]] monotonic, align 1
+// CHECK-NEXT: store i8 [[TMP149]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP150:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP151:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP150]] monotonic, align 1
+// CHECK-NEXT: store i8 [[TMP151]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP152:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP153:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP152]], ptr [[CX_ATOMIC_EXPECTED_PTR284]], align 1
+// CHECK-NEXT: store i8 [[TMP153]], ptr [[CX_ATOMIC_DESIRED_PTR285]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED287:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR284]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED288:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR285]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR289:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED287]], i8 [[CX_CMPXCHG_DESIRED288]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV290:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR289]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV290]], ptr [[CX_ATOMIC_EXPECTED_PTR286]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS291:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR289]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL292:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR286]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL292]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP154:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP155:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP154]], ptr [[CX_ATOMIC_EXPECTED_PTR293]], align 1
+// CHECK-NEXT: store i8 [[TMP155]], ptr [[CX_ATOMIC_DESIRED_PTR294]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED296:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR293]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED297:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR294]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR298:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED296]], i8 [[CX_CMPXCHG_DESIRED297]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV299:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR298]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV299]], ptr [[CX_ATOMIC_EXPECTED_PTR295]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS300:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR298]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL301:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR295]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL301]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP156:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP157:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP156]] acquire, align 1
-// CHECK-NEXT: store i8 [[TMP157]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP158:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP159:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP158]] acquire, align 1
+// CHECK-NEXT: [[TMP157:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP156]] monotonic, align 1
+// CHECK-NEXT: [[TMP158:%.*]] = icmp sgt i8 [[TMP157]], [[TMP156]]
+// CHECK-NEXT: [[TMP159:%.*]] = select i1 [[TMP158]], i8 [[TMP156]], i8 [[TMP157]]
// CHECK-NEXT: store i8 [[TMP159]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP160:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP161:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP160]] acquire, align 1
-// CHECK-NEXT: store i8 [[TMP161]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP162:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP163:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP162]] acquire, align 1
+// CHECK-NEXT: [[TMP161:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP160]] monotonic, align 1
+// CHECK-NEXT: [[TMP162:%.*]] = icmp slt i8 [[TMP161]], [[TMP160]]
+// CHECK-NEXT: [[TMP163:%.*]] = select i1 [[TMP162]], i8 [[TMP160]], i8 [[TMP161]]
// CHECK-NEXT: store i8 [[TMP163]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP164:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP165:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP166:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP164]], i8 [[TMP165]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP167:%.*]] = extractvalue { i8, i1 } [[TMP166]], 0
+// CHECK-NEXT: [[TMP165:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP164]] monotonic, align 1
+// CHECK-NEXT: [[TMP166:%.*]] = icmp slt i8 [[TMP165]], [[TMP164]]
+// CHECK-NEXT: [[TMP167:%.*]] = select i1 [[TMP166]], i8 [[TMP164]], i8 [[TMP165]]
// CHECK-NEXT: store i8 [[TMP167]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP168:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP169:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP170:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP168]], i8 [[TMP169]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP171:%.*]] = extractvalue { i8, i1 } [[TMP170]], 0
+// CHECK-NEXT: [[TMP169:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP168]] monotonic, align 1
+// CHECK-NEXT: [[TMP170:%.*]] = icmp sgt i8 [[TMP169]], [[TMP168]]
+// CHECK-NEXT: [[TMP171:%.*]] = select i1 [[TMP170]], i8 [[TMP168]], i8 [[TMP169]]
// CHECK-NEXT: store i8 [[TMP171]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP172:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP173:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP172]] acquire, align 1
-// CHECK-NEXT: [[TMP174:%.*]] = icmp sgt i8 [[TMP173]], [[TMP172]]
-// CHECK-NEXT: [[TMP175:%.*]] = select i1 [[TMP174]], i8 [[TMP172]], i8 [[TMP173]]
-// CHECK-NEXT: store i8 [[TMP175]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP173:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP172]], ptr [[CX_ATOMIC_EXPECTED_PTR302]], align 1
+// CHECK-NEXT: store i8 [[TMP173]], ptr [[CX_ATOMIC_DESIRED_PTR303]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED305:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR302]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED306:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR303]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR307:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED305]], i8 [[CX_CMPXCHG_DESIRED306]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV308:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR307]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV308]], ptr [[CX_ATOMIC_EXPECTED_PTR304]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS309:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR307]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL310:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR304]], align 1
+// CHECK-NEXT: [[CX_CAPTURE_CAPTURED311:%.*]] = select i1 [[CX_CMPXCHG_SUCCESS309]], i8 [[TMP172]], i8 [[CX_CAPTURE_ACTUAL310]]
+// CHECK-NEXT: store i8 [[CX_CAPTURE_CAPTURED311]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP174:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP175:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP174]], ptr [[CX_ATOMIC_EXPECTED_PTR312]], align 1
+// CHECK-NEXT: store i8 [[TMP175]], ptr [[CX_ATOMIC_DESIRED_PTR313]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED315:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR312]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED316:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR313]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR317:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED315]], i8 [[CX_CMPXCHG_DESIRED316]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV318:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR317]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV318]], ptr [[CX_ATOMIC_EXPECTED_PTR314]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS319:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR317]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL320:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR314]], align 1
+// CHECK-NEXT: [[CX_CAPTURE_CAPTURED321:%.*]] = select i1 [[CX_CMPXCHG_SUCCESS319]], i8 [[TMP174]], i8 [[CX_CAPTURE_ACTUAL320]]
+// CHECK-NEXT: store i8 [[CX_CAPTURE_CAPTURED321]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP176:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP177:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP176]] acquire, align 1
-// CHECK-NEXT: [[TMP178:%.*]] = icmp slt i8 [[TMP177]], [[TMP176]]
-// CHECK-NEXT: [[TMP179:%.*]] = select i1 [[TMP178]], i8 [[TMP176]], i8 [[TMP177]]
-// CHECK-NEXT: store i8 [[TMP179]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP177:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP176]], ptr [[CX_ATOMIC_EXPECTED_PTR322]], align 1
+// CHECK-NEXT: store i8 [[TMP177]], ptr [[CX_ATOMIC_DESIRED_PTR323]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED325:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR322]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED326:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR323]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR327:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED325]], i8 [[CX_CMPXCHG_DESIRED326]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV328:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR327]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV328]], ptr [[CX_ATOMIC_EXPECTED_PTR324]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS329:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR327]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL330:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR324]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS329]], label [[CX_ATOMIC_EXIT331:%.*]], label [[CX_ATOMIC_CONT332:%.*]]
+// CHECK: cx.atomic.cont332:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL330]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT331]]
+// CHECK: cx.atomic.exit331:
+// CHECK-NEXT: [[TMP178:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP179:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP178]], ptr [[CX_ATOMIC_EXPECTED_PTR333]], align 1
+// CHECK-NEXT: store i8 [[TMP179]], ptr [[CX_ATOMIC_DESIRED_PTR334]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED336:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR333]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED337:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR334]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR338:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED336]], i8 [[CX_CMPXCHG_DESIRED337]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV339:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR338]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV339]], ptr [[CX_ATOMIC_EXPECTED_PTR335]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS340:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR338]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL341:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR335]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS340]], label [[CX_ATOMIC_EXIT342:%.*]], label [[CX_ATOMIC_CONT343:%.*]]
+// CHECK: cx.atomic.cont343:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL341]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT342]]
+// CHECK: cx.atomic.exit342:
// CHECK-NEXT: [[TMP180:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP181:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP180]] acquire, align 1
-// CHECK-NEXT: [[TMP182:%.*]] = icmp slt i8 [[TMP181]], [[TMP180]]
-// CHECK-NEXT: [[TMP183:%.*]] = select i1 [[TMP182]], i8 [[TMP180]], i8 [[TMP181]]
-// CHECK-NEXT: store i8 [[TMP183]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP184:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP185:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP184]] acquire, align 1
-// CHECK-NEXT: [[TMP186:%.*]] = icmp sgt i8 [[TMP185]], [[TMP184]]
-// CHECK-NEXT: [[TMP187:%.*]] = select i1 [[TMP186]], i8 [[TMP184]], i8 [[TMP185]]
-// CHECK-NEXT: store i8 [[TMP187]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP188:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP189:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP190:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP188]], i8 [[TMP189]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP191:%.*]] = extractvalue { i8, i1 } [[TMP190]], 0
-// CHECK-NEXT: [[TMP192:%.*]] = extractvalue { i8, i1 } [[TMP190]], 1
-// CHECK-NEXT: [[TMP193:%.*]] = select i1 [[TMP192]], i8 [[TMP188]], i8 [[TMP191]]
+// CHECK-NEXT: [[TMP181:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP180]], ptr [[CX_ATOMIC_EXPECTED_PTR344]], align 1
+// CHECK-NEXT: store i8 [[TMP181]], ptr [[CX_ATOMIC_DESIRED_PTR345]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED347:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR344]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED348:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR345]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR349:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED347]], i8 [[CX_CMPXCHG_DESIRED348]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV350:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR349]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV350]], ptr [[CX_ATOMIC_EXPECTED_PTR346]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS351:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR349]], 1
+// CHECK-NEXT: [[TMP182:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS351]] to i8
+// CHECK-NEXT: store i8 [[TMP182]], ptr [[CR]], align 1
+// CHECK-NEXT: [[TMP183:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP184:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP183]], ptr [[CX_ATOMIC_EXPECTED_PTR352]], align 1
+// CHECK-NEXT: store i8 [[TMP184]], ptr [[CX_ATOMIC_DESIRED_PTR353]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED355:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR352]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED356:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR353]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR357:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED355]], i8 [[CX_CMPXCHG_DESIRED356]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV358:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR357]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV358]], ptr [[CX_ATOMIC_EXPECTED_PTR354]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS359:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR357]], 1
+// CHECK-NEXT: [[TMP185:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS359]] to i8
+// CHECK-NEXT: store i8 [[TMP185]], ptr [[CR]], align 1
+// CHECK-NEXT: [[TMP186:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP187:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP186]], ptr [[CX_ATOMIC_EXPECTED_PTR360]], align 1
+// CHECK-NEXT: store i8 [[TMP187]], ptr [[CX_ATOMIC_DESIRED_PTR361]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED363:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR360]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED364:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR361]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR365:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED363]], i8 [[CX_CMPXCHG_DESIRED364]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV366:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR365]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV366]], ptr [[CX_ATOMIC_EXPECTED_PTR362]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS367:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR365]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL368:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR362]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS367]], label [[CX_ATOMIC_EXIT369:%.*]], label [[CX_ATOMIC_CONT370:%.*]]
+// CHECK: cx.atomic.cont370:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL368]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT369]]
+// CHECK: cx.atomic.exit369:
+// CHECK-NEXT: [[TMP188:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS367]] to i8
+// CHECK-NEXT: store i8 [[TMP188]], ptr [[CR]], align 1
+// CHECK-NEXT: [[TMP189:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP190:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP189]], ptr [[CX_ATOMIC_EXPECTED_PTR371]], align 1
+// CHECK-NEXT: store i8 [[TMP190]], ptr [[CX_ATOMIC_DESIRED_PTR372]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED374:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR371]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED375:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR372]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR376:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED374]], i8 [[CX_CMPXCHG_DESIRED375]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV377:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR376]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV377]], ptr [[CX_ATOMIC_EXPECTED_PTR373]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS378:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR376]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL379:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR373]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS378]], label [[CX_ATOMIC_EXIT380:%.*]], label [[CX_ATOMIC_CONT381:%.*]]
+// CHECK: cx.atomic.cont381:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL379]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT380]]
+// CHECK: cx.atomic.exit380:
+// CHECK-NEXT: [[TMP191:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS378]] to i8
+// CHECK-NEXT: store i8 [[TMP191]], ptr [[CR]], align 1
+// CHECK-NEXT: [[TMP192:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP193:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP192]] release, align 1
// CHECK-NEXT: store i8 [[TMP193]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP194:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP195:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP196:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP194]], i8 [[TMP195]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP197:%.*]] = extractvalue { i8, i1 } [[TMP196]], 0
-// CHECK-NEXT: [[TMP198:%.*]] = extractvalue { i8, i1 } [[TMP196]], 1
-// CHECK-NEXT: [[TMP199:%.*]] = select i1 [[TMP198]], i8 [[TMP194]], i8 [[TMP197]]
+// CHECK-NEXT: [[TMP195:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP194]] release, align 1
+// CHECK-NEXT: store i8 [[TMP195]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP196:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP197:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP196]] release, align 1
+// CHECK-NEXT: store i8 [[TMP197]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP198:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP199:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP198]] release, align 1
// CHECK-NEXT: store i8 [[TMP199]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP200:%.*]] = load i8, ptr [[CE]], align 1
// CHECK-NEXT: [[TMP201:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP202:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP200]], i8 [[TMP201]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP203:%.*]] = extractvalue { i8, i1 } [[TMP202]], 0
-// CHECK-NEXT: [[TMP204:%.*]] = extractvalue { i8, i1 } [[TMP202]], 1
-// CHECK-NEXT: br i1 [[TMP204]], label [[CX_ATOMIC_EXIT15:%.*]], label [[CX_ATOMIC_CONT16:%.*]]
-// CHECK: cx.atomic.cont16:
-// CHECK-NEXT: store i8 [[TMP203]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT15]]
-// CHECK: cx.atomic.exit15:
-// CHECK-NEXT: [[TMP205:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP206:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP207:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP205]], i8 [[TMP206]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP208:%.*]] = extractvalue { i8, i1 } [[TMP207]], 0
-// CHECK-NEXT: [[TMP209:%.*]] = extractvalue { i8, i1 } [[TMP207]], 1
-// CHECK-NEXT: br i1 [[TMP209]], label [[CX_ATOMIC_EXIT17:%.*]], label [[CX_ATOMIC_CONT18:%.*]]
-// CHECK: cx.atomic.cont18:
-// CHECK-NEXT: store i8 [[TMP208]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT17]]
-// CHECK: cx.atomic.exit17:
-// CHECK-NEXT: [[TMP210:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP211:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP212:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP210]], i8 [[TMP211]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP213:%.*]] = extractvalue { i8, i1 } [[TMP212]], 1
-// CHECK-NEXT: [[TMP214:%.*]] = sext i1 [[TMP213]] to i8
-// CHECK-NEXT: store i8 [[TMP214]], ptr [[CR]], align 1
-// CHECK-NEXT: [[TMP215:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP216:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP217:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP215]], i8 [[TMP216]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP218:%.*]] = extractvalue { i8, i1 } [[TMP217]], 1
-// CHECK-NEXT: [[TMP219:%.*]] = sext i1 [[TMP218]] to i8
-// CHECK-NEXT: store i8 [[TMP219]], ptr [[CR]], align 1
+// CHECK-NEXT: store i8 [[TMP200]], ptr [[CX_ATOMIC_EXPECTED_PTR382]], align 1
+// CHECK-NEXT: store i8 [[TMP201]], ptr [[CX_ATOMIC_DESIRED_PTR383]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED385:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR382]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED386:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR383]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR387:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED385]], i8 [[CX_CMPXCHG_DESIRED386]] release monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV388:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR387]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV388]], ptr [[CX_ATOMIC_EXPECTED_PTR384]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS389:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR387]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL390:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR384]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL390]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP202:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP203:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP202]], ptr [[CX_ATOMIC_EXPECTED_PTR391]], align 1
+// CHECK-NEXT: store i8 [[TMP203]], ptr [[CX_ATOMIC_DESIRED_PTR392]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED394:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR391]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED395:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR392]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR396:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED394]], i8 [[CX_CMPXCHG_DESIRED395]] release monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV397:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR396]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV397]], ptr [[CX_ATOMIC_EXPECTED_PTR393]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS398:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR396]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL399:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR393]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL399]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP204:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP205:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP204]] release, align 1
+// CHECK-NEXT: [[TMP206:%.*]] = icmp sgt i8 [[TMP205]], [[TMP204]]
+// CHECK-NEXT: [[TMP207:%.*]] = select i1 [[TMP206]], i8 [[TMP204]], i8 [[TMP205]]
+// CHECK-NEXT: store i8 [[TMP207]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP208:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP209:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP208]] release, align 1
+// CHECK-NEXT: [[TMP210:%.*]] = icmp slt i8 [[TMP209]], [[TMP208]]
+// CHECK-NEXT: [[TMP211:%.*]] = select i1 [[TMP210]], i8 [[TMP208]], i8 [[TMP209]]
+// CHECK-NEXT: store i8 [[TMP211]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP212:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP213:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP212]] release, align 1
+// CHECK-NEXT: [[TMP214:%.*]] = icmp slt i8 [[TMP213]], [[TMP212]]
+// CHECK-NEXT: [[TMP215:%.*]] = select i1 [[TMP214]], i8 [[TMP212]], i8 [[TMP213]]
+// CHECK-NEXT: store i8 [[TMP215]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP216:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP217:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP216]] release, align 1
+// CHECK-NEXT: [[TMP218:%.*]] = icmp sgt i8 [[TMP217]], [[TMP216]]
+// CHECK-NEXT: [[TMP219:%.*]] = select i1 [[TMP218]], i8 [[TMP216]], i8 [[TMP217]]
+// CHECK-NEXT: store i8 [[TMP219]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP220:%.*]] = load i8, ptr [[CE]], align 1
// CHECK-NEXT: [[TMP221:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP222:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP220]], i8 [[TMP221]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP223:%.*]] = extractvalue { i8, i1 } [[TMP222]], 0
-// CHECK-NEXT: [[TMP224:%.*]] = extractvalue { i8, i1 } [[TMP222]], 1
-// CHECK-NEXT: br i1 [[TMP224]], label [[CX_ATOMIC_EXIT19:%.*]], label [[CX_ATOMIC_CONT20:%.*]]
-// CHECK: cx.atomic.cont20:
-// CHECK-NEXT: store i8 [[TMP223]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT19]]
-// CHECK: cx.atomic.exit19:
-// CHECK-NEXT: [[TMP225:%.*]] = extractvalue { i8, i1 } [[TMP222]], 1
-// CHECK-NEXT: [[TMP226:%.*]] = sext i1 [[TMP225]] to i8
-// CHECK-NEXT: store i8 [[TMP226]], ptr [[CR]], align 1
-// CHECK-NEXT: [[TMP227:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP228:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP229:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP227]], i8 [[TMP228]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP230:%.*]] = extractvalue { i8, i1 } [[TMP229]], 0
-// CHECK-NEXT: [[TMP231:%.*]] = extractvalue { i8, i1 } [[TMP229]], 1
-// CHECK-NEXT: br i1 [[TMP231]], label [[CX_ATOMIC_EXIT21:%.*]], label [[CX_ATOMIC_CONT22:%.*]]
-// CHECK: cx.atomic.cont22:
-// CHECK-NEXT: store i8 [[TMP230]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT21]]
-// CHECK: cx.atomic.exit21:
-// CHECK-NEXT: [[TMP232:%.*]] = extractvalue { i8, i1 } [[TMP229]], 1
-// CHECK-NEXT: [[TMP233:%.*]] = sext i1 [[TMP232]] to i8
+// CHECK-NEXT: store i8 [[TMP220]], ptr [[CX_ATOMIC_EXPECTED_PTR400]], align 1
+// CHECK-NEXT: store i8 [[TMP221]], ptr [[CX_ATOMIC_DESIRED_PTR401]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED403:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR400]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED404:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR401]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR405:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED403]], i8 [[CX_CMPXCHG_DESIRED404]] release monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV406:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR405]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV406]], ptr [[CX_ATOMIC_EXPECTED_PTR402]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS407:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR405]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL408:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR402]], align 1
+// CHECK-NEXT: [[CX_CAPTURE_CAPTURED409:%.*]] = select i1 [[CX_CMPXCHG_SUCCESS407]], i8 [[TMP220]], i8 [[CX_CAPTURE_ACTUAL408]]
+// CHECK-NEXT: store i8 [[CX_CAPTURE_CAPTURED409]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP222:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP223:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP222]], ptr [[CX_ATOMIC_EXPECTED_PTR410]], align 1
+// CHECK-NEXT: store i8 [[TMP223]], ptr [[CX_ATOMIC_DESIRED_PTR411]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED413:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR410]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED414:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR411]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR415:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED413]], i8 [[CX_CMPXCHG_DESIRED414]] release monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV416:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR415]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV416]], ptr [[CX_ATOMIC_EXPECTED_PTR412]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS417:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR415]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL418:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR412]], align 1
+// CHECK-NEXT: [[CX_CAPTURE_CAPTURED419:%.*]] = select i1 [[CX_CMPXCHG_SUCCESS417]], i8 [[TMP222]], i8 [[CX_CAPTURE_ACTUAL418]]
+// CHECK-NEXT: store i8 [[CX_CAPTURE_CAPTURED419]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP224:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP225:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP224]], ptr [[CX_ATOMIC_EXPECTED_PTR420]], align 1
+// CHECK-NEXT: store i8 [[TMP225]], ptr [[CX_ATOMIC_DESIRED_PTR421]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED423:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR420]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED424:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR421]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR425:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED423]], i8 [[CX_CMPXCHG_DESIRED424]] release monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV426:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR425]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV426]], ptr [[CX_ATOMIC_EXPECTED_PTR422]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS427:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR425]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL428:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR422]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS427]], label [[CX_ATOMIC_EXIT429:%.*]], label [[CX_ATOMIC_CONT430:%.*]]
+// CHECK: cx.atomic.cont430:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL428]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT429]]
+// CHECK: cx.atomic.exit429:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP226:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP227:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP226]], ptr [[CX_ATOMIC_EXPECTED_PTR431]], align 1
+// CHECK-NEXT: store i8 [[TMP227]], ptr [[CX_ATOMIC_DESIRED_PTR432]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED434:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR431]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED435:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR432]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR436:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED434]], i8 [[CX_CMPXCHG_DESIRED435]] release monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV437:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR436]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV437]], ptr [[CX_ATOMIC_EXPECTED_PTR433]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS438:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR436]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL439:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR433]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS438]], label [[CX_ATOMIC_EXIT440:%.*]], label [[CX_ATOMIC_CONT441:%.*]]
+// CHECK: cx.atomic.cont441:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL439]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT440]]
+// CHECK: cx.atomic.exit440:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP228:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP229:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP228]], ptr [[CX_ATOMIC_EXPECTED_PTR442]], align 1
+// CHECK-NEXT: store i8 [[TMP229]], ptr [[CX_ATOMIC_DESIRED_PTR443]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED445:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR442]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED446:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR443]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR447:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED445]], i8 [[CX_CMPXCHG_DESIRED446]] release monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV448:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR447]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV448]], ptr [[CX_ATOMIC_EXPECTED_PTR444]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS449:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR447]], 1
+// CHECK-NEXT: [[TMP230:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS449]] to i8
+// CHECK-NEXT: store i8 [[TMP230]], ptr [[CR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP231:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP232:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP231]], ptr [[CX_ATOMIC_EXPECTED_PTR450]], align 1
+// CHECK-NEXT: store i8 [[TMP232]], ptr [[CX_ATOMIC_DESIRED_PTR451]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED453:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR450]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED454:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR451]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR455:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED453]], i8 [[CX_CMPXCHG_DESIRED454]] release monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV456:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR455]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV456]], ptr [[CX_ATOMIC_EXPECTED_PTR452]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS457:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR455]], 1
+// CHECK-NEXT: [[TMP233:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS457]] to i8
// CHECK-NEXT: store i8 [[TMP233]], ptr [[CR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP234:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP235:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP234]] monotonic, align 1
-// CHECK-NEXT: store i8 [[TMP235]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP236:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP237:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP236]] monotonic, align 1
-// CHECK-NEXT: store i8 [[TMP237]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP238:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP239:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP238]] monotonic, align 1
-// CHECK-NEXT: store i8 [[TMP239]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP235:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP234]], ptr [[CX_ATOMIC_EXPECTED_PTR458]], align 1
+// CHECK-NEXT: store i8 [[TMP235]], ptr [[CX_ATOMIC_DESIRED_PTR459]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED461:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR458]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED462:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR459]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR463:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED461]], i8 [[CX_CMPXCHG_DESIRED462]] release monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV464:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR463]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV464]], ptr [[CX_ATOMIC_EXPECTED_PTR460]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS465:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR463]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL466:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR460]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS465]], label [[CX_ATOMIC_EXIT467:%.*]], label [[CX_ATOMIC_CONT468:%.*]]
+// CHECK: cx.atomic.cont468:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL466]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT467]]
+// CHECK: cx.atomic.exit467:
+// CHECK-NEXT: [[TMP236:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS465]] to i8
+// CHECK-NEXT: store i8 [[TMP236]], ptr [[CR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP237:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP238:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP237]], ptr [[CX_ATOMIC_EXPECTED_PTR469]], align 1
+// CHECK-NEXT: store i8 [[TMP238]], ptr [[CX_ATOMIC_DESIRED_PTR470]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED472:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR469]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED473:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR470]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR474:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED472]], i8 [[CX_CMPXCHG_DESIRED473]] release monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV475:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR474]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV475]], ptr [[CX_ATOMIC_EXPECTED_PTR471]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS476:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR474]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL477:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR471]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS476]], label [[CX_ATOMIC_EXIT478:%.*]], label [[CX_ATOMIC_CONT479:%.*]]
+// CHECK: cx.atomic.cont479:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL477]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT478]]
+// CHECK: cx.atomic.exit478:
+// CHECK-NEXT: [[TMP239:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS476]] to i8
+// CHECK-NEXT: store i8 [[TMP239]], ptr [[CR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP240:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP241:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP240]] monotonic, align 1
+// CHECK-NEXT: [[TMP241:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP240]] seq_cst, align 1
// CHECK-NEXT: store i8 [[TMP241]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP242:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP243:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP244:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP242]], i8 [[TMP243]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP245:%.*]] = extractvalue { i8, i1 } [[TMP244]], 0
+// CHECK-NEXT: [[TMP243:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP242]] seq_cst, align 1
+// CHECK-NEXT: store i8 [[TMP243]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP244:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP245:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP244]] seq_cst, align 1
// CHECK-NEXT: store i8 [[TMP245]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP246:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP247:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP248:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP246]], i8 [[TMP247]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP249:%.*]] = extractvalue { i8, i1 } [[TMP248]], 0
-// CHECK-NEXT: store i8 [[TMP249]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP247:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP246]] seq_cst, align 1
+// CHECK-NEXT: store i8 [[TMP247]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP248:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP249:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP248]], ptr [[CX_ATOMIC_EXPECTED_PTR480]], align 1
+// CHECK-NEXT: store i8 [[TMP249]], ptr [[CX_ATOMIC_DESIRED_PTR481]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED483:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR480]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED484:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR481]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR485:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED483]], i8 [[CX_CMPXCHG_DESIRED484]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV486:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR485]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV486]], ptr [[CX_ATOMIC_EXPECTED_PTR482]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS487:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR485]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL488:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR482]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL488]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP250:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP251:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP250]] monotonic, align 1
-// CHECK-NEXT: [[TMP252:%.*]] = icmp sgt i8 [[TMP251]], [[TMP250]]
-// CHECK-NEXT: [[TMP253:%.*]] = select i1 [[TMP252]], i8 [[TMP250]], i8 [[TMP251]]
-// CHECK-NEXT: store i8 [[TMP253]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP254:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP255:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP254]] monotonic, align 1
-// CHECK-NEXT: [[TMP256:%.*]] = icmp slt i8 [[TMP255]], [[TMP254]]
-// CHECK-NEXT: [[TMP257:%.*]] = select i1 [[TMP256]], i8 [[TMP254]], i8 [[TMP255]]
-// CHECK-NEXT: store i8 [[TMP257]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP258:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP259:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP258]] monotonic, align 1
-// CHECK-NEXT: [[TMP260:%.*]] = icmp slt i8 [[TMP259]], [[TMP258]]
-// CHECK-NEXT: [[TMP261:%.*]] = select i1 [[TMP260]], i8 [[TMP258]], i8 [[TMP259]]
-// CHECK-NEXT: store i8 [[TMP261]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP262:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP263:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP262]] monotonic, align 1
-// CHECK-NEXT: [[TMP264:%.*]] = icmp sgt i8 [[TMP263]], [[TMP262]]
-// CHECK-NEXT: [[TMP265:%.*]] = select i1 [[TMP264]], i8 [[TMP262]], i8 [[TMP263]]
-// CHECK-NEXT: store i8 [[TMP265]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP266:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP267:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP268:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP266]], i8 [[TMP267]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP269:%.*]] = extractvalue { i8, i1 } [[TMP268]], 0
-// CHECK-NEXT: [[TMP270:%.*]] = extractvalue { i8, i1 } [[TMP268]], 1
-// CHECK-NEXT: [[TMP271:%.*]] = select i1 [[TMP270]], i8 [[TMP266]], i8 [[TMP269]]
-// CHECK-NEXT: store i8 [[TMP271]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP251:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP250]], ptr [[CX_ATOMIC_EXPECTED_PTR489]], align 1
+// CHECK-NEXT: store i8 [[TMP251]], ptr [[CX_ATOMIC_DESIRED_PTR490]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED492:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR489]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED493:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR490]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR494:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED492]], i8 [[CX_CMPXCHG_DESIRED493]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV495:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR494]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV495]], ptr [[CX_ATOMIC_EXPECTED_PTR491]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS496:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR494]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL497:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR491]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL497]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP252:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP253:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP252]] seq_cst, align 1
+// CHECK-NEXT: [[TMP254:%.*]] = icmp sgt i8 [[TMP253]], [[TMP252]]
+// CHECK-NEXT: [[TMP255:%.*]] = select i1 [[TMP254]], i8 [[TMP252]], i8 [[TMP253]]
+// CHECK-NEXT: store i8 [[TMP255]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP256:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP257:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP256]] seq_cst, align 1
+// CHECK-NEXT: [[TMP258:%.*]] = icmp slt i8 [[TMP257]], [[TMP256]]
+// CHECK-NEXT: [[TMP259:%.*]] = select i1 [[TMP258]], i8 [[TMP256]], i8 [[TMP257]]
+// CHECK-NEXT: store i8 [[TMP259]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP260:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP261:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP260]] seq_cst, align 1
+// CHECK-NEXT: [[TMP262:%.*]] = icmp slt i8 [[TMP261]], [[TMP260]]
+// CHECK-NEXT: [[TMP263:%.*]] = select i1 [[TMP262]], i8 [[TMP260]], i8 [[TMP261]]
+// CHECK-NEXT: store i8 [[TMP263]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP264:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP265:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP264]] seq_cst, align 1
+// CHECK-NEXT: [[TMP266:%.*]] = icmp sgt i8 [[TMP265]], [[TMP264]]
+// CHECK-NEXT: [[TMP267:%.*]] = select i1 [[TMP266]], i8 [[TMP264]], i8 [[TMP265]]
+// CHECK-NEXT: store i8 [[TMP267]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP268:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP269:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP268]], ptr [[CX_ATOMIC_EXPECTED_PTR498]], align 1
+// CHECK-NEXT: store i8 [[TMP269]], ptr [[CX_ATOMIC_DESIRED_PTR499]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED501:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR498]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED502:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR499]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR503:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED501]], i8 [[CX_CMPXCHG_DESIRED502]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV504:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR503]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV504]], ptr [[CX_ATOMIC_EXPECTED_PTR500]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS505:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR503]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL506:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR500]], align 1
+// CHECK-NEXT: [[CX_CAPTURE_CAPTURED507:%.*]] = select i1 [[CX_CMPXCHG_SUCCESS505]], i8 [[TMP268]], i8 [[CX_CAPTURE_ACTUAL506]]
+// CHECK-NEXT: store i8 [[CX_CAPTURE_CAPTURED507]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP270:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP271:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP270]], ptr [[CX_ATOMIC_EXPECTED_PTR508]], align 1
+// CHECK-NEXT: store i8 [[TMP271]], ptr [[CX_ATOMIC_DESIRED_PTR509]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED511:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR508]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED512:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR509]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR513:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED511]], i8 [[CX_CMPXCHG_DESIRED512]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV514:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR513]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV514]], ptr [[CX_ATOMIC_EXPECTED_PTR510]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS515:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR513]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL516:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR510]], align 1
+// CHECK-NEXT: [[CX_CAPTURE_CAPTURED517:%.*]] = select i1 [[CX_CMPXCHG_SUCCESS515]], i8 [[TMP270]], i8 [[CX_CAPTURE_ACTUAL516]]
+// CHECK-NEXT: store i8 [[CX_CAPTURE_CAPTURED517]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP272:%.*]] = load i8, ptr [[CE]], align 1
// CHECK-NEXT: [[TMP273:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP274:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP272]], i8 [[TMP273]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP275:%.*]] = extractvalue { i8, i1 } [[TMP274]], 0
-// CHECK-NEXT: [[TMP276:%.*]] = extractvalue { i8, i1 } [[TMP274]], 1
-// CHECK-NEXT: [[TMP277:%.*]] = select i1 [[TMP276]], i8 [[TMP272]], i8 [[TMP275]]
-// CHECK-NEXT: store i8 [[TMP277]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP278:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP279:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP280:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP278]], i8 [[TMP279]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP281:%.*]] = extractvalue { i8, i1 } [[TMP280]], 0
-// CHECK-NEXT: [[TMP282:%.*]] = extractvalue { i8, i1 } [[TMP280]], 1
-// CHECK-NEXT: br i1 [[TMP282]], label [[CX_ATOMIC_EXIT23:%.*]], label [[CX_ATOMIC_CONT24:%.*]]
-// CHECK: cx.atomic.cont24:
-// CHECK-NEXT: store i8 [[TMP281]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT23]]
-// CHECK: cx.atomic.exit23:
-// CHECK-NEXT: [[TMP283:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP284:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP285:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP283]], i8 [[TMP284]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP286:%.*]] = extractvalue { i8, i1 } [[TMP285]], 0
-// CHECK-NEXT: [[TMP287:%.*]] = extractvalue { i8, i1 } [[TMP285]], 1
-// CHECK-NEXT: br i1 [[TMP287]], label [[CX_ATOMIC_EXIT25:%.*]], label [[CX_ATOMIC_CONT26:%.*]]
-// CHECK: cx.atomic.cont26:
-// CHECK-NEXT: store i8 [[TMP286]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT25]]
-// CHECK: cx.atomic.exit25:
-// CHECK-NEXT: [[TMP288:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP289:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP290:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP288]], i8 [[TMP289]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP291:%.*]] = extractvalue { i8, i1 } [[TMP290]], 1
-// CHECK-NEXT: [[TMP292:%.*]] = sext i1 [[TMP291]] to i8
-// CHECK-NEXT: store i8 [[TMP292]], ptr [[CR]], align 1
-// CHECK-NEXT: [[TMP293:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP294:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP295:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP293]], i8 [[TMP294]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP296:%.*]] = extractvalue { i8, i1 } [[TMP295]], 1
-// CHECK-NEXT: [[TMP297:%.*]] = sext i1 [[TMP296]] to i8
-// CHECK-NEXT: store i8 [[TMP297]], ptr [[CR]], align 1
-// CHECK-NEXT: [[TMP298:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP299:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP300:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP298]], i8 [[TMP299]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP301:%.*]] = extractvalue { i8, i1 } [[TMP300]], 0
-// CHECK-NEXT: [[TMP302:%.*]] = extractvalue { i8, i1 } [[TMP300]], 1
-// CHECK-NEXT: br i1 [[TMP302]], label [[CX_ATOMIC_EXIT27:%.*]], label [[CX_ATOMIC_CONT28:%.*]]
-// CHECK: cx.atomic.cont28:
-// CHECK-NEXT: store i8 [[TMP301]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT27]]
-// CHECK: cx.atomic.exit27:
-// CHECK-NEXT: [[TMP303:%.*]] = extractvalue { i8, i1 } [[TMP300]], 1
-// CHECK-NEXT: [[TMP304:%.*]] = sext i1 [[TMP303]] to i8
-// CHECK-NEXT: store i8 [[TMP304]], ptr [[CR]], align 1
-// CHECK-NEXT: [[TMP305:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP306:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP307:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP305]], i8 [[TMP306]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP308:%.*]] = extractvalue { i8, i1 } [[TMP307]], 0
-// CHECK-NEXT: [[TMP309:%.*]] = extractvalue { i8, i1 } [[TMP307]], 1
-// CHECK-NEXT: br i1 [[TMP309]], label [[CX_ATOMIC_EXIT29:%.*]], label [[CX_ATOMIC_CONT30:%.*]]
-// CHECK: cx.atomic.cont30:
-// CHECK-NEXT: store i8 [[TMP308]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT29]]
-// CHECK: cx.atomic.exit29:
-// CHECK-NEXT: [[TMP310:%.*]] = extractvalue { i8, i1 } [[TMP307]], 1
-// CHECK-NEXT: [[TMP311:%.*]] = sext i1 [[TMP310]] to i8
-// CHECK-NEXT: store i8 [[TMP311]], ptr [[CR]], align 1
-// CHECK-NEXT: [[TMP312:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP313:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP312]] release, align 1
-// CHECK-NEXT: store i8 [[TMP313]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP314:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP315:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP314]] release, align 1
-// CHECK-NEXT: store i8 [[TMP315]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP316:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP317:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP316]] release, align 1
-// CHECK-NEXT: store i8 [[TMP317]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP318:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP319:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP318]] release, align 1
-// CHECK-NEXT: store i8 [[TMP319]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP320:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP321:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP322:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP320]], i8 [[TMP321]] release monotonic, align 1
-// CHECK-NEXT: [[TMP323:%.*]] = extractvalue { i8, i1 } [[TMP322]], 0
-// CHECK-NEXT: store i8 [[TMP323]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP324:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP325:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP326:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP324]], i8 [[TMP325]] release monotonic, align 1
-// CHECK-NEXT: [[TMP327:%.*]] = extractvalue { i8, i1 } [[TMP326]], 0
-// CHECK-NEXT: store i8 [[TMP327]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP328:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP329:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP328]] release, align 1
-// CHECK-NEXT: [[TMP330:%.*]] = icmp sgt i8 [[TMP329]], [[TMP328]]
-// CHECK-NEXT: [[TMP331:%.*]] = select i1 [[TMP330]], i8 [[TMP328]], i8 [[TMP329]]
-// CHECK-NEXT: store i8 [[TMP331]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP332:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP333:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP332]] release, align 1
-// CHECK-NEXT: [[TMP334:%.*]] = icmp slt i8 [[TMP333]], [[TMP332]]
-// CHECK-NEXT: [[TMP335:%.*]] = select i1 [[TMP334]], i8 [[TMP332]], i8 [[TMP333]]
-// CHECK-NEXT: store i8 [[TMP335]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP336:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP337:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP336]] release, align 1
-// CHECK-NEXT: [[TMP338:%.*]] = icmp slt i8 [[TMP337]], [[TMP336]]
-// CHECK-NEXT: [[TMP339:%.*]] = select i1 [[TMP338]], i8 [[TMP336]], i8 [[TMP337]]
-// CHECK-NEXT: store i8 [[TMP339]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP340:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP341:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP340]] release, align 1
-// CHECK-NEXT: [[TMP342:%.*]] = icmp sgt i8 [[TMP341]], [[TMP340]]
-// CHECK-NEXT: [[TMP343:%.*]] = select i1 [[TMP342]], i8 [[TMP340]], i8 [[TMP341]]
-// CHECK-NEXT: store i8 [[TMP343]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP344:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP345:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP346:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP344]], i8 [[TMP345]] release monotonic, align 1
-// CHECK-NEXT: [[TMP347:%.*]] = extractvalue { i8, i1 } [[TMP346]], 0
-// CHECK-NEXT: [[TMP348:%.*]] = extractvalue { i8, i1 } [[TMP346]], 1
-// CHECK-NEXT: [[TMP349:%.*]] = select i1 [[TMP348]], i8 [[TMP344]], i8 [[TMP347]]
-// CHECK-NEXT: store i8 [[TMP349]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP350:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP351:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP352:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP350]], i8 [[TMP351]] release monotonic, align 1
-// CHECK-NEXT: [[TMP353:%.*]] = extractvalue { i8, i1 } [[TMP352]], 0
-// CHECK-NEXT: [[TMP354:%.*]] = extractvalue { i8, i1 } [[TMP352]], 1
-// CHECK-NEXT: [[TMP355:%.*]] = select i1 [[TMP354]], i8 [[TMP350]], i8 [[TMP353]]
-// CHECK-NEXT: store i8 [[TMP355]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP356:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP357:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP358:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP356]], i8 [[TMP357]] release monotonic, align 1
-// CHECK-NEXT: [[TMP359:%.*]] = extractvalue { i8, i1 } [[TMP358]], 0
-// CHECK-NEXT: [[TMP360:%.*]] = extractvalue { i8, i1 } [[TMP358]], 1
-// CHECK-NEXT: br i1 [[TMP360]], label [[CX_ATOMIC_EXIT31:%.*]], label [[CX_ATOMIC_CONT32:%.*]]
-// CHECK: cx.atomic.cont32:
-// CHECK-NEXT: store i8 [[TMP359]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT31]]
-// CHECK: cx.atomic.exit31:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP361:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP362:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP363:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP361]], i8 [[TMP362]] release monotonic, align 1
-// CHECK-NEXT: [[TMP364:%.*]] = extractvalue { i8, i1 } [[TMP363]], 0
-// CHECK-NEXT: [[TMP365:%.*]] = extractvalue { i8, i1 } [[TMP363]], 1
-// CHECK-NEXT: br i1 [[TMP365]], label [[CX_ATOMIC_EXIT33:%.*]], label [[CX_ATOMIC_CONT34:%.*]]
-// CHECK: cx.atomic.cont34:
-// CHECK-NEXT: store i8 [[TMP364]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT33]]
-// CHECK: cx.atomic.exit33:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP366:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP367:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP368:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP366]], i8 [[TMP367]] release monotonic, align 1
-// CHECK-NEXT: [[TMP369:%.*]] = extractvalue { i8, i1 } [[TMP368]], 1
-// CHECK-NEXT: [[TMP370:%.*]] = sext i1 [[TMP369]] to i8
-// CHECK-NEXT: store i8 [[TMP370]], ptr [[CR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP371:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP372:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP373:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP371]], i8 [[TMP372]] release monotonic, align 1
-// CHECK-NEXT: [[TMP374:%.*]] = extractvalue { i8, i1 } [[TMP373]], 1
-// CHECK-NEXT: [[TMP375:%.*]] = sext i1 [[TMP374]] to i8
-// CHECK-NEXT: store i8 [[TMP375]], ptr [[CR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP376:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP377:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP378:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP376]], i8 [[TMP377]] release monotonic, align 1
-// CHECK-NEXT: [[TMP379:%.*]] = extractvalue { i8, i1 } [[TMP378]], 0
-// CHECK-NEXT: [[TMP380:%.*]] = extractvalue { i8, i1 } [[TMP378]], 1
-// CHECK-NEXT: br i1 [[TMP380]], label [[CX_ATOMIC_EXIT35:%.*]], label [[CX_ATOMIC_CONT36:%.*]]
-// CHECK: cx.atomic.cont36:
-// CHECK-NEXT: store i8 [[TMP379]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT35]]
-// CHECK: cx.atomic.exit35:
-// CHECK-NEXT: [[TMP381:%.*]] = extractvalue { i8, i1 } [[TMP378]], 1
-// CHECK-NEXT: [[TMP382:%.*]] = sext i1 [[TMP381]] to i8
-// CHECK-NEXT: store i8 [[TMP382]], ptr [[CR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP383:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP384:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP385:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP383]], i8 [[TMP384]] release monotonic, align 1
-// CHECK-NEXT: [[TMP386:%.*]] = extractvalue { i8, i1 } [[TMP385]], 0
-// CHECK-NEXT: [[TMP387:%.*]] = extractvalue { i8, i1 } [[TMP385]], 1
-// CHECK-NEXT: br i1 [[TMP387]], label [[CX_ATOMIC_EXIT37:%.*]], label [[CX_ATOMIC_CONT38:%.*]]
-// CHECK: cx.atomic.cont38:
-// CHECK-NEXT: store i8 [[TMP386]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT37]]
-// CHECK: cx.atomic.exit37:
-// CHECK-NEXT: [[TMP388:%.*]] = extractvalue { i8, i1 } [[TMP385]], 1
-// CHECK-NEXT: [[TMP389:%.*]] = sext i1 [[TMP388]] to i8
-// CHECK-NEXT: store i8 [[TMP389]], ptr [[CR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP390:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP391:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP390]] seq_cst, align 1
-// CHECK-NEXT: store i8 [[TMP391]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP392:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP393:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP392]] seq_cst, align 1
-// CHECK-NEXT: store i8 [[TMP393]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP394:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP395:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP394]] seq_cst, align 1
-// CHECK-NEXT: store i8 [[TMP395]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP396:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP397:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP396]] seq_cst, align 1
-// CHECK-NEXT: store i8 [[TMP397]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP398:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP399:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP400:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP398]], i8 [[TMP399]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP401:%.*]] = extractvalue { i8, i1 } [[TMP400]], 0
-// CHECK-NEXT: store i8 [[TMP401]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP402:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP403:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP404:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP402]], i8 [[TMP403]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP405:%.*]] = extractvalue { i8, i1 } [[TMP404]], 0
-// CHECK-NEXT: store i8 [[TMP405]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP406:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP407:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP406]] seq_cst, align 1
-// CHECK-NEXT: [[TMP408:%.*]] = icmp sgt i8 [[TMP407]], [[TMP406]]
-// CHECK-NEXT: [[TMP409:%.*]] = select i1 [[TMP408]], i8 [[TMP406]], i8 [[TMP407]]
-// CHECK-NEXT: store i8 [[TMP409]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP410:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP411:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP410]] seq_cst, align 1
-// CHECK-NEXT: [[TMP412:%.*]] = icmp slt i8 [[TMP411]], [[TMP410]]
-// CHECK-NEXT: [[TMP413:%.*]] = select i1 [[TMP412]], i8 [[TMP410]], i8 [[TMP411]]
-// CHECK-NEXT: store i8 [[TMP413]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP414:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP415:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP414]] seq_cst, align 1
-// CHECK-NEXT: [[TMP416:%.*]] = icmp slt i8 [[TMP415]], [[TMP414]]
-// CHECK-NEXT: [[TMP417:%.*]] = select i1 [[TMP416]], i8 [[TMP414]], i8 [[TMP415]]
-// CHECK-NEXT: store i8 [[TMP417]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP418:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP419:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP418]] seq_cst, align 1
-// CHECK-NEXT: [[TMP420:%.*]] = icmp sgt i8 [[TMP419]], [[TMP418]]
-// CHECK-NEXT: [[TMP421:%.*]] = select i1 [[TMP420]], i8 [[TMP418]], i8 [[TMP419]]
-// CHECK-NEXT: store i8 [[TMP421]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP422:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP423:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP424:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP422]], i8 [[TMP423]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP425:%.*]] = extractvalue { i8, i1 } [[TMP424]], 0
-// CHECK-NEXT: [[TMP426:%.*]] = extractvalue { i8, i1 } [[TMP424]], 1
-// CHECK-NEXT: [[TMP427:%.*]] = select i1 [[TMP426]], i8 [[TMP422]], i8 [[TMP425]]
-// CHECK-NEXT: store i8 [[TMP427]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP428:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP429:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP430:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP428]], i8 [[TMP429]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP431:%.*]] = extractvalue { i8, i1 } [[TMP430]], 0
-// CHECK-NEXT: [[TMP432:%.*]] = extractvalue { i8, i1 } [[TMP430]], 1
-// CHECK-NEXT: [[TMP433:%.*]] = select i1 [[TMP432]], i8 [[TMP428]], i8 [[TMP431]]
-// CHECK-NEXT: store i8 [[TMP433]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP434:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP435:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP436:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP434]], i8 [[TMP435]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP437:%.*]] = extractvalue { i8, i1 } [[TMP436]], 0
-// CHECK-NEXT: [[TMP438:%.*]] = extractvalue { i8, i1 } [[TMP436]], 1
-// CHECK-NEXT: br i1 [[TMP438]], label [[CX_ATOMIC_EXIT39:%.*]], label [[CX_ATOMIC_CONT40:%.*]]
-// CHECK: cx.atomic.cont40:
-// CHECK-NEXT: store i8 [[TMP437]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT39]]
-// CHECK: cx.atomic.exit39:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP439:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP440:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP441:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP439]], i8 [[TMP440]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP442:%.*]] = extractvalue { i8, i1 } [[TMP441]], 0
-// CHECK-NEXT: [[TMP443:%.*]] = extractvalue { i8, i1 } [[TMP441]], 1
-// CHECK-NEXT: br i1 [[TMP443]], label [[CX_ATOMIC_EXIT41:%.*]], label [[CX_ATOMIC_CONT42:%.*]]
-// CHECK: cx.atomic.cont42:
-// CHECK-NEXT: store i8 [[TMP442]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT41]]
-// CHECK: cx.atomic.exit41:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP444:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP445:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP446:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP444]], i8 [[TMP445]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP447:%.*]] = extractvalue { i8, i1 } [[TMP446]], 1
-// CHECK-NEXT: [[TMP448:%.*]] = sext i1 [[TMP447]] to i8
-// CHECK-NEXT: store i8 [[TMP448]], ptr [[CR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP449:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP450:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP451:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP449]], i8 [[TMP450]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP452:%.*]] = extractvalue { i8, i1 } [[TMP451]], 1
-// CHECK-NEXT: [[TMP453:%.*]] = sext i1 [[TMP452]] to i8
-// CHECK-NEXT: store i8 [[TMP453]], ptr [[CR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP454:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP455:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP456:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP454]], i8 [[TMP455]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP457:%.*]] = extractvalue { i8, i1 } [[TMP456]], 0
-// CHECK-NEXT: [[TMP458:%.*]] = extractvalue { i8, i1 } [[TMP456]], 1
-// CHECK-NEXT: br i1 [[TMP458]], label [[CX_ATOMIC_EXIT43:%.*]], label [[CX_ATOMIC_CONT44:%.*]]
-// CHECK: cx.atomic.cont44:
-// CHECK-NEXT: store i8 [[TMP457]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT43]]
-// CHECK: cx.atomic.exit43:
-// CHECK-NEXT: [[TMP459:%.*]] = extractvalue { i8, i1 } [[TMP456]], 1
-// CHECK-NEXT: [[TMP460:%.*]] = sext i1 [[TMP459]] to i8
-// CHECK-NEXT: store i8 [[TMP460]], ptr [[CR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP461:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP462:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP463:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP461]], i8 [[TMP462]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP464:%.*]] = extractvalue { i8, i1 } [[TMP463]], 0
-// CHECK-NEXT: [[TMP465:%.*]] = extractvalue { i8, i1 } [[TMP463]], 1
-// CHECK-NEXT: br i1 [[TMP465]], label [[CX_ATOMIC_EXIT45:%.*]], label [[CX_ATOMIC_CONT46:%.*]]
-// CHECK: cx.atomic.cont46:
-// CHECK-NEXT: store i8 [[TMP464]], ptr [[CV]], align 1
-// CHECK-NEXT: br label [[CX_ATOMIC_EXIT45]]
-// CHECK: cx.atomic.exit45:
-// CHECK-NEXT: [[TMP466:%.*]] = extractvalue { i8, i1 } [[TMP463]], 1
-// CHECK-NEXT: [[TMP467:%.*]] = sext i1 [[TMP466]] to i8
-// CHECK-NEXT: store i8 [[TMP467]], ptr [[CR]], align 1
+// CHECK-NEXT: store i8 [[TMP272]], ptr [[CX_ATOMIC_EXPECTED_PTR518]], align 1
+// CHECK-NEXT: store i8 [[TMP273]], ptr [[CX_ATOMIC_DESIRED_PTR519]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED521:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR518]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED522:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR519]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR523:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED521]], i8 [[CX_CMPXCHG_DESIRED522]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV524:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR523]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV524]], ptr [[CX_ATOMIC_EXPECTED_PTR520]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS525:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR523]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL526:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR520]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS525]], label [[CX_ATOMIC_EXIT527:%.*]], label [[CX_ATOMIC_CONT528:%.*]]
+// CHECK: cx.atomic.cont528:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL526]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT527]]
+// CHECK: cx.atomic.exit527:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP274:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP275:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP274]], ptr [[CX_ATOMIC_EXPECTED_PTR529]], align 1
+// CHECK-NEXT: store i8 [[TMP275]], ptr [[CX_ATOMIC_DESIRED_PTR530]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED532:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR529]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED533:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR530]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR534:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED532]], i8 [[CX_CMPXCHG_DESIRED533]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV535:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR534]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV535]], ptr [[CX_ATOMIC_EXPECTED_PTR531]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS536:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR534]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL537:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR531]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS536]], label [[CX_ATOMIC_EXIT538:%.*]], label [[CX_ATOMIC_CONT539:%.*]]
+// CHECK: cx.atomic.cont539:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL537]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT538]]
+// CHECK: cx.atomic.exit538:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP276:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP277:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP276]], ptr [[CX_ATOMIC_EXPECTED_PTR540]], align 1
+// CHECK-NEXT: store i8 [[TMP277]], ptr [[CX_ATOMIC_DESIRED_PTR541]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED543:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR540]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED544:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR541]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR545:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED543]], i8 [[CX_CMPXCHG_DESIRED544]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV546:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR545]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV546]], ptr [[CX_ATOMIC_EXPECTED_PTR542]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS547:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR545]], 1
+// CHECK-NEXT: [[TMP278:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS547]] to i8
+// CHECK-NEXT: store i8 [[TMP278]], ptr [[CR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP279:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP280:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP279]], ptr [[CX_ATOMIC_EXPECTED_PTR548]], align 1
+// CHECK-NEXT: store i8 [[TMP280]], ptr [[CX_ATOMIC_DESIRED_PTR549]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED551:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR548]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED552:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR549]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR553:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED551]], i8 [[CX_CMPXCHG_DESIRED552]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV554:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR553]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV554]], ptr [[CX_ATOMIC_EXPECTED_PTR550]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS555:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR553]], 1
+// CHECK-NEXT: [[TMP281:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS555]] to i8
+// CHECK-NEXT: store i8 [[TMP281]], ptr [[CR]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP282:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP283:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP282]], ptr [[CX_ATOMIC_EXPECTED_PTR556]], align 1
+// CHECK-NEXT: store i8 [[TMP283]], ptr [[CX_ATOMIC_DESIRED_PTR557]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED559:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR556]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED560:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR557]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR561:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED559]], i8 [[CX_CMPXCHG_DESIRED560]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV562:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR561]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV562]], ptr [[CX_ATOMIC_EXPECTED_PTR558]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS563:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR561]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL564:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR558]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS563]], label [[CX_ATOMIC_EXIT565:%.*]], label [[CX_ATOMIC_CONT566:%.*]]
+// CHECK: cx.atomic.cont566:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL564]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT565]]
+// CHECK: cx.atomic.exit565:
+// CHECK-NEXT: [[TMP284:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS563]] to i8
+// CHECK-NEXT: store i8 [[TMP284]], ptr [[CR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP285:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP286:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP285]], ptr [[CX_ATOMIC_EXPECTED_PTR567]], align 1
+// CHECK-NEXT: store i8 [[TMP286]], ptr [[CX_ATOMIC_DESIRED_PTR568]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED570:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR567]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED571:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR568]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR572:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED570]], i8 [[CX_CMPXCHG_DESIRED571]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV573:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR572]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV573]], ptr [[CX_ATOMIC_EXPECTED_PTR569]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS574:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR572]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL575:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR569]], align 1
+// CHECK-NEXT: br i1 [[CX_CMPXCHG_SUCCESS574]], label [[CX_ATOMIC_EXIT576:%.*]], label [[CX_ATOMIC_CONT577:%.*]]
+// CHECK: cx.atomic.cont577:
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL575]], ptr [[CV]], align 1
+// CHECK-NEXT: br label [[CX_ATOMIC_EXIT576]]
+// CHECK: cx.atomic.exit576:
+// CHECK-NEXT: [[TMP287:%.*]] = sext i1 [[CX_CMPXCHG_SUCCESS574]] to i8
+// CHECK-NEXT: store i8 [[TMP287]], ptr [[CR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP288:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP289:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP288]] monotonic, align 1
+// CHECK-NEXT: store i8 [[TMP289]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP290:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP291:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP290]] monotonic, align 1
+// CHECK-NEXT: store i8 [[TMP291]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP292:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP293:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP292]] monotonic, align 1
+// CHECK-NEXT: store i8 [[TMP293]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP294:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP295:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP294]] monotonic, align 1
+// CHECK-NEXT: store i8 [[TMP295]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP296:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP297:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP296]], ptr [[UCX_ATOMIC_EXPECTED_PTR]], align 1
+// CHECK-NEXT: store i8 [[TMP297]], ptr [[UCX_ATOMIC_DESIRED_PTR]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED]], i8 [[UCX_CMPXCHG_DESIRED]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV]], ptr [[UCX_ATOMIC_EXPECTED_PTR578]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR578]], align 1
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP298:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP299:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP298]], ptr [[UCX_ATOMIC_EXPECTED_PTR579]], align 1
+// CHECK-NEXT: store i8 [[TMP299]], ptr [[UCX_ATOMIC_DESIRED_PTR580]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED582:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR579]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED583:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR580]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR584:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED582]], i8 [[UCX_CMPXCHG_DESIRED583]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV585:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR584]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV585]], ptr [[UCX_ATOMIC_EXPECTED_PTR581]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS586:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR584]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL587:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR581]], align 1
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL587]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP300:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP301:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP300]] monotonic, align 1
+// CHECK-NEXT: [[TMP302:%.*]] = icmp ugt i8 [[TMP301]], [[TMP300]]
+// CHECK-NEXT: [[TMP303:%.*]] = select i1 [[TMP302]], i8 [[TMP300]], i8 [[TMP301]]
+// CHECK-NEXT: store i8 [[TMP303]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP304:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP305:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP304]] monotonic, align 1
+// CHECK-NEXT: [[TMP306:%.*]] = icmp ult i8 [[TMP305]], [[TMP304]]
+// CHECK-NEXT: [[TMP307:%.*]] = select i1 [[TMP306]], i8 [[TMP304]], i8 [[TMP305]]
+// CHECK-NEXT: store i8 [[TMP307]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP308:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP309:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP308]] monotonic, align 1
+// CHECK-NEXT: [[TMP310:%.*]] = icmp ult i8 [[TMP309]], [[TMP308]]
+// CHECK-NEXT: [[TMP311:%.*]] = select i1 [[TMP310]], i8 [[TMP308]], i8 [[TMP309]]
+// CHECK-NEXT: store i8 [[TMP311]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP312:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP313:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP312]] monotonic, align 1
+// CHECK-NEXT: [[TMP314:%.*]] = icmp ugt i8 [[TMP313]], [[TMP312]]
+// CHECK-NEXT: [[TMP315:%.*]] = select i1 [[TMP314]], i8 [[TMP312]], i8 [[TMP313]]
+// CHECK-NEXT: store i8 [[TMP315]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP316:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP317:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP316]], ptr [[UCX_ATOMIC_EXPECTED_PTR588]], align 1
+// CHECK-NEXT: store i8 [[TMP317]], ptr [[UCX_ATOMIC_DESIRED_PTR589]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED591:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR588]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED592:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR589]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR593:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED591]], i8 [[UCX_CMPXCHG_DESIRED592]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV594:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR593]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV594]], ptr [[UCX_ATOMIC_EXPECTED_PTR590]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS595:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR593]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL596:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR590]], align 1
+// CHECK-NEXT: [[UCX_CAPTURE_CAPTURED:%.*]] = select i1 [[UCX_CMPXCHG_SUCCESS595]], i8 [[TMP316]], i8 [[UCX_CAPTURE_ACTUAL596]]
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_CAPTURED]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP318:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP319:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP318]], ptr [[UCX_ATOMIC_EXPECTED_PTR597]], align 1
+// CHECK-NEXT: store i8 [[TMP319]], ptr [[UCX_ATOMIC_DESIRED_PTR598]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED600:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR597]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED601:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR598]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR602:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED600]], i8 [[UCX_CMPXCHG_DESIRED601]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV603:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR602]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV603]], ptr [[UCX_ATOMIC_EXPECTED_PTR599]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS604:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR602]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL605:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR599]], align 1
+// CHECK-NEXT: [[UCX_CAPTURE_CAPTURED606:%.*]] = select i1 [[UCX_CMPXCHG_SUCCESS604]], i8 [[TMP318]], i8 [[UCX_CAPTURE_ACTUAL605]]
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_CAPTURED606]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP320:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP321:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP320]], ptr [[UCX_ATOMIC_EXPECTED_PTR607]], align 1
+// CHECK-NEXT: store i8 [[TMP321]], ptr [[UCX_ATOMIC_DESIRED_PTR608]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED610:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR607]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED611:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR608]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR612:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED610]], i8 [[UCX_CMPXCHG_DESIRED611]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV613:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR612]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV613]], ptr [[UCX_ATOMIC_EXPECTED_PTR609]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS614:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR612]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL615:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR609]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS614]], label [[UCX_ATOMIC_EXIT:%.*]], label [[UCX_ATOMIC_CONT:%.*]]
+// CHECK: ucx.atomic.cont:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL615]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT]]
+// CHECK: ucx.atomic.exit:
+// CHECK-NEXT: [[TMP322:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP323:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP322]], ptr [[UCX_ATOMIC_EXPECTED_PTR616]], align 1
+// CHECK-NEXT: store i8 [[TMP323]], ptr [[UCX_ATOMIC_DESIRED_PTR617]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED619:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR616]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED620:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR617]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR621:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED619]], i8 [[UCX_CMPXCHG_DESIRED620]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV622:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR621]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV622]], ptr [[UCX_ATOMIC_EXPECTED_PTR618]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS623:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR621]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL624:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR618]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS623]], label [[UCX_ATOMIC_EXIT625:%.*]], label [[UCX_ATOMIC_CONT626:%.*]]
+// CHECK: ucx.atomic.cont626:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL624]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT625]]
+// CHECK: ucx.atomic.exit625:
+// CHECK-NEXT: [[TMP324:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP325:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP324]], ptr [[UCX_ATOMIC_EXPECTED_PTR627]], align 1
+// CHECK-NEXT: store i8 [[TMP325]], ptr [[UCX_ATOMIC_DESIRED_PTR628]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED630:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR627]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED631:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR628]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR632:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED630]], i8 [[UCX_CMPXCHG_DESIRED631]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV633:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR632]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV633]], ptr [[UCX_ATOMIC_EXPECTED_PTR629]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS634:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR632]], 1
+// CHECK-NEXT: [[TMP326:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS634]] to i8
+// CHECK-NEXT: store i8 [[TMP326]], ptr [[UCR]], align 1
+// CHECK-NEXT: [[TMP327:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP328:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP327]], ptr [[UCX_ATOMIC_EXPECTED_PTR635]], align 1
+// CHECK-NEXT: store i8 [[TMP328]], ptr [[UCX_ATOMIC_DESIRED_PTR636]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED638:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR635]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED639:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR636]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR640:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED638]], i8 [[UCX_CMPXCHG_DESIRED639]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV641:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR640]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV641]], ptr [[UCX_ATOMIC_EXPECTED_PTR637]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS642:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR640]], 1
+// CHECK-NEXT: [[TMP329:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS642]] to i8
+// CHECK-NEXT: store i8 [[TMP329]], ptr [[UCR]], align 1
+// CHECK-NEXT: [[TMP330:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP331:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP330]], ptr [[UCX_ATOMIC_EXPECTED_PTR643]], align 1
+// CHECK-NEXT: store i8 [[TMP331]], ptr [[UCX_ATOMIC_DESIRED_PTR644]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED646:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR643]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED647:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR644]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR648:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED646]], i8 [[UCX_CMPXCHG_DESIRED647]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV649:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR648]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV649]], ptr [[UCX_ATOMIC_EXPECTED_PTR645]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS650:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR648]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL651:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR645]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS650]], label [[UCX_ATOMIC_EXIT652:%.*]], label [[UCX_ATOMIC_CONT653:%.*]]
+// CHECK: ucx.atomic.cont653:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL651]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT652]]
+// CHECK: ucx.atomic.exit652:
+// CHECK-NEXT: [[TMP332:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS650]] to i8
+// CHECK-NEXT: store i8 [[TMP332]], ptr [[UCR]], align 1
+// CHECK-NEXT: [[TMP333:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP334:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP333]], ptr [[UCX_ATOMIC_EXPECTED_PTR654]], align 1
+// CHECK-NEXT: store i8 [[TMP334]], ptr [[UCX_ATOMIC_DESIRED_PTR655]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED657:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR654]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED658:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR655]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR659:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED657]], i8 [[UCX_CMPXCHG_DESIRED658]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV660:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR659]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV660]], ptr [[UCX_ATOMIC_EXPECTED_PTR656]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS661:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR659]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL662:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR656]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS661]], label [[UCX_ATOMIC_EXIT663:%.*]], label [[UCX_ATOMIC_CONT664:%.*]]
+// CHECK: ucx.atomic.cont664:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL662]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT663]]
+// CHECK: ucx.atomic.exit663:
+// CHECK-NEXT: [[TMP335:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS661]] to i8
+// CHECK-NEXT: store i8 [[TMP335]], ptr [[UCR]], align 1
+// CHECK-NEXT: [[TMP336:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP337:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP336]] acq_rel, align 1
+// CHECK-NEXT: store i8 [[TMP337]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP338:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP339:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP338]] acq_rel, align 1
+// CHECK-NEXT: store i8 [[TMP339]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP340:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP341:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP340]] acq_rel, align 1
+// CHECK-NEXT: store i8 [[TMP341]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP342:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP343:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP342]] acq_rel, align 1
+// CHECK-NEXT: store i8 [[TMP343]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP344:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP345:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP344]], ptr [[UCX_ATOMIC_EXPECTED_PTR665]], align 1
+// CHECK-NEXT: store i8 [[TMP345]], ptr [[UCX_ATOMIC_DESIRED_PTR666]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED668:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR665]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED669:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR666]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR670:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED668]], i8 [[UCX_CMPXCHG_DESIRED669]] acq_rel acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV671:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR670]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV671]], ptr [[UCX_ATOMIC_EXPECTED_PTR667]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS672:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR670]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL673:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR667]], align 1
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL673]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP346:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP347:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP346]], ptr [[UCX_ATOMIC_EXPECTED_PTR674]], align 1
+// CHECK-NEXT: store i8 [[TMP347]], ptr [[UCX_ATOMIC_DESIRED_PTR675]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED677:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR674]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED678:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR675]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR679:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED677]], i8 [[UCX_CMPXCHG_DESIRED678]] acq_rel acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV680:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR679]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV680]], ptr [[UCX_ATOMIC_EXPECTED_PTR676]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS681:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR679]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL682:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR676]], align 1
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL682]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP348:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP349:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP348]] acq_rel, align 1
+// CHECK-NEXT: [[TMP350:%.*]] = icmp ugt i8 [[TMP349]], [[TMP348]]
+// CHECK-NEXT: [[TMP351:%.*]] = select i1 [[TMP350]], i8 [[TMP348]], i8 [[TMP349]]
+// CHECK-NEXT: store i8 [[TMP351]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP352:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP353:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP352]] acq_rel, align 1
+// CHECK-NEXT: [[TMP354:%.*]] = icmp ult i8 [[TMP353]], [[TMP352]]
+// CHECK-NEXT: [[TMP355:%.*]] = select i1 [[TMP354]], i8 [[TMP352]], i8 [[TMP353]]
+// CHECK-NEXT: store i8 [[TMP355]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP356:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP357:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP356]] acq_rel, align 1
+// CHECK-NEXT: [[TMP358:%.*]] = icmp ult i8 [[TMP357]], [[TMP356]]
+// CHECK-NEXT: [[TMP359:%.*]] = select i1 [[TMP358]], i8 [[TMP356]], i8 [[TMP357]]
+// CHECK-NEXT: store i8 [[TMP359]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP360:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP361:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP360]] acq_rel, align 1
+// CHECK-NEXT: [[TMP362:%.*]] = icmp ugt i8 [[TMP361]], [[TMP360]]
+// CHECK-NEXT: [[TMP363:%.*]] = select i1 [[TMP362]], i8 [[TMP360]], i8 [[TMP361]]
+// CHECK-NEXT: store i8 [[TMP363]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP364:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP365:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP364]], ptr [[UCX_ATOMIC_EXPECTED_PTR683]], align 1
+// CHECK-NEXT: store i8 [[TMP365]], ptr [[UCX_ATOMIC_DESIRED_PTR684]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED686:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR683]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED687:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR684]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR688:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED686]], i8 [[UCX_CMPXCHG_DESIRED687]] acq_rel acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV689:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR688]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV689]], ptr [[UCX_ATOMIC_EXPECTED_PTR685]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS690:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR688]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL691:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR685]], align 1
+// CHECK-NEXT: [[UCX_CAPTURE_CAPTURED692:%.*]] = select i1 [[UCX_CMPXCHG_SUCCESS690]], i8 [[TMP364]], i8 [[UCX_CAPTURE_ACTUAL691]]
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_CAPTURED692]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP366:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP367:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP366]], ptr [[UCX_ATOMIC_EXPECTED_PTR693]], align 1
+// CHECK-NEXT: store i8 [[TMP367]], ptr [[UCX_ATOMIC_DESIRED_PTR694]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED696:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR693]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED697:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR694]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR698:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED696]], i8 [[UCX_CMPXCHG_DESIRED697]] acq_rel acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV699:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR698]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV699]], ptr [[UCX_ATOMIC_EXPECTED_PTR695]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS700:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR698]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL701:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR695]], align 1
+// CHECK-NEXT: [[UCX_CAPTURE_CAPTURED702:%.*]] = select i1 [[UCX_CMPXCHG_SUCCESS700]], i8 [[TMP366]], i8 [[UCX_CAPTURE_ACTUAL701]]
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_CAPTURED702]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP368:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP369:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP368]], ptr [[UCX_ATOMIC_EXPECTED_PTR703]], align 1
+// CHECK-NEXT: store i8 [[TMP369]], ptr [[UCX_ATOMIC_DESIRED_PTR704]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED706:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR703]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED707:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR704]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR708:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED706]], i8 [[UCX_CMPXCHG_DESIRED707]] acq_rel acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV709:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR708]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV709]], ptr [[UCX_ATOMIC_EXPECTED_PTR705]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS710:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR708]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL711:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR705]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS710]], label [[UCX_ATOMIC_EXIT712:%.*]], label [[UCX_ATOMIC_CONT713:%.*]]
+// CHECK: ucx.atomic.cont713:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL711]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT712]]
+// CHECK: ucx.atomic.exit712:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP370:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP371:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP370]], ptr [[UCX_ATOMIC_EXPECTED_PTR714]], align 1
+// CHECK-NEXT: store i8 [[TMP371]], ptr [[UCX_ATOMIC_DESIRED_PTR715]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED717:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR714]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED718:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR715]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR719:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED717]], i8 [[UCX_CMPXCHG_DESIRED718]] acq_rel acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV720:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR719]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV720]], ptr [[UCX_ATOMIC_EXPECTED_PTR716]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS721:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR719]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL722:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR716]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS721]], label [[UCX_ATOMIC_EXIT723:%.*]], label [[UCX_ATOMIC_CONT724:%.*]]
+// CHECK: ucx.atomic.cont724:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL722]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT723]]
+// CHECK: ucx.atomic.exit723:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP372:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP373:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP372]], ptr [[UCX_ATOMIC_EXPECTED_PTR725]], align 1
+// CHECK-NEXT: store i8 [[TMP373]], ptr [[UCX_ATOMIC_DESIRED_PTR726]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED728:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR725]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED729:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR726]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR730:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED728]], i8 [[UCX_CMPXCHG_DESIRED729]] acq_rel acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV731:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR730]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV731]], ptr [[UCX_ATOMIC_EXPECTED_PTR727]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS732:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR730]], 1
+// CHECK-NEXT: [[TMP374:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS732]] to i8
+// CHECK-NEXT: store i8 [[TMP374]], ptr [[UCR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP375:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP376:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP375]], ptr [[UCX_ATOMIC_EXPECTED_PTR733]], align 1
+// CHECK-NEXT: store i8 [[TMP376]], ptr [[UCX_ATOMIC_DESIRED_PTR734]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED736:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR733]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED737:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR734]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR738:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED736]], i8 [[UCX_CMPXCHG_DESIRED737]] acq_rel acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV739:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR738]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV739]], ptr [[UCX_ATOMIC_EXPECTED_PTR735]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS740:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR738]], 1
+// CHECK-NEXT: [[TMP377:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS740]] to i8
+// CHECK-NEXT: store i8 [[TMP377]], ptr [[UCR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP378:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP379:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP378]], ptr [[UCX_ATOMIC_EXPECTED_PTR741]], align 1
+// CHECK-NEXT: store i8 [[TMP379]], ptr [[UCX_ATOMIC_DESIRED_PTR742]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED744:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR741]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED745:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR742]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR746:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED744]], i8 [[UCX_CMPXCHG_DESIRED745]] acq_rel acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV747:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR746]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV747]], ptr [[UCX_ATOMIC_EXPECTED_PTR743]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS748:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR746]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL749:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR743]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS748]], label [[UCX_ATOMIC_EXIT750:%.*]], label [[UCX_ATOMIC_CONT751:%.*]]
+// CHECK: ucx.atomic.cont751:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL749]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT750]]
+// CHECK: ucx.atomic.exit750:
+// CHECK-NEXT: [[TMP380:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS748]] to i8
+// CHECK-NEXT: store i8 [[TMP380]], ptr [[UCR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP381:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP382:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP381]], ptr [[UCX_ATOMIC_EXPECTED_PTR752]], align 1
+// CHECK-NEXT: store i8 [[TMP382]], ptr [[UCX_ATOMIC_DESIRED_PTR753]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED755:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR752]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED756:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR753]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR757:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED755]], i8 [[UCX_CMPXCHG_DESIRED756]] acq_rel acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV758:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR757]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV758]], ptr [[UCX_ATOMIC_EXPECTED_PTR754]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS759:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR757]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL760:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR754]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS759]], label [[UCX_ATOMIC_EXIT761:%.*]], label [[UCX_ATOMIC_CONT762:%.*]]
+// CHECK: ucx.atomic.cont762:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL760]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT761]]
+// CHECK: ucx.atomic.exit761:
+// CHECK-NEXT: [[TMP383:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS759]] to i8
+// CHECK-NEXT: store i8 [[TMP383]], ptr [[UCR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP384:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP385:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP384]] acquire, align 1
+// CHECK-NEXT: store i8 [[TMP385]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP386:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP387:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP386]] acquire, align 1
+// CHECK-NEXT: store i8 [[TMP387]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP388:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP389:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP388]] acquire, align 1
+// CHECK-NEXT: store i8 [[TMP389]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP390:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP391:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP390]] acquire, align 1
+// CHECK-NEXT: store i8 [[TMP391]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP392:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP393:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP392]], ptr [[UCX_ATOMIC_EXPECTED_PTR763]], align 1
+// CHECK-NEXT: store i8 [[TMP393]], ptr [[UCX_ATOMIC_DESIRED_PTR764]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED766:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR763]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED767:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR764]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR768:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED766]], i8 [[UCX_CMPXCHG_DESIRED767]] acquire acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV769:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR768]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV769]], ptr [[UCX_ATOMIC_EXPECTED_PTR765]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS770:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR768]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL771:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR765]], align 1
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL771]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP394:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP395:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP394]], ptr [[UCX_ATOMIC_EXPECTED_PTR772]], align 1
+// CHECK-NEXT: store i8 [[TMP395]], ptr [[UCX_ATOMIC_DESIRED_PTR773]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED775:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR772]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED776:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR773]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR777:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED775]], i8 [[UCX_CMPXCHG_DESIRED776]] acquire acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV778:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR777]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV778]], ptr [[UCX_ATOMIC_EXPECTED_PTR774]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS779:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR777]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL780:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR774]], align 1
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL780]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP396:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP397:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP396]] acquire, align 1
+// CHECK-NEXT: [[TMP398:%.*]] = icmp ugt i8 [[TMP397]], [[TMP396]]
+// CHECK-NEXT: [[TMP399:%.*]] = select i1 [[TMP398]], i8 [[TMP396]], i8 [[TMP397]]
+// CHECK-NEXT: store i8 [[TMP399]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP400:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP401:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP400]] acquire, align 1
+// CHECK-NEXT: [[TMP402:%.*]] = icmp ult i8 [[TMP401]], [[TMP400]]
+// CHECK-NEXT: [[TMP403:%.*]] = select i1 [[TMP402]], i8 [[TMP400]], i8 [[TMP401]]
+// CHECK-NEXT: store i8 [[TMP403]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP404:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP405:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP404]] acquire, align 1
+// CHECK-NEXT: [[TMP406:%.*]] = icmp ult i8 [[TMP405]], [[TMP404]]
+// CHECK-NEXT: [[TMP407:%.*]] = select i1 [[TMP406]], i8 [[TMP404]], i8 [[TMP405]]
+// CHECK-NEXT: store i8 [[TMP407]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP408:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP409:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP408]] acquire, align 1
+// CHECK-NEXT: [[TMP410:%.*]] = icmp ugt i8 [[TMP409]], [[TMP408]]
+// CHECK-NEXT: [[TMP411:%.*]] = select i1 [[TMP410]], i8 [[TMP408]], i8 [[TMP409]]
+// CHECK-NEXT: store i8 [[TMP411]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP412:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP413:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP412]], ptr [[UCX_ATOMIC_EXPECTED_PTR781]], align 1
+// CHECK-NEXT: store i8 [[TMP413]], ptr [[UCX_ATOMIC_DESIRED_PTR782]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED784:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR781]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED785:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR782]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR786:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED784]], i8 [[UCX_CMPXCHG_DESIRED785]] acquire acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV787:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR786]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV787]], ptr [[UCX_ATOMIC_EXPECTED_PTR783]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS788:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR786]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL789:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR783]], align 1
+// CHECK-NEXT: [[UCX_CAPTURE_CAPTURED790:%.*]] = select i1 [[UCX_CMPXCHG_SUCCESS788]], i8 [[TMP412]], i8 [[UCX_CAPTURE_ACTUAL789]]
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_CAPTURED790]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP414:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP415:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP414]], ptr [[UCX_ATOMIC_EXPECTED_PTR791]], align 1
+// CHECK-NEXT: store i8 [[TMP415]], ptr [[UCX_ATOMIC_DESIRED_PTR792]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED794:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR791]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED795:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR792]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR796:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED794]], i8 [[UCX_CMPXCHG_DESIRED795]] acquire acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV797:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR796]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV797]], ptr [[UCX_ATOMIC_EXPECTED_PTR793]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS798:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR796]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL799:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR793]], align 1
+// CHECK-NEXT: [[UCX_CAPTURE_CAPTURED800:%.*]] = select i1 [[UCX_CMPXCHG_SUCCESS798]], i8 [[TMP414]], i8 [[UCX_CAPTURE_ACTUAL799]]
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_CAPTURED800]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP416:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP417:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP416]], ptr [[UCX_ATOMIC_EXPECTED_PTR801]], align 1
+// CHECK-NEXT: store i8 [[TMP417]], ptr [[UCX_ATOMIC_DESIRED_PTR802]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED804:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR801]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED805:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR802]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR806:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED804]], i8 [[UCX_CMPXCHG_DESIRED805]] acquire acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV807:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR806]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV807]], ptr [[UCX_ATOMIC_EXPECTED_PTR803]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS808:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR806]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL809:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR803]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS808]], label [[UCX_ATOMIC_EXIT810:%.*]], label [[UCX_ATOMIC_CONT811:%.*]]
+// CHECK: ucx.atomic.cont811:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL809]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT810]]
+// CHECK: ucx.atomic.exit810:
+// CHECK-NEXT: [[TMP418:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP419:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP418]], ptr [[UCX_ATOMIC_EXPECTED_PTR812]], align 1
+// CHECK-NEXT: store i8 [[TMP419]], ptr [[UCX_ATOMIC_DESIRED_PTR813]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED815:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR812]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED816:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR813]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR817:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED815]], i8 [[UCX_CMPXCHG_DESIRED816]] acquire acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV818:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR817]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV818]], ptr [[UCX_ATOMIC_EXPECTED_PTR814]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS819:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR817]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL820:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR814]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS819]], label [[UCX_ATOMIC_EXIT821:%.*]], label [[UCX_ATOMIC_CONT822:%.*]]
+// CHECK: ucx.atomic.cont822:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL820]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT821]]
+// CHECK: ucx.atomic.exit821:
+// CHECK-NEXT: [[TMP420:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP421:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP420]], ptr [[UCX_ATOMIC_EXPECTED_PTR823]], align 1
+// CHECK-NEXT: store i8 [[TMP421]], ptr [[UCX_ATOMIC_DESIRED_PTR824]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED826:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR823]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED827:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR824]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR828:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED826]], i8 [[UCX_CMPXCHG_DESIRED827]] acquire acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV829:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR828]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV829]], ptr [[UCX_ATOMIC_EXPECTED_PTR825]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS830:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR828]], 1
+// CHECK-NEXT: [[TMP422:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS830]] to i8
+// CHECK-NEXT: store i8 [[TMP422]], ptr [[UCR]], align 1
+// CHECK-NEXT: [[TMP423:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP424:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP423]], ptr [[UCX_ATOMIC_EXPECTED_PTR831]], align 1
+// CHECK-NEXT: store i8 [[TMP424]], ptr [[UCX_ATOMIC_DESIRED_PTR832]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED834:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR831]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED835:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR832]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR836:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED834]], i8 [[UCX_CMPXCHG_DESIRED835]] acquire acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV837:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR836]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV837]], ptr [[UCX_ATOMIC_EXPECTED_PTR833]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS838:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR836]], 1
+// CHECK-NEXT: [[TMP425:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS838]] to i8
+// CHECK-NEXT: store i8 [[TMP425]], ptr [[UCR]], align 1
+// CHECK-NEXT: [[TMP426:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP427:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP426]], ptr [[UCX_ATOMIC_EXPECTED_PTR839]], align 1
+// CHECK-NEXT: store i8 [[TMP427]], ptr [[UCX_ATOMIC_DESIRED_PTR840]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED842:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR839]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED843:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR840]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR844:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED842]], i8 [[UCX_CMPXCHG_DESIRED843]] acquire acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV845:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR844]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV845]], ptr [[UCX_ATOMIC_EXPECTED_PTR841]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS846:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR844]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL847:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR841]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS846]], label [[UCX_ATOMIC_EXIT848:%.*]], label [[UCX_ATOMIC_CONT849:%.*]]
+// CHECK: ucx.atomic.cont849:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL847]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT848]]
+// CHECK: ucx.atomic.exit848:
+// CHECK-NEXT: [[TMP428:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS846]] to i8
+// CHECK-NEXT: store i8 [[TMP428]], ptr [[UCR]], align 1
+// CHECK-NEXT: [[TMP429:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP430:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP429]], ptr [[UCX_ATOMIC_EXPECTED_PTR850]], align 1
+// CHECK-NEXT: store i8 [[TMP430]], ptr [[UCX_ATOMIC_DESIRED_PTR851]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED853:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR850]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED854:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR851]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR855:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED853]], i8 [[UCX_CMPXCHG_DESIRED854]] acquire acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV856:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR855]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV856]], ptr [[UCX_ATOMIC_EXPECTED_PTR852]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS857:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR855]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL858:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR852]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS857]], label [[UCX_ATOMIC_EXIT859:%.*]], label [[UCX_ATOMIC_CONT860:%.*]]
+// CHECK: ucx.atomic.cont860:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL858]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT859]]
+// CHECK: ucx.atomic.exit859:
+// CHECK-NEXT: [[TMP431:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS857]] to i8
+// CHECK-NEXT: store i8 [[TMP431]], ptr [[UCR]], align 1
+// CHECK-NEXT: [[TMP432:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP433:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP432]] monotonic, align 1
+// CHECK-NEXT: store i8 [[TMP433]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP434:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP435:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP434]] monotonic, align 1
+// CHECK-NEXT: store i8 [[TMP435]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP436:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP437:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP436]] monotonic, align 1
+// CHECK-NEXT: store i8 [[TMP437]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP438:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP439:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP438]] monotonic, align 1
+// CHECK-NEXT: store i8 [[TMP439]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP440:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP441:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP440]], ptr [[UCX_ATOMIC_EXPECTED_PTR861]], align 1
+// CHECK-NEXT: store i8 [[TMP441]], ptr [[UCX_ATOMIC_DESIRED_PTR862]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED864:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR861]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED865:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR862]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR866:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED864]], i8 [[UCX_CMPXCHG_DESIRED865]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV867:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR866]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV867]], ptr [[UCX_ATOMIC_EXPECTED_PTR863]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS868:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR866]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL869:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR863]], align 1
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL869]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP442:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP443:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP442]], ptr [[UCX_ATOMIC_EXPECTED_PTR870]], align 1
+// CHECK-NEXT: store i8 [[TMP443]], ptr [[UCX_ATOMIC_DESIRED_PTR871]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED873:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR870]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED874:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR871]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR875:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED873]], i8 [[UCX_CMPXCHG_DESIRED874]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV876:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR875]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV876]], ptr [[UCX_ATOMIC_EXPECTED_PTR872]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS877:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR875]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL878:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR872]], align 1
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL878]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP444:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP445:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP444]] monotonic, align 1
+// CHECK-NEXT: [[TMP446:%.*]] = icmp ugt i8 [[TMP445]], [[TMP444]]
+// CHECK-NEXT: [[TMP447:%.*]] = select i1 [[TMP446]], i8 [[TMP444]], i8 [[TMP445]]
+// CHECK-NEXT: store i8 [[TMP447]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP448:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP449:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP448]] monotonic, align 1
+// CHECK-NEXT: [[TMP450:%.*]] = icmp ult i8 [[TMP449]], [[TMP448]]
+// CHECK-NEXT: [[TMP451:%.*]] = select i1 [[TMP450]], i8 [[TMP448]], i8 [[TMP449]]
+// CHECK-NEXT: store i8 [[TMP451]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP452:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP453:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP452]] monotonic, align 1
+// CHECK-NEXT: [[TMP454:%.*]] = icmp ult i8 [[TMP453]], [[TMP452]]
+// CHECK-NEXT: [[TMP455:%.*]] = select i1 [[TMP454]], i8 [[TMP452]], i8 [[TMP453]]
+// CHECK-NEXT: store i8 [[TMP455]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP456:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP457:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP456]] monotonic, align 1
+// CHECK-NEXT: [[TMP458:%.*]] = icmp ugt i8 [[TMP457]], [[TMP456]]
+// CHECK-NEXT: [[TMP459:%.*]] = select i1 [[TMP458]], i8 [[TMP456]], i8 [[TMP457]]
+// CHECK-NEXT: store i8 [[TMP459]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP460:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP461:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP460]], ptr [[UCX_ATOMIC_EXPECTED_PTR879]], align 1
+// CHECK-NEXT: store i8 [[TMP461]], ptr [[UCX_ATOMIC_DESIRED_PTR880]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED882:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR879]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED883:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR880]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR884:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED882]], i8 [[UCX_CMPXCHG_DESIRED883]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV885:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR884]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV885]], ptr [[UCX_ATOMIC_EXPECTED_PTR881]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS886:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR884]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL887:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR881]], align 1
+// CHECK-NEXT: [[UCX_CAPTURE_CAPTURED888:%.*]] = select i1 [[UCX_CMPXCHG_SUCCESS886]], i8 [[TMP460]], i8 [[UCX_CAPTURE_ACTUAL887]]
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_CAPTURED888]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP462:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP463:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP462]], ptr [[UCX_ATOMIC_EXPECTED_PTR889]], align 1
+// CHECK-NEXT: store i8 [[TMP463]], ptr [[UCX_ATOMIC_DESIRED_PTR890]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED892:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR889]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED893:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR890]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR894:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED892]], i8 [[UCX_CMPXCHG_DESIRED893]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV895:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR894]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV895]], ptr [[UCX_ATOMIC_EXPECTED_PTR891]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS896:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR894]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL897:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR891]], align 1
+// CHECK-NEXT: [[UCX_CAPTURE_CAPTURED898:%.*]] = select i1 [[UCX_CMPXCHG_SUCCESS896]], i8 [[TMP462]], i8 [[UCX_CAPTURE_ACTUAL897]]
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_CAPTURED898]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP464:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP465:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP464]], ptr [[UCX_ATOMIC_EXPECTED_PTR899]], align 1
+// CHECK-NEXT: store i8 [[TMP465]], ptr [[UCX_ATOMIC_DESIRED_PTR900]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED902:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR899]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED903:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR900]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR904:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED902]], i8 [[UCX_CMPXCHG_DESIRED903]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV905:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR904]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV905]], ptr [[UCX_ATOMIC_EXPECTED_PTR901]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS906:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR904]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL907:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR901]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS906]], label [[UCX_ATOMIC_EXIT908:%.*]], label [[UCX_ATOMIC_CONT909:%.*]]
+// CHECK: ucx.atomic.cont909:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL907]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT908]]
+// CHECK: ucx.atomic.exit908:
+// CHECK-NEXT: [[TMP466:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP467:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP466]], ptr [[UCX_ATOMIC_EXPECTED_PTR910]], align 1
+// CHECK-NEXT: store i8 [[TMP467]], ptr [[UCX_ATOMIC_DESIRED_PTR911]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED913:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR910]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED914:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR911]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR915:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED913]], i8 [[UCX_CMPXCHG_DESIRED914]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV916:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR915]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV916]], ptr [[UCX_ATOMIC_EXPECTED_PTR912]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS917:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR915]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL918:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR912]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS917]], label [[UCX_ATOMIC_EXIT919:%.*]], label [[UCX_ATOMIC_CONT920:%.*]]
+// CHECK: ucx.atomic.cont920:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL918]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT919]]
+// CHECK: ucx.atomic.exit919:
// CHECK-NEXT: [[TMP468:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP469:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP468]] monotonic, align 1
-// CHECK-NEXT: store i8 [[TMP469]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP470:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP471:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP470]] monotonic, align 1
-// CHECK-NEXT: store i8 [[TMP471]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP472:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP473:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP472]] monotonic, align 1
-// CHECK-NEXT: store i8 [[TMP473]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP469:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP468]], ptr [[UCX_ATOMIC_EXPECTED_PTR921]], align 1
+// CHECK-NEXT: store i8 [[TMP469]], ptr [[UCX_ATOMIC_DESIRED_PTR922]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED924:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR921]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED925:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR922]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR926:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED924]], i8 [[UCX_CMPXCHG_DESIRED925]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV927:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR926]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV927]], ptr [[UCX_ATOMIC_EXPECTED_PTR923]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS928:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR926]], 1
+// CHECK-NEXT: [[TMP470:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS928]] to i8
+// CHECK-NEXT: store i8 [[TMP470]], ptr [[UCR]], align 1
+// CHECK-NEXT: [[TMP471:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP472:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP471]], ptr [[UCX_ATOMIC_EXPECTED_PTR929]], align 1
+// CHECK-NEXT: store i8 [[TMP472]], ptr [[UCX_ATOMIC_DESIRED_PTR930]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED932:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR929]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED933:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR930]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR934:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED932]], i8 [[UCX_CMPXCHG_DESIRED933]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV935:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR934]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV935]], ptr [[UCX_ATOMIC_EXPECTED_PTR931]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS936:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR934]], 1
+// CHECK-NEXT: [[TMP473:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS936]] to i8
+// CHECK-NEXT: store i8 [[TMP473]], ptr [[UCR]], align 1
// CHECK-NEXT: [[TMP474:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP475:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP474]] monotonic, align 1
-// CHECK-NEXT: store i8 [[TMP475]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP476:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP477:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP478:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP476]], i8 [[TMP477]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP479:%.*]] = extractvalue { i8, i1 } [[TMP478]], 0
-// CHECK-NEXT: store i8 [[TMP479]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP475:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP474]], ptr [[UCX_ATOMIC_EXPECTED_PTR937]], align 1
+// CHECK-NEXT: store i8 [[TMP475]], ptr [[UCX_ATOMIC_DESIRED_PTR938]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED940:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR937]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED941:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR938]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR942:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED940]], i8 [[UCX_CMPXCHG_DESIRED941]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV943:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR942]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV943]], ptr [[UCX_ATOMIC_EXPECTED_PTR939]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS944:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR942]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL945:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR939]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS944]], label [[UCX_ATOMIC_EXIT946:%.*]], label [[UCX_ATOMIC_CONT947:%.*]]
+// CHECK: ucx.atomic.cont947:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL945]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT946]]
+// CHECK: ucx.atomic.exit946:
+// CHECK-NEXT: [[TMP476:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS944]] to i8
+// CHECK-NEXT: store i8 [[TMP476]], ptr [[UCR]], align 1
+// CHECK-NEXT: [[TMP477:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP478:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP477]], ptr [[UCX_ATOMIC_EXPECTED_PTR948]], align 1
+// CHECK-NEXT: store i8 [[TMP478]], ptr [[UCX_ATOMIC_DESIRED_PTR949]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED951:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR948]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED952:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR949]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR953:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED951]], i8 [[UCX_CMPXCHG_DESIRED952]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV954:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR953]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV954]], ptr [[UCX_ATOMIC_EXPECTED_PTR950]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS955:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR953]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL956:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR950]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS955]], label [[UCX_ATOMIC_EXIT957:%.*]], label [[UCX_ATOMIC_CONT958:%.*]]
+// CHECK: ucx.atomic.cont958:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL956]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT957]]
+// CHECK: ucx.atomic.exit957:
+// CHECK-NEXT: [[TMP479:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS955]] to i8
+// CHECK-NEXT: store i8 [[TMP479]], ptr [[UCR]], align 1
// CHECK-NEXT: [[TMP480:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP481:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP482:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP480]], i8 [[TMP481]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP483:%.*]] = extractvalue { i8, i1 } [[TMP482]], 0
+// CHECK-NEXT: [[TMP481:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP480]] release, align 1
+// CHECK-NEXT: store i8 [[TMP481]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP482:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP483:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP482]] release, align 1
// CHECK-NEXT: store i8 [[TMP483]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP484:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP485:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP484]] monotonic, align 1
-// CHECK-NEXT: [[TMP486:%.*]] = icmp ugt i8 [[TMP485]], [[TMP484]]
-// CHECK-NEXT: [[TMP487:%.*]] = select i1 [[TMP486]], i8 [[TMP484]], i8 [[TMP485]]
+// CHECK-NEXT: [[TMP485:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP484]] release, align 1
+// CHECK-NEXT: store i8 [[TMP485]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP486:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP487:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP486]] release, align 1
// CHECK-NEXT: store i8 [[TMP487]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP488:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP489:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP488]] monotonic, align 1
-// CHECK-NEXT: [[TMP490:%.*]] = icmp ult i8 [[TMP489]], [[TMP488]]
-// CHECK-NEXT: [[TMP491:%.*]] = select i1 [[TMP490]], i8 [[TMP488]], i8 [[TMP489]]
-// CHECK-NEXT: store i8 [[TMP491]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP489:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP488]], ptr [[UCX_ATOMIC_EXPECTED_PTR959]], align 1
+// CHECK-NEXT: store i8 [[TMP489]], ptr [[UCX_ATOMIC_DESIRED_PTR960]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED962:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR959]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED963:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR960]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR964:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED962]], i8 [[UCX_CMPXCHG_DESIRED963]] release monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV965:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR964]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV965]], ptr [[UCX_ATOMIC_EXPECTED_PTR961]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS966:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR964]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL967:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR961]], align 1
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL967]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP490:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP491:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP490]], ptr [[UCX_ATOMIC_EXPECTED_PTR968]], align 1
+// CHECK-NEXT: store i8 [[TMP491]], ptr [[UCX_ATOMIC_DESIRED_PTR969]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED971:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR968]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED972:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR969]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR973:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED971]], i8 [[UCX_CMPXCHG_DESIRED972]] release monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV974:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR973]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV974]], ptr [[UCX_ATOMIC_EXPECTED_PTR970]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS975:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR973]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL976:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR970]], align 1
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL976]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP492:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP493:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP492]] monotonic, align 1
-// CHECK-NEXT: [[TMP494:%.*]] = icmp ult i8 [[TMP493]], [[TMP492]]
+// CHECK-NEXT: [[TMP493:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP492]] release, align 1
+// CHECK-NEXT: [[TMP494:%.*]] = icmp ugt i8 [[TMP493]], [[TMP492]]
// CHECK-NEXT: [[TMP495:%.*]] = select i1 [[TMP494]], i8 [[TMP492]], i8 [[TMP493]]
// CHECK-NEXT: store i8 [[TMP495]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP496:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP497:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP496]] monotonic, align 1
-// CHECK-NEXT: [[TMP498:%.*]] = icmp ugt i8 [[TMP497]], [[TMP496]]
+// CHECK-NEXT: [[TMP497:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP496]] release, align 1
+// CHECK-NEXT: [[TMP498:%.*]] = icmp ult i8 [[TMP497]], [[TMP496]]
// CHECK-NEXT: [[TMP499:%.*]] = select i1 [[TMP498]], i8 [[TMP496]], i8 [[TMP497]]
// CHECK-NEXT: store i8 [[TMP499]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP500:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP501:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP502:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP500]], i8 [[TMP501]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP503:%.*]] = extractvalue { i8, i1 } [[TMP502]], 0
-// CHECK-NEXT: [[TMP504:%.*]] = extractvalue { i8, i1 } [[TMP502]], 1
-// CHECK-NEXT: [[TMP505:%.*]] = select i1 [[TMP504]], i8 [[TMP500]], i8 [[TMP503]]
-// CHECK-NEXT: store i8 [[TMP505]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP506:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP507:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP508:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP506]], i8 [[TMP507]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP509:%.*]] = extractvalue { i8, i1 } [[TMP508]], 0
-// CHECK-NEXT: [[TMP510:%.*]] = extractvalue { i8, i1 } [[TMP508]], 1
-// CHECK-NEXT: [[TMP511:%.*]] = select i1 [[TMP510]], i8 [[TMP506]], i8 [[TMP509]]
-// CHECK-NEXT: store i8 [[TMP511]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP501:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP500]] release, align 1
+// CHECK-NEXT: [[TMP502:%.*]] = icmp ult i8 [[TMP501]], [[TMP500]]
+// CHECK-NEXT: [[TMP503:%.*]] = select i1 [[TMP502]], i8 [[TMP500]], i8 [[TMP501]]
+// CHECK-NEXT: store i8 [[TMP503]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP504:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP505:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP504]] release, align 1
+// CHECK-NEXT: [[TMP506:%.*]] = icmp ugt i8 [[TMP505]], [[TMP504]]
+// CHECK-NEXT: [[TMP507:%.*]] = select i1 [[TMP506]], i8 [[TMP504]], i8 [[TMP505]]
+// CHECK-NEXT: store i8 [[TMP507]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP508:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP509:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP508]], ptr [[UCX_ATOMIC_EXPECTED_PTR977]], align 1
+// CHECK-NEXT: store i8 [[TMP509]], ptr [[UCX_ATOMIC_DESIRED_PTR978]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED980:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR977]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED981:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR978]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR982:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED980]], i8 [[UCX_CMPXCHG_DESIRED981]] release monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV983:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR982]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV983]], ptr [[UCX_ATOMIC_EXPECTED_PTR979]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS984:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR982]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL985:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR979]], align 1
+// CHECK-NEXT: [[UCX_CAPTURE_CAPTURED986:%.*]] = select i1 [[UCX_CMPXCHG_SUCCESS984]], i8 [[TMP508]], i8 [[UCX_CAPTURE_ACTUAL985]]
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_CAPTURED986]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP510:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP511:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP510]], ptr [[UCX_ATOMIC_EXPECTED_PTR987]], align 1
+// CHECK-NEXT: store i8 [[TMP511]], ptr [[UCX_ATOMIC_DESIRED_PTR988]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED990:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR987]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED991:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR988]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR992:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED990]], i8 [[UCX_CMPXCHG_DESIRED991]] release monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV993:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR992]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV993]], ptr [[UCX_ATOMIC_EXPECTED_PTR989]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS994:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR992]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL995:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR989]], align 1
+// CHECK-NEXT: [[UCX_CAPTURE_CAPTURED996:%.*]] = select i1 [[UCX_CMPXCHG_SUCCESS994]], i8 [[TMP510]], i8 [[UCX_CAPTURE_ACTUAL995]]
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_CAPTURED996]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP512:%.*]] = load i8, ptr [[UCE]], align 1
// CHECK-NEXT: [[TMP513:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP514:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP512]], i8 [[TMP513]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP515:%.*]] = extractvalue { i8, i1 } [[TMP514]], 0
-// CHECK-NEXT: [[TMP516:%.*]] = extractvalue { i8, i1 } [[TMP514]], 1
-// CHECK-NEXT: br i1 [[TMP516]], label [[UCX_ATOMIC_EXIT:%.*]], label [[UCX_ATOMIC_CONT:%.*]]
-// CHECK: ucx.atomic.cont:
-// CHECK-NEXT: store i8 [[TMP515]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT]]
-// CHECK: ucx.atomic.exit:
-// CHECK-NEXT: [[TMP517:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP518:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP519:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP517]], i8 [[TMP518]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP520:%.*]] = extractvalue { i8, i1 } [[TMP519]], 0
-// CHECK-NEXT: [[TMP521:%.*]] = extractvalue { i8, i1 } [[TMP519]], 1
-// CHECK-NEXT: br i1 [[TMP521]], label [[UCX_ATOMIC_EXIT47:%.*]], label [[UCX_ATOMIC_CONT48:%.*]]
-// CHECK: ucx.atomic.cont48:
-// CHECK-NEXT: store i8 [[TMP520]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT47]]
-// CHECK: ucx.atomic.exit47:
+// CHECK-NEXT: store i8 [[TMP512]], ptr [[UCX_ATOMIC_EXPECTED_PTR997]], align 1
+// CHECK-NEXT: store i8 [[TMP513]], ptr [[UCX_ATOMIC_DESIRED_PTR998]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED1000:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR997]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED1001:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR998]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR1002:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED1000]], i8 [[UCX_CMPXCHG_DESIRED1001]] release monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV1003:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1002]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV1003]], ptr [[UCX_ATOMIC_EXPECTED_PTR999]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS1004:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1002]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL1005:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR999]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS1004]], label [[UCX_ATOMIC_EXIT1006:%.*]], label [[UCX_ATOMIC_CONT1007:%.*]]
+// CHECK: ucx.atomic.cont1007:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL1005]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT1006]]
+// CHECK: ucx.atomic.exit1006:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP514:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP515:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP514]], ptr [[UCX_ATOMIC_EXPECTED_PTR1008]], align 1
+// CHECK-NEXT: store i8 [[TMP515]], ptr [[UCX_ATOMIC_DESIRED_PTR1009]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED1011:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1008]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED1012:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR1009]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR1013:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED1011]], i8 [[UCX_CMPXCHG_DESIRED1012]] release monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV1014:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1013]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV1014]], ptr [[UCX_ATOMIC_EXPECTED_PTR1010]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS1015:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1013]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL1016:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1010]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS1015]], label [[UCX_ATOMIC_EXIT1017:%.*]], label [[UCX_ATOMIC_CONT1018:%.*]]
+// CHECK: ucx.atomic.cont1018:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL1016]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT1017]]
+// CHECK: ucx.atomic.exit1017:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP516:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP517:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP516]], ptr [[UCX_ATOMIC_EXPECTED_PTR1019]], align 1
+// CHECK-NEXT: store i8 [[TMP517]], ptr [[UCX_ATOMIC_DESIRED_PTR1020]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED1022:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1019]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED1023:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR1020]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR1024:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED1022]], i8 [[UCX_CMPXCHG_DESIRED1023]] release monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV1025:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1024]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV1025]], ptr [[UCX_ATOMIC_EXPECTED_PTR1021]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS1026:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1024]], 1
+// CHECK-NEXT: [[TMP518:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS1026]] to i8
+// CHECK-NEXT: store i8 [[TMP518]], ptr [[UCR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP519:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP520:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP519]], ptr [[UCX_ATOMIC_EXPECTED_PTR1027]], align 1
+// CHECK-NEXT: store i8 [[TMP520]], ptr [[UCX_ATOMIC_DESIRED_PTR1028]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED1030:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1027]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED1031:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR1028]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR1032:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED1030]], i8 [[UCX_CMPXCHG_DESIRED1031]] release monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV1033:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1032]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV1033]], ptr [[UCX_ATOMIC_EXPECTED_PTR1029]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS1034:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1032]], 1
+// CHECK-NEXT: [[TMP521:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS1034]] to i8
+// CHECK-NEXT: store i8 [[TMP521]], ptr [[UCR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP522:%.*]] = load i8, ptr [[UCE]], align 1
// CHECK-NEXT: [[TMP523:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP524:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP522]], i8 [[TMP523]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP525:%.*]] = extractvalue { i8, i1 } [[TMP524]], 1
-// CHECK-NEXT: [[TMP526:%.*]] = zext i1 [[TMP525]] to i8
-// CHECK-NEXT: store i8 [[TMP526]], ptr [[UCR]], align 1
-// CHECK-NEXT: [[TMP527:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP528:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP529:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP527]], i8 [[TMP528]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP530:%.*]] = extractvalue { i8, i1 } [[TMP529]], 1
-// CHECK-NEXT: [[TMP531:%.*]] = zext i1 [[TMP530]] to i8
-// CHECK-NEXT: store i8 [[TMP531]], ptr [[UCR]], align 1
+// CHECK-NEXT: store i8 [[TMP522]], ptr [[UCX_ATOMIC_EXPECTED_PTR1035]], align 1
+// CHECK-NEXT: store i8 [[TMP523]], ptr [[UCX_ATOMIC_DESIRED_PTR1036]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED1038:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1035]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED1039:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR1036]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR1040:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED1038]], i8 [[UCX_CMPXCHG_DESIRED1039]] release monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV1041:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1040]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV1041]], ptr [[UCX_ATOMIC_EXPECTED_PTR1037]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS1042:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1040]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL1043:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1037]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS1042]], label [[UCX_ATOMIC_EXIT1044:%.*]], label [[UCX_ATOMIC_CONT1045:%.*]]
+// CHECK: ucx.atomic.cont1045:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL1043]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT1044]]
+// CHECK: ucx.atomic.exit1044:
+// CHECK-NEXT: [[TMP524:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS1042]] to i8
+// CHECK-NEXT: store i8 [[TMP524]], ptr [[UCR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP525:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP526:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP525]], ptr [[UCX_ATOMIC_EXPECTED_PTR1046]], align 1
+// CHECK-NEXT: store i8 [[TMP526]], ptr [[UCX_ATOMIC_DESIRED_PTR1047]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED1049:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1046]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED1050:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR1047]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR1051:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED1049]], i8 [[UCX_CMPXCHG_DESIRED1050]] release monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV1052:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1051]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV1052]], ptr [[UCX_ATOMIC_EXPECTED_PTR1048]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS1053:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1051]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL1054:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1048]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS1053]], label [[UCX_ATOMIC_EXIT1055:%.*]], label [[UCX_ATOMIC_CONT1056:%.*]]
+// CHECK: ucx.atomic.cont1056:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL1054]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT1055]]
+// CHECK: ucx.atomic.exit1055:
+// CHECK-NEXT: [[TMP527:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS1053]] to i8
+// CHECK-NEXT: store i8 [[TMP527]], ptr [[UCR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP528:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP529:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP528]] seq_cst, align 1
+// CHECK-NEXT: store i8 [[TMP529]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP530:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP531:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP530]] seq_cst, align 1
+// CHECK-NEXT: store i8 [[TMP531]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP532:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP533:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP534:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP532]], i8 [[TMP533]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP535:%.*]] = extractvalue { i8, i1 } [[TMP534]], 0
-// CHECK-NEXT: [[TMP536:%.*]] = extractvalue { i8, i1 } [[TMP534]], 1
-// CHECK-NEXT: br i1 [[TMP536]], label [[UCX_ATOMIC_EXIT49:%.*]], label [[UCX_ATOMIC_CONT50:%.*]]
-// CHECK: ucx.atomic.cont50:
+// CHECK-NEXT: [[TMP533:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP532]] seq_cst, align 1
+// CHECK-NEXT: store i8 [[TMP533]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP534:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP535:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP534]] seq_cst, align 1
// CHECK-NEXT: store i8 [[TMP535]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT49]]
-// CHECK: ucx.atomic.exit49:
-// CHECK-NEXT: [[TMP537:%.*]] = extractvalue { i8, i1 } [[TMP534]], 1
-// CHECK-NEXT: [[TMP538:%.*]] = zext i1 [[TMP537]] to i8
-// CHECK-NEXT: store i8 [[TMP538]], ptr [[UCR]], align 1
-// CHECK-NEXT: [[TMP539:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP540:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP541:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP539]], i8 [[TMP540]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP542:%.*]] = extractvalue { i8, i1 } [[TMP541]], 0
-// CHECK-NEXT: [[TMP543:%.*]] = extractvalue { i8, i1 } [[TMP541]], 1
-// CHECK-NEXT: br i1 [[TMP543]], label [[UCX_ATOMIC_EXIT51:%.*]], label [[UCX_ATOMIC_CONT52:%.*]]
-// CHECK: ucx.atomic.cont52:
-// CHECK-NEXT: store i8 [[TMP542]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT51]]
-// CHECK: ucx.atomic.exit51:
-// CHECK-NEXT: [[TMP544:%.*]] = extractvalue { i8, i1 } [[TMP541]], 1
-// CHECK-NEXT: [[TMP545:%.*]] = zext i1 [[TMP544]] to i8
-// CHECK-NEXT: store i8 [[TMP545]], ptr [[UCR]], align 1
-// CHECK-NEXT: [[TMP546:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP547:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP546]] acq_rel, align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP536:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP537:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP536]], ptr [[UCX_ATOMIC_EXPECTED_PTR1057]], align 1
+// CHECK-NEXT: store i8 [[TMP537]], ptr [[UCX_ATOMIC_DESIRED_PTR1058]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED1060:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1057]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED1061:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR1058]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR1062:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED1060]], i8 [[UCX_CMPXCHG_DESIRED1061]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV1063:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1062]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV1063]], ptr [[UCX_ATOMIC_EXPECTED_PTR1059]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS1064:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1062]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL1065:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1059]], align 1
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL1065]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP538:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP539:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP538]], ptr [[UCX_ATOMIC_EXPECTED_PTR1066]], align 1
+// CHECK-NEXT: store i8 [[TMP539]], ptr [[UCX_ATOMIC_DESIRED_PTR1067]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED1069:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1066]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED1070:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR1067]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR1071:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED1069]], i8 [[UCX_CMPXCHG_DESIRED1070]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV1072:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1071]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV1072]], ptr [[UCX_ATOMIC_EXPECTED_PTR1068]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS1073:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1071]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL1074:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1068]], align 1
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL1074]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP540:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP541:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP540]] seq_cst, align 1
+// CHECK-NEXT: [[TMP542:%.*]] = icmp ugt i8 [[TMP541]], [[TMP540]]
+// CHECK-NEXT: [[TMP543:%.*]] = select i1 [[TMP542]], i8 [[TMP540]], i8 [[TMP541]]
+// CHECK-NEXT: store i8 [[TMP543]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP544:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP545:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP544]] seq_cst, align 1
+// CHECK-NEXT: [[TMP546:%.*]] = icmp ult i8 [[TMP545]], [[TMP544]]
+// CHECK-NEXT: [[TMP547:%.*]] = select i1 [[TMP546]], i8 [[TMP544]], i8 [[TMP545]]
// CHECK-NEXT: store i8 [[TMP547]], ptr [[UCV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP548:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP549:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP548]] acq_rel, align 1
-// CHECK-NEXT: store i8 [[TMP549]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP550:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP551:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP550]] acq_rel, align 1
+// CHECK-NEXT: [[TMP549:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP548]] seq_cst, align 1
+// CHECK-NEXT: [[TMP550:%.*]] = icmp ult i8 [[TMP549]], [[TMP548]]
+// CHECK-NEXT: [[TMP551:%.*]] = select i1 [[TMP550]], i8 [[TMP548]], i8 [[TMP549]]
// CHECK-NEXT: store i8 [[TMP551]], ptr [[UCV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP552:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP553:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP552]] acq_rel, align 1
-// CHECK-NEXT: store i8 [[TMP553]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP554:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP555:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP556:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP554]], i8 [[TMP555]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP557:%.*]] = extractvalue { i8, i1 } [[TMP556]], 0
-// CHECK-NEXT: store i8 [[TMP557]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP553:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP552]] seq_cst, align 1
+// CHECK-NEXT: [[TMP554:%.*]] = icmp ugt i8 [[TMP553]], [[TMP552]]
+// CHECK-NEXT: [[TMP555:%.*]] = select i1 [[TMP554]], i8 [[TMP552]], i8 [[TMP553]]
+// CHECK-NEXT: store i8 [[TMP555]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP556:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP557:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP556]], ptr [[UCX_ATOMIC_EXPECTED_PTR1075]], align 1
+// CHECK-NEXT: store i8 [[TMP557]], ptr [[UCX_ATOMIC_DESIRED_PTR1076]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED1078:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1075]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED1079:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR1076]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR1080:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED1078]], i8 [[UCX_CMPXCHG_DESIRED1079]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV1081:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1080]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV1081]], ptr [[UCX_ATOMIC_EXPECTED_PTR1077]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS1082:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1080]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL1083:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1077]], align 1
+// CHECK-NEXT: [[UCX_CAPTURE_CAPTURED1084:%.*]] = select i1 [[UCX_CMPXCHG_SUCCESS1082]], i8 [[TMP556]], i8 [[UCX_CAPTURE_ACTUAL1083]]
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_CAPTURED1084]], ptr [[UCV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP558:%.*]] = load i8, ptr [[UCE]], align 1
// CHECK-NEXT: [[TMP559:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP560:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP558]], i8 [[TMP559]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP561:%.*]] = extractvalue { i8, i1 } [[TMP560]], 0
-// CHECK-NEXT: store i8 [[TMP561]], ptr [[UCV]], align 1
+// CHECK-NEXT: store i8 [[TMP558]], ptr [[UCX_ATOMIC_EXPECTED_PTR1085]], align 1
+// CHECK-NEXT: store i8 [[TMP559]], ptr [[UCX_ATOMIC_DESIRED_PTR1086]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED1088:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1085]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED1089:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR1086]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR1090:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED1088]], i8 [[UCX_CMPXCHG_DESIRED1089]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV1091:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1090]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV1091]], ptr [[UCX_ATOMIC_EXPECTED_PTR1087]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS1092:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1090]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL1093:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1087]], align 1
+// CHECK-NEXT: [[UCX_CAPTURE_CAPTURED1094:%.*]] = select i1 [[UCX_CMPXCHG_SUCCESS1092]], i8 [[TMP558]], i8 [[UCX_CAPTURE_ACTUAL1093]]
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_CAPTURED1094]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP560:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP561:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP560]], ptr [[UCX_ATOMIC_EXPECTED_PTR1095]], align 1
+// CHECK-NEXT: store i8 [[TMP561]], ptr [[UCX_ATOMIC_DESIRED_PTR1096]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED1098:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1095]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED1099:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR1096]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR1100:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED1098]], i8 [[UCX_CMPXCHG_DESIRED1099]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV1101:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1100]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV1101]], ptr [[UCX_ATOMIC_EXPECTED_PTR1097]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS1102:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1100]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL1103:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1097]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS1102]], label [[UCX_ATOMIC_EXIT1104:%.*]], label [[UCX_ATOMIC_CONT1105:%.*]]
+// CHECK: ucx.atomic.cont1105:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL1103]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT1104]]
+// CHECK: ucx.atomic.exit1104:
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP562:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP563:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP562]] acq_rel, align 1
-// CHECK-NEXT: [[TMP564:%.*]] = icmp ugt i8 [[TMP563]], [[TMP562]]
-// CHECK-NEXT: [[TMP565:%.*]] = select i1 [[TMP564]], i8 [[TMP562]], i8 [[TMP563]]
-// CHECK-NEXT: store i8 [[TMP565]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP566:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP567:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP566]] acq_rel, align 1
-// CHECK-NEXT: [[TMP568:%.*]] = icmp ult i8 [[TMP567]], [[TMP566]]
-// CHECK-NEXT: [[TMP569:%.*]] = select i1 [[TMP568]], i8 [[TMP566]], i8 [[TMP567]]
-// CHECK-NEXT: store i8 [[TMP569]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP563:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP562]], ptr [[UCX_ATOMIC_EXPECTED_PTR1106]], align 1
+// CHECK-NEXT: store i8 [[TMP563]], ptr [[UCX_ATOMIC_DESIRED_PTR1107]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED1109:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1106]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED1110:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR1107]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR1111:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED1109]], i8 [[UCX_CMPXCHG_DESIRED1110]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV1112:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1111]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV1112]], ptr [[UCX_ATOMIC_EXPECTED_PTR1108]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS1113:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1111]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL1114:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1108]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS1113]], label [[UCX_ATOMIC_EXIT1115:%.*]], label [[UCX_ATOMIC_CONT1116:%.*]]
+// CHECK: ucx.atomic.cont1116:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL1114]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT1115]]
+// CHECK: ucx.atomic.exit1115:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP564:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP565:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP564]], ptr [[UCX_ATOMIC_EXPECTED_PTR1117]], align 1
+// CHECK-NEXT: store i8 [[TMP565]], ptr [[UCX_ATOMIC_DESIRED_PTR1118]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED1120:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1117]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED1121:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR1118]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR1122:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED1120]], i8 [[UCX_CMPXCHG_DESIRED1121]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV1123:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1122]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV1123]], ptr [[UCX_ATOMIC_EXPECTED_PTR1119]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS1124:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1122]], 1
+// CHECK-NEXT: [[TMP566:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS1124]] to i8
+// CHECK-NEXT: store i8 [[TMP566]], ptr [[UCR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP567:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP568:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP567]], ptr [[UCX_ATOMIC_EXPECTED_PTR1125]], align 1
+// CHECK-NEXT: store i8 [[TMP568]], ptr [[UCX_ATOMIC_DESIRED_PTR1126]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED1128:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1125]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED1129:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR1126]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR1130:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED1128]], i8 [[UCX_CMPXCHG_DESIRED1129]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV1131:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1130]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV1131]], ptr [[UCX_ATOMIC_EXPECTED_PTR1127]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS1132:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1130]], 1
+// CHECK-NEXT: [[TMP569:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS1132]] to i8
+// CHECK-NEXT: store i8 [[TMP569]], ptr [[UCR]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP570:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP571:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP570]] acq_rel, align 1
-// CHECK-NEXT: [[TMP572:%.*]] = icmp ult i8 [[TMP571]], [[TMP570]]
-// CHECK-NEXT: [[TMP573:%.*]] = select i1 [[TMP572]], i8 [[TMP570]], i8 [[TMP571]]
-// CHECK-NEXT: store i8 [[TMP573]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP574:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP575:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP574]] acq_rel, align 1
-// CHECK-NEXT: [[TMP576:%.*]] = icmp ugt i8 [[TMP575]], [[TMP574]]
-// CHECK-NEXT: [[TMP577:%.*]] = select i1 [[TMP576]], i8 [[TMP574]], i8 [[TMP575]]
-// CHECK-NEXT: store i8 [[TMP577]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP578:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP579:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP580:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP578]], i8 [[TMP579]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP581:%.*]] = extractvalue { i8, i1 } [[TMP580]], 0
-// CHECK-NEXT: [[TMP582:%.*]] = extractvalue { i8, i1 } [[TMP580]], 1
-// CHECK-NEXT: [[TMP583:%.*]] = select i1 [[TMP582]], i8 [[TMP578]], i8 [[TMP581]]
-// CHECK-NEXT: store i8 [[TMP583]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP584:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP585:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP586:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP584]], i8 [[TMP585]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP587:%.*]] = extractvalue { i8, i1 } [[TMP586]], 0
-// CHECK-NEXT: [[TMP588:%.*]] = extractvalue { i8, i1 } [[TMP586]], 1
-// CHECK-NEXT: [[TMP589:%.*]] = select i1 [[TMP588]], i8 [[TMP584]], i8 [[TMP587]]
-// CHECK-NEXT: store i8 [[TMP589]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP590:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP591:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP592:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP590]], i8 [[TMP591]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP593:%.*]] = extractvalue { i8, i1 } [[TMP592]], 0
-// CHECK-NEXT: [[TMP594:%.*]] = extractvalue { i8, i1 } [[TMP592]], 1
-// CHECK-NEXT: br i1 [[TMP594]], label [[UCX_ATOMIC_EXIT53:%.*]], label [[UCX_ATOMIC_CONT54:%.*]]
-// CHECK: ucx.atomic.cont54:
-// CHECK-NEXT: store i8 [[TMP593]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT53]]
-// CHECK: ucx.atomic.exit53:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP595:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP596:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP597:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP595]], i8 [[TMP596]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP598:%.*]] = extractvalue { i8, i1 } [[TMP597]], 0
-// CHECK-NEXT: [[TMP599:%.*]] = extractvalue { i8, i1 } [[TMP597]], 1
-// CHECK-NEXT: br i1 [[TMP599]], label [[UCX_ATOMIC_EXIT55:%.*]], label [[UCX_ATOMIC_CONT56:%.*]]
-// CHECK: ucx.atomic.cont56:
-// CHECK-NEXT: store i8 [[TMP598]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT55]]
-// CHECK: ucx.atomic.exit55:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP600:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP601:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP602:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP600]], i8 [[TMP601]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP603:%.*]] = extractvalue { i8, i1 } [[TMP602]], 1
-// CHECK-NEXT: [[TMP604:%.*]] = zext i1 [[TMP603]] to i8
-// CHECK-NEXT: store i8 [[TMP604]], ptr [[UCR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP605:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP606:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP607:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP605]], i8 [[TMP606]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP608:%.*]] = extractvalue { i8, i1 } [[TMP607]], 1
-// CHECK-NEXT: [[TMP609:%.*]] = zext i1 [[TMP608]] to i8
-// CHECK-NEXT: store i8 [[TMP609]], ptr [[UCR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP610:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP611:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP612:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP610]], i8 [[TMP611]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP613:%.*]] = extractvalue { i8, i1 } [[TMP612]], 0
-// CHECK-NEXT: [[TMP614:%.*]] = extractvalue { i8, i1 } [[TMP612]], 1
-// CHECK-NEXT: br i1 [[TMP614]], label [[UCX_ATOMIC_EXIT57:%.*]], label [[UCX_ATOMIC_CONT58:%.*]]
-// CHECK: ucx.atomic.cont58:
-// CHECK-NEXT: store i8 [[TMP613]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT57]]
-// CHECK: ucx.atomic.exit57:
-// CHECK-NEXT: [[TMP615:%.*]] = extractvalue { i8, i1 } [[TMP612]], 1
-// CHECK-NEXT: [[TMP616:%.*]] = zext i1 [[TMP615]] to i8
-// CHECK-NEXT: store i8 [[TMP616]], ptr [[UCR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP617:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP618:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP619:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP617]], i8 [[TMP618]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP620:%.*]] = extractvalue { i8, i1 } [[TMP619]], 0
-// CHECK-NEXT: [[TMP621:%.*]] = extractvalue { i8, i1 } [[TMP619]], 1
-// CHECK-NEXT: br i1 [[TMP621]], label [[UCX_ATOMIC_EXIT59:%.*]], label [[UCX_ATOMIC_CONT60:%.*]]
-// CHECK: ucx.atomic.cont60:
-// CHECK-NEXT: store i8 [[TMP620]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT59]]
-// CHECK: ucx.atomic.exit59:
-// CHECK-NEXT: [[TMP622:%.*]] = extractvalue { i8, i1 } [[TMP619]], 1
-// CHECK-NEXT: [[TMP623:%.*]] = zext i1 [[TMP622]] to i8
-// CHECK-NEXT: store i8 [[TMP623]], ptr [[UCR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP624:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP625:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP624]] acquire, align 1
-// CHECK-NEXT: store i8 [[TMP625]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP626:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP627:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP626]] acquire, align 1
-// CHECK-NEXT: store i8 [[TMP627]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP628:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP629:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP628]] acquire, align 1
-// CHECK-NEXT: store i8 [[TMP629]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP630:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP631:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP630]] acquire, align 1
-// CHECK-NEXT: store i8 [[TMP631]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP632:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP633:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP634:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP632]], i8 [[TMP633]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP635:%.*]] = extractvalue { i8, i1 } [[TMP634]], 0
-// CHECK-NEXT: store i8 [[TMP635]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP636:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP637:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP638:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP636]], i8 [[TMP637]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP639:%.*]] = extractvalue { i8, i1 } [[TMP638]], 0
-// CHECK-NEXT: store i8 [[TMP639]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP640:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP641:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP640]] acquire, align 1
-// CHECK-NEXT: [[TMP642:%.*]] = icmp ugt i8 [[TMP641]], [[TMP640]]
-// CHECK-NEXT: [[TMP643:%.*]] = select i1 [[TMP642]], i8 [[TMP640]], i8 [[TMP641]]
-// CHECK-NEXT: store i8 [[TMP643]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP644:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP645:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP644]] acquire, align 1
-// CHECK-NEXT: [[TMP646:%.*]] = icmp ult i8 [[TMP645]], [[TMP644]]
-// CHECK-NEXT: [[TMP647:%.*]] = select i1 [[TMP646]], i8 [[TMP644]], i8 [[TMP645]]
-// CHECK-NEXT: store i8 [[TMP647]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP648:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP649:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP648]] acquire, align 1
-// CHECK-NEXT: [[TMP650:%.*]] = icmp ult i8 [[TMP649]], [[TMP648]]
-// CHECK-NEXT: [[TMP651:%.*]] = select i1 [[TMP650]], i8 [[TMP648]], i8 [[TMP649]]
-// CHECK-NEXT: store i8 [[TMP651]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP652:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP653:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP652]] acquire, align 1
-// CHECK-NEXT: [[TMP654:%.*]] = icmp ugt i8 [[TMP653]], [[TMP652]]
-// CHECK-NEXT: [[TMP655:%.*]] = select i1 [[TMP654]], i8 [[TMP652]], i8 [[TMP653]]
-// CHECK-NEXT: store i8 [[TMP655]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP656:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP657:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP658:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP656]], i8 [[TMP657]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP659:%.*]] = extractvalue { i8, i1 } [[TMP658]], 0
-// CHECK-NEXT: [[TMP660:%.*]] = extractvalue { i8, i1 } [[TMP658]], 1
-// CHECK-NEXT: [[TMP661:%.*]] = select i1 [[TMP660]], i8 [[TMP656]], i8 [[TMP659]]
-// CHECK-NEXT: store i8 [[TMP661]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP662:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP663:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP664:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP662]], i8 [[TMP663]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP665:%.*]] = extractvalue { i8, i1 } [[TMP664]], 0
-// CHECK-NEXT: [[TMP666:%.*]] = extractvalue { i8, i1 } [[TMP664]], 1
-// CHECK-NEXT: [[TMP667:%.*]] = select i1 [[TMP666]], i8 [[TMP662]], i8 [[TMP665]]
-// CHECK-NEXT: store i8 [[TMP667]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP668:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP669:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP670:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP668]], i8 [[TMP669]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP671:%.*]] = extractvalue { i8, i1 } [[TMP670]], 0
-// CHECK-NEXT: [[TMP672:%.*]] = extractvalue { i8, i1 } [[TMP670]], 1
-// CHECK-NEXT: br i1 [[TMP672]], label [[UCX_ATOMIC_EXIT61:%.*]], label [[UCX_ATOMIC_CONT62:%.*]]
-// CHECK: ucx.atomic.cont62:
-// CHECK-NEXT: store i8 [[TMP671]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT61]]
-// CHECK: ucx.atomic.exit61:
-// CHECK-NEXT: [[TMP673:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP674:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP675:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP673]], i8 [[TMP674]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP676:%.*]] = extractvalue { i8, i1 } [[TMP675]], 0
-// CHECK-NEXT: [[TMP677:%.*]] = extractvalue { i8, i1 } [[TMP675]], 1
-// CHECK-NEXT: br i1 [[TMP677]], label [[UCX_ATOMIC_EXIT63:%.*]], label [[UCX_ATOMIC_CONT64:%.*]]
-// CHECK: ucx.atomic.cont64:
-// CHECK-NEXT: store i8 [[TMP676]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT63]]
-// CHECK: ucx.atomic.exit63:
-// CHECK-NEXT: [[TMP678:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP679:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP680:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP678]], i8 [[TMP679]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP681:%.*]] = extractvalue { i8, i1 } [[TMP680]], 1
-// CHECK-NEXT: [[TMP682:%.*]] = zext i1 [[TMP681]] to i8
-// CHECK-NEXT: store i8 [[TMP682]], ptr [[UCR]], align 1
-// CHECK-NEXT: [[TMP683:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP684:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP685:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP683]], i8 [[TMP684]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP686:%.*]] = extractvalue { i8, i1 } [[TMP685]], 1
-// CHECK-NEXT: [[TMP687:%.*]] = zext i1 [[TMP686]] to i8
-// CHECK-NEXT: store i8 [[TMP687]], ptr [[UCR]], align 1
-// CHECK-NEXT: [[TMP688:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP689:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP690:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP688]], i8 [[TMP689]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP691:%.*]] = extractvalue { i8, i1 } [[TMP690]], 0
-// CHECK-NEXT: [[TMP692:%.*]] = extractvalue { i8, i1 } [[TMP690]], 1
-// CHECK-NEXT: br i1 [[TMP692]], label [[UCX_ATOMIC_EXIT65:%.*]], label [[UCX_ATOMIC_CONT66:%.*]]
-// CHECK: ucx.atomic.cont66:
-// CHECK-NEXT: store i8 [[TMP691]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT65]]
-// CHECK: ucx.atomic.exit65:
-// CHECK-NEXT: [[TMP693:%.*]] = extractvalue { i8, i1 } [[TMP690]], 1
-// CHECK-NEXT: [[TMP694:%.*]] = zext i1 [[TMP693]] to i8
-// CHECK-NEXT: store i8 [[TMP694]], ptr [[UCR]], align 1
-// CHECK-NEXT: [[TMP695:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP696:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP697:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP695]], i8 [[TMP696]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP698:%.*]] = extractvalue { i8, i1 } [[TMP697]], 0
-// CHECK-NEXT: [[TMP699:%.*]] = extractvalue { i8, i1 } [[TMP697]], 1
-// CHECK-NEXT: br i1 [[TMP699]], label [[UCX_ATOMIC_EXIT67:%.*]], label [[UCX_ATOMIC_CONT68:%.*]]
-// CHECK: ucx.atomic.cont68:
-// CHECK-NEXT: store i8 [[TMP698]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT67]]
-// CHECK: ucx.atomic.exit67:
-// CHECK-NEXT: [[TMP700:%.*]] = extractvalue { i8, i1 } [[TMP697]], 1
-// CHECK-NEXT: [[TMP701:%.*]] = zext i1 [[TMP700]] to i8
-// CHECK-NEXT: store i8 [[TMP701]], ptr [[UCR]], align 1
-// CHECK-NEXT: [[TMP702:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP703:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP702]] monotonic, align 1
-// CHECK-NEXT: store i8 [[TMP703]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP704:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP705:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP704]] monotonic, align 1
-// CHECK-NEXT: store i8 [[TMP705]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP706:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP707:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP706]] monotonic, align 1
-// CHECK-NEXT: store i8 [[TMP707]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP708:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP709:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP708]] monotonic, align 1
-// CHECK-NEXT: store i8 [[TMP709]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP710:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP711:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP712:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP710]], i8 [[TMP711]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP713:%.*]] = extractvalue { i8, i1 } [[TMP712]], 0
-// CHECK-NEXT: store i8 [[TMP713]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP714:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP715:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP716:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP714]], i8 [[TMP715]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP717:%.*]] = extractvalue { i8, i1 } [[TMP716]], 0
-// CHECK-NEXT: store i8 [[TMP717]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP718:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP719:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP718]] monotonic, align 1
-// CHECK-NEXT: [[TMP720:%.*]] = icmp ugt i8 [[TMP719]], [[TMP718]]
-// CHECK-NEXT: [[TMP721:%.*]] = select i1 [[TMP720]], i8 [[TMP718]], i8 [[TMP719]]
-// CHECK-NEXT: store i8 [[TMP721]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP722:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP723:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP722]] monotonic, align 1
-// CHECK-NEXT: [[TMP724:%.*]] = icmp ult i8 [[TMP723]], [[TMP722]]
-// CHECK-NEXT: [[TMP725:%.*]] = select i1 [[TMP724]], i8 [[TMP722]], i8 [[TMP723]]
-// CHECK-NEXT: store i8 [[TMP725]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP726:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP727:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP726]] monotonic, align 1
-// CHECK-NEXT: [[TMP728:%.*]] = icmp ult i8 [[TMP727]], [[TMP726]]
-// CHECK-NEXT: [[TMP729:%.*]] = select i1 [[TMP728]], i8 [[TMP726]], i8 [[TMP727]]
-// CHECK-NEXT: store i8 [[TMP729]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP730:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP731:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP730]] monotonic, align 1
-// CHECK-NEXT: [[TMP732:%.*]] = icmp ugt i8 [[TMP731]], [[TMP730]]
-// CHECK-NEXT: [[TMP733:%.*]] = select i1 [[TMP732]], i8 [[TMP730]], i8 [[TMP731]]
-// CHECK-NEXT: store i8 [[TMP733]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP734:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP735:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP736:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP734]], i8 [[TMP735]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP737:%.*]] = extractvalue { i8, i1 } [[TMP736]], 0
-// CHECK-NEXT: [[TMP738:%.*]] = extractvalue { i8, i1 } [[TMP736]], 1
-// CHECK-NEXT: [[TMP739:%.*]] = select i1 [[TMP738]], i8 [[TMP734]], i8 [[TMP737]]
-// CHECK-NEXT: store i8 [[TMP739]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP740:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP741:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP742:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP740]], i8 [[TMP741]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP743:%.*]] = extractvalue { i8, i1 } [[TMP742]], 0
-// CHECK-NEXT: [[TMP744:%.*]] = extractvalue { i8, i1 } [[TMP742]], 1
-// CHECK-NEXT: [[TMP745:%.*]] = select i1 [[TMP744]], i8 [[TMP740]], i8 [[TMP743]]
-// CHECK-NEXT: store i8 [[TMP745]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP746:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP747:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP748:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP746]], i8 [[TMP747]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP749:%.*]] = extractvalue { i8, i1 } [[TMP748]], 0
-// CHECK-NEXT: [[TMP750:%.*]] = extractvalue { i8, i1 } [[TMP748]], 1
-// CHECK-NEXT: br i1 [[TMP750]], label [[UCX_ATOMIC_EXIT69:%.*]], label [[UCX_ATOMIC_CONT70:%.*]]
-// CHECK: ucx.atomic.cont70:
-// CHECK-NEXT: store i8 [[TMP749]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT69]]
-// CHECK: ucx.atomic.exit69:
-// CHECK-NEXT: [[TMP751:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP752:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP753:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP751]], i8 [[TMP752]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP754:%.*]] = extractvalue { i8, i1 } [[TMP753]], 0
-// CHECK-NEXT: [[TMP755:%.*]] = extractvalue { i8, i1 } [[TMP753]], 1
-// CHECK-NEXT: br i1 [[TMP755]], label [[UCX_ATOMIC_EXIT71:%.*]], label [[UCX_ATOMIC_CONT72:%.*]]
-// CHECK: ucx.atomic.cont72:
-// CHECK-NEXT: store i8 [[TMP754]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT71]]
-// CHECK: ucx.atomic.exit71:
-// CHECK-NEXT: [[TMP756:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP757:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP758:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP756]], i8 [[TMP757]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP759:%.*]] = extractvalue { i8, i1 } [[TMP758]], 1
-// CHECK-NEXT: [[TMP760:%.*]] = zext i1 [[TMP759]] to i8
-// CHECK-NEXT: store i8 [[TMP760]], ptr [[UCR]], align 1
-// CHECK-NEXT: [[TMP761:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP762:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP763:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP761]], i8 [[TMP762]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP764:%.*]] = extractvalue { i8, i1 } [[TMP763]], 1
-// CHECK-NEXT: [[TMP765:%.*]] = zext i1 [[TMP764]] to i8
-// CHECK-NEXT: store i8 [[TMP765]], ptr [[UCR]], align 1
-// CHECK-NEXT: [[TMP766:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP767:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP768:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP766]], i8 [[TMP767]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP769:%.*]] = extractvalue { i8, i1 } [[TMP768]], 0
-// CHECK-NEXT: [[TMP770:%.*]] = extractvalue { i8, i1 } [[TMP768]], 1
-// CHECK-NEXT: br i1 [[TMP770]], label [[UCX_ATOMIC_EXIT73:%.*]], label [[UCX_ATOMIC_CONT74:%.*]]
-// CHECK: ucx.atomic.cont74:
-// CHECK-NEXT: store i8 [[TMP769]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT73]]
-// CHECK: ucx.atomic.exit73:
-// CHECK-NEXT: [[TMP771:%.*]] = extractvalue { i8, i1 } [[TMP768]], 1
-// CHECK-NEXT: [[TMP772:%.*]] = zext i1 [[TMP771]] to i8
-// CHECK-NEXT: store i8 [[TMP772]], ptr [[UCR]], align 1
-// CHECK-NEXT: [[TMP773:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP774:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP775:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP773]], i8 [[TMP774]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP776:%.*]] = extractvalue { i8, i1 } [[TMP775]], 0
-// CHECK-NEXT: [[TMP777:%.*]] = extractvalue { i8, i1 } [[TMP775]], 1
-// CHECK-NEXT: br i1 [[TMP777]], label [[UCX_ATOMIC_EXIT75:%.*]], label [[UCX_ATOMIC_CONT76:%.*]]
-// CHECK: ucx.atomic.cont76:
-// CHECK-NEXT: store i8 [[TMP776]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT75]]
-// CHECK: ucx.atomic.exit75:
-// CHECK-NEXT: [[TMP778:%.*]] = extractvalue { i8, i1 } [[TMP775]], 1
-// CHECK-NEXT: [[TMP779:%.*]] = zext i1 [[TMP778]] to i8
-// CHECK-NEXT: store i8 [[TMP779]], ptr [[UCR]], align 1
-// CHECK-NEXT: [[TMP780:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP781:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP780]] release, align 1
-// CHECK-NEXT: store i8 [[TMP781]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP782:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP783:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP782]] release, align 1
-// CHECK-NEXT: store i8 [[TMP783]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP784:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP785:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP784]] release, align 1
-// CHECK-NEXT: store i8 [[TMP785]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP786:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP787:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP786]] release, align 1
-// CHECK-NEXT: store i8 [[TMP787]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP788:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP789:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP790:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP788]], i8 [[TMP789]] release monotonic, align 1
-// CHECK-NEXT: [[TMP791:%.*]] = extractvalue { i8, i1 } [[TMP790]], 0
-// CHECK-NEXT: store i8 [[TMP791]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP792:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP793:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP794:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP792]], i8 [[TMP793]] release monotonic, align 1
-// CHECK-NEXT: [[TMP795:%.*]] = extractvalue { i8, i1 } [[TMP794]], 0
-// CHECK-NEXT: store i8 [[TMP795]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP796:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP797:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP796]] release, align 1
-// CHECK-NEXT: [[TMP798:%.*]] = icmp ugt i8 [[TMP797]], [[TMP796]]
-// CHECK-NEXT: [[TMP799:%.*]] = select i1 [[TMP798]], i8 [[TMP796]], i8 [[TMP797]]
-// CHECK-NEXT: store i8 [[TMP799]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP800:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP801:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP800]] release, align 1
-// CHECK-NEXT: [[TMP802:%.*]] = icmp ult i8 [[TMP801]], [[TMP800]]
-// CHECK-NEXT: [[TMP803:%.*]] = select i1 [[TMP802]], i8 [[TMP800]], i8 [[TMP801]]
-// CHECK-NEXT: store i8 [[TMP803]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP804:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP805:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP804]] release, align 1
-// CHECK-NEXT: [[TMP806:%.*]] = icmp ult i8 [[TMP805]], [[TMP804]]
-// CHECK-NEXT: [[TMP807:%.*]] = select i1 [[TMP806]], i8 [[TMP804]], i8 [[TMP805]]
-// CHECK-NEXT: store i8 [[TMP807]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP808:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP809:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP808]] release, align 1
-// CHECK-NEXT: [[TMP810:%.*]] = icmp ugt i8 [[TMP809]], [[TMP808]]
-// CHECK-NEXT: [[TMP811:%.*]] = select i1 [[TMP810]], i8 [[TMP808]], i8 [[TMP809]]
-// CHECK-NEXT: store i8 [[TMP811]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP812:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP813:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP814:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP812]], i8 [[TMP813]] release monotonic, align 1
-// CHECK-NEXT: [[TMP815:%.*]] = extractvalue { i8, i1 } [[TMP814]], 0
-// CHECK-NEXT: [[TMP816:%.*]] = extractvalue { i8, i1 } [[TMP814]], 1
-// CHECK-NEXT: [[TMP817:%.*]] = select i1 [[TMP816]], i8 [[TMP812]], i8 [[TMP815]]
-// CHECK-NEXT: store i8 [[TMP817]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP818:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP819:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP820:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP818]], i8 [[TMP819]] release monotonic, align 1
-// CHECK-NEXT: [[TMP821:%.*]] = extractvalue { i8, i1 } [[TMP820]], 0
-// CHECK-NEXT: [[TMP822:%.*]] = extractvalue { i8, i1 } [[TMP820]], 1
-// CHECK-NEXT: [[TMP823:%.*]] = select i1 [[TMP822]], i8 [[TMP818]], i8 [[TMP821]]
-// CHECK-NEXT: store i8 [[TMP823]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP824:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP825:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP826:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP824]], i8 [[TMP825]] release monotonic, align 1
-// CHECK-NEXT: [[TMP827:%.*]] = extractvalue { i8, i1 } [[TMP826]], 0
-// CHECK-NEXT: [[TMP828:%.*]] = extractvalue { i8, i1 } [[TMP826]], 1
-// CHECK-NEXT: br i1 [[TMP828]], label [[UCX_ATOMIC_EXIT77:%.*]], label [[UCX_ATOMIC_CONT78:%.*]]
-// CHECK: ucx.atomic.cont78:
-// CHECK-NEXT: store i8 [[TMP827]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT77]]
-// CHECK: ucx.atomic.exit77:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP829:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP830:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP831:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP829]], i8 [[TMP830]] release monotonic, align 1
-// CHECK-NEXT: [[TMP832:%.*]] = extractvalue { i8, i1 } [[TMP831]], 0
-// CHECK-NEXT: [[TMP833:%.*]] = extractvalue { i8, i1 } [[TMP831]], 1
-// CHECK-NEXT: br i1 [[TMP833]], label [[UCX_ATOMIC_EXIT79:%.*]], label [[UCX_ATOMIC_CONT80:%.*]]
-// CHECK: ucx.atomic.cont80:
-// CHECK-NEXT: store i8 [[TMP832]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT79]]
-// CHECK: ucx.atomic.exit79:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP834:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP835:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP836:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP834]], i8 [[TMP835]] release monotonic, align 1
-// CHECK-NEXT: [[TMP837:%.*]] = extractvalue { i8, i1 } [[TMP836]], 1
-// CHECK-NEXT: [[TMP838:%.*]] = zext i1 [[TMP837]] to i8
-// CHECK-NEXT: store i8 [[TMP838]], ptr [[UCR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP839:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP840:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP841:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP839]], i8 [[TMP840]] release monotonic, align 1
-// CHECK-NEXT: [[TMP842:%.*]] = extractvalue { i8, i1 } [[TMP841]], 1
-// CHECK-NEXT: [[TMP843:%.*]] = zext i1 [[TMP842]] to i8
-// CHECK-NEXT: store i8 [[TMP843]], ptr [[UCR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP844:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP845:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP846:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP844]], i8 [[TMP845]] release monotonic, align 1
-// CHECK-NEXT: [[TMP847:%.*]] = extractvalue { i8, i1 } [[TMP846]], 0
-// CHECK-NEXT: [[TMP848:%.*]] = extractvalue { i8, i1 } [[TMP846]], 1
-// CHECK-NEXT: br i1 [[TMP848]], label [[UCX_ATOMIC_EXIT81:%.*]], label [[UCX_ATOMIC_CONT82:%.*]]
-// CHECK: ucx.atomic.cont82:
-// CHECK-NEXT: store i8 [[TMP847]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT81]]
-// CHECK: ucx.atomic.exit81:
-// CHECK-NEXT: [[TMP849:%.*]] = extractvalue { i8, i1 } [[TMP846]], 1
-// CHECK-NEXT: [[TMP850:%.*]] = zext i1 [[TMP849]] to i8
-// CHECK-NEXT: store i8 [[TMP850]], ptr [[UCR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP851:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP852:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP853:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP851]], i8 [[TMP852]] release monotonic, align 1
-// CHECK-NEXT: [[TMP854:%.*]] = extractvalue { i8, i1 } [[TMP853]], 0
-// CHECK-NEXT: [[TMP855:%.*]] = extractvalue { i8, i1 } [[TMP853]], 1
-// CHECK-NEXT: br i1 [[TMP855]], label [[UCX_ATOMIC_EXIT83:%.*]], label [[UCX_ATOMIC_CONT84:%.*]]
-// CHECK: ucx.atomic.cont84:
-// CHECK-NEXT: store i8 [[TMP854]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT83]]
-// CHECK: ucx.atomic.exit83:
-// CHECK-NEXT: [[TMP856:%.*]] = extractvalue { i8, i1 } [[TMP853]], 1
-// CHECK-NEXT: [[TMP857:%.*]] = zext i1 [[TMP856]] to i8
-// CHECK-NEXT: store i8 [[TMP857]], ptr [[UCR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP858:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP859:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP858]] seq_cst, align 1
-// CHECK-NEXT: store i8 [[TMP859]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP860:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP861:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP860]] seq_cst, align 1
-// CHECK-NEXT: store i8 [[TMP861]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP862:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP863:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP862]] seq_cst, align 1
-// CHECK-NEXT: store i8 [[TMP863]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP864:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP865:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP864]] seq_cst, align 1
-// CHECK-NEXT: store i8 [[TMP865]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP866:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP867:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP868:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP866]], i8 [[TMP867]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP869:%.*]] = extractvalue { i8, i1 } [[TMP868]], 0
-// CHECK-NEXT: store i8 [[TMP869]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP870:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP871:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP872:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP870]], i8 [[TMP871]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP873:%.*]] = extractvalue { i8, i1 } [[TMP872]], 0
-// CHECK-NEXT: store i8 [[TMP873]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP874:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP875:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP874]] seq_cst, align 1
-// CHECK-NEXT: [[TMP876:%.*]] = icmp ugt i8 [[TMP875]], [[TMP874]]
-// CHECK-NEXT: [[TMP877:%.*]] = select i1 [[TMP876]], i8 [[TMP874]], i8 [[TMP875]]
-// CHECK-NEXT: store i8 [[TMP877]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP878:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP879:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP878]] seq_cst, align 1
-// CHECK-NEXT: [[TMP880:%.*]] = icmp ult i8 [[TMP879]], [[TMP878]]
-// CHECK-NEXT: [[TMP881:%.*]] = select i1 [[TMP880]], i8 [[TMP878]], i8 [[TMP879]]
-// CHECK-NEXT: store i8 [[TMP881]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP882:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP883:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP882]] seq_cst, align 1
-// CHECK-NEXT: [[TMP884:%.*]] = icmp ult i8 [[TMP883]], [[TMP882]]
-// CHECK-NEXT: [[TMP885:%.*]] = select i1 [[TMP884]], i8 [[TMP882]], i8 [[TMP883]]
-// CHECK-NEXT: store i8 [[TMP885]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP886:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP887:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP886]] seq_cst, align 1
-// CHECK-NEXT: [[TMP888:%.*]] = icmp ugt i8 [[TMP887]], [[TMP886]]
-// CHECK-NEXT: [[TMP889:%.*]] = select i1 [[TMP888]], i8 [[TMP886]], i8 [[TMP887]]
-// CHECK-NEXT: store i8 [[TMP889]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP890:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP891:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP892:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP890]], i8 [[TMP891]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP893:%.*]] = extractvalue { i8, i1 } [[TMP892]], 0
-// CHECK-NEXT: [[TMP894:%.*]] = extractvalue { i8, i1 } [[TMP892]], 1
-// CHECK-NEXT: [[TMP895:%.*]] = select i1 [[TMP894]], i8 [[TMP890]], i8 [[TMP893]]
-// CHECK-NEXT: store i8 [[TMP895]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP896:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP897:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP898:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP896]], i8 [[TMP897]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP899:%.*]] = extractvalue { i8, i1 } [[TMP898]], 0
-// CHECK-NEXT: [[TMP900:%.*]] = extractvalue { i8, i1 } [[TMP898]], 1
-// CHECK-NEXT: [[TMP901:%.*]] = select i1 [[TMP900]], i8 [[TMP896]], i8 [[TMP899]]
-// CHECK-NEXT: store i8 [[TMP901]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP902:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP903:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP904:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP902]], i8 [[TMP903]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP905:%.*]] = extractvalue { i8, i1 } [[TMP904]], 0
-// CHECK-NEXT: [[TMP906:%.*]] = extractvalue { i8, i1 } [[TMP904]], 1
-// CHECK-NEXT: br i1 [[TMP906]], label [[UCX_ATOMIC_EXIT85:%.*]], label [[UCX_ATOMIC_CONT86:%.*]]
-// CHECK: ucx.atomic.cont86:
-// CHECK-NEXT: store i8 [[TMP905]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT85]]
-// CHECK: ucx.atomic.exit85:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP907:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP908:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP909:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP907]], i8 [[TMP908]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP910:%.*]] = extractvalue { i8, i1 } [[TMP909]], 0
-// CHECK-NEXT: [[TMP911:%.*]] = extractvalue { i8, i1 } [[TMP909]], 1
-// CHECK-NEXT: br i1 [[TMP911]], label [[UCX_ATOMIC_EXIT87:%.*]], label [[UCX_ATOMIC_CONT88:%.*]]
-// CHECK: ucx.atomic.cont88:
-// CHECK-NEXT: store i8 [[TMP910]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT87]]
-// CHECK: ucx.atomic.exit87:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP912:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP913:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP914:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP912]], i8 [[TMP913]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP915:%.*]] = extractvalue { i8, i1 } [[TMP914]], 1
-// CHECK-NEXT: [[TMP916:%.*]] = zext i1 [[TMP915]] to i8
-// CHECK-NEXT: store i8 [[TMP916]], ptr [[UCR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP917:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP918:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP919:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP917]], i8 [[TMP918]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP920:%.*]] = extractvalue { i8, i1 } [[TMP919]], 1
-// CHECK-NEXT: [[TMP921:%.*]] = zext i1 [[TMP920]] to i8
-// CHECK-NEXT: store i8 [[TMP921]], ptr [[UCR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP922:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP923:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP924:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP922]], i8 [[TMP923]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP925:%.*]] = extractvalue { i8, i1 } [[TMP924]], 0
-// CHECK-NEXT: [[TMP926:%.*]] = extractvalue { i8, i1 } [[TMP924]], 1
-// CHECK-NEXT: br i1 [[TMP926]], label [[UCX_ATOMIC_EXIT89:%.*]], label [[UCX_ATOMIC_CONT90:%.*]]
-// CHECK: ucx.atomic.cont90:
-// CHECK-NEXT: store i8 [[TMP925]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT89]]
-// CHECK: ucx.atomic.exit89:
-// CHECK-NEXT: [[TMP927:%.*]] = extractvalue { i8, i1 } [[TMP924]], 1
-// CHECK-NEXT: [[TMP928:%.*]] = zext i1 [[TMP927]] to i8
-// CHECK-NEXT: store i8 [[TMP928]], ptr [[UCR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP929:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP930:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP931:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP929]], i8 [[TMP930]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP932:%.*]] = extractvalue { i8, i1 } [[TMP931]], 0
-// CHECK-NEXT: [[TMP933:%.*]] = extractvalue { i8, i1 } [[TMP931]], 1
-// CHECK-NEXT: br i1 [[TMP933]], label [[UCX_ATOMIC_EXIT91:%.*]], label [[UCX_ATOMIC_CONT92:%.*]]
-// CHECK: ucx.atomic.cont92:
-// CHECK-NEXT: store i8 [[TMP932]], ptr [[UCV]], align 1
-// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT91]]
-// CHECK: ucx.atomic.exit91:
-// CHECK-NEXT: [[TMP934:%.*]] = extractvalue { i8, i1 } [[TMP931]], 1
-// CHECK-NEXT: [[TMP935:%.*]] = zext i1 [[TMP934]] to i8
-// CHECK-NEXT: store i8 [[TMP935]], ptr [[UCR]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP936:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP937:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP936]] monotonic, align 2
-// CHECK-NEXT: store i16 [[TMP937]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP938:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP939:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP938]] monotonic, align 2
-// CHECK-NEXT: store i16 [[TMP939]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP940:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP941:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP940]] monotonic, align 2
-// CHECK-NEXT: store i16 [[TMP941]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP942:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP943:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP942]] monotonic, align 2
-// CHECK-NEXT: store i16 [[TMP943]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP944:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP945:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP946:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP944]], i16 [[TMP945]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP947:%.*]] = extractvalue { i16, i1 } [[TMP946]], 0
-// CHECK-NEXT: store i16 [[TMP947]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP948:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP949:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP950:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP948]], i16 [[TMP949]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP951:%.*]] = extractvalue { i16, i1 } [[TMP950]], 0
-// CHECK-NEXT: store i16 [[TMP951]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP952:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP953:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP952]] monotonic, align 2
-// CHECK-NEXT: [[TMP954:%.*]] = icmp sgt i16 [[TMP953]], [[TMP952]]
-// CHECK-NEXT: [[TMP955:%.*]] = select i1 [[TMP954]], i16 [[TMP952]], i16 [[TMP953]]
-// CHECK-NEXT: store i16 [[TMP955]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP956:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP957:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP956]] monotonic, align 2
-// CHECK-NEXT: [[TMP958:%.*]] = icmp slt i16 [[TMP957]], [[TMP956]]
-// CHECK-NEXT: [[TMP959:%.*]] = select i1 [[TMP958]], i16 [[TMP956]], i16 [[TMP957]]
-// CHECK-NEXT: store i16 [[TMP959]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP960:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP961:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP960]] monotonic, align 2
-// CHECK-NEXT: [[TMP962:%.*]] = icmp slt i16 [[TMP961]], [[TMP960]]
-// CHECK-NEXT: [[TMP963:%.*]] = select i1 [[TMP962]], i16 [[TMP960]], i16 [[TMP961]]
-// CHECK-NEXT: store i16 [[TMP963]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP964:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP965:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP964]] monotonic, align 2
-// CHECK-NEXT: [[TMP966:%.*]] = icmp sgt i16 [[TMP965]], [[TMP964]]
-// CHECK-NEXT: [[TMP967:%.*]] = select i1 [[TMP966]], i16 [[TMP964]], i16 [[TMP965]]
-// CHECK-NEXT: store i16 [[TMP967]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP968:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP969:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP970:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP968]], i16 [[TMP969]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP971:%.*]] = extractvalue { i16, i1 } [[TMP970]], 0
-// CHECK-NEXT: [[TMP972:%.*]] = extractvalue { i16, i1 } [[TMP970]], 1
-// CHECK-NEXT: [[TMP973:%.*]] = select i1 [[TMP972]], i16 [[TMP968]], i16 [[TMP971]]
-// CHECK-NEXT: store i16 [[TMP973]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP974:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP975:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP976:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP974]], i16 [[TMP975]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP977:%.*]] = extractvalue { i16, i1 } [[TMP976]], 0
-// CHECK-NEXT: [[TMP978:%.*]] = extractvalue { i16, i1 } [[TMP976]], 1
-// CHECK-NEXT: [[TMP979:%.*]] = select i1 [[TMP978]], i16 [[TMP974]], i16 [[TMP977]]
-// CHECK-NEXT: store i16 [[TMP979]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP980:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP981:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP982:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP980]], i16 [[TMP981]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP983:%.*]] = extractvalue { i16, i1 } [[TMP982]], 0
-// CHECK-NEXT: [[TMP984:%.*]] = extractvalue { i16, i1 } [[TMP982]], 1
-// CHECK-NEXT: br i1 [[TMP984]], label [[SX_ATOMIC_EXIT:%.*]], label [[SX_ATOMIC_CONT:%.*]]
+// CHECK-NEXT: [[TMP571:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP570]], ptr [[UCX_ATOMIC_EXPECTED_PTR1133]], align 1
+// CHECK-NEXT: store i8 [[TMP571]], ptr [[UCX_ATOMIC_DESIRED_PTR1134]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED1136:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1133]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED1137:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR1134]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR1138:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED1136]], i8 [[UCX_CMPXCHG_DESIRED1137]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV1139:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1138]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV1139]], ptr [[UCX_ATOMIC_EXPECTED_PTR1135]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS1140:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1138]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL1141:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1135]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS1140]], label [[UCX_ATOMIC_EXIT1142:%.*]], label [[UCX_ATOMIC_CONT1143:%.*]]
+// CHECK: ucx.atomic.cont1143:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL1141]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT1142]]
+// CHECK: ucx.atomic.exit1142:
+// CHECK-NEXT: [[TMP572:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS1140]] to i8
+// CHECK-NEXT: store i8 [[TMP572]], ptr [[UCR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP573:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP574:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP573]], ptr [[UCX_ATOMIC_EXPECTED_PTR1144]], align 1
+// CHECK-NEXT: store i8 [[TMP574]], ptr [[UCX_ATOMIC_DESIRED_PTR1145]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED1147:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1144]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED1148:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR1145]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR1149:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED1147]], i8 [[UCX_CMPXCHG_DESIRED1148]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV1150:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1149]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV1150]], ptr [[UCX_ATOMIC_EXPECTED_PTR1146]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS1151:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR1149]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL1152:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1146]], align 1
+// CHECK-NEXT: br i1 [[UCX_CMPXCHG_SUCCESS1151]], label [[UCX_ATOMIC_EXIT1153:%.*]], label [[UCX_ATOMIC_CONT1154:%.*]]
+// CHECK: ucx.atomic.cont1154:
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL1152]], ptr [[UCV]], align 1
+// CHECK-NEXT: br label [[UCX_ATOMIC_EXIT1153]]
+// CHECK: ucx.atomic.exit1153:
+// CHECK-NEXT: [[TMP575:%.*]] = zext i1 [[UCX_CMPXCHG_SUCCESS1151]] to i8
+// CHECK-NEXT: store i8 [[TMP575]], ptr [[UCR]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP576:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP577:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP576]] monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP577]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP578:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP579:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP578]] monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP579]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP580:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP581:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP580]] monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP581]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP582:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP583:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP582]] monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP583]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP584:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP585:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP584]], ptr [[SX_ATOMIC_EXPECTED_PTR]], align 2
+// CHECK-NEXT: store i16 [[TMP585]], ptr [[SX_ATOMIC_DESIRED_PTR]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED]], i16 [[SX_CMPXCHG_DESIRED]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV]], ptr [[SX_ATOMIC_EXPECTED_PTR1155]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1155]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP586:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP587:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP586]], ptr [[SX_ATOMIC_EXPECTED_PTR1156]], align 2
+// CHECK-NEXT: store i16 [[TMP587]], ptr [[SX_ATOMIC_DESIRED_PTR1157]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1159:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1156]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1160:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1157]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1161:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1159]], i16 [[SX_CMPXCHG_DESIRED1160]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1162:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1161]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1162]], ptr [[SX_ATOMIC_EXPECTED_PTR1158]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1163:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1161]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1164:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1158]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1164]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP588:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP589:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP588]] monotonic, align 2
+// CHECK-NEXT: [[TMP590:%.*]] = icmp sgt i16 [[TMP589]], [[TMP588]]
+// CHECK-NEXT: [[TMP591:%.*]] = select i1 [[TMP590]], i16 [[TMP588]], i16 [[TMP589]]
+// CHECK-NEXT: store i16 [[TMP591]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP592:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP593:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP592]] monotonic, align 2
+// CHECK-NEXT: [[TMP594:%.*]] = icmp slt i16 [[TMP593]], [[TMP592]]
+// CHECK-NEXT: [[TMP595:%.*]] = select i1 [[TMP594]], i16 [[TMP592]], i16 [[TMP593]]
+// CHECK-NEXT: store i16 [[TMP595]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP596:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP597:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP596]] monotonic, align 2
+// CHECK-NEXT: [[TMP598:%.*]] = icmp slt i16 [[TMP597]], [[TMP596]]
+// CHECK-NEXT: [[TMP599:%.*]] = select i1 [[TMP598]], i16 [[TMP596]], i16 [[TMP597]]
+// CHECK-NEXT: store i16 [[TMP599]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP600:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP601:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP600]] monotonic, align 2
+// CHECK-NEXT: [[TMP602:%.*]] = icmp sgt i16 [[TMP601]], [[TMP600]]
+// CHECK-NEXT: [[TMP603:%.*]] = select i1 [[TMP602]], i16 [[TMP600]], i16 [[TMP601]]
+// CHECK-NEXT: store i16 [[TMP603]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP604:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP605:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP604]], ptr [[SX_ATOMIC_EXPECTED_PTR1165]], align 2
+// CHECK-NEXT: store i16 [[TMP605]], ptr [[SX_ATOMIC_DESIRED_PTR1166]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1168:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1165]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1169:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1166]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1170:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1168]], i16 [[SX_CMPXCHG_DESIRED1169]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1171:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1170]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1171]], ptr [[SX_ATOMIC_EXPECTED_PTR1167]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1172:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1170]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1173:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1167]], align 2
+// CHECK-NEXT: [[SX_CAPTURE_CAPTURED:%.*]] = select i1 [[SX_CMPXCHG_SUCCESS1172]], i16 [[TMP604]], i16 [[SX_CAPTURE_ACTUAL1173]]
+// CHECK-NEXT: store i16 [[SX_CAPTURE_CAPTURED]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP606:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP607:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP606]], ptr [[SX_ATOMIC_EXPECTED_PTR1174]], align 2
+// CHECK-NEXT: store i16 [[TMP607]], ptr [[SX_ATOMIC_DESIRED_PTR1175]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1177:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1174]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1178:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1175]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1179:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1177]], i16 [[SX_CMPXCHG_DESIRED1178]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1180:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1179]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1180]], ptr [[SX_ATOMIC_EXPECTED_PTR1176]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1181:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1179]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1182:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1176]], align 2
+// CHECK-NEXT: [[SX_CAPTURE_CAPTURED1183:%.*]] = select i1 [[SX_CMPXCHG_SUCCESS1181]], i16 [[TMP606]], i16 [[SX_CAPTURE_ACTUAL1182]]
+// CHECK-NEXT: store i16 [[SX_CAPTURE_CAPTURED1183]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP608:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP609:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP608]], ptr [[SX_ATOMIC_EXPECTED_PTR1184]], align 2
+// CHECK-NEXT: store i16 [[TMP609]], ptr [[SX_ATOMIC_DESIRED_PTR1185]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1187:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1184]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1188:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1185]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1189:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1187]], i16 [[SX_CMPXCHG_DESIRED1188]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1190:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1189]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1190]], ptr [[SX_ATOMIC_EXPECTED_PTR1186]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1191:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1189]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1192:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1186]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1191]], label [[SX_ATOMIC_EXIT:%.*]], label [[SX_ATOMIC_CONT:%.*]]
// CHECK: sx.atomic.cont:
-// CHECK-NEXT: store i16 [[TMP983]], ptr [[SV]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1192]], ptr [[SV]], align 2
// CHECK-NEXT: br label [[SX_ATOMIC_EXIT]]
// CHECK: sx.atomic.exit:
-// CHECK-NEXT: [[TMP985:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP986:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP987:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP985]], i16 [[TMP986]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP988:%.*]] = extractvalue { i16, i1 } [[TMP987]], 0
-// CHECK-NEXT: [[TMP989:%.*]] = extractvalue { i16, i1 } [[TMP987]], 1
-// CHECK-NEXT: br i1 [[TMP989]], label [[SX_ATOMIC_EXIT93:%.*]], label [[SX_ATOMIC_CONT94:%.*]]
-// CHECK: sx.atomic.cont94:
-// CHECK-NEXT: store i16 [[TMP988]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT93]]
-// CHECK: sx.atomic.exit93:
-// CHECK-NEXT: [[TMP990:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP991:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP992:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP990]], i16 [[TMP991]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP993:%.*]] = extractvalue { i16, i1 } [[TMP992]], 1
-// CHECK-NEXT: [[TMP994:%.*]] = sext i1 [[TMP993]] to i16
-// CHECK-NEXT: store i16 [[TMP994]], ptr [[SR]], align 2
-// CHECK-NEXT: [[TMP995:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP996:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP997:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP995]], i16 [[TMP996]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP998:%.*]] = extractvalue { i16, i1 } [[TMP997]], 1
-// CHECK-NEXT: [[TMP999:%.*]] = sext i1 [[TMP998]] to i16
-// CHECK-NEXT: store i16 [[TMP999]], ptr [[SR]], align 2
-// CHECK-NEXT: [[TMP1000:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1001:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1002:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1000]], i16 [[TMP1001]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1003:%.*]] = extractvalue { i16, i1 } [[TMP1002]], 0
-// CHECK-NEXT: [[TMP1004:%.*]] = extractvalue { i16, i1 } [[TMP1002]], 1
-// CHECK-NEXT: br i1 [[TMP1004]], label [[SX_ATOMIC_EXIT95:%.*]], label [[SX_ATOMIC_CONT96:%.*]]
-// CHECK: sx.atomic.cont96:
-// CHECK-NEXT: store i16 [[TMP1003]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT95]]
-// CHECK: sx.atomic.exit95:
-// CHECK-NEXT: [[TMP1005:%.*]] = extractvalue { i16, i1 } [[TMP1002]], 1
-// CHECK-NEXT: [[TMP1006:%.*]] = sext i1 [[TMP1005]] to i16
-// CHECK-NEXT: store i16 [[TMP1006]], ptr [[SR]], align 2
-// CHECK-NEXT: [[TMP1007:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1008:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1009:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1007]], i16 [[TMP1008]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1010:%.*]] = extractvalue { i16, i1 } [[TMP1009]], 0
-// CHECK-NEXT: [[TMP1011:%.*]] = extractvalue { i16, i1 } [[TMP1009]], 1
-// CHECK-NEXT: br i1 [[TMP1011]], label [[SX_ATOMIC_EXIT97:%.*]], label [[SX_ATOMIC_CONT98:%.*]]
-// CHECK: sx.atomic.cont98:
-// CHECK-NEXT: store i16 [[TMP1010]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT97]]
-// CHECK: sx.atomic.exit97:
-// CHECK-NEXT: [[TMP1012:%.*]] = extractvalue { i16, i1 } [[TMP1009]], 1
-// CHECK-NEXT: [[TMP1013:%.*]] = sext i1 [[TMP1012]] to i16
-// CHECK-NEXT: store i16 [[TMP1013]], ptr [[SR]], align 2
-// CHECK-NEXT: [[TMP1014:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1015:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1014]] acq_rel, align 2
-// CHECK-NEXT: store i16 [[TMP1015]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1016:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1017:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1016]] acq_rel, align 2
-// CHECK-NEXT: store i16 [[TMP1017]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1018:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1019:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1018]] acq_rel, align 2
-// CHECK-NEXT: store i16 [[TMP1019]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1020:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1021:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1020]] acq_rel, align 2
-// CHECK-NEXT: store i16 [[TMP1021]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1022:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1023:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1024:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1022]], i16 [[TMP1023]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1025:%.*]] = extractvalue { i16, i1 } [[TMP1024]], 0
-// CHECK-NEXT: store i16 [[TMP1025]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1026:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1027:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1028:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1026]], i16 [[TMP1027]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1029:%.*]] = extractvalue { i16, i1 } [[TMP1028]], 0
-// CHECK-NEXT: store i16 [[TMP1029]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1030:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1031:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1030]] acq_rel, align 2
-// CHECK-NEXT: [[TMP1032:%.*]] = icmp sgt i16 [[TMP1031]], [[TMP1030]]
-// CHECK-NEXT: [[TMP1033:%.*]] = select i1 [[TMP1032]], i16 [[TMP1030]], i16 [[TMP1031]]
-// CHECK-NEXT: store i16 [[TMP1033]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1034:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1035:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1034]] acq_rel, align 2
-// CHECK-NEXT: [[TMP1036:%.*]] = icmp slt i16 [[TMP1035]], [[TMP1034]]
-// CHECK-NEXT: [[TMP1037:%.*]] = select i1 [[TMP1036]], i16 [[TMP1034]], i16 [[TMP1035]]
-// CHECK-NEXT: store i16 [[TMP1037]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1038:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1039:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1038]] acq_rel, align 2
-// CHECK-NEXT: [[TMP1040:%.*]] = icmp slt i16 [[TMP1039]], [[TMP1038]]
-// CHECK-NEXT: [[TMP1041:%.*]] = select i1 [[TMP1040]], i16 [[TMP1038]], i16 [[TMP1039]]
-// CHECK-NEXT: store i16 [[TMP1041]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1042:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1043:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1042]] acq_rel, align 2
-// CHECK-NEXT: [[TMP1044:%.*]] = icmp sgt i16 [[TMP1043]], [[TMP1042]]
-// CHECK-NEXT: [[TMP1045:%.*]] = select i1 [[TMP1044]], i16 [[TMP1042]], i16 [[TMP1043]]
-// CHECK-NEXT: store i16 [[TMP1045]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1046:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1047:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1048:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1046]], i16 [[TMP1047]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1049:%.*]] = extractvalue { i16, i1 } [[TMP1048]], 0
-// CHECK-NEXT: [[TMP1050:%.*]] = extractvalue { i16, i1 } [[TMP1048]], 1
-// CHECK-NEXT: [[TMP1051:%.*]] = select i1 [[TMP1050]], i16 [[TMP1046]], i16 [[TMP1049]]
-// CHECK-NEXT: store i16 [[TMP1051]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1052:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1053:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1054:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1052]], i16 [[TMP1053]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1055:%.*]] = extractvalue { i16, i1 } [[TMP1054]], 0
-// CHECK-NEXT: [[TMP1056:%.*]] = extractvalue { i16, i1 } [[TMP1054]], 1
-// CHECK-NEXT: [[TMP1057:%.*]] = select i1 [[TMP1056]], i16 [[TMP1052]], i16 [[TMP1055]]
-// CHECK-NEXT: store i16 [[TMP1057]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1058:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1059:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1060:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1058]], i16 [[TMP1059]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1061:%.*]] = extractvalue { i16, i1 } [[TMP1060]], 0
-// CHECK-NEXT: [[TMP1062:%.*]] = extractvalue { i16, i1 } [[TMP1060]], 1
-// CHECK-NEXT: br i1 [[TMP1062]], label [[SX_ATOMIC_EXIT99:%.*]], label [[SX_ATOMIC_CONT100:%.*]]
-// CHECK: sx.atomic.cont100:
-// CHECK-NEXT: store i16 [[TMP1061]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT99]]
-// CHECK: sx.atomic.exit99:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1063:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1064:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1065:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1063]], i16 [[TMP1064]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1066:%.*]] = extractvalue { i16, i1 } [[TMP1065]], 0
-// CHECK-NEXT: [[TMP1067:%.*]] = extractvalue { i16, i1 } [[TMP1065]], 1
-// CHECK-NEXT: br i1 [[TMP1067]], label [[SX_ATOMIC_EXIT101:%.*]], label [[SX_ATOMIC_CONT102:%.*]]
-// CHECK: sx.atomic.cont102:
-// CHECK-NEXT: store i16 [[TMP1066]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT101]]
-// CHECK: sx.atomic.exit101:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1068:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1069:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1070:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1068]], i16 [[TMP1069]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1071:%.*]] = extractvalue { i16, i1 } [[TMP1070]], 1
-// CHECK-NEXT: [[TMP1072:%.*]] = sext i1 [[TMP1071]] to i16
-// CHECK-NEXT: store i16 [[TMP1072]], ptr [[SR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1073:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1074:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1075:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1073]], i16 [[TMP1074]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1076:%.*]] = extractvalue { i16, i1 } [[TMP1075]], 1
-// CHECK-NEXT: [[TMP1077:%.*]] = sext i1 [[TMP1076]] to i16
-// CHECK-NEXT: store i16 [[TMP1077]], ptr [[SR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1078:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1079:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1080:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1078]], i16 [[TMP1079]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1081:%.*]] = extractvalue { i16, i1 } [[TMP1080]], 0
-// CHECK-NEXT: [[TMP1082:%.*]] = extractvalue { i16, i1 } [[TMP1080]], 1
-// CHECK-NEXT: br i1 [[TMP1082]], label [[SX_ATOMIC_EXIT103:%.*]], label [[SX_ATOMIC_CONT104:%.*]]
-// CHECK: sx.atomic.cont104:
-// CHECK-NEXT: store i16 [[TMP1081]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT103]]
-// CHECK: sx.atomic.exit103:
-// CHECK-NEXT: [[TMP1083:%.*]] = extractvalue { i16, i1 } [[TMP1080]], 1
-// CHECK-NEXT: [[TMP1084:%.*]] = sext i1 [[TMP1083]] to i16
-// CHECK-NEXT: store i16 [[TMP1084]], ptr [[SR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1085:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1086:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1087:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1085]], i16 [[TMP1086]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1088:%.*]] = extractvalue { i16, i1 } [[TMP1087]], 0
-// CHECK-NEXT: [[TMP1089:%.*]] = extractvalue { i16, i1 } [[TMP1087]], 1
-// CHECK-NEXT: br i1 [[TMP1089]], label [[SX_ATOMIC_EXIT105:%.*]], label [[SX_ATOMIC_CONT106:%.*]]
-// CHECK: sx.atomic.cont106:
-// CHECK-NEXT: store i16 [[TMP1088]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT105]]
-// CHECK: sx.atomic.exit105:
-// CHECK-NEXT: [[TMP1090:%.*]] = extractvalue { i16, i1 } [[TMP1087]], 1
-// CHECK-NEXT: [[TMP1091:%.*]] = sext i1 [[TMP1090]] to i16
-// CHECK-NEXT: store i16 [[TMP1091]], ptr [[SR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1092:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1093:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1092]] acquire, align 2
-// CHECK-NEXT: store i16 [[TMP1093]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1094:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1095:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1094]] acquire, align 2
-// CHECK-NEXT: store i16 [[TMP1095]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1096:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1097:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1096]] acquire, align 2
-// CHECK-NEXT: store i16 [[TMP1097]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1098:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1099:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1098]] acquire, align 2
-// CHECK-NEXT: store i16 [[TMP1099]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1100:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1101:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1102:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1100]], i16 [[TMP1101]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1103:%.*]] = extractvalue { i16, i1 } [[TMP1102]], 0
-// CHECK-NEXT: store i16 [[TMP1103]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1104:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1105:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1106:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1104]], i16 [[TMP1105]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1107:%.*]] = extractvalue { i16, i1 } [[TMP1106]], 0
-// CHECK-NEXT: store i16 [[TMP1107]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1108:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1109:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1108]] acquire, align 2
-// CHECK-NEXT: [[TMP1110:%.*]] = icmp sgt i16 [[TMP1109]], [[TMP1108]]
-// CHECK-NEXT: [[TMP1111:%.*]] = select i1 [[TMP1110]], i16 [[TMP1108]], i16 [[TMP1109]]
-// CHECK-NEXT: store i16 [[TMP1111]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1112:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1113:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1112]] acquire, align 2
-// CHECK-NEXT: [[TMP1114:%.*]] = icmp slt i16 [[TMP1113]], [[TMP1112]]
-// CHECK-NEXT: [[TMP1115:%.*]] = select i1 [[TMP1114]], i16 [[TMP1112]], i16 [[TMP1113]]
-// CHECK-NEXT: store i16 [[TMP1115]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1116:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1117:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1116]] acquire, align 2
-// CHECK-NEXT: [[TMP1118:%.*]] = icmp slt i16 [[TMP1117]], [[TMP1116]]
-// CHECK-NEXT: [[TMP1119:%.*]] = select i1 [[TMP1118]], i16 [[TMP1116]], i16 [[TMP1117]]
-// CHECK-NEXT: store i16 [[TMP1119]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1120:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1121:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1120]] acquire, align 2
-// CHECK-NEXT: [[TMP1122:%.*]] = icmp sgt i16 [[TMP1121]], [[TMP1120]]
-// CHECK-NEXT: [[TMP1123:%.*]] = select i1 [[TMP1122]], i16 [[TMP1120]], i16 [[TMP1121]]
-// CHECK-NEXT: store i16 [[TMP1123]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1124:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1125:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1126:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1124]], i16 [[TMP1125]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1127:%.*]] = extractvalue { i16, i1 } [[TMP1126]], 0
-// CHECK-NEXT: [[TMP1128:%.*]] = extractvalue { i16, i1 } [[TMP1126]], 1
-// CHECK-NEXT: [[TMP1129:%.*]] = select i1 [[TMP1128]], i16 [[TMP1124]], i16 [[TMP1127]]
-// CHECK-NEXT: store i16 [[TMP1129]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1130:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1131:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1132:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1130]], i16 [[TMP1131]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1133:%.*]] = extractvalue { i16, i1 } [[TMP1132]], 0
-// CHECK-NEXT: [[TMP1134:%.*]] = extractvalue { i16, i1 } [[TMP1132]], 1
-// CHECK-NEXT: [[TMP1135:%.*]] = select i1 [[TMP1134]], i16 [[TMP1130]], i16 [[TMP1133]]
-// CHECK-NEXT: store i16 [[TMP1135]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1136:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1137:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1138:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1136]], i16 [[TMP1137]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1139:%.*]] = extractvalue { i16, i1 } [[TMP1138]], 0
-// CHECK-NEXT: [[TMP1140:%.*]] = extractvalue { i16, i1 } [[TMP1138]], 1
-// CHECK-NEXT: br i1 [[TMP1140]], label [[SX_ATOMIC_EXIT107:%.*]], label [[SX_ATOMIC_CONT108:%.*]]
-// CHECK: sx.atomic.cont108:
-// CHECK-NEXT: store i16 [[TMP1139]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT107]]
-// CHECK: sx.atomic.exit107:
-// CHECK-NEXT: [[TMP1141:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1142:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1143:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1141]], i16 [[TMP1142]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1144:%.*]] = extractvalue { i16, i1 } [[TMP1143]], 0
-// CHECK-NEXT: [[TMP1145:%.*]] = extractvalue { i16, i1 } [[TMP1143]], 1
-// CHECK-NEXT: br i1 [[TMP1145]], label [[SX_ATOMIC_EXIT109:%.*]], label [[SX_ATOMIC_CONT110:%.*]]
-// CHECK: sx.atomic.cont110:
-// CHECK-NEXT: store i16 [[TMP1144]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT109]]
-// CHECK: sx.atomic.exit109:
-// CHECK-NEXT: [[TMP1146:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1147:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1148:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1146]], i16 [[TMP1147]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1149:%.*]] = extractvalue { i16, i1 } [[TMP1148]], 1
-// CHECK-NEXT: [[TMP1150:%.*]] = sext i1 [[TMP1149]] to i16
-// CHECK-NEXT: store i16 [[TMP1150]], ptr [[SR]], align 2
-// CHECK-NEXT: [[TMP1151:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1152:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1153:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1151]], i16 [[TMP1152]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1154:%.*]] = extractvalue { i16, i1 } [[TMP1153]], 1
-// CHECK-NEXT: [[TMP1155:%.*]] = sext i1 [[TMP1154]] to i16
-// CHECK-NEXT: store i16 [[TMP1155]], ptr [[SR]], align 2
-// CHECK-NEXT: [[TMP1156:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1157:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1158:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1156]], i16 [[TMP1157]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1159:%.*]] = extractvalue { i16, i1 } [[TMP1158]], 0
-// CHECK-NEXT: [[TMP1160:%.*]] = extractvalue { i16, i1 } [[TMP1158]], 1
-// CHECK-NEXT: br i1 [[TMP1160]], label [[SX_ATOMIC_EXIT111:%.*]], label [[SX_ATOMIC_CONT112:%.*]]
-// CHECK: sx.atomic.cont112:
-// CHECK-NEXT: store i16 [[TMP1159]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT111]]
-// CHECK: sx.atomic.exit111:
-// CHECK-NEXT: [[TMP1161:%.*]] = extractvalue { i16, i1 } [[TMP1158]], 1
-// CHECK-NEXT: [[TMP1162:%.*]] = sext i1 [[TMP1161]] to i16
-// CHECK-NEXT: store i16 [[TMP1162]], ptr [[SR]], align 2
-// CHECK-NEXT: [[TMP1163:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1164:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1165:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1163]], i16 [[TMP1164]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1166:%.*]] = extractvalue { i16, i1 } [[TMP1165]], 0
-// CHECK-NEXT: [[TMP1167:%.*]] = extractvalue { i16, i1 } [[TMP1165]], 1
-// CHECK-NEXT: br i1 [[TMP1167]], label [[SX_ATOMIC_EXIT113:%.*]], label [[SX_ATOMIC_CONT114:%.*]]
-// CHECK: sx.atomic.cont114:
-// CHECK-NEXT: store i16 [[TMP1166]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT113]]
-// CHECK: sx.atomic.exit113:
-// CHECK-NEXT: [[TMP1168:%.*]] = extractvalue { i16, i1 } [[TMP1165]], 1
-// CHECK-NEXT: [[TMP1169:%.*]] = sext i1 [[TMP1168]] to i16
-// CHECK-NEXT: store i16 [[TMP1169]], ptr [[SR]], align 2
-// CHECK-NEXT: [[TMP1170:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1171:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1170]] monotonic, align 2
-// CHECK-NEXT: store i16 [[TMP1171]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1172:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1173:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1172]] monotonic, align 2
-// CHECK-NEXT: store i16 [[TMP1173]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1174:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1175:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1174]] monotonic, align 2
-// CHECK-NEXT: store i16 [[TMP1175]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1176:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1177:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1176]] monotonic, align 2
-// CHECK-NEXT: store i16 [[TMP1177]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1178:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1179:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1180:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1178]], i16 [[TMP1179]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1181:%.*]] = extractvalue { i16, i1 } [[TMP1180]], 0
-// CHECK-NEXT: store i16 [[TMP1181]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1182:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1183:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1184:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1182]], i16 [[TMP1183]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1185:%.*]] = extractvalue { i16, i1 } [[TMP1184]], 0
-// CHECK-NEXT: store i16 [[TMP1185]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1186:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1187:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1186]] monotonic, align 2
-// CHECK-NEXT: [[TMP1188:%.*]] = icmp sgt i16 [[TMP1187]], [[TMP1186]]
-// CHECK-NEXT: [[TMP1189:%.*]] = select i1 [[TMP1188]], i16 [[TMP1186]], i16 [[TMP1187]]
-// CHECK-NEXT: store i16 [[TMP1189]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1190:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1191:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1190]] monotonic, align 2
-// CHECK-NEXT: [[TMP1192:%.*]] = icmp slt i16 [[TMP1191]], [[TMP1190]]
-// CHECK-NEXT: [[TMP1193:%.*]] = select i1 [[TMP1192]], i16 [[TMP1190]], i16 [[TMP1191]]
-// CHECK-NEXT: store i16 [[TMP1193]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1194:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1195:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1194]] monotonic, align 2
-// CHECK-NEXT: [[TMP1196:%.*]] = icmp slt i16 [[TMP1195]], [[TMP1194]]
-// CHECK-NEXT: [[TMP1197:%.*]] = select i1 [[TMP1196]], i16 [[TMP1194]], i16 [[TMP1195]]
-// CHECK-NEXT: store i16 [[TMP1197]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1198:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1199:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1198]] monotonic, align 2
-// CHECK-NEXT: [[TMP1200:%.*]] = icmp sgt i16 [[TMP1199]], [[TMP1198]]
-// CHECK-NEXT: [[TMP1201:%.*]] = select i1 [[TMP1200]], i16 [[TMP1198]], i16 [[TMP1199]]
-// CHECK-NEXT: store i16 [[TMP1201]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1202:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1203:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1204:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1202]], i16 [[TMP1203]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1205:%.*]] = extractvalue { i16, i1 } [[TMP1204]], 0
-// CHECK-NEXT: [[TMP1206:%.*]] = extractvalue { i16, i1 } [[TMP1204]], 1
-// CHECK-NEXT: [[TMP1207:%.*]] = select i1 [[TMP1206]], i16 [[TMP1202]], i16 [[TMP1205]]
-// CHECK-NEXT: store i16 [[TMP1207]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1208:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1209:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1210:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1208]], i16 [[TMP1209]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1211:%.*]] = extractvalue { i16, i1 } [[TMP1210]], 0
-// CHECK-NEXT: [[TMP1212:%.*]] = extractvalue { i16, i1 } [[TMP1210]], 1
-// CHECK-NEXT: [[TMP1213:%.*]] = select i1 [[TMP1212]], i16 [[TMP1208]], i16 [[TMP1211]]
-// CHECK-NEXT: store i16 [[TMP1213]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP1214:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1215:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1216:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1214]], i16 [[TMP1215]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1217:%.*]] = extractvalue { i16, i1 } [[TMP1216]], 0
-// CHECK-NEXT: [[TMP1218:%.*]] = extractvalue { i16, i1 } [[TMP1216]], 1
-// CHECK-NEXT: br i1 [[TMP1218]], label [[SX_ATOMIC_EXIT115:%.*]], label [[SX_ATOMIC_CONT116:%.*]]
-// CHECK: sx.atomic.cont116:
-// CHECK-NEXT: store i16 [[TMP1217]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT115]]
-// CHECK: sx.atomic.exit115:
-// CHECK-NEXT: [[TMP1219:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1220:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1221:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1219]], i16 [[TMP1220]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1222:%.*]] = extractvalue { i16, i1 } [[TMP1221]], 0
-// CHECK-NEXT: [[TMP1223:%.*]] = extractvalue { i16, i1 } [[TMP1221]], 1
-// CHECK-NEXT: br i1 [[TMP1223]], label [[SX_ATOMIC_EXIT117:%.*]], label [[SX_ATOMIC_CONT118:%.*]]
-// CHECK: sx.atomic.cont118:
-// CHECK-NEXT: store i16 [[TMP1222]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT117]]
-// CHECK: sx.atomic.exit117:
-// CHECK-NEXT: [[TMP1224:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1225:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1226:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1224]], i16 [[TMP1225]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1227:%.*]] = extractvalue { i16, i1 } [[TMP1226]], 1
-// CHECK-NEXT: [[TMP1228:%.*]] = sext i1 [[TMP1227]] to i16
-// CHECK-NEXT: store i16 [[TMP1228]], ptr [[SR]], align 2
-// CHECK-NEXT: [[TMP1229:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1230:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1231:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1229]], i16 [[TMP1230]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1232:%.*]] = extractvalue { i16, i1 } [[TMP1231]], 1
-// CHECK-NEXT: [[TMP1233:%.*]] = sext i1 [[TMP1232]] to i16
-// CHECK-NEXT: store i16 [[TMP1233]], ptr [[SR]], align 2
-// CHECK-NEXT: [[TMP1234:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1235:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1236:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1234]], i16 [[TMP1235]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1237:%.*]] = extractvalue { i16, i1 } [[TMP1236]], 0
-// CHECK-NEXT: [[TMP1238:%.*]] = extractvalue { i16, i1 } [[TMP1236]], 1
-// CHECK-NEXT: br i1 [[TMP1238]], label [[SX_ATOMIC_EXIT119:%.*]], label [[SX_ATOMIC_CONT120:%.*]]
-// CHECK: sx.atomic.cont120:
-// CHECK-NEXT: store i16 [[TMP1237]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT119]]
-// CHECK: sx.atomic.exit119:
-// CHECK-NEXT: [[TMP1239:%.*]] = extractvalue { i16, i1 } [[TMP1236]], 1
-// CHECK-NEXT: [[TMP1240:%.*]] = sext i1 [[TMP1239]] to i16
-// CHECK-NEXT: store i16 [[TMP1240]], ptr [[SR]], align 2
-// CHECK-NEXT: [[TMP1241:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1242:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1243:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1241]], i16 [[TMP1242]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1244:%.*]] = extractvalue { i16, i1 } [[TMP1243]], 0
-// CHECK-NEXT: [[TMP1245:%.*]] = extractvalue { i16, i1 } [[TMP1243]], 1
-// CHECK-NEXT: br i1 [[TMP1245]], label [[SX_ATOMIC_EXIT121:%.*]], label [[SX_ATOMIC_CONT122:%.*]]
-// CHECK: sx.atomic.cont122:
-// CHECK-NEXT: store i16 [[TMP1244]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT121]]
-// CHECK: sx.atomic.exit121:
-// CHECK-NEXT: [[TMP1246:%.*]] = extractvalue { i16, i1 } [[TMP1243]], 1
-// CHECK-NEXT: [[TMP1247:%.*]] = sext i1 [[TMP1246]] to i16
-// CHECK-NEXT: store i16 [[TMP1247]], ptr [[SR]], align 2
-// CHECK-NEXT: [[TMP1248:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1249:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1248]] release, align 2
-// CHECK-NEXT: store i16 [[TMP1249]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1250:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1251:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1250]] release, align 2
-// CHECK-NEXT: store i16 [[TMP1251]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1252:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1253:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1252]] release, align 2
-// CHECK-NEXT: store i16 [[TMP1253]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1254:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1255:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1254]] release, align 2
-// CHECK-NEXT: store i16 [[TMP1255]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1256:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1257:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1258:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1256]], i16 [[TMP1257]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1259:%.*]] = extractvalue { i16, i1 } [[TMP1258]], 0
-// CHECK-NEXT: store i16 [[TMP1259]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1260:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1261:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1262:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1260]], i16 [[TMP1261]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1263:%.*]] = extractvalue { i16, i1 } [[TMP1262]], 0
-// CHECK-NEXT: store i16 [[TMP1263]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1264:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1265:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1264]] release, align 2
-// CHECK-NEXT: [[TMP1266:%.*]] = icmp sgt i16 [[TMP1265]], [[TMP1264]]
-// CHECK-NEXT: [[TMP1267:%.*]] = select i1 [[TMP1266]], i16 [[TMP1264]], i16 [[TMP1265]]
-// CHECK-NEXT: store i16 [[TMP1267]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1268:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1269:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1268]] release, align 2
-// CHECK-NEXT: [[TMP1270:%.*]] = icmp slt i16 [[TMP1269]], [[TMP1268]]
-// CHECK-NEXT: [[TMP1271:%.*]] = select i1 [[TMP1270]], i16 [[TMP1268]], i16 [[TMP1269]]
-// CHECK-NEXT: store i16 [[TMP1271]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1272:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1273:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1272]] release, align 2
-// CHECK-NEXT: [[TMP1274:%.*]] = icmp slt i16 [[TMP1273]], [[TMP1272]]
-// CHECK-NEXT: [[TMP1275:%.*]] = select i1 [[TMP1274]], i16 [[TMP1272]], i16 [[TMP1273]]
-// CHECK-NEXT: store i16 [[TMP1275]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1276:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1277:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1276]] release, align 2
-// CHECK-NEXT: [[TMP1278:%.*]] = icmp sgt i16 [[TMP1277]], [[TMP1276]]
-// CHECK-NEXT: [[TMP1279:%.*]] = select i1 [[TMP1278]], i16 [[TMP1276]], i16 [[TMP1277]]
-// CHECK-NEXT: store i16 [[TMP1279]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1280:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1281:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1282:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1280]], i16 [[TMP1281]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1283:%.*]] = extractvalue { i16, i1 } [[TMP1282]], 0
-// CHECK-NEXT: [[TMP1284:%.*]] = extractvalue { i16, i1 } [[TMP1282]], 1
-// CHECK-NEXT: [[TMP1285:%.*]] = select i1 [[TMP1284]], i16 [[TMP1280]], i16 [[TMP1283]]
-// CHECK-NEXT: store i16 [[TMP1285]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1286:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1287:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1288:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1286]], i16 [[TMP1287]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1289:%.*]] = extractvalue { i16, i1 } [[TMP1288]], 0
-// CHECK-NEXT: [[TMP1290:%.*]] = extractvalue { i16, i1 } [[TMP1288]], 1
-// CHECK-NEXT: [[TMP1291:%.*]] = select i1 [[TMP1290]], i16 [[TMP1286]], i16 [[TMP1289]]
-// CHECK-NEXT: store i16 [[TMP1291]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1292:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1293:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1294:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1292]], i16 [[TMP1293]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1295:%.*]] = extractvalue { i16, i1 } [[TMP1294]], 0
-// CHECK-NEXT: [[TMP1296:%.*]] = extractvalue { i16, i1 } [[TMP1294]], 1
-// CHECK-NEXT: br i1 [[TMP1296]], label [[SX_ATOMIC_EXIT123:%.*]], label [[SX_ATOMIC_CONT124:%.*]]
-// CHECK: sx.atomic.cont124:
-// CHECK-NEXT: store i16 [[TMP1295]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT123]]
-// CHECK: sx.atomic.exit123:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1297:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1298:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1299:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1297]], i16 [[TMP1298]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1300:%.*]] = extractvalue { i16, i1 } [[TMP1299]], 0
-// CHECK-NEXT: [[TMP1301:%.*]] = extractvalue { i16, i1 } [[TMP1299]], 1
-// CHECK-NEXT: br i1 [[TMP1301]], label [[SX_ATOMIC_EXIT125:%.*]], label [[SX_ATOMIC_CONT126:%.*]]
-// CHECK: sx.atomic.cont126:
-// CHECK-NEXT: store i16 [[TMP1300]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT125]]
-// CHECK: sx.atomic.exit125:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1302:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1303:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1304:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1302]], i16 [[TMP1303]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1305:%.*]] = extractvalue { i16, i1 } [[TMP1304]], 1
-// CHECK-NEXT: [[TMP1306:%.*]] = sext i1 [[TMP1305]] to i16
-// CHECK-NEXT: store i16 [[TMP1306]], ptr [[SR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1307:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1308:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1309:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1307]], i16 [[TMP1308]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1310:%.*]] = extractvalue { i16, i1 } [[TMP1309]], 1
-// CHECK-NEXT: [[TMP1311:%.*]] = sext i1 [[TMP1310]] to i16
-// CHECK-NEXT: store i16 [[TMP1311]], ptr [[SR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1312:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1313:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1314:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1312]], i16 [[TMP1313]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1315:%.*]] = extractvalue { i16, i1 } [[TMP1314]], 0
-// CHECK-NEXT: [[TMP1316:%.*]] = extractvalue { i16, i1 } [[TMP1314]], 1
-// CHECK-NEXT: br i1 [[TMP1316]], label [[SX_ATOMIC_EXIT127:%.*]], label [[SX_ATOMIC_CONT128:%.*]]
-// CHECK: sx.atomic.cont128:
-// CHECK-NEXT: store i16 [[TMP1315]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT127]]
-// CHECK: sx.atomic.exit127:
-// CHECK-NEXT: [[TMP1317:%.*]] = extractvalue { i16, i1 } [[TMP1314]], 1
-// CHECK-NEXT: [[TMP1318:%.*]] = sext i1 [[TMP1317]] to i16
-// CHECK-NEXT: store i16 [[TMP1318]], ptr [[SR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1319:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1320:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1321:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1319]], i16 [[TMP1320]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1322:%.*]] = extractvalue { i16, i1 } [[TMP1321]], 0
-// CHECK-NEXT: [[TMP1323:%.*]] = extractvalue { i16, i1 } [[TMP1321]], 1
-// CHECK-NEXT: br i1 [[TMP1323]], label [[SX_ATOMIC_EXIT129:%.*]], label [[SX_ATOMIC_CONT130:%.*]]
-// CHECK: sx.atomic.cont130:
-// CHECK-NEXT: store i16 [[TMP1322]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT129]]
-// CHECK: sx.atomic.exit129:
-// CHECK-NEXT: [[TMP1324:%.*]] = extractvalue { i16, i1 } [[TMP1321]], 1
-// CHECK-NEXT: [[TMP1325:%.*]] = sext i1 [[TMP1324]] to i16
-// CHECK-NEXT: store i16 [[TMP1325]], ptr [[SR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1326:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1327:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1326]] seq_cst, align 2
-// CHECK-NEXT: store i16 [[TMP1327]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1328:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1329:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1328]] seq_cst, align 2
-// CHECK-NEXT: store i16 [[TMP1329]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1330:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1331:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1330]] seq_cst, align 2
-// CHECK-NEXT: store i16 [[TMP1331]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1332:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1333:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1332]] seq_cst, align 2
-// CHECK-NEXT: store i16 [[TMP1333]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1334:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1335:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1336:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1334]], i16 [[TMP1335]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1337:%.*]] = extractvalue { i16, i1 } [[TMP1336]], 0
-// CHECK-NEXT: store i16 [[TMP1337]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1338:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1339:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1340:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1338]], i16 [[TMP1339]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1341:%.*]] = extractvalue { i16, i1 } [[TMP1340]], 0
-// CHECK-NEXT: store i16 [[TMP1341]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1342:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1343:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1342]] seq_cst, align 2
-// CHECK-NEXT: [[TMP1344:%.*]] = icmp sgt i16 [[TMP1343]], [[TMP1342]]
-// CHECK-NEXT: [[TMP1345:%.*]] = select i1 [[TMP1344]], i16 [[TMP1342]], i16 [[TMP1343]]
-// CHECK-NEXT: store i16 [[TMP1345]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1346:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1347:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1346]] seq_cst, align 2
-// CHECK-NEXT: [[TMP1348:%.*]] = icmp slt i16 [[TMP1347]], [[TMP1346]]
-// CHECK-NEXT: [[TMP1349:%.*]] = select i1 [[TMP1348]], i16 [[TMP1346]], i16 [[TMP1347]]
-// CHECK-NEXT: store i16 [[TMP1349]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1350:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1351:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP1350]] seq_cst, align 2
-// CHECK-NEXT: [[TMP1352:%.*]] = icmp slt i16 [[TMP1351]], [[TMP1350]]
-// CHECK-NEXT: [[TMP1353:%.*]] = select i1 [[TMP1352]], i16 [[TMP1350]], i16 [[TMP1351]]
-// CHECK-NEXT: store i16 [[TMP1353]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1354:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1355:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP1354]] seq_cst, align 2
-// CHECK-NEXT: [[TMP1356:%.*]] = icmp sgt i16 [[TMP1355]], [[TMP1354]]
-// CHECK-NEXT: [[TMP1357:%.*]] = select i1 [[TMP1356]], i16 [[TMP1354]], i16 [[TMP1355]]
-// CHECK-NEXT: store i16 [[TMP1357]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1358:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1359:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1360:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1358]], i16 [[TMP1359]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1361:%.*]] = extractvalue { i16, i1 } [[TMP1360]], 0
-// CHECK-NEXT: [[TMP1362:%.*]] = extractvalue { i16, i1 } [[TMP1360]], 1
-// CHECK-NEXT: [[TMP1363:%.*]] = select i1 [[TMP1362]], i16 [[TMP1358]], i16 [[TMP1361]]
-// CHECK-NEXT: store i16 [[TMP1363]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1364:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1365:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1366:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1364]], i16 [[TMP1365]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1367:%.*]] = extractvalue { i16, i1 } [[TMP1366]], 0
-// CHECK-NEXT: [[TMP1368:%.*]] = extractvalue { i16, i1 } [[TMP1366]], 1
-// CHECK-NEXT: [[TMP1369:%.*]] = select i1 [[TMP1368]], i16 [[TMP1364]], i16 [[TMP1367]]
-// CHECK-NEXT: store i16 [[TMP1369]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1370:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1371:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1372:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1370]], i16 [[TMP1371]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1373:%.*]] = extractvalue { i16, i1 } [[TMP1372]], 0
-// CHECK-NEXT: [[TMP1374:%.*]] = extractvalue { i16, i1 } [[TMP1372]], 1
-// CHECK-NEXT: br i1 [[TMP1374]], label [[SX_ATOMIC_EXIT131:%.*]], label [[SX_ATOMIC_CONT132:%.*]]
-// CHECK: sx.atomic.cont132:
-// CHECK-NEXT: store i16 [[TMP1373]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT131]]
-// CHECK: sx.atomic.exit131:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1375:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1376:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1377:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1375]], i16 [[TMP1376]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1378:%.*]] = extractvalue { i16, i1 } [[TMP1377]], 0
-// CHECK-NEXT: [[TMP1379:%.*]] = extractvalue { i16, i1 } [[TMP1377]], 1
-// CHECK-NEXT: br i1 [[TMP1379]], label [[SX_ATOMIC_EXIT133:%.*]], label [[SX_ATOMIC_CONT134:%.*]]
-// CHECK: sx.atomic.cont134:
-// CHECK-NEXT: store i16 [[TMP1378]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT133]]
-// CHECK: sx.atomic.exit133:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1380:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1381:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1382:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1380]], i16 [[TMP1381]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1383:%.*]] = extractvalue { i16, i1 } [[TMP1382]], 1
-// CHECK-NEXT: [[TMP1384:%.*]] = sext i1 [[TMP1383]] to i16
-// CHECK-NEXT: store i16 [[TMP1384]], ptr [[SR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1385:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1386:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1387:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1385]], i16 [[TMP1386]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1388:%.*]] = extractvalue { i16, i1 } [[TMP1387]], 1
-// CHECK-NEXT: [[TMP1389:%.*]] = sext i1 [[TMP1388]] to i16
-// CHECK-NEXT: store i16 [[TMP1389]], ptr [[SR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1390:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1391:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1392:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1390]], i16 [[TMP1391]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1393:%.*]] = extractvalue { i16, i1 } [[TMP1392]], 0
-// CHECK-NEXT: [[TMP1394:%.*]] = extractvalue { i16, i1 } [[TMP1392]], 1
-// CHECK-NEXT: br i1 [[TMP1394]], label [[SX_ATOMIC_EXIT135:%.*]], label [[SX_ATOMIC_CONT136:%.*]]
-// CHECK: sx.atomic.cont136:
-// CHECK-NEXT: store i16 [[TMP1393]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT135]]
-// CHECK: sx.atomic.exit135:
-// CHECK-NEXT: [[TMP1395:%.*]] = extractvalue { i16, i1 } [[TMP1392]], 1
-// CHECK-NEXT: [[TMP1396:%.*]] = sext i1 [[TMP1395]] to i16
-// CHECK-NEXT: store i16 [[TMP1396]], ptr [[SR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1397:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP1398:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP1399:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP1397]], i16 [[TMP1398]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1400:%.*]] = extractvalue { i16, i1 } [[TMP1399]], 0
-// CHECK-NEXT: [[TMP1401:%.*]] = extractvalue { i16, i1 } [[TMP1399]], 1
-// CHECK-NEXT: br i1 [[TMP1401]], label [[SX_ATOMIC_EXIT137:%.*]], label [[SX_ATOMIC_CONT138:%.*]]
-// CHECK: sx.atomic.cont138:
-// CHECK-NEXT: store i16 [[TMP1400]], ptr [[SV]], align 2
-// CHECK-NEXT: br label [[SX_ATOMIC_EXIT137]]
-// CHECK: sx.atomic.exit137:
-// CHECK-NEXT: [[TMP1402:%.*]] = extractvalue { i16, i1 } [[TMP1399]], 1
-// CHECK-NEXT: [[TMP1403:%.*]] = sext i1 [[TMP1402]] to i16
-// CHECK-NEXT: store i16 [[TMP1403]], ptr [[SR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1404:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1405:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1404]] monotonic, align 2
-// CHECK-NEXT: store i16 [[TMP1405]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1406:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1407:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1406]] monotonic, align 2
-// CHECK-NEXT: store i16 [[TMP1407]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1408:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1409:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1408]] monotonic, align 2
-// CHECK-NEXT: store i16 [[TMP1409]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1410:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1411:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1410]] monotonic, align 2
-// CHECK-NEXT: store i16 [[TMP1411]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1412:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1413:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1414:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1412]], i16 [[TMP1413]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1415:%.*]] = extractvalue { i16, i1 } [[TMP1414]], 0
-// CHECK-NEXT: store i16 [[TMP1415]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1416:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1417:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1418:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1416]], i16 [[TMP1417]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1419:%.*]] = extractvalue { i16, i1 } [[TMP1418]], 0
-// CHECK-NEXT: store i16 [[TMP1419]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1420:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1421:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1420]] monotonic, align 2
-// CHECK-NEXT: [[TMP1422:%.*]] = icmp ugt i16 [[TMP1421]], [[TMP1420]]
-// CHECK-NEXT: [[TMP1423:%.*]] = select i1 [[TMP1422]], i16 [[TMP1420]], i16 [[TMP1421]]
-// CHECK-NEXT: store i16 [[TMP1423]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1424:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1425:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1424]] monotonic, align 2
-// CHECK-NEXT: [[TMP1426:%.*]] = icmp ult i16 [[TMP1425]], [[TMP1424]]
-// CHECK-NEXT: [[TMP1427:%.*]] = select i1 [[TMP1426]], i16 [[TMP1424]], i16 [[TMP1425]]
-// CHECK-NEXT: store i16 [[TMP1427]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1428:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1429:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1428]] monotonic, align 2
-// CHECK-NEXT: [[TMP1430:%.*]] = icmp ult i16 [[TMP1429]], [[TMP1428]]
-// CHECK-NEXT: [[TMP1431:%.*]] = select i1 [[TMP1430]], i16 [[TMP1428]], i16 [[TMP1429]]
-// CHECK-NEXT: store i16 [[TMP1431]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1432:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1433:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1432]] monotonic, align 2
-// CHECK-NEXT: [[TMP1434:%.*]] = icmp ugt i16 [[TMP1433]], [[TMP1432]]
-// CHECK-NEXT: [[TMP1435:%.*]] = select i1 [[TMP1434]], i16 [[TMP1432]], i16 [[TMP1433]]
-// CHECK-NEXT: store i16 [[TMP1435]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1436:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1437:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1438:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1436]], i16 [[TMP1437]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1439:%.*]] = extractvalue { i16, i1 } [[TMP1438]], 0
-// CHECK-NEXT: [[TMP1440:%.*]] = extractvalue { i16, i1 } [[TMP1438]], 1
-// CHECK-NEXT: [[TMP1441:%.*]] = select i1 [[TMP1440]], i16 [[TMP1436]], i16 [[TMP1439]]
-// CHECK-NEXT: store i16 [[TMP1441]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1442:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1443:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1444:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1442]], i16 [[TMP1443]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1445:%.*]] = extractvalue { i16, i1 } [[TMP1444]], 0
-// CHECK-NEXT: [[TMP1446:%.*]] = extractvalue { i16, i1 } [[TMP1444]], 1
-// CHECK-NEXT: [[TMP1447:%.*]] = select i1 [[TMP1446]], i16 [[TMP1442]], i16 [[TMP1445]]
-// CHECK-NEXT: store i16 [[TMP1447]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1448:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1449:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1450:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1448]], i16 [[TMP1449]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1451:%.*]] = extractvalue { i16, i1 } [[TMP1450]], 0
-// CHECK-NEXT: [[TMP1452:%.*]] = extractvalue { i16, i1 } [[TMP1450]], 1
-// CHECK-NEXT: br i1 [[TMP1452]], label [[USX_ATOMIC_EXIT:%.*]], label [[USX_ATOMIC_CONT:%.*]]
+// CHECK-NEXT: [[TMP610:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP611:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP610]], ptr [[SX_ATOMIC_EXPECTED_PTR1193]], align 2
+// CHECK-NEXT: store i16 [[TMP611]], ptr [[SX_ATOMIC_DESIRED_PTR1194]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1196:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1193]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1197:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1194]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1198:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1196]], i16 [[SX_CMPXCHG_DESIRED1197]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1199:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1198]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1199]], ptr [[SX_ATOMIC_EXPECTED_PTR1195]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1200:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1198]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1201:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1195]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1200]], label [[SX_ATOMIC_EXIT1202:%.*]], label [[SX_ATOMIC_CONT1203:%.*]]
+// CHECK: sx.atomic.cont1203:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1201]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1202]]
+// CHECK: sx.atomic.exit1202:
+// CHECK-NEXT: [[TMP612:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP613:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP612]], ptr [[SX_ATOMIC_EXPECTED_PTR1204]], align 2
+// CHECK-NEXT: store i16 [[TMP613]], ptr [[SX_ATOMIC_DESIRED_PTR1205]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1207:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1204]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1208:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1205]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1209:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1207]], i16 [[SX_CMPXCHG_DESIRED1208]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1210:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1209]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1210]], ptr [[SX_ATOMIC_EXPECTED_PTR1206]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1211:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1209]], 1
+// CHECK-NEXT: [[TMP614:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1211]] to i16
+// CHECK-NEXT: store i16 [[TMP614]], ptr [[SR]], align 2
+// CHECK-NEXT: [[TMP615:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP616:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP615]], ptr [[SX_ATOMIC_EXPECTED_PTR1212]], align 2
+// CHECK-NEXT: store i16 [[TMP616]], ptr [[SX_ATOMIC_DESIRED_PTR1213]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1215:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1212]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1216:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1213]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1217:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1215]], i16 [[SX_CMPXCHG_DESIRED1216]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1218:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1217]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1218]], ptr [[SX_ATOMIC_EXPECTED_PTR1214]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1219:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1217]], 1
+// CHECK-NEXT: [[TMP617:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1219]] to i16
+// CHECK-NEXT: store i16 [[TMP617]], ptr [[SR]], align 2
+// CHECK-NEXT: [[TMP618:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP619:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP618]], ptr [[SX_ATOMIC_EXPECTED_PTR1220]], align 2
+// CHECK-NEXT: store i16 [[TMP619]], ptr [[SX_ATOMIC_DESIRED_PTR1221]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1223:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1220]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1224:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1221]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1225:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1223]], i16 [[SX_CMPXCHG_DESIRED1224]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1226:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1225]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1226]], ptr [[SX_ATOMIC_EXPECTED_PTR1222]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1227:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1225]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1228:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1222]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1227]], label [[SX_ATOMIC_EXIT1229:%.*]], label [[SX_ATOMIC_CONT1230:%.*]]
+// CHECK: sx.atomic.cont1230:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1228]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1229]]
+// CHECK: sx.atomic.exit1229:
+// CHECK-NEXT: [[TMP620:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1227]] to i16
+// CHECK-NEXT: store i16 [[TMP620]], ptr [[SR]], align 2
+// CHECK-NEXT: [[TMP621:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP622:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP621]], ptr [[SX_ATOMIC_EXPECTED_PTR1231]], align 2
+// CHECK-NEXT: store i16 [[TMP622]], ptr [[SX_ATOMIC_DESIRED_PTR1232]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1234:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1231]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1235:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1232]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1236:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1234]], i16 [[SX_CMPXCHG_DESIRED1235]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1237:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1236]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1237]], ptr [[SX_ATOMIC_EXPECTED_PTR1233]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1238:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1236]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1239:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1233]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1238]], label [[SX_ATOMIC_EXIT1240:%.*]], label [[SX_ATOMIC_CONT1241:%.*]]
+// CHECK: sx.atomic.cont1241:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1239]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1240]]
+// CHECK: sx.atomic.exit1240:
+// CHECK-NEXT: [[TMP623:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1238]] to i16
+// CHECK-NEXT: store i16 [[TMP623]], ptr [[SR]], align 2
+// CHECK-NEXT: [[TMP624:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP625:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP624]] acq_rel, align 2
+// CHECK-NEXT: store i16 [[TMP625]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP626:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP627:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP626]] acq_rel, align 2
+// CHECK-NEXT: store i16 [[TMP627]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP628:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP629:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP628]] acq_rel, align 2
+// CHECK-NEXT: store i16 [[TMP629]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP630:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP631:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP630]] acq_rel, align 2
+// CHECK-NEXT: store i16 [[TMP631]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP632:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP633:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP632]], ptr [[SX_ATOMIC_EXPECTED_PTR1242]], align 2
+// CHECK-NEXT: store i16 [[TMP633]], ptr [[SX_ATOMIC_DESIRED_PTR1243]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1245:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1242]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1246:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1243]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1247:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1245]], i16 [[SX_CMPXCHG_DESIRED1246]] acq_rel acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1248:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1247]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1248]], ptr [[SX_ATOMIC_EXPECTED_PTR1244]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1249:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1247]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1250:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1244]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1250]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP634:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP635:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP634]], ptr [[SX_ATOMIC_EXPECTED_PTR1251]], align 2
+// CHECK-NEXT: store i16 [[TMP635]], ptr [[SX_ATOMIC_DESIRED_PTR1252]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1254:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1251]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1255:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1252]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1256:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1254]], i16 [[SX_CMPXCHG_DESIRED1255]] acq_rel acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1257:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1256]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1257]], ptr [[SX_ATOMIC_EXPECTED_PTR1253]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1258:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1256]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1259:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1253]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1259]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP636:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP637:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP636]] acq_rel, align 2
+// CHECK-NEXT: [[TMP638:%.*]] = icmp sgt i16 [[TMP637]], [[TMP636]]
+// CHECK-NEXT: [[TMP639:%.*]] = select i1 [[TMP638]], i16 [[TMP636]], i16 [[TMP637]]
+// CHECK-NEXT: store i16 [[TMP639]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP640:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP641:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP640]] acq_rel, align 2
+// CHECK-NEXT: [[TMP642:%.*]] = icmp slt i16 [[TMP641]], [[TMP640]]
+// CHECK-NEXT: [[TMP643:%.*]] = select i1 [[TMP642]], i16 [[TMP640]], i16 [[TMP641]]
+// CHECK-NEXT: store i16 [[TMP643]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP644:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP645:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP644]] acq_rel, align 2
+// CHECK-NEXT: [[TMP646:%.*]] = icmp slt i16 [[TMP645]], [[TMP644]]
+// CHECK-NEXT: [[TMP647:%.*]] = select i1 [[TMP646]], i16 [[TMP644]], i16 [[TMP645]]
+// CHECK-NEXT: store i16 [[TMP647]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP648:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP649:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP648]] acq_rel, align 2
+// CHECK-NEXT: [[TMP650:%.*]] = icmp sgt i16 [[TMP649]], [[TMP648]]
+// CHECK-NEXT: [[TMP651:%.*]] = select i1 [[TMP650]], i16 [[TMP648]], i16 [[TMP649]]
+// CHECK-NEXT: store i16 [[TMP651]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP652:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP653:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP652]], ptr [[SX_ATOMIC_EXPECTED_PTR1260]], align 2
+// CHECK-NEXT: store i16 [[TMP653]], ptr [[SX_ATOMIC_DESIRED_PTR1261]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1263:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1260]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1264:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1261]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1265:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1263]], i16 [[SX_CMPXCHG_DESIRED1264]] acq_rel acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1266:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1265]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1266]], ptr [[SX_ATOMIC_EXPECTED_PTR1262]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1267:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1265]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1268:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1262]], align 2
+// CHECK-NEXT: [[SX_CAPTURE_CAPTURED1269:%.*]] = select i1 [[SX_CMPXCHG_SUCCESS1267]], i16 [[TMP652]], i16 [[SX_CAPTURE_ACTUAL1268]]
+// CHECK-NEXT: store i16 [[SX_CAPTURE_CAPTURED1269]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP654:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP655:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP654]], ptr [[SX_ATOMIC_EXPECTED_PTR1270]], align 2
+// CHECK-NEXT: store i16 [[TMP655]], ptr [[SX_ATOMIC_DESIRED_PTR1271]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1273:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1270]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1274:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1271]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1275:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1273]], i16 [[SX_CMPXCHG_DESIRED1274]] acq_rel acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1276:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1275]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1276]], ptr [[SX_ATOMIC_EXPECTED_PTR1272]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1277:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1275]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1278:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1272]], align 2
+// CHECK-NEXT: [[SX_CAPTURE_CAPTURED1279:%.*]] = select i1 [[SX_CMPXCHG_SUCCESS1277]], i16 [[TMP654]], i16 [[SX_CAPTURE_ACTUAL1278]]
+// CHECK-NEXT: store i16 [[SX_CAPTURE_CAPTURED1279]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP656:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP657:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP656]], ptr [[SX_ATOMIC_EXPECTED_PTR1280]], align 2
+// CHECK-NEXT: store i16 [[TMP657]], ptr [[SX_ATOMIC_DESIRED_PTR1281]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1283:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1280]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1284:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1281]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1285:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1283]], i16 [[SX_CMPXCHG_DESIRED1284]] acq_rel acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1286:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1285]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1286]], ptr [[SX_ATOMIC_EXPECTED_PTR1282]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1287:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1285]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1288:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1282]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1287]], label [[SX_ATOMIC_EXIT1289:%.*]], label [[SX_ATOMIC_CONT1290:%.*]]
+// CHECK: sx.atomic.cont1290:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1288]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1289]]
+// CHECK: sx.atomic.exit1289:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP658:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP659:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP658]], ptr [[SX_ATOMIC_EXPECTED_PTR1291]], align 2
+// CHECK-NEXT: store i16 [[TMP659]], ptr [[SX_ATOMIC_DESIRED_PTR1292]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1294:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1291]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1295:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1292]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1296:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1294]], i16 [[SX_CMPXCHG_DESIRED1295]] acq_rel acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1297:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1296]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1297]], ptr [[SX_ATOMIC_EXPECTED_PTR1293]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1298:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1296]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1299:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1293]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1298]], label [[SX_ATOMIC_EXIT1300:%.*]], label [[SX_ATOMIC_CONT1301:%.*]]
+// CHECK: sx.atomic.cont1301:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1299]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1300]]
+// CHECK: sx.atomic.exit1300:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP660:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP661:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP660]], ptr [[SX_ATOMIC_EXPECTED_PTR1302]], align 2
+// CHECK-NEXT: store i16 [[TMP661]], ptr [[SX_ATOMIC_DESIRED_PTR1303]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1305:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1302]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1306:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1303]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1307:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1305]], i16 [[SX_CMPXCHG_DESIRED1306]] acq_rel acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1308:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1307]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1308]], ptr [[SX_ATOMIC_EXPECTED_PTR1304]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1309:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1307]], 1
+// CHECK-NEXT: [[TMP662:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1309]] to i16
+// CHECK-NEXT: store i16 [[TMP662]], ptr [[SR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP663:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP664:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP663]], ptr [[SX_ATOMIC_EXPECTED_PTR1310]], align 2
+// CHECK-NEXT: store i16 [[TMP664]], ptr [[SX_ATOMIC_DESIRED_PTR1311]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1313:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1310]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1314:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1311]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1315:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1313]], i16 [[SX_CMPXCHG_DESIRED1314]] acq_rel acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1316:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1315]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1316]], ptr [[SX_ATOMIC_EXPECTED_PTR1312]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1317:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1315]], 1
+// CHECK-NEXT: [[TMP665:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1317]] to i16
+// CHECK-NEXT: store i16 [[TMP665]], ptr [[SR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP666:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP667:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP666]], ptr [[SX_ATOMIC_EXPECTED_PTR1318]], align 2
+// CHECK-NEXT: store i16 [[TMP667]], ptr [[SX_ATOMIC_DESIRED_PTR1319]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1321:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1318]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1322:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1319]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1323:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1321]], i16 [[SX_CMPXCHG_DESIRED1322]] acq_rel acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1324:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1323]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1324]], ptr [[SX_ATOMIC_EXPECTED_PTR1320]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1325:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1323]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1326:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1320]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1325]], label [[SX_ATOMIC_EXIT1327:%.*]], label [[SX_ATOMIC_CONT1328:%.*]]
+// CHECK: sx.atomic.cont1328:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1326]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1327]]
+// CHECK: sx.atomic.exit1327:
+// CHECK-NEXT: [[TMP668:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1325]] to i16
+// CHECK-NEXT: store i16 [[TMP668]], ptr [[SR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP669:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP670:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP669]], ptr [[SX_ATOMIC_EXPECTED_PTR1329]], align 2
+// CHECK-NEXT: store i16 [[TMP670]], ptr [[SX_ATOMIC_DESIRED_PTR1330]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1332:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1329]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1333:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1330]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1334:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1332]], i16 [[SX_CMPXCHG_DESIRED1333]] acq_rel acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1335:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1334]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1335]], ptr [[SX_ATOMIC_EXPECTED_PTR1331]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1336:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1334]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1337:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1331]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1336]], label [[SX_ATOMIC_EXIT1338:%.*]], label [[SX_ATOMIC_CONT1339:%.*]]
+// CHECK: sx.atomic.cont1339:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1337]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1338]]
+// CHECK: sx.atomic.exit1338:
+// CHECK-NEXT: [[TMP671:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1336]] to i16
+// CHECK-NEXT: store i16 [[TMP671]], ptr [[SR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP672:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP673:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP672]] acquire, align 2
+// CHECK-NEXT: store i16 [[TMP673]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP674:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP675:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP674]] acquire, align 2
+// CHECK-NEXT: store i16 [[TMP675]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP676:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP677:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP676]] acquire, align 2
+// CHECK-NEXT: store i16 [[TMP677]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP678:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP679:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP678]] acquire, align 2
+// CHECK-NEXT: store i16 [[TMP679]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP680:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP681:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP680]], ptr [[SX_ATOMIC_EXPECTED_PTR1340]], align 2
+// CHECK-NEXT: store i16 [[TMP681]], ptr [[SX_ATOMIC_DESIRED_PTR1341]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1343:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1340]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1344:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1341]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1345:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1343]], i16 [[SX_CMPXCHG_DESIRED1344]] acquire acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1346:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1345]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1346]], ptr [[SX_ATOMIC_EXPECTED_PTR1342]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1347:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1345]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1348:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1342]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1348]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP682:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP683:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP682]], ptr [[SX_ATOMIC_EXPECTED_PTR1349]], align 2
+// CHECK-NEXT: store i16 [[TMP683]], ptr [[SX_ATOMIC_DESIRED_PTR1350]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1352:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1349]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1353:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1350]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1354:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1352]], i16 [[SX_CMPXCHG_DESIRED1353]] acquire acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1355:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1354]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1355]], ptr [[SX_ATOMIC_EXPECTED_PTR1351]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1356:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1354]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1357:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1351]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1357]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP684:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP685:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP684]] acquire, align 2
+// CHECK-NEXT: [[TMP686:%.*]] = icmp sgt i16 [[TMP685]], [[TMP684]]
+// CHECK-NEXT: [[TMP687:%.*]] = select i1 [[TMP686]], i16 [[TMP684]], i16 [[TMP685]]
+// CHECK-NEXT: store i16 [[TMP687]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP688:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP689:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP688]] acquire, align 2
+// CHECK-NEXT: [[TMP690:%.*]] = icmp slt i16 [[TMP689]], [[TMP688]]
+// CHECK-NEXT: [[TMP691:%.*]] = select i1 [[TMP690]], i16 [[TMP688]], i16 [[TMP689]]
+// CHECK-NEXT: store i16 [[TMP691]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP692:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP693:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP692]] acquire, align 2
+// CHECK-NEXT: [[TMP694:%.*]] = icmp slt i16 [[TMP693]], [[TMP692]]
+// CHECK-NEXT: [[TMP695:%.*]] = select i1 [[TMP694]], i16 [[TMP692]], i16 [[TMP693]]
+// CHECK-NEXT: store i16 [[TMP695]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP696:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP697:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP696]] acquire, align 2
+// CHECK-NEXT: [[TMP698:%.*]] = icmp sgt i16 [[TMP697]], [[TMP696]]
+// CHECK-NEXT: [[TMP699:%.*]] = select i1 [[TMP698]], i16 [[TMP696]], i16 [[TMP697]]
+// CHECK-NEXT: store i16 [[TMP699]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP700:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP701:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP700]], ptr [[SX_ATOMIC_EXPECTED_PTR1358]], align 2
+// CHECK-NEXT: store i16 [[TMP701]], ptr [[SX_ATOMIC_DESIRED_PTR1359]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1361:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1358]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1362:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1359]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1363:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1361]], i16 [[SX_CMPXCHG_DESIRED1362]] acquire acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1364:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1363]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1364]], ptr [[SX_ATOMIC_EXPECTED_PTR1360]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1365:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1363]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1366:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1360]], align 2
+// CHECK-NEXT: [[SX_CAPTURE_CAPTURED1367:%.*]] = select i1 [[SX_CMPXCHG_SUCCESS1365]], i16 [[TMP700]], i16 [[SX_CAPTURE_ACTUAL1366]]
+// CHECK-NEXT: store i16 [[SX_CAPTURE_CAPTURED1367]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP702:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP703:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP702]], ptr [[SX_ATOMIC_EXPECTED_PTR1368]], align 2
+// CHECK-NEXT: store i16 [[TMP703]], ptr [[SX_ATOMIC_DESIRED_PTR1369]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1371:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1368]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1372:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1369]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1373:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1371]], i16 [[SX_CMPXCHG_DESIRED1372]] acquire acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1374:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1373]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1374]], ptr [[SX_ATOMIC_EXPECTED_PTR1370]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1375:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1373]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1376:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1370]], align 2
+// CHECK-NEXT: [[SX_CAPTURE_CAPTURED1377:%.*]] = select i1 [[SX_CMPXCHG_SUCCESS1375]], i16 [[TMP702]], i16 [[SX_CAPTURE_ACTUAL1376]]
+// CHECK-NEXT: store i16 [[SX_CAPTURE_CAPTURED1377]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP704:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP705:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP704]], ptr [[SX_ATOMIC_EXPECTED_PTR1378]], align 2
+// CHECK-NEXT: store i16 [[TMP705]], ptr [[SX_ATOMIC_DESIRED_PTR1379]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1381:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1378]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1382:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1379]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1383:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1381]], i16 [[SX_CMPXCHG_DESIRED1382]] acquire acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1384:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1383]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1384]], ptr [[SX_ATOMIC_EXPECTED_PTR1380]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1385:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1383]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1386:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1380]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1385]], label [[SX_ATOMIC_EXIT1387:%.*]], label [[SX_ATOMIC_CONT1388:%.*]]
+// CHECK: sx.atomic.cont1388:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1386]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1387]]
+// CHECK: sx.atomic.exit1387:
+// CHECK-NEXT: [[TMP706:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP707:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP706]], ptr [[SX_ATOMIC_EXPECTED_PTR1389]], align 2
+// CHECK-NEXT: store i16 [[TMP707]], ptr [[SX_ATOMIC_DESIRED_PTR1390]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1392:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1389]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1393:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1390]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1394:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1392]], i16 [[SX_CMPXCHG_DESIRED1393]] acquire acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1395:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1394]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1395]], ptr [[SX_ATOMIC_EXPECTED_PTR1391]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1396:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1394]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1397:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1391]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1396]], label [[SX_ATOMIC_EXIT1398:%.*]], label [[SX_ATOMIC_CONT1399:%.*]]
+// CHECK: sx.atomic.cont1399:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1397]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1398]]
+// CHECK: sx.atomic.exit1398:
+// CHECK-NEXT: [[TMP708:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP709:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP708]], ptr [[SX_ATOMIC_EXPECTED_PTR1400]], align 2
+// CHECK-NEXT: store i16 [[TMP709]], ptr [[SX_ATOMIC_DESIRED_PTR1401]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1403:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1400]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1404:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1401]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1405:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1403]], i16 [[SX_CMPXCHG_DESIRED1404]] acquire acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1406:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1405]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1406]], ptr [[SX_ATOMIC_EXPECTED_PTR1402]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1407:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1405]], 1
+// CHECK-NEXT: [[TMP710:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1407]] to i16
+// CHECK-NEXT: store i16 [[TMP710]], ptr [[SR]], align 2
+// CHECK-NEXT: [[TMP711:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP712:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP711]], ptr [[SX_ATOMIC_EXPECTED_PTR1408]], align 2
+// CHECK-NEXT: store i16 [[TMP712]], ptr [[SX_ATOMIC_DESIRED_PTR1409]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1411:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1408]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1412:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1409]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1413:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1411]], i16 [[SX_CMPXCHG_DESIRED1412]] acquire acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1414:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1413]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1414]], ptr [[SX_ATOMIC_EXPECTED_PTR1410]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1415:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1413]], 1
+// CHECK-NEXT: [[TMP713:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1415]] to i16
+// CHECK-NEXT: store i16 [[TMP713]], ptr [[SR]], align 2
+// CHECK-NEXT: [[TMP714:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP715:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP714]], ptr [[SX_ATOMIC_EXPECTED_PTR1416]], align 2
+// CHECK-NEXT: store i16 [[TMP715]], ptr [[SX_ATOMIC_DESIRED_PTR1417]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1419:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1416]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1420:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1417]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1421:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1419]], i16 [[SX_CMPXCHG_DESIRED1420]] acquire acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1422:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1421]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1422]], ptr [[SX_ATOMIC_EXPECTED_PTR1418]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1423:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1421]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1424:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1418]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1423]], label [[SX_ATOMIC_EXIT1425:%.*]], label [[SX_ATOMIC_CONT1426:%.*]]
+// CHECK: sx.atomic.cont1426:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1424]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1425]]
+// CHECK: sx.atomic.exit1425:
+// CHECK-NEXT: [[TMP716:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1423]] to i16
+// CHECK-NEXT: store i16 [[TMP716]], ptr [[SR]], align 2
+// CHECK-NEXT: [[TMP717:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP718:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP717]], ptr [[SX_ATOMIC_EXPECTED_PTR1427]], align 2
+// CHECK-NEXT: store i16 [[TMP718]], ptr [[SX_ATOMIC_DESIRED_PTR1428]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1430:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1427]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1431:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1428]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1432:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1430]], i16 [[SX_CMPXCHG_DESIRED1431]] acquire acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1433:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1432]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1433]], ptr [[SX_ATOMIC_EXPECTED_PTR1429]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1434:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1432]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1435:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1429]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1434]], label [[SX_ATOMIC_EXIT1436:%.*]], label [[SX_ATOMIC_CONT1437:%.*]]
+// CHECK: sx.atomic.cont1437:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1435]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1436]]
+// CHECK: sx.atomic.exit1436:
+// CHECK-NEXT: [[TMP719:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1434]] to i16
+// CHECK-NEXT: store i16 [[TMP719]], ptr [[SR]], align 2
+// CHECK-NEXT: [[TMP720:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP721:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP720]] monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP721]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP722:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP723:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP722]] monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP723]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP724:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP725:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP724]] monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP725]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP726:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP727:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP726]] monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP727]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP728:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP729:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP728]], ptr [[SX_ATOMIC_EXPECTED_PTR1438]], align 2
+// CHECK-NEXT: store i16 [[TMP729]], ptr [[SX_ATOMIC_DESIRED_PTR1439]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1441:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1438]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1442:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1439]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1443:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1441]], i16 [[SX_CMPXCHG_DESIRED1442]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1444:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1443]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1444]], ptr [[SX_ATOMIC_EXPECTED_PTR1440]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1445:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1443]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1446:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1440]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1446]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP730:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP731:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP730]], ptr [[SX_ATOMIC_EXPECTED_PTR1447]], align 2
+// CHECK-NEXT: store i16 [[TMP731]], ptr [[SX_ATOMIC_DESIRED_PTR1448]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1450:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1447]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1451:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1448]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1452:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1450]], i16 [[SX_CMPXCHG_DESIRED1451]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1453:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1452]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1453]], ptr [[SX_ATOMIC_EXPECTED_PTR1449]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1454:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1452]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1455:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1449]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1455]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP732:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP733:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP732]] monotonic, align 2
+// CHECK-NEXT: [[TMP734:%.*]] = icmp sgt i16 [[TMP733]], [[TMP732]]
+// CHECK-NEXT: [[TMP735:%.*]] = select i1 [[TMP734]], i16 [[TMP732]], i16 [[TMP733]]
+// CHECK-NEXT: store i16 [[TMP735]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP736:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP737:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP736]] monotonic, align 2
+// CHECK-NEXT: [[TMP738:%.*]] = icmp slt i16 [[TMP737]], [[TMP736]]
+// CHECK-NEXT: [[TMP739:%.*]] = select i1 [[TMP738]], i16 [[TMP736]], i16 [[TMP737]]
+// CHECK-NEXT: store i16 [[TMP739]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP740:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP741:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP740]] monotonic, align 2
+// CHECK-NEXT: [[TMP742:%.*]] = icmp slt i16 [[TMP741]], [[TMP740]]
+// CHECK-NEXT: [[TMP743:%.*]] = select i1 [[TMP742]], i16 [[TMP740]], i16 [[TMP741]]
+// CHECK-NEXT: store i16 [[TMP743]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP744:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP745:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP744]] monotonic, align 2
+// CHECK-NEXT: [[TMP746:%.*]] = icmp sgt i16 [[TMP745]], [[TMP744]]
+// CHECK-NEXT: [[TMP747:%.*]] = select i1 [[TMP746]], i16 [[TMP744]], i16 [[TMP745]]
+// CHECK-NEXT: store i16 [[TMP747]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP748:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP749:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP748]], ptr [[SX_ATOMIC_EXPECTED_PTR1456]], align 2
+// CHECK-NEXT: store i16 [[TMP749]], ptr [[SX_ATOMIC_DESIRED_PTR1457]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1459:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1456]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1460:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1457]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1461:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1459]], i16 [[SX_CMPXCHG_DESIRED1460]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1462:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1461]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1462]], ptr [[SX_ATOMIC_EXPECTED_PTR1458]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1463:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1461]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1464:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1458]], align 2
+// CHECK-NEXT: [[SX_CAPTURE_CAPTURED1465:%.*]] = select i1 [[SX_CMPXCHG_SUCCESS1463]], i16 [[TMP748]], i16 [[SX_CAPTURE_ACTUAL1464]]
+// CHECK-NEXT: store i16 [[SX_CAPTURE_CAPTURED1465]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP750:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP751:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP750]], ptr [[SX_ATOMIC_EXPECTED_PTR1466]], align 2
+// CHECK-NEXT: store i16 [[TMP751]], ptr [[SX_ATOMIC_DESIRED_PTR1467]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1469:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1466]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1470:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1467]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1471:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1469]], i16 [[SX_CMPXCHG_DESIRED1470]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1472:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1471]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1472]], ptr [[SX_ATOMIC_EXPECTED_PTR1468]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1473:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1471]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1474:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1468]], align 2
+// CHECK-NEXT: [[SX_CAPTURE_CAPTURED1475:%.*]] = select i1 [[SX_CMPXCHG_SUCCESS1473]], i16 [[TMP750]], i16 [[SX_CAPTURE_ACTUAL1474]]
+// CHECK-NEXT: store i16 [[SX_CAPTURE_CAPTURED1475]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP752:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP753:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP752]], ptr [[SX_ATOMIC_EXPECTED_PTR1476]], align 2
+// CHECK-NEXT: store i16 [[TMP753]], ptr [[SX_ATOMIC_DESIRED_PTR1477]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1479:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1476]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1480:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1477]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1481:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1479]], i16 [[SX_CMPXCHG_DESIRED1480]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1482:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1481]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1482]], ptr [[SX_ATOMIC_EXPECTED_PTR1478]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1483:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1481]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1484:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1478]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1483]], label [[SX_ATOMIC_EXIT1485:%.*]], label [[SX_ATOMIC_CONT1486:%.*]]
+// CHECK: sx.atomic.cont1486:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1484]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1485]]
+// CHECK: sx.atomic.exit1485:
+// CHECK-NEXT: [[TMP754:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP755:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP754]], ptr [[SX_ATOMIC_EXPECTED_PTR1487]], align 2
+// CHECK-NEXT: store i16 [[TMP755]], ptr [[SX_ATOMIC_DESIRED_PTR1488]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1490:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1487]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1491:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1488]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1492:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1490]], i16 [[SX_CMPXCHG_DESIRED1491]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1493:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1492]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1493]], ptr [[SX_ATOMIC_EXPECTED_PTR1489]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1494:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1492]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1495:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1489]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1494]], label [[SX_ATOMIC_EXIT1496:%.*]], label [[SX_ATOMIC_CONT1497:%.*]]
+// CHECK: sx.atomic.cont1497:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1495]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1496]]
+// CHECK: sx.atomic.exit1496:
+// CHECK-NEXT: [[TMP756:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP757:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP756]], ptr [[SX_ATOMIC_EXPECTED_PTR1498]], align 2
+// CHECK-NEXT: store i16 [[TMP757]], ptr [[SX_ATOMIC_DESIRED_PTR1499]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1501:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1498]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1502:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1499]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1503:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1501]], i16 [[SX_CMPXCHG_DESIRED1502]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1504:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1503]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1504]], ptr [[SX_ATOMIC_EXPECTED_PTR1500]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1505:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1503]], 1
+// CHECK-NEXT: [[TMP758:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1505]] to i16
+// CHECK-NEXT: store i16 [[TMP758]], ptr [[SR]], align 2
+// CHECK-NEXT: [[TMP759:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP760:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP759]], ptr [[SX_ATOMIC_EXPECTED_PTR1506]], align 2
+// CHECK-NEXT: store i16 [[TMP760]], ptr [[SX_ATOMIC_DESIRED_PTR1507]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1509:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1506]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1510:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1507]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1511:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1509]], i16 [[SX_CMPXCHG_DESIRED1510]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1512:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1511]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1512]], ptr [[SX_ATOMIC_EXPECTED_PTR1508]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1513:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1511]], 1
+// CHECK-NEXT: [[TMP761:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1513]] to i16
+// CHECK-NEXT: store i16 [[TMP761]], ptr [[SR]], align 2
+// CHECK-NEXT: [[TMP762:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP763:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP762]], ptr [[SX_ATOMIC_EXPECTED_PTR1514]], align 2
+// CHECK-NEXT: store i16 [[TMP763]], ptr [[SX_ATOMIC_DESIRED_PTR1515]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1517:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1514]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1518:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1515]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1519:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1517]], i16 [[SX_CMPXCHG_DESIRED1518]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1520:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1519]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1520]], ptr [[SX_ATOMIC_EXPECTED_PTR1516]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1521:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1519]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1522:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1516]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1521]], label [[SX_ATOMIC_EXIT1523:%.*]], label [[SX_ATOMIC_CONT1524:%.*]]
+// CHECK: sx.atomic.cont1524:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1522]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1523]]
+// CHECK: sx.atomic.exit1523:
+// CHECK-NEXT: [[TMP764:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1521]] to i16
+// CHECK-NEXT: store i16 [[TMP764]], ptr [[SR]], align 2
+// CHECK-NEXT: [[TMP765:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP766:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP765]], ptr [[SX_ATOMIC_EXPECTED_PTR1525]], align 2
+// CHECK-NEXT: store i16 [[TMP766]], ptr [[SX_ATOMIC_DESIRED_PTR1526]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1528:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1525]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1529:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1526]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1530:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1528]], i16 [[SX_CMPXCHG_DESIRED1529]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1531:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1530]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1531]], ptr [[SX_ATOMIC_EXPECTED_PTR1527]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1532:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1530]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1533:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1527]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1532]], label [[SX_ATOMIC_EXIT1534:%.*]], label [[SX_ATOMIC_CONT1535:%.*]]
+// CHECK: sx.atomic.cont1535:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1533]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1534]]
+// CHECK: sx.atomic.exit1534:
+// CHECK-NEXT: [[TMP767:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1532]] to i16
+// CHECK-NEXT: store i16 [[TMP767]], ptr [[SR]], align 2
+// CHECK-NEXT: [[TMP768:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP769:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP768]] release, align 2
+// CHECK-NEXT: store i16 [[TMP769]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP770:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP771:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP770]] release, align 2
+// CHECK-NEXT: store i16 [[TMP771]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP772:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP773:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP772]] release, align 2
+// CHECK-NEXT: store i16 [[TMP773]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP774:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP775:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP774]] release, align 2
+// CHECK-NEXT: store i16 [[TMP775]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP776:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP777:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP776]], ptr [[SX_ATOMIC_EXPECTED_PTR1536]], align 2
+// CHECK-NEXT: store i16 [[TMP777]], ptr [[SX_ATOMIC_DESIRED_PTR1537]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1539:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1536]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1540:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1537]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1541:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1539]], i16 [[SX_CMPXCHG_DESIRED1540]] release monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1542:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1541]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1542]], ptr [[SX_ATOMIC_EXPECTED_PTR1538]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1543:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1541]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1544:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1538]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1544]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP778:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP779:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP778]], ptr [[SX_ATOMIC_EXPECTED_PTR1545]], align 2
+// CHECK-NEXT: store i16 [[TMP779]], ptr [[SX_ATOMIC_DESIRED_PTR1546]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1548:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1545]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1549:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1546]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1550:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1548]], i16 [[SX_CMPXCHG_DESIRED1549]] release monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1551:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1550]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1551]], ptr [[SX_ATOMIC_EXPECTED_PTR1547]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1552:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1550]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1553:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1547]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1553]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP780:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP781:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP780]] release, align 2
+// CHECK-NEXT: [[TMP782:%.*]] = icmp sgt i16 [[TMP781]], [[TMP780]]
+// CHECK-NEXT: [[TMP783:%.*]] = select i1 [[TMP782]], i16 [[TMP780]], i16 [[TMP781]]
+// CHECK-NEXT: store i16 [[TMP783]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP784:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP785:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP784]] release, align 2
+// CHECK-NEXT: [[TMP786:%.*]] = icmp slt i16 [[TMP785]], [[TMP784]]
+// CHECK-NEXT: [[TMP787:%.*]] = select i1 [[TMP786]], i16 [[TMP784]], i16 [[TMP785]]
+// CHECK-NEXT: store i16 [[TMP787]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP788:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP789:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP788]] release, align 2
+// CHECK-NEXT: [[TMP790:%.*]] = icmp slt i16 [[TMP789]], [[TMP788]]
+// CHECK-NEXT: [[TMP791:%.*]] = select i1 [[TMP790]], i16 [[TMP788]], i16 [[TMP789]]
+// CHECK-NEXT: store i16 [[TMP791]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP792:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP793:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP792]] release, align 2
+// CHECK-NEXT: [[TMP794:%.*]] = icmp sgt i16 [[TMP793]], [[TMP792]]
+// CHECK-NEXT: [[TMP795:%.*]] = select i1 [[TMP794]], i16 [[TMP792]], i16 [[TMP793]]
+// CHECK-NEXT: store i16 [[TMP795]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP796:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP797:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP796]], ptr [[SX_ATOMIC_EXPECTED_PTR1554]], align 2
+// CHECK-NEXT: store i16 [[TMP797]], ptr [[SX_ATOMIC_DESIRED_PTR1555]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1557:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1554]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1558:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1555]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1559:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1557]], i16 [[SX_CMPXCHG_DESIRED1558]] release monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1560:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1559]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1560]], ptr [[SX_ATOMIC_EXPECTED_PTR1556]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1561:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1559]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1562:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1556]], align 2
+// CHECK-NEXT: [[SX_CAPTURE_CAPTURED1563:%.*]] = select i1 [[SX_CMPXCHG_SUCCESS1561]], i16 [[TMP796]], i16 [[SX_CAPTURE_ACTUAL1562]]
+// CHECK-NEXT: store i16 [[SX_CAPTURE_CAPTURED1563]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP798:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP799:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP798]], ptr [[SX_ATOMIC_EXPECTED_PTR1564]], align 2
+// CHECK-NEXT: store i16 [[TMP799]], ptr [[SX_ATOMIC_DESIRED_PTR1565]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1567:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1564]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1568:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1565]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1569:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1567]], i16 [[SX_CMPXCHG_DESIRED1568]] release monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1570:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1569]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1570]], ptr [[SX_ATOMIC_EXPECTED_PTR1566]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1571:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1569]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1572:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1566]], align 2
+// CHECK-NEXT: [[SX_CAPTURE_CAPTURED1573:%.*]] = select i1 [[SX_CMPXCHG_SUCCESS1571]], i16 [[TMP798]], i16 [[SX_CAPTURE_ACTUAL1572]]
+// CHECK-NEXT: store i16 [[SX_CAPTURE_CAPTURED1573]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP800:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP801:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP800]], ptr [[SX_ATOMIC_EXPECTED_PTR1574]], align 2
+// CHECK-NEXT: store i16 [[TMP801]], ptr [[SX_ATOMIC_DESIRED_PTR1575]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1577:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1574]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1578:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1575]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1579:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1577]], i16 [[SX_CMPXCHG_DESIRED1578]] release monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1580:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1579]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1580]], ptr [[SX_ATOMIC_EXPECTED_PTR1576]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1581:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1579]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1582:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1576]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1581]], label [[SX_ATOMIC_EXIT1583:%.*]], label [[SX_ATOMIC_CONT1584:%.*]]
+// CHECK: sx.atomic.cont1584:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1582]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1583]]
+// CHECK: sx.atomic.exit1583:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP802:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP803:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP802]], ptr [[SX_ATOMIC_EXPECTED_PTR1585]], align 2
+// CHECK-NEXT: store i16 [[TMP803]], ptr [[SX_ATOMIC_DESIRED_PTR1586]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1588:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1585]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1589:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1586]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1590:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1588]], i16 [[SX_CMPXCHG_DESIRED1589]] release monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1591:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1590]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1591]], ptr [[SX_ATOMIC_EXPECTED_PTR1587]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1592:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1590]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1593:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1587]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1592]], label [[SX_ATOMIC_EXIT1594:%.*]], label [[SX_ATOMIC_CONT1595:%.*]]
+// CHECK: sx.atomic.cont1595:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1593]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1594]]
+// CHECK: sx.atomic.exit1594:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP804:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP805:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP804]], ptr [[SX_ATOMIC_EXPECTED_PTR1596]], align 2
+// CHECK-NEXT: store i16 [[TMP805]], ptr [[SX_ATOMIC_DESIRED_PTR1597]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1599:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1596]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1600:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1597]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1601:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1599]], i16 [[SX_CMPXCHG_DESIRED1600]] release monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1602:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1601]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1602]], ptr [[SX_ATOMIC_EXPECTED_PTR1598]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1603:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1601]], 1
+// CHECK-NEXT: [[TMP806:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1603]] to i16
+// CHECK-NEXT: store i16 [[TMP806]], ptr [[SR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP807:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP808:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP807]], ptr [[SX_ATOMIC_EXPECTED_PTR1604]], align 2
+// CHECK-NEXT: store i16 [[TMP808]], ptr [[SX_ATOMIC_DESIRED_PTR1605]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1607:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1604]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1608:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1605]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1609:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1607]], i16 [[SX_CMPXCHG_DESIRED1608]] release monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1610:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1609]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1610]], ptr [[SX_ATOMIC_EXPECTED_PTR1606]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1611:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1609]], 1
+// CHECK-NEXT: [[TMP809:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1611]] to i16
+// CHECK-NEXT: store i16 [[TMP809]], ptr [[SR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP810:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP811:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP810]], ptr [[SX_ATOMIC_EXPECTED_PTR1612]], align 2
+// CHECK-NEXT: store i16 [[TMP811]], ptr [[SX_ATOMIC_DESIRED_PTR1613]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1615:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1612]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1616:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1613]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1617:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1615]], i16 [[SX_CMPXCHG_DESIRED1616]] release monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1618:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1617]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1618]], ptr [[SX_ATOMIC_EXPECTED_PTR1614]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1619:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1617]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1620:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1614]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1619]], label [[SX_ATOMIC_EXIT1621:%.*]], label [[SX_ATOMIC_CONT1622:%.*]]
+// CHECK: sx.atomic.cont1622:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1620]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1621]]
+// CHECK: sx.atomic.exit1621:
+// CHECK-NEXT: [[TMP812:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1619]] to i16
+// CHECK-NEXT: store i16 [[TMP812]], ptr [[SR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP813:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP814:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP813]], ptr [[SX_ATOMIC_EXPECTED_PTR1623]], align 2
+// CHECK-NEXT: store i16 [[TMP814]], ptr [[SX_ATOMIC_DESIRED_PTR1624]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1626:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1623]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1627:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1624]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1628:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1626]], i16 [[SX_CMPXCHG_DESIRED1627]] release monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1629:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1628]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1629]], ptr [[SX_ATOMIC_EXPECTED_PTR1625]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1630:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1628]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1631:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1625]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1630]], label [[SX_ATOMIC_EXIT1632:%.*]], label [[SX_ATOMIC_CONT1633:%.*]]
+// CHECK: sx.atomic.cont1633:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1631]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1632]]
+// CHECK: sx.atomic.exit1632:
+// CHECK-NEXT: [[TMP815:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1630]] to i16
+// CHECK-NEXT: store i16 [[TMP815]], ptr [[SR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP816:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP817:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP816]] seq_cst, align 2
+// CHECK-NEXT: store i16 [[TMP817]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP818:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP819:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP818]] seq_cst, align 2
+// CHECK-NEXT: store i16 [[TMP819]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP820:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP821:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP820]] seq_cst, align 2
+// CHECK-NEXT: store i16 [[TMP821]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP822:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP823:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP822]] seq_cst, align 2
+// CHECK-NEXT: store i16 [[TMP823]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP824:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP825:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP824]], ptr [[SX_ATOMIC_EXPECTED_PTR1634]], align 2
+// CHECK-NEXT: store i16 [[TMP825]], ptr [[SX_ATOMIC_DESIRED_PTR1635]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1637:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1634]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1638:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1635]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1639:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1637]], i16 [[SX_CMPXCHG_DESIRED1638]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1640:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1639]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1640]], ptr [[SX_ATOMIC_EXPECTED_PTR1636]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1641:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1639]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1642:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1636]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1642]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP826:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP827:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP826]], ptr [[SX_ATOMIC_EXPECTED_PTR1643]], align 2
+// CHECK-NEXT: store i16 [[TMP827]], ptr [[SX_ATOMIC_DESIRED_PTR1644]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1646:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1643]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1647:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1644]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1648:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1646]], i16 [[SX_CMPXCHG_DESIRED1647]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1649:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1648]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1649]], ptr [[SX_ATOMIC_EXPECTED_PTR1645]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1650:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1648]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1651:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1645]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1651]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP828:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP829:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP828]] seq_cst, align 2
+// CHECK-NEXT: [[TMP830:%.*]] = icmp sgt i16 [[TMP829]], [[TMP828]]
+// CHECK-NEXT: [[TMP831:%.*]] = select i1 [[TMP830]], i16 [[TMP828]], i16 [[TMP829]]
+// CHECK-NEXT: store i16 [[TMP831]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP832:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP833:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP832]] seq_cst, align 2
+// CHECK-NEXT: [[TMP834:%.*]] = icmp slt i16 [[TMP833]], [[TMP832]]
+// CHECK-NEXT: [[TMP835:%.*]] = select i1 [[TMP834]], i16 [[TMP832]], i16 [[TMP833]]
+// CHECK-NEXT: store i16 [[TMP835]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP836:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP837:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP836]] seq_cst, align 2
+// CHECK-NEXT: [[TMP838:%.*]] = icmp slt i16 [[TMP837]], [[TMP836]]
+// CHECK-NEXT: [[TMP839:%.*]] = select i1 [[TMP838]], i16 [[TMP836]], i16 [[TMP837]]
+// CHECK-NEXT: store i16 [[TMP839]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP840:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP841:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP840]] seq_cst, align 2
+// CHECK-NEXT: [[TMP842:%.*]] = icmp sgt i16 [[TMP841]], [[TMP840]]
+// CHECK-NEXT: [[TMP843:%.*]] = select i1 [[TMP842]], i16 [[TMP840]], i16 [[TMP841]]
+// CHECK-NEXT: store i16 [[TMP843]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP844:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP845:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP844]], ptr [[SX_ATOMIC_EXPECTED_PTR1652]], align 2
+// CHECK-NEXT: store i16 [[TMP845]], ptr [[SX_ATOMIC_DESIRED_PTR1653]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1655:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1652]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1656:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1653]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1657:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1655]], i16 [[SX_CMPXCHG_DESIRED1656]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1658:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1657]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1658]], ptr [[SX_ATOMIC_EXPECTED_PTR1654]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1659:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1657]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1660:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1654]], align 2
+// CHECK-NEXT: [[SX_CAPTURE_CAPTURED1661:%.*]] = select i1 [[SX_CMPXCHG_SUCCESS1659]], i16 [[TMP844]], i16 [[SX_CAPTURE_ACTUAL1660]]
+// CHECK-NEXT: store i16 [[SX_CAPTURE_CAPTURED1661]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP846:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP847:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP846]], ptr [[SX_ATOMIC_EXPECTED_PTR1662]], align 2
+// CHECK-NEXT: store i16 [[TMP847]], ptr [[SX_ATOMIC_DESIRED_PTR1663]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1665:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1662]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1666:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1663]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1667:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1665]], i16 [[SX_CMPXCHG_DESIRED1666]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1668:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1667]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1668]], ptr [[SX_ATOMIC_EXPECTED_PTR1664]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1669:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1667]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1670:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1664]], align 2
+// CHECK-NEXT: [[SX_CAPTURE_CAPTURED1671:%.*]] = select i1 [[SX_CMPXCHG_SUCCESS1669]], i16 [[TMP846]], i16 [[SX_CAPTURE_ACTUAL1670]]
+// CHECK-NEXT: store i16 [[SX_CAPTURE_CAPTURED1671]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP848:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP849:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP848]], ptr [[SX_ATOMIC_EXPECTED_PTR1672]], align 2
+// CHECK-NEXT: store i16 [[TMP849]], ptr [[SX_ATOMIC_DESIRED_PTR1673]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1675:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1672]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1676:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1673]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1677:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1675]], i16 [[SX_CMPXCHG_DESIRED1676]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1678:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1677]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1678]], ptr [[SX_ATOMIC_EXPECTED_PTR1674]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1679:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1677]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1680:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1674]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1679]], label [[SX_ATOMIC_EXIT1681:%.*]], label [[SX_ATOMIC_CONT1682:%.*]]
+// CHECK: sx.atomic.cont1682:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1680]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1681]]
+// CHECK: sx.atomic.exit1681:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP850:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP851:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP850]], ptr [[SX_ATOMIC_EXPECTED_PTR1683]], align 2
+// CHECK-NEXT: store i16 [[TMP851]], ptr [[SX_ATOMIC_DESIRED_PTR1684]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1686:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1683]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1687:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1684]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1688:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1686]], i16 [[SX_CMPXCHG_DESIRED1687]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1689:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1688]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1689]], ptr [[SX_ATOMIC_EXPECTED_PTR1685]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1690:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1688]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1691:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1685]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1690]], label [[SX_ATOMIC_EXIT1692:%.*]], label [[SX_ATOMIC_CONT1693:%.*]]
+// CHECK: sx.atomic.cont1693:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1691]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1692]]
+// CHECK: sx.atomic.exit1692:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP852:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP853:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP852]], ptr [[SX_ATOMIC_EXPECTED_PTR1694]], align 2
+// CHECK-NEXT: store i16 [[TMP853]], ptr [[SX_ATOMIC_DESIRED_PTR1695]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1697:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1694]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1698:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1695]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1699:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1697]], i16 [[SX_CMPXCHG_DESIRED1698]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1700:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1699]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1700]], ptr [[SX_ATOMIC_EXPECTED_PTR1696]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1701:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1699]], 1
+// CHECK-NEXT: [[TMP854:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1701]] to i16
+// CHECK-NEXT: store i16 [[TMP854]], ptr [[SR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP855:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP856:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP855]], ptr [[SX_ATOMIC_EXPECTED_PTR1702]], align 2
+// CHECK-NEXT: store i16 [[TMP856]], ptr [[SX_ATOMIC_DESIRED_PTR1703]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1705:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1702]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1706:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1703]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1707:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1705]], i16 [[SX_CMPXCHG_DESIRED1706]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1708:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1707]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1708]], ptr [[SX_ATOMIC_EXPECTED_PTR1704]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1709:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1707]], 1
+// CHECK-NEXT: [[TMP857:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1709]] to i16
+// CHECK-NEXT: store i16 [[TMP857]], ptr [[SR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP858:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP859:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP858]], ptr [[SX_ATOMIC_EXPECTED_PTR1710]], align 2
+// CHECK-NEXT: store i16 [[TMP859]], ptr [[SX_ATOMIC_DESIRED_PTR1711]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1713:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1710]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1714:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1711]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1715:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1713]], i16 [[SX_CMPXCHG_DESIRED1714]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1716:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1715]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1716]], ptr [[SX_ATOMIC_EXPECTED_PTR1712]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1717:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1715]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1718:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1712]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1717]], label [[SX_ATOMIC_EXIT1719:%.*]], label [[SX_ATOMIC_CONT1720:%.*]]
+// CHECK: sx.atomic.cont1720:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1718]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1719]]
+// CHECK: sx.atomic.exit1719:
+// CHECK-NEXT: [[TMP860:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1717]] to i16
+// CHECK-NEXT: store i16 [[TMP860]], ptr [[SR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP861:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP862:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP861]], ptr [[SX_ATOMIC_EXPECTED_PTR1721]], align 2
+// CHECK-NEXT: store i16 [[TMP862]], ptr [[SX_ATOMIC_DESIRED_PTR1722]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED1724:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1721]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED1725:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR1722]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR1726:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED1724]], i16 [[SX_CMPXCHG_DESIRED1725]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV1727:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1726]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV1727]], ptr [[SX_ATOMIC_EXPECTED_PTR1723]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS1728:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR1726]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL1729:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1723]], align 2
+// CHECK-NEXT: br i1 [[SX_CMPXCHG_SUCCESS1728]], label [[SX_ATOMIC_EXIT1730:%.*]], label [[SX_ATOMIC_CONT1731:%.*]]
+// CHECK: sx.atomic.cont1731:
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL1729]], ptr [[SV]], align 2
+// CHECK-NEXT: br label [[SX_ATOMIC_EXIT1730]]
+// CHECK: sx.atomic.exit1730:
+// CHECK-NEXT: [[TMP863:%.*]] = sext i1 [[SX_CMPXCHG_SUCCESS1728]] to i16
+// CHECK-NEXT: store i16 [[TMP863]], ptr [[SR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP864:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP865:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP864]] monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP865]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP866:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP867:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP866]] monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP867]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP868:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP869:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP868]] monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP869]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP870:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP871:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP870]] monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP871]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP872:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP873:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP872]], ptr [[USX_ATOMIC_EXPECTED_PTR]], align 2
+// CHECK-NEXT: store i16 [[TMP873]], ptr [[USX_ATOMIC_DESIRED_PTR]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED]], i16 [[USX_CMPXCHG_DESIRED]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV]], ptr [[USX_ATOMIC_EXPECTED_PTR1732]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1732]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP874:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP875:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP874]], ptr [[USX_ATOMIC_EXPECTED_PTR1733]], align 2
+// CHECK-NEXT: store i16 [[TMP875]], ptr [[USX_ATOMIC_DESIRED_PTR1734]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1736:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1733]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1737:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1734]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1738:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1736]], i16 [[USX_CMPXCHG_DESIRED1737]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1739:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1738]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1739]], ptr [[USX_ATOMIC_EXPECTED_PTR1735]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1740:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1738]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1741:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1735]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL1741]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP876:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP877:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP876]] monotonic, align 2
+// CHECK-NEXT: [[TMP878:%.*]] = icmp ugt i16 [[TMP877]], [[TMP876]]
+// CHECK-NEXT: [[TMP879:%.*]] = select i1 [[TMP878]], i16 [[TMP876]], i16 [[TMP877]]
+// CHECK-NEXT: store i16 [[TMP879]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP880:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP881:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP880]] monotonic, align 2
+// CHECK-NEXT: [[TMP882:%.*]] = icmp ult i16 [[TMP881]], [[TMP880]]
+// CHECK-NEXT: [[TMP883:%.*]] = select i1 [[TMP882]], i16 [[TMP880]], i16 [[TMP881]]
+// CHECK-NEXT: store i16 [[TMP883]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP884:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP885:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP884]] monotonic, align 2
+// CHECK-NEXT: [[TMP886:%.*]] = icmp ult i16 [[TMP885]], [[TMP884]]
+// CHECK-NEXT: [[TMP887:%.*]] = select i1 [[TMP886]], i16 [[TMP884]], i16 [[TMP885]]
+// CHECK-NEXT: store i16 [[TMP887]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP888:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP889:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP888]] monotonic, align 2
+// CHECK-NEXT: [[TMP890:%.*]] = icmp ugt i16 [[TMP889]], [[TMP888]]
+// CHECK-NEXT: [[TMP891:%.*]] = select i1 [[TMP890]], i16 [[TMP888]], i16 [[TMP889]]
+// CHECK-NEXT: store i16 [[TMP891]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP892:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP893:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP892]], ptr [[USX_ATOMIC_EXPECTED_PTR1742]], align 2
+// CHECK-NEXT: store i16 [[TMP893]], ptr [[USX_ATOMIC_DESIRED_PTR1743]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1745:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1742]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1746:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1743]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1747:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1745]], i16 [[USX_CMPXCHG_DESIRED1746]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1748:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1747]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1748]], ptr [[USX_ATOMIC_EXPECTED_PTR1744]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1749:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1747]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1750:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1744]], align 2
+// CHECK-NEXT: [[USX_CAPTURE_CAPTURED:%.*]] = select i1 [[USX_CMPXCHG_SUCCESS1749]], i16 [[TMP892]], i16 [[USX_CAPTURE_ACTUAL1750]]
+// CHECK-NEXT: store i16 [[USX_CAPTURE_CAPTURED]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP894:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP895:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP894]], ptr [[USX_ATOMIC_EXPECTED_PTR1751]], align 2
+// CHECK-NEXT: store i16 [[TMP895]], ptr [[USX_ATOMIC_DESIRED_PTR1752]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1754:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1751]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1755:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1752]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1756:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1754]], i16 [[USX_CMPXCHG_DESIRED1755]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1757:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1756]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1757]], ptr [[USX_ATOMIC_EXPECTED_PTR1753]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1758:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1756]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1759:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1753]], align 2
+// CHECK-NEXT: [[USX_CAPTURE_CAPTURED1760:%.*]] = select i1 [[USX_CMPXCHG_SUCCESS1758]], i16 [[TMP894]], i16 [[USX_CAPTURE_ACTUAL1759]]
+// CHECK-NEXT: store i16 [[USX_CAPTURE_CAPTURED1760]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP896:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP897:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP896]], ptr [[USX_ATOMIC_EXPECTED_PTR1761]], align 2
+// CHECK-NEXT: store i16 [[TMP897]], ptr [[USX_ATOMIC_DESIRED_PTR1762]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1764:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1761]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1765:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1762]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1766:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1764]], i16 [[USX_CMPXCHG_DESIRED1765]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1767:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1766]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1767]], ptr [[USX_ATOMIC_EXPECTED_PTR1763]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1768:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1766]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1769:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1763]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS1768]], label [[USX_ATOMIC_EXIT:%.*]], label [[USX_ATOMIC_CONT:%.*]]
// CHECK: usx.atomic.cont:
-// CHECK-NEXT: store i16 [[TMP1451]], ptr [[USV]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL1769]], ptr [[USV]], align 2
// CHECK-NEXT: br label [[USX_ATOMIC_EXIT]]
// CHECK: usx.atomic.exit:
-// CHECK-NEXT: [[TMP1453:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1454:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1455:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1453]], i16 [[TMP1454]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1456:%.*]] = extractvalue { i16, i1 } [[TMP1455]], 0
-// CHECK-NEXT: [[TMP1457:%.*]] = extractvalue { i16, i1 } [[TMP1455]], 1
-// CHECK-NEXT: br i1 [[TMP1457]], label [[USX_ATOMIC_EXIT139:%.*]], label [[USX_ATOMIC_CONT140:%.*]]
-// CHECK: usx.atomic.cont140:
-// CHECK-NEXT: store i16 [[TMP1456]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT139]]
-// CHECK: usx.atomic.exit139:
-// CHECK-NEXT: [[TMP1458:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1459:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1460:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1458]], i16 [[TMP1459]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1461:%.*]] = extractvalue { i16, i1 } [[TMP1460]], 1
-// CHECK-NEXT: [[TMP1462:%.*]] = zext i1 [[TMP1461]] to i16
-// CHECK-NEXT: store i16 [[TMP1462]], ptr [[USR]], align 2
-// CHECK-NEXT: [[TMP1463:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1464:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1465:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1463]], i16 [[TMP1464]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1466:%.*]] = extractvalue { i16, i1 } [[TMP1465]], 1
-// CHECK-NEXT: [[TMP1467:%.*]] = zext i1 [[TMP1466]] to i16
-// CHECK-NEXT: store i16 [[TMP1467]], ptr [[USR]], align 2
-// CHECK-NEXT: [[TMP1468:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1469:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1470:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1468]], i16 [[TMP1469]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1471:%.*]] = extractvalue { i16, i1 } [[TMP1470]], 0
-// CHECK-NEXT: [[TMP1472:%.*]] = extractvalue { i16, i1 } [[TMP1470]], 1
-// CHECK-NEXT: br i1 [[TMP1472]], label [[USX_ATOMIC_EXIT141:%.*]], label [[USX_ATOMIC_CONT142:%.*]]
-// CHECK: usx.atomic.cont142:
-// CHECK-NEXT: store i16 [[TMP1471]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT141]]
-// CHECK: usx.atomic.exit141:
-// CHECK-NEXT: [[TMP1473:%.*]] = extractvalue { i16, i1 } [[TMP1470]], 1
-// CHECK-NEXT: [[TMP1474:%.*]] = zext i1 [[TMP1473]] to i16
-// CHECK-NEXT: store i16 [[TMP1474]], ptr [[USR]], align 2
-// CHECK-NEXT: [[TMP1475:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1476:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1477:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1475]], i16 [[TMP1476]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1478:%.*]] = extractvalue { i16, i1 } [[TMP1477]], 0
-// CHECK-NEXT: [[TMP1479:%.*]] = extractvalue { i16, i1 } [[TMP1477]], 1
-// CHECK-NEXT: br i1 [[TMP1479]], label [[USX_ATOMIC_EXIT143:%.*]], label [[USX_ATOMIC_CONT144:%.*]]
-// CHECK: usx.atomic.cont144:
-// CHECK-NEXT: store i16 [[TMP1478]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT143]]
-// CHECK: usx.atomic.exit143:
-// CHECK-NEXT: [[TMP1480:%.*]] = extractvalue { i16, i1 } [[TMP1477]], 1
-// CHECK-NEXT: [[TMP1481:%.*]] = zext i1 [[TMP1480]] to i16
-// CHECK-NEXT: store i16 [[TMP1481]], ptr [[USR]], align 2
-// CHECK-NEXT: [[TMP1482:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1483:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1482]] acq_rel, align 2
-// CHECK-NEXT: store i16 [[TMP1483]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1484:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1485:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1484]] acq_rel, align 2
-// CHECK-NEXT: store i16 [[TMP1485]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1486:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1487:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1486]] acq_rel, align 2
-// CHECK-NEXT: store i16 [[TMP1487]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1488:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1489:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1488]] acq_rel, align 2
-// CHECK-NEXT: store i16 [[TMP1489]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1490:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1491:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1492:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1490]], i16 [[TMP1491]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1493:%.*]] = extractvalue { i16, i1 } [[TMP1492]], 0
-// CHECK-NEXT: store i16 [[TMP1493]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1494:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1495:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1496:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1494]], i16 [[TMP1495]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1497:%.*]] = extractvalue { i16, i1 } [[TMP1496]], 0
-// CHECK-NEXT: store i16 [[TMP1497]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1498:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1499:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1498]] acq_rel, align 2
-// CHECK-NEXT: [[TMP1500:%.*]] = icmp ugt i16 [[TMP1499]], [[TMP1498]]
-// CHECK-NEXT: [[TMP1501:%.*]] = select i1 [[TMP1500]], i16 [[TMP1498]], i16 [[TMP1499]]
-// CHECK-NEXT: store i16 [[TMP1501]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1502:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1503:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1502]] acq_rel, align 2
-// CHECK-NEXT: [[TMP1504:%.*]] = icmp ult i16 [[TMP1503]], [[TMP1502]]
-// CHECK-NEXT: [[TMP1505:%.*]] = select i1 [[TMP1504]], i16 [[TMP1502]], i16 [[TMP1503]]
-// CHECK-NEXT: store i16 [[TMP1505]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1506:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1507:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1506]] acq_rel, align 2
-// CHECK-NEXT: [[TMP1508:%.*]] = icmp ult i16 [[TMP1507]], [[TMP1506]]
-// CHECK-NEXT: [[TMP1509:%.*]] = select i1 [[TMP1508]], i16 [[TMP1506]], i16 [[TMP1507]]
-// CHECK-NEXT: store i16 [[TMP1509]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1510:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1511:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1510]] acq_rel, align 2
-// CHECK-NEXT: [[TMP1512:%.*]] = icmp ugt i16 [[TMP1511]], [[TMP1510]]
-// CHECK-NEXT: [[TMP1513:%.*]] = select i1 [[TMP1512]], i16 [[TMP1510]], i16 [[TMP1511]]
-// CHECK-NEXT: store i16 [[TMP1513]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1514:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1515:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1516:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1514]], i16 [[TMP1515]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1517:%.*]] = extractvalue { i16, i1 } [[TMP1516]], 0
-// CHECK-NEXT: [[TMP1518:%.*]] = extractvalue { i16, i1 } [[TMP1516]], 1
-// CHECK-NEXT: [[TMP1519:%.*]] = select i1 [[TMP1518]], i16 [[TMP1514]], i16 [[TMP1517]]
-// CHECK-NEXT: store i16 [[TMP1519]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1520:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1521:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1522:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1520]], i16 [[TMP1521]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1523:%.*]] = extractvalue { i16, i1 } [[TMP1522]], 0
-// CHECK-NEXT: [[TMP1524:%.*]] = extractvalue { i16, i1 } [[TMP1522]], 1
-// CHECK-NEXT: [[TMP1525:%.*]] = select i1 [[TMP1524]], i16 [[TMP1520]], i16 [[TMP1523]]
-// CHECK-NEXT: store i16 [[TMP1525]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1526:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1527:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1528:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1526]], i16 [[TMP1527]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1529:%.*]] = extractvalue { i16, i1 } [[TMP1528]], 0
-// CHECK-NEXT: [[TMP1530:%.*]] = extractvalue { i16, i1 } [[TMP1528]], 1
-// CHECK-NEXT: br i1 [[TMP1530]], label [[USX_ATOMIC_EXIT145:%.*]], label [[USX_ATOMIC_CONT146:%.*]]
-// CHECK: usx.atomic.cont146:
-// CHECK-NEXT: store i16 [[TMP1529]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT145]]
-// CHECK: usx.atomic.exit145:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1531:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1532:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1533:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1531]], i16 [[TMP1532]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1534:%.*]] = extractvalue { i16, i1 } [[TMP1533]], 0
-// CHECK-NEXT: [[TMP1535:%.*]] = extractvalue { i16, i1 } [[TMP1533]], 1
-// CHECK-NEXT: br i1 [[TMP1535]], label [[USX_ATOMIC_EXIT147:%.*]], label [[USX_ATOMIC_CONT148:%.*]]
-// CHECK: usx.atomic.cont148:
-// CHECK-NEXT: store i16 [[TMP1534]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT147]]
-// CHECK: usx.atomic.exit147:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1536:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1537:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1538:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1536]], i16 [[TMP1537]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1539:%.*]] = extractvalue { i16, i1 } [[TMP1538]], 1
-// CHECK-NEXT: [[TMP1540:%.*]] = zext i1 [[TMP1539]] to i16
-// CHECK-NEXT: store i16 [[TMP1540]], ptr [[USR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1541:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1542:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1543:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1541]], i16 [[TMP1542]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1544:%.*]] = extractvalue { i16, i1 } [[TMP1543]], 1
-// CHECK-NEXT: [[TMP1545:%.*]] = zext i1 [[TMP1544]] to i16
-// CHECK-NEXT: store i16 [[TMP1545]], ptr [[USR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1546:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1547:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1548:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1546]], i16 [[TMP1547]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1549:%.*]] = extractvalue { i16, i1 } [[TMP1548]], 0
-// CHECK-NEXT: [[TMP1550:%.*]] = extractvalue { i16, i1 } [[TMP1548]], 1
-// CHECK-NEXT: br i1 [[TMP1550]], label [[USX_ATOMIC_EXIT149:%.*]], label [[USX_ATOMIC_CONT150:%.*]]
-// CHECK: usx.atomic.cont150:
-// CHECK-NEXT: store i16 [[TMP1549]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT149]]
-// CHECK: usx.atomic.exit149:
-// CHECK-NEXT: [[TMP1551:%.*]] = extractvalue { i16, i1 } [[TMP1548]], 1
-// CHECK-NEXT: [[TMP1552:%.*]] = zext i1 [[TMP1551]] to i16
-// CHECK-NEXT: store i16 [[TMP1552]], ptr [[USR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1553:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1554:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1555:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1553]], i16 [[TMP1554]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP1556:%.*]] = extractvalue { i16, i1 } [[TMP1555]], 0
-// CHECK-NEXT: [[TMP1557:%.*]] = extractvalue { i16, i1 } [[TMP1555]], 1
-// CHECK-NEXT: br i1 [[TMP1557]], label [[USX_ATOMIC_EXIT151:%.*]], label [[USX_ATOMIC_CONT152:%.*]]
-// CHECK: usx.atomic.cont152:
-// CHECK-NEXT: store i16 [[TMP1556]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT151]]
-// CHECK: usx.atomic.exit151:
-// CHECK-NEXT: [[TMP1558:%.*]] = extractvalue { i16, i1 } [[TMP1555]], 1
-// CHECK-NEXT: [[TMP1559:%.*]] = zext i1 [[TMP1558]] to i16
-// CHECK-NEXT: store i16 [[TMP1559]], ptr [[USR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1560:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1561:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1560]] acquire, align 2
-// CHECK-NEXT: store i16 [[TMP1561]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1562:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1563:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1562]] acquire, align 2
-// CHECK-NEXT: store i16 [[TMP1563]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1564:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1565:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1564]] acquire, align 2
-// CHECK-NEXT: store i16 [[TMP1565]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1566:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1567:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1566]] acquire, align 2
-// CHECK-NEXT: store i16 [[TMP1567]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1568:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1569:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1570:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1568]], i16 [[TMP1569]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1571:%.*]] = extractvalue { i16, i1 } [[TMP1570]], 0
-// CHECK-NEXT: store i16 [[TMP1571]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1572:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1573:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1574:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1572]], i16 [[TMP1573]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1575:%.*]] = extractvalue { i16, i1 } [[TMP1574]], 0
-// CHECK-NEXT: store i16 [[TMP1575]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1576:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1577:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1576]] acquire, align 2
-// CHECK-NEXT: [[TMP1578:%.*]] = icmp ugt i16 [[TMP1577]], [[TMP1576]]
-// CHECK-NEXT: [[TMP1579:%.*]] = select i1 [[TMP1578]], i16 [[TMP1576]], i16 [[TMP1577]]
-// CHECK-NEXT: store i16 [[TMP1579]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1580:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1581:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1580]] acquire, align 2
-// CHECK-NEXT: [[TMP1582:%.*]] = icmp ult i16 [[TMP1581]], [[TMP1580]]
-// CHECK-NEXT: [[TMP1583:%.*]] = select i1 [[TMP1582]], i16 [[TMP1580]], i16 [[TMP1581]]
-// CHECK-NEXT: store i16 [[TMP1583]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1584:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1585:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1584]] acquire, align 2
-// CHECK-NEXT: [[TMP1586:%.*]] = icmp ult i16 [[TMP1585]], [[TMP1584]]
-// CHECK-NEXT: [[TMP1587:%.*]] = select i1 [[TMP1586]], i16 [[TMP1584]], i16 [[TMP1585]]
-// CHECK-NEXT: store i16 [[TMP1587]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1588:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1589:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1588]] acquire, align 2
-// CHECK-NEXT: [[TMP1590:%.*]] = icmp ugt i16 [[TMP1589]], [[TMP1588]]
-// CHECK-NEXT: [[TMP1591:%.*]] = select i1 [[TMP1590]], i16 [[TMP1588]], i16 [[TMP1589]]
-// CHECK-NEXT: store i16 [[TMP1591]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1592:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1593:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1594:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1592]], i16 [[TMP1593]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1595:%.*]] = extractvalue { i16, i1 } [[TMP1594]], 0
-// CHECK-NEXT: [[TMP1596:%.*]] = extractvalue { i16, i1 } [[TMP1594]], 1
-// CHECK-NEXT: [[TMP1597:%.*]] = select i1 [[TMP1596]], i16 [[TMP1592]], i16 [[TMP1595]]
-// CHECK-NEXT: store i16 [[TMP1597]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1598:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1599:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1600:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1598]], i16 [[TMP1599]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1601:%.*]] = extractvalue { i16, i1 } [[TMP1600]], 0
-// CHECK-NEXT: [[TMP1602:%.*]] = extractvalue { i16, i1 } [[TMP1600]], 1
-// CHECK-NEXT: [[TMP1603:%.*]] = select i1 [[TMP1602]], i16 [[TMP1598]], i16 [[TMP1601]]
-// CHECK-NEXT: store i16 [[TMP1603]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1604:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1605:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1606:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1604]], i16 [[TMP1605]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1607:%.*]] = extractvalue { i16, i1 } [[TMP1606]], 0
-// CHECK-NEXT: [[TMP1608:%.*]] = extractvalue { i16, i1 } [[TMP1606]], 1
-// CHECK-NEXT: br i1 [[TMP1608]], label [[USX_ATOMIC_EXIT153:%.*]], label [[USX_ATOMIC_CONT154:%.*]]
-// CHECK: usx.atomic.cont154:
-// CHECK-NEXT: store i16 [[TMP1607]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT153]]
-// CHECK: usx.atomic.exit153:
-// CHECK-NEXT: [[TMP1609:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1610:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1611:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1609]], i16 [[TMP1610]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1612:%.*]] = extractvalue { i16, i1 } [[TMP1611]], 0
-// CHECK-NEXT: [[TMP1613:%.*]] = extractvalue { i16, i1 } [[TMP1611]], 1
-// CHECK-NEXT: br i1 [[TMP1613]], label [[USX_ATOMIC_EXIT155:%.*]], label [[USX_ATOMIC_CONT156:%.*]]
-// CHECK: usx.atomic.cont156:
-// CHECK-NEXT: store i16 [[TMP1612]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT155]]
-// CHECK: usx.atomic.exit155:
-// CHECK-NEXT: [[TMP1614:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1615:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1616:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1614]], i16 [[TMP1615]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1617:%.*]] = extractvalue { i16, i1 } [[TMP1616]], 1
-// CHECK-NEXT: [[TMP1618:%.*]] = zext i1 [[TMP1617]] to i16
-// CHECK-NEXT: store i16 [[TMP1618]], ptr [[USR]], align 2
-// CHECK-NEXT: [[TMP1619:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1620:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1621:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1619]], i16 [[TMP1620]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1622:%.*]] = extractvalue { i16, i1 } [[TMP1621]], 1
-// CHECK-NEXT: [[TMP1623:%.*]] = zext i1 [[TMP1622]] to i16
-// CHECK-NEXT: store i16 [[TMP1623]], ptr [[USR]], align 2
-// CHECK-NEXT: [[TMP1624:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1625:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1626:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1624]], i16 [[TMP1625]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1627:%.*]] = extractvalue { i16, i1 } [[TMP1626]], 0
-// CHECK-NEXT: [[TMP1628:%.*]] = extractvalue { i16, i1 } [[TMP1626]], 1
-// CHECK-NEXT: br i1 [[TMP1628]], label [[USX_ATOMIC_EXIT157:%.*]], label [[USX_ATOMIC_CONT158:%.*]]
-// CHECK: usx.atomic.cont158:
-// CHECK-NEXT: store i16 [[TMP1627]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT157]]
-// CHECK: usx.atomic.exit157:
-// CHECK-NEXT: [[TMP1629:%.*]] = extractvalue { i16, i1 } [[TMP1626]], 1
-// CHECK-NEXT: [[TMP1630:%.*]] = zext i1 [[TMP1629]] to i16
-// CHECK-NEXT: store i16 [[TMP1630]], ptr [[USR]], align 2
-// CHECK-NEXT: [[TMP1631:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1632:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1633:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1631]], i16 [[TMP1632]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP1634:%.*]] = extractvalue { i16, i1 } [[TMP1633]], 0
-// CHECK-NEXT: [[TMP1635:%.*]] = extractvalue { i16, i1 } [[TMP1633]], 1
-// CHECK-NEXT: br i1 [[TMP1635]], label [[USX_ATOMIC_EXIT159:%.*]], label [[USX_ATOMIC_CONT160:%.*]]
-// CHECK: usx.atomic.cont160:
-// CHECK-NEXT: store i16 [[TMP1634]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT159]]
-// CHECK: usx.atomic.exit159:
-// CHECK-NEXT: [[TMP1636:%.*]] = extractvalue { i16, i1 } [[TMP1633]], 1
-// CHECK-NEXT: [[TMP1637:%.*]] = zext i1 [[TMP1636]] to i16
-// CHECK-NEXT: store i16 [[TMP1637]], ptr [[USR]], align 2
-// CHECK-NEXT: [[TMP1638:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1639:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1638]] monotonic, align 2
-// CHECK-NEXT: store i16 [[TMP1639]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1640:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1641:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1640]] monotonic, align 2
-// CHECK-NEXT: store i16 [[TMP1641]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1642:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1643:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1642]] monotonic, align 2
-// CHECK-NEXT: store i16 [[TMP1643]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1644:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1645:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1644]] monotonic, align 2
-// CHECK-NEXT: store i16 [[TMP1645]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1646:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1647:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1648:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1646]], i16 [[TMP1647]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1649:%.*]] = extractvalue { i16, i1 } [[TMP1648]], 0
-// CHECK-NEXT: store i16 [[TMP1649]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1650:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1651:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1652:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1650]], i16 [[TMP1651]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1653:%.*]] = extractvalue { i16, i1 } [[TMP1652]], 0
-// CHECK-NEXT: store i16 [[TMP1653]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1654:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1655:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1654]] monotonic, align 2
-// CHECK-NEXT: [[TMP1656:%.*]] = icmp ugt i16 [[TMP1655]], [[TMP1654]]
-// CHECK-NEXT: [[TMP1657:%.*]] = select i1 [[TMP1656]], i16 [[TMP1654]], i16 [[TMP1655]]
-// CHECK-NEXT: store i16 [[TMP1657]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1658:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1659:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1658]] monotonic, align 2
-// CHECK-NEXT: [[TMP1660:%.*]] = icmp ult i16 [[TMP1659]], [[TMP1658]]
-// CHECK-NEXT: [[TMP1661:%.*]] = select i1 [[TMP1660]], i16 [[TMP1658]], i16 [[TMP1659]]
-// CHECK-NEXT: store i16 [[TMP1661]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1662:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1663:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1662]] monotonic, align 2
-// CHECK-NEXT: [[TMP1664:%.*]] = icmp ult i16 [[TMP1663]], [[TMP1662]]
-// CHECK-NEXT: [[TMP1665:%.*]] = select i1 [[TMP1664]], i16 [[TMP1662]], i16 [[TMP1663]]
-// CHECK-NEXT: store i16 [[TMP1665]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1666:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1667:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1666]] monotonic, align 2
-// CHECK-NEXT: [[TMP1668:%.*]] = icmp ugt i16 [[TMP1667]], [[TMP1666]]
-// CHECK-NEXT: [[TMP1669:%.*]] = select i1 [[TMP1668]], i16 [[TMP1666]], i16 [[TMP1667]]
-// CHECK-NEXT: store i16 [[TMP1669]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1670:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1671:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1672:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1670]], i16 [[TMP1671]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1673:%.*]] = extractvalue { i16, i1 } [[TMP1672]], 0
-// CHECK-NEXT: [[TMP1674:%.*]] = extractvalue { i16, i1 } [[TMP1672]], 1
-// CHECK-NEXT: [[TMP1675:%.*]] = select i1 [[TMP1674]], i16 [[TMP1670]], i16 [[TMP1673]]
-// CHECK-NEXT: store i16 [[TMP1675]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1676:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1677:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1678:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1676]], i16 [[TMP1677]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1679:%.*]] = extractvalue { i16, i1 } [[TMP1678]], 0
-// CHECK-NEXT: [[TMP1680:%.*]] = extractvalue { i16, i1 } [[TMP1678]], 1
-// CHECK-NEXT: [[TMP1681:%.*]] = select i1 [[TMP1680]], i16 [[TMP1676]], i16 [[TMP1679]]
-// CHECK-NEXT: store i16 [[TMP1681]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP1682:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1683:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1684:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1682]], i16 [[TMP1683]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1685:%.*]] = extractvalue { i16, i1 } [[TMP1684]], 0
-// CHECK-NEXT: [[TMP1686:%.*]] = extractvalue { i16, i1 } [[TMP1684]], 1
-// CHECK-NEXT: br i1 [[TMP1686]], label [[USX_ATOMIC_EXIT161:%.*]], label [[USX_ATOMIC_CONT162:%.*]]
-// CHECK: usx.atomic.cont162:
-// CHECK-NEXT: store i16 [[TMP1685]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT161]]
-// CHECK: usx.atomic.exit161:
-// CHECK-NEXT: [[TMP1687:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1688:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1689:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1687]], i16 [[TMP1688]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1690:%.*]] = extractvalue { i16, i1 } [[TMP1689]], 0
-// CHECK-NEXT: [[TMP1691:%.*]] = extractvalue { i16, i1 } [[TMP1689]], 1
-// CHECK-NEXT: br i1 [[TMP1691]], label [[USX_ATOMIC_EXIT163:%.*]], label [[USX_ATOMIC_CONT164:%.*]]
-// CHECK: usx.atomic.cont164:
-// CHECK-NEXT: store i16 [[TMP1690]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT163]]
-// CHECK: usx.atomic.exit163:
-// CHECK-NEXT: [[TMP1692:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1693:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1694:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1692]], i16 [[TMP1693]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1695:%.*]] = extractvalue { i16, i1 } [[TMP1694]], 1
-// CHECK-NEXT: [[TMP1696:%.*]] = zext i1 [[TMP1695]] to i16
-// CHECK-NEXT: store i16 [[TMP1696]], ptr [[USR]], align 2
-// CHECK-NEXT: [[TMP1697:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1698:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1699:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1697]], i16 [[TMP1698]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1700:%.*]] = extractvalue { i16, i1 } [[TMP1699]], 1
-// CHECK-NEXT: [[TMP1701:%.*]] = zext i1 [[TMP1700]] to i16
-// CHECK-NEXT: store i16 [[TMP1701]], ptr [[USR]], align 2
-// CHECK-NEXT: [[TMP1702:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1703:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1704:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1702]], i16 [[TMP1703]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1705:%.*]] = extractvalue { i16, i1 } [[TMP1704]], 0
-// CHECK-NEXT: [[TMP1706:%.*]] = extractvalue { i16, i1 } [[TMP1704]], 1
-// CHECK-NEXT: br i1 [[TMP1706]], label [[USX_ATOMIC_EXIT165:%.*]], label [[USX_ATOMIC_CONT166:%.*]]
-// CHECK: usx.atomic.cont166:
-// CHECK-NEXT: store i16 [[TMP1705]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT165]]
-// CHECK: usx.atomic.exit165:
-// CHECK-NEXT: [[TMP1707:%.*]] = extractvalue { i16, i1 } [[TMP1704]], 1
-// CHECK-NEXT: [[TMP1708:%.*]] = zext i1 [[TMP1707]] to i16
-// CHECK-NEXT: store i16 [[TMP1708]], ptr [[USR]], align 2
-// CHECK-NEXT: [[TMP1709:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1710:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1711:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1709]], i16 [[TMP1710]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP1712:%.*]] = extractvalue { i16, i1 } [[TMP1711]], 0
-// CHECK-NEXT: [[TMP1713:%.*]] = extractvalue { i16, i1 } [[TMP1711]], 1
-// CHECK-NEXT: br i1 [[TMP1713]], label [[USX_ATOMIC_EXIT167:%.*]], label [[USX_ATOMIC_CONT168:%.*]]
-// CHECK: usx.atomic.cont168:
-// CHECK-NEXT: store i16 [[TMP1712]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT167]]
-// CHECK: usx.atomic.exit167:
-// CHECK-NEXT: [[TMP1714:%.*]] = extractvalue { i16, i1 } [[TMP1711]], 1
-// CHECK-NEXT: [[TMP1715:%.*]] = zext i1 [[TMP1714]] to i16
-// CHECK-NEXT: store i16 [[TMP1715]], ptr [[USR]], align 2
-// CHECK-NEXT: [[TMP1716:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1717:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1716]] release, align 2
-// CHECK-NEXT: store i16 [[TMP1717]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1718:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1719:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1718]] release, align 2
-// CHECK-NEXT: store i16 [[TMP1719]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1720:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1721:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1720]] release, align 2
-// CHECK-NEXT: store i16 [[TMP1721]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1722:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1723:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1722]] release, align 2
-// CHECK-NEXT: store i16 [[TMP1723]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1724:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1725:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1726:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1724]], i16 [[TMP1725]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1727:%.*]] = extractvalue { i16, i1 } [[TMP1726]], 0
-// CHECK-NEXT: store i16 [[TMP1727]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1728:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1729:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1730:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1728]], i16 [[TMP1729]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1731:%.*]] = extractvalue { i16, i1 } [[TMP1730]], 0
-// CHECK-NEXT: store i16 [[TMP1731]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1732:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1733:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1732]] release, align 2
-// CHECK-NEXT: [[TMP1734:%.*]] = icmp ugt i16 [[TMP1733]], [[TMP1732]]
-// CHECK-NEXT: [[TMP1735:%.*]] = select i1 [[TMP1734]], i16 [[TMP1732]], i16 [[TMP1733]]
-// CHECK-NEXT: store i16 [[TMP1735]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1736:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1737:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1736]] release, align 2
-// CHECK-NEXT: [[TMP1738:%.*]] = icmp ult i16 [[TMP1737]], [[TMP1736]]
-// CHECK-NEXT: [[TMP1739:%.*]] = select i1 [[TMP1738]], i16 [[TMP1736]], i16 [[TMP1737]]
-// CHECK-NEXT: store i16 [[TMP1739]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1740:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1741:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1740]] release, align 2
-// CHECK-NEXT: [[TMP1742:%.*]] = icmp ult i16 [[TMP1741]], [[TMP1740]]
-// CHECK-NEXT: [[TMP1743:%.*]] = select i1 [[TMP1742]], i16 [[TMP1740]], i16 [[TMP1741]]
-// CHECK-NEXT: store i16 [[TMP1743]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1744:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1745:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1744]] release, align 2
-// CHECK-NEXT: [[TMP1746:%.*]] = icmp ugt i16 [[TMP1745]], [[TMP1744]]
-// CHECK-NEXT: [[TMP1747:%.*]] = select i1 [[TMP1746]], i16 [[TMP1744]], i16 [[TMP1745]]
-// CHECK-NEXT: store i16 [[TMP1747]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1748:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1749:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1750:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1748]], i16 [[TMP1749]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1751:%.*]] = extractvalue { i16, i1 } [[TMP1750]], 0
-// CHECK-NEXT: [[TMP1752:%.*]] = extractvalue { i16, i1 } [[TMP1750]], 1
-// CHECK-NEXT: [[TMP1753:%.*]] = select i1 [[TMP1752]], i16 [[TMP1748]], i16 [[TMP1751]]
-// CHECK-NEXT: store i16 [[TMP1753]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1754:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1755:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1756:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1754]], i16 [[TMP1755]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1757:%.*]] = extractvalue { i16, i1 } [[TMP1756]], 0
-// CHECK-NEXT: [[TMP1758:%.*]] = extractvalue { i16, i1 } [[TMP1756]], 1
-// CHECK-NEXT: [[TMP1759:%.*]] = select i1 [[TMP1758]], i16 [[TMP1754]], i16 [[TMP1757]]
-// CHECK-NEXT: store i16 [[TMP1759]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1760:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1761:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1762:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1760]], i16 [[TMP1761]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1763:%.*]] = extractvalue { i16, i1 } [[TMP1762]], 0
-// CHECK-NEXT: [[TMP1764:%.*]] = extractvalue { i16, i1 } [[TMP1762]], 1
-// CHECK-NEXT: br i1 [[TMP1764]], label [[USX_ATOMIC_EXIT169:%.*]], label [[USX_ATOMIC_CONT170:%.*]]
-// CHECK: usx.atomic.cont170:
-// CHECK-NEXT: store i16 [[TMP1763]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT169]]
-// CHECK: usx.atomic.exit169:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1765:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1766:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1767:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1765]], i16 [[TMP1766]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1768:%.*]] = extractvalue { i16, i1 } [[TMP1767]], 0
-// CHECK-NEXT: [[TMP1769:%.*]] = extractvalue { i16, i1 } [[TMP1767]], 1
-// CHECK-NEXT: br i1 [[TMP1769]], label [[USX_ATOMIC_EXIT171:%.*]], label [[USX_ATOMIC_CONT172:%.*]]
-// CHECK: usx.atomic.cont172:
-// CHECK-NEXT: store i16 [[TMP1768]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT171]]
-// CHECK: usx.atomic.exit171:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1770:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1771:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1772:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1770]], i16 [[TMP1771]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1773:%.*]] = extractvalue { i16, i1 } [[TMP1772]], 1
-// CHECK-NEXT: [[TMP1774:%.*]] = zext i1 [[TMP1773]] to i16
-// CHECK-NEXT: store i16 [[TMP1774]], ptr [[USR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1775:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1776:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1777:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1775]], i16 [[TMP1776]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1778:%.*]] = extractvalue { i16, i1 } [[TMP1777]], 1
-// CHECK-NEXT: [[TMP1779:%.*]] = zext i1 [[TMP1778]] to i16
-// CHECK-NEXT: store i16 [[TMP1779]], ptr [[USR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1780:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1781:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1782:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1780]], i16 [[TMP1781]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1783:%.*]] = extractvalue { i16, i1 } [[TMP1782]], 0
-// CHECK-NEXT: [[TMP1784:%.*]] = extractvalue { i16, i1 } [[TMP1782]], 1
-// CHECK-NEXT: br i1 [[TMP1784]], label [[USX_ATOMIC_EXIT173:%.*]], label [[USX_ATOMIC_CONT174:%.*]]
-// CHECK: usx.atomic.cont174:
-// CHECK-NEXT: store i16 [[TMP1783]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT173]]
-// CHECK: usx.atomic.exit173:
-// CHECK-NEXT: [[TMP1785:%.*]] = extractvalue { i16, i1 } [[TMP1782]], 1
-// CHECK-NEXT: [[TMP1786:%.*]] = zext i1 [[TMP1785]] to i16
-// CHECK-NEXT: store i16 [[TMP1786]], ptr [[USR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1787:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1788:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1789:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1787]], i16 [[TMP1788]] release monotonic, align 2
-// CHECK-NEXT: [[TMP1790:%.*]] = extractvalue { i16, i1 } [[TMP1789]], 0
-// CHECK-NEXT: [[TMP1791:%.*]] = extractvalue { i16, i1 } [[TMP1789]], 1
-// CHECK-NEXT: br i1 [[TMP1791]], label [[USX_ATOMIC_EXIT175:%.*]], label [[USX_ATOMIC_CONT176:%.*]]
-// CHECK: usx.atomic.cont176:
-// CHECK-NEXT: store i16 [[TMP1790]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT175]]
-// CHECK: usx.atomic.exit175:
-// CHECK-NEXT: [[TMP1792:%.*]] = extractvalue { i16, i1 } [[TMP1789]], 1
-// CHECK-NEXT: [[TMP1793:%.*]] = zext i1 [[TMP1792]] to i16
-// CHECK-NEXT: store i16 [[TMP1793]], ptr [[USR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1794:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1795:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1794]] seq_cst, align 2
-// CHECK-NEXT: store i16 [[TMP1795]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1796:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1797:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1796]] seq_cst, align 2
-// CHECK-NEXT: store i16 [[TMP1797]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1798:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1799:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1798]] seq_cst, align 2
-// CHECK-NEXT: store i16 [[TMP1799]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1800:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1801:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1800]] seq_cst, align 2
-// CHECK-NEXT: store i16 [[TMP1801]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1802:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1803:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1804:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1802]], i16 [[TMP1803]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1805:%.*]] = extractvalue { i16, i1 } [[TMP1804]], 0
-// CHECK-NEXT: store i16 [[TMP1805]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1806:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1807:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1808:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1806]], i16 [[TMP1807]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1809:%.*]] = extractvalue { i16, i1 } [[TMP1808]], 0
-// CHECK-NEXT: store i16 [[TMP1809]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1810:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1811:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1810]] seq_cst, align 2
-// CHECK-NEXT: [[TMP1812:%.*]] = icmp ugt i16 [[TMP1811]], [[TMP1810]]
-// CHECK-NEXT: [[TMP1813:%.*]] = select i1 [[TMP1812]], i16 [[TMP1810]], i16 [[TMP1811]]
-// CHECK-NEXT: store i16 [[TMP1813]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1814:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1815:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1814]] seq_cst, align 2
-// CHECK-NEXT: [[TMP1816:%.*]] = icmp ult i16 [[TMP1815]], [[TMP1814]]
-// CHECK-NEXT: [[TMP1817:%.*]] = select i1 [[TMP1816]], i16 [[TMP1814]], i16 [[TMP1815]]
-// CHECK-NEXT: store i16 [[TMP1817]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1818:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1819:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1818]] seq_cst, align 2
-// CHECK-NEXT: [[TMP1820:%.*]] = icmp ult i16 [[TMP1819]], [[TMP1818]]
-// CHECK-NEXT: [[TMP1821:%.*]] = select i1 [[TMP1820]], i16 [[TMP1818]], i16 [[TMP1819]]
-// CHECK-NEXT: store i16 [[TMP1821]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1822:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1823:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1822]] seq_cst, align 2
-// CHECK-NEXT: [[TMP1824:%.*]] = icmp ugt i16 [[TMP1823]], [[TMP1822]]
-// CHECK-NEXT: [[TMP1825:%.*]] = select i1 [[TMP1824]], i16 [[TMP1822]], i16 [[TMP1823]]
-// CHECK-NEXT: store i16 [[TMP1825]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1826:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1827:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1828:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1826]], i16 [[TMP1827]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1829:%.*]] = extractvalue { i16, i1 } [[TMP1828]], 0
-// CHECK-NEXT: [[TMP1830:%.*]] = extractvalue { i16, i1 } [[TMP1828]], 1
-// CHECK-NEXT: [[TMP1831:%.*]] = select i1 [[TMP1830]], i16 [[TMP1826]], i16 [[TMP1829]]
-// CHECK-NEXT: store i16 [[TMP1831]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1832:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1833:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1834:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1832]], i16 [[TMP1833]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1835:%.*]] = extractvalue { i16, i1 } [[TMP1834]], 0
-// CHECK-NEXT: [[TMP1836:%.*]] = extractvalue { i16, i1 } [[TMP1834]], 1
-// CHECK-NEXT: [[TMP1837:%.*]] = select i1 [[TMP1836]], i16 [[TMP1832]], i16 [[TMP1835]]
-// CHECK-NEXT: store i16 [[TMP1837]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1838:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1839:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1840:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1838]], i16 [[TMP1839]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1841:%.*]] = extractvalue { i16, i1 } [[TMP1840]], 0
-// CHECK-NEXT: [[TMP1842:%.*]] = extractvalue { i16, i1 } [[TMP1840]], 1
-// CHECK-NEXT: br i1 [[TMP1842]], label [[USX_ATOMIC_EXIT177:%.*]], label [[USX_ATOMIC_CONT178:%.*]]
-// CHECK: usx.atomic.cont178:
-// CHECK-NEXT: store i16 [[TMP1841]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT177]]
-// CHECK: usx.atomic.exit177:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1843:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1844:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1845:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1843]], i16 [[TMP1844]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1846:%.*]] = extractvalue { i16, i1 } [[TMP1845]], 0
-// CHECK-NEXT: [[TMP1847:%.*]] = extractvalue { i16, i1 } [[TMP1845]], 1
-// CHECK-NEXT: br i1 [[TMP1847]], label [[USX_ATOMIC_EXIT179:%.*]], label [[USX_ATOMIC_CONT180:%.*]]
-// CHECK: usx.atomic.cont180:
-// CHECK-NEXT: store i16 [[TMP1846]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT179]]
-// CHECK: usx.atomic.exit179:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1848:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1849:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1850:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1848]], i16 [[TMP1849]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1851:%.*]] = extractvalue { i16, i1 } [[TMP1850]], 1
-// CHECK-NEXT: [[TMP1852:%.*]] = zext i1 [[TMP1851]] to i16
-// CHECK-NEXT: store i16 [[TMP1852]], ptr [[USR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1853:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1854:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1855:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1853]], i16 [[TMP1854]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1856:%.*]] = extractvalue { i16, i1 } [[TMP1855]], 1
-// CHECK-NEXT: [[TMP1857:%.*]] = zext i1 [[TMP1856]] to i16
-// CHECK-NEXT: store i16 [[TMP1857]], ptr [[USR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1858:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1859:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1860:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1858]], i16 [[TMP1859]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1861:%.*]] = extractvalue { i16, i1 } [[TMP1860]], 0
-// CHECK-NEXT: [[TMP1862:%.*]] = extractvalue { i16, i1 } [[TMP1860]], 1
-// CHECK-NEXT: br i1 [[TMP1862]], label [[USX_ATOMIC_EXIT181:%.*]], label [[USX_ATOMIC_CONT182:%.*]]
-// CHECK: usx.atomic.cont182:
-// CHECK-NEXT: store i16 [[TMP1861]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT181]]
-// CHECK: usx.atomic.exit181:
-// CHECK-NEXT: [[TMP1863:%.*]] = extractvalue { i16, i1 } [[TMP1860]], 1
-// CHECK-NEXT: [[TMP1864:%.*]] = zext i1 [[TMP1863]] to i16
-// CHECK-NEXT: store i16 [[TMP1864]], ptr [[USR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1865:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP1866:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP1867:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP1865]], i16 [[TMP1866]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP1868:%.*]] = extractvalue { i16, i1 } [[TMP1867]], 0
-// CHECK-NEXT: [[TMP1869:%.*]] = extractvalue { i16, i1 } [[TMP1867]], 1
-// CHECK-NEXT: br i1 [[TMP1869]], label [[USX_ATOMIC_EXIT183:%.*]], label [[USX_ATOMIC_CONT184:%.*]]
-// CHECK: usx.atomic.cont184:
-// CHECK-NEXT: store i16 [[TMP1868]], ptr [[USV]], align 2
-// CHECK-NEXT: br label [[USX_ATOMIC_EXIT183]]
-// CHECK: usx.atomic.exit183:
-// CHECK-NEXT: [[TMP1870:%.*]] = extractvalue { i16, i1 } [[TMP1867]], 1
-// CHECK-NEXT: [[TMP1871:%.*]] = zext i1 [[TMP1870]] to i16
-// CHECK-NEXT: store i16 [[TMP1871]], ptr [[USR]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1872:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1873:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1872]] monotonic, align 4
-// CHECK-NEXT: store i32 [[TMP1873]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP1874:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1875:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1874]] monotonic, align 4
-// CHECK-NEXT: store i32 [[TMP1875]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP1876:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1877:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1876]] monotonic, align 4
-// CHECK-NEXT: store i32 [[TMP1877]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP1878:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1879:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1878]] monotonic, align 4
-// CHECK-NEXT: store i32 [[TMP1879]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP1880:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1881:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP1882:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1880]], i32 [[TMP1881]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP1883:%.*]] = extractvalue { i32, i1 } [[TMP1882]], 0
-// CHECK-NEXT: store i32 [[TMP1883]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP1884:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1885:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP1886:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1884]], i32 [[TMP1885]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP1887:%.*]] = extractvalue { i32, i1 } [[TMP1886]], 0
-// CHECK-NEXT: store i32 [[TMP1887]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP1888:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1889:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1888]] monotonic, align 4
-// CHECK-NEXT: [[TMP1890:%.*]] = icmp sgt i32 [[TMP1889]], [[TMP1888]]
-// CHECK-NEXT: [[TMP1891:%.*]] = select i1 [[TMP1890]], i32 [[TMP1888]], i32 [[TMP1889]]
-// CHECK-NEXT: store i32 [[TMP1891]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP1892:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1893:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1892]] monotonic, align 4
-// CHECK-NEXT: [[TMP1894:%.*]] = icmp slt i32 [[TMP1893]], [[TMP1892]]
-// CHECK-NEXT: [[TMP1895:%.*]] = select i1 [[TMP1894]], i32 [[TMP1892]], i32 [[TMP1893]]
-// CHECK-NEXT: store i32 [[TMP1895]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP1896:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1897:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1896]] monotonic, align 4
-// CHECK-NEXT: [[TMP1898:%.*]] = icmp slt i32 [[TMP1897]], [[TMP1896]]
-// CHECK-NEXT: [[TMP1899:%.*]] = select i1 [[TMP1898]], i32 [[TMP1896]], i32 [[TMP1897]]
-// CHECK-NEXT: store i32 [[TMP1899]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP1900:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1901:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1900]] monotonic, align 4
-// CHECK-NEXT: [[TMP1902:%.*]] = icmp sgt i32 [[TMP1901]], [[TMP1900]]
-// CHECK-NEXT: [[TMP1903:%.*]] = select i1 [[TMP1902]], i32 [[TMP1900]], i32 [[TMP1901]]
-// CHECK-NEXT: store i32 [[TMP1903]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP1904:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1905:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP1906:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1904]], i32 [[TMP1905]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP1907:%.*]] = extractvalue { i32, i1 } [[TMP1906]], 0
-// CHECK-NEXT: [[TMP1908:%.*]] = extractvalue { i32, i1 } [[TMP1906]], 1
-// CHECK-NEXT: [[TMP1909:%.*]] = select i1 [[TMP1908]], i32 [[TMP1904]], i32 [[TMP1907]]
-// CHECK-NEXT: store i32 [[TMP1909]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP1910:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1911:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP1912:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1910]], i32 [[TMP1911]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP1913:%.*]] = extractvalue { i32, i1 } [[TMP1912]], 0
-// CHECK-NEXT: [[TMP1914:%.*]] = extractvalue { i32, i1 } [[TMP1912]], 1
-// CHECK-NEXT: [[TMP1915:%.*]] = select i1 [[TMP1914]], i32 [[TMP1910]], i32 [[TMP1913]]
-// CHECK-NEXT: store i32 [[TMP1915]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP1916:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1917:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP1918:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1916]], i32 [[TMP1917]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP1919:%.*]] = extractvalue { i32, i1 } [[TMP1918]], 0
-// CHECK-NEXT: [[TMP1920:%.*]] = extractvalue { i32, i1 } [[TMP1918]], 1
-// CHECK-NEXT: br i1 [[TMP1920]], label [[IX_ATOMIC_EXIT:%.*]], label [[IX_ATOMIC_CONT:%.*]]
+// CHECK-NEXT: [[TMP898:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP899:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP898]], ptr [[USX_ATOMIC_EXPECTED_PTR1770]], align 2
+// CHECK-NEXT: store i16 [[TMP899]], ptr [[USX_ATOMIC_DESIRED_PTR1771]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1773:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1770]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1774:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1771]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1775:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1773]], i16 [[USX_CMPXCHG_DESIRED1774]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1776:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1775]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1776]], ptr [[USX_ATOMIC_EXPECTED_PTR1772]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1777:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1775]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1778:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1772]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS1777]], label [[USX_ATOMIC_EXIT1779:%.*]], label [[USX_ATOMIC_CONT1780:%.*]]
+// CHECK: usx.atomic.cont1780:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL1778]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT1779]]
+// CHECK: usx.atomic.exit1779:
+// CHECK-NEXT: [[TMP900:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP901:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP900]], ptr [[USX_ATOMIC_EXPECTED_PTR1781]], align 2
+// CHECK-NEXT: store i16 [[TMP901]], ptr [[USX_ATOMIC_DESIRED_PTR1782]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1784:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1781]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1785:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1782]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1786:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1784]], i16 [[USX_CMPXCHG_DESIRED1785]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1787:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1786]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1787]], ptr [[USX_ATOMIC_EXPECTED_PTR1783]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1788:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1786]], 1
+// CHECK-NEXT: [[TMP902:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS1788]] to i16
+// CHECK-NEXT: store i16 [[TMP902]], ptr [[USR]], align 2
+// CHECK-NEXT: [[TMP903:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP904:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP903]], ptr [[USX_ATOMIC_EXPECTED_PTR1789]], align 2
+// CHECK-NEXT: store i16 [[TMP904]], ptr [[USX_ATOMIC_DESIRED_PTR1790]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1792:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1789]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1793:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1790]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1794:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1792]], i16 [[USX_CMPXCHG_DESIRED1793]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1795:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1794]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1795]], ptr [[USX_ATOMIC_EXPECTED_PTR1791]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1796:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1794]], 1
+// CHECK-NEXT: [[TMP905:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS1796]] to i16
+// CHECK-NEXT: store i16 [[TMP905]], ptr [[USR]], align 2
+// CHECK-NEXT: [[TMP906:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP907:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP906]], ptr [[USX_ATOMIC_EXPECTED_PTR1797]], align 2
+// CHECK-NEXT: store i16 [[TMP907]], ptr [[USX_ATOMIC_DESIRED_PTR1798]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1800:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1797]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1801:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1798]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1802:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1800]], i16 [[USX_CMPXCHG_DESIRED1801]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1803:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1802]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1803]], ptr [[USX_ATOMIC_EXPECTED_PTR1799]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1804:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1802]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1805:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1799]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS1804]], label [[USX_ATOMIC_EXIT1806:%.*]], label [[USX_ATOMIC_CONT1807:%.*]]
+// CHECK: usx.atomic.cont1807:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL1805]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT1806]]
+// CHECK: usx.atomic.exit1806:
+// CHECK-NEXT: [[TMP908:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS1804]] to i16
+// CHECK-NEXT: store i16 [[TMP908]], ptr [[USR]], align 2
+// CHECK-NEXT: [[TMP909:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP910:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP909]], ptr [[USX_ATOMIC_EXPECTED_PTR1808]], align 2
+// CHECK-NEXT: store i16 [[TMP910]], ptr [[USX_ATOMIC_DESIRED_PTR1809]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1811:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1808]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1812:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1809]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1813:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1811]], i16 [[USX_CMPXCHG_DESIRED1812]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1814:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1813]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1814]], ptr [[USX_ATOMIC_EXPECTED_PTR1810]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1815:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1813]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1816:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1810]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS1815]], label [[USX_ATOMIC_EXIT1817:%.*]], label [[USX_ATOMIC_CONT1818:%.*]]
+// CHECK: usx.atomic.cont1818:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL1816]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT1817]]
+// CHECK: usx.atomic.exit1817:
+// CHECK-NEXT: [[TMP911:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS1815]] to i16
+// CHECK-NEXT: store i16 [[TMP911]], ptr [[USR]], align 2
+// CHECK-NEXT: [[TMP912:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP913:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP912]] acq_rel, align 2
+// CHECK-NEXT: store i16 [[TMP913]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP914:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP915:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP914]] acq_rel, align 2
+// CHECK-NEXT: store i16 [[TMP915]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP916:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP917:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP916]] acq_rel, align 2
+// CHECK-NEXT: store i16 [[TMP917]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP918:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP919:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP918]] acq_rel, align 2
+// CHECK-NEXT: store i16 [[TMP919]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP920:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP921:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP920]], ptr [[USX_ATOMIC_EXPECTED_PTR1819]], align 2
+// CHECK-NEXT: store i16 [[TMP921]], ptr [[USX_ATOMIC_DESIRED_PTR1820]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1822:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1819]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1823:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1820]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1824:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1822]], i16 [[USX_CMPXCHG_DESIRED1823]] acq_rel acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1825:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1824]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1825]], ptr [[USX_ATOMIC_EXPECTED_PTR1821]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1826:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1824]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1827:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1821]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL1827]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP922:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP923:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP922]], ptr [[USX_ATOMIC_EXPECTED_PTR1828]], align 2
+// CHECK-NEXT: store i16 [[TMP923]], ptr [[USX_ATOMIC_DESIRED_PTR1829]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1831:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1828]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1832:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1829]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1833:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1831]], i16 [[USX_CMPXCHG_DESIRED1832]] acq_rel acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1834:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1833]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1834]], ptr [[USX_ATOMIC_EXPECTED_PTR1830]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1835:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1833]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1836:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1830]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL1836]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP924:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP925:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP924]] acq_rel, align 2
+// CHECK-NEXT: [[TMP926:%.*]] = icmp ugt i16 [[TMP925]], [[TMP924]]
+// CHECK-NEXT: [[TMP927:%.*]] = select i1 [[TMP926]], i16 [[TMP924]], i16 [[TMP925]]
+// CHECK-NEXT: store i16 [[TMP927]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP928:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP929:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP928]] acq_rel, align 2
+// CHECK-NEXT: [[TMP930:%.*]] = icmp ult i16 [[TMP929]], [[TMP928]]
+// CHECK-NEXT: [[TMP931:%.*]] = select i1 [[TMP930]], i16 [[TMP928]], i16 [[TMP929]]
+// CHECK-NEXT: store i16 [[TMP931]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP932:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP933:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP932]] acq_rel, align 2
+// CHECK-NEXT: [[TMP934:%.*]] = icmp ult i16 [[TMP933]], [[TMP932]]
+// CHECK-NEXT: [[TMP935:%.*]] = select i1 [[TMP934]], i16 [[TMP932]], i16 [[TMP933]]
+// CHECK-NEXT: store i16 [[TMP935]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP936:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP937:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP936]] acq_rel, align 2
+// CHECK-NEXT: [[TMP938:%.*]] = icmp ugt i16 [[TMP937]], [[TMP936]]
+// CHECK-NEXT: [[TMP939:%.*]] = select i1 [[TMP938]], i16 [[TMP936]], i16 [[TMP937]]
+// CHECK-NEXT: store i16 [[TMP939]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP940:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP941:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP940]], ptr [[USX_ATOMIC_EXPECTED_PTR1837]], align 2
+// CHECK-NEXT: store i16 [[TMP941]], ptr [[USX_ATOMIC_DESIRED_PTR1838]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1840:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1837]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1841:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1838]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1842:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1840]], i16 [[USX_CMPXCHG_DESIRED1841]] acq_rel acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1843:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1842]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1843]], ptr [[USX_ATOMIC_EXPECTED_PTR1839]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1844:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1842]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1845:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1839]], align 2
+// CHECK-NEXT: [[USX_CAPTURE_CAPTURED1846:%.*]] = select i1 [[USX_CMPXCHG_SUCCESS1844]], i16 [[TMP940]], i16 [[USX_CAPTURE_ACTUAL1845]]
+// CHECK-NEXT: store i16 [[USX_CAPTURE_CAPTURED1846]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP942:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP943:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP942]], ptr [[USX_ATOMIC_EXPECTED_PTR1847]], align 2
+// CHECK-NEXT: store i16 [[TMP943]], ptr [[USX_ATOMIC_DESIRED_PTR1848]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1850:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1847]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1851:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1848]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1852:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1850]], i16 [[USX_CMPXCHG_DESIRED1851]] acq_rel acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1853:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1852]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1853]], ptr [[USX_ATOMIC_EXPECTED_PTR1849]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1854:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1852]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1855:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1849]], align 2
+// CHECK-NEXT: [[USX_CAPTURE_CAPTURED1856:%.*]] = select i1 [[USX_CMPXCHG_SUCCESS1854]], i16 [[TMP942]], i16 [[USX_CAPTURE_ACTUAL1855]]
+// CHECK-NEXT: store i16 [[USX_CAPTURE_CAPTURED1856]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP944:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP945:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP944]], ptr [[USX_ATOMIC_EXPECTED_PTR1857]], align 2
+// CHECK-NEXT: store i16 [[TMP945]], ptr [[USX_ATOMIC_DESIRED_PTR1858]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1860:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1857]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1861:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1858]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1862:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1860]], i16 [[USX_CMPXCHG_DESIRED1861]] acq_rel acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1863:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1862]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1863]], ptr [[USX_ATOMIC_EXPECTED_PTR1859]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1864:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1862]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1865:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1859]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS1864]], label [[USX_ATOMIC_EXIT1866:%.*]], label [[USX_ATOMIC_CONT1867:%.*]]
+// CHECK: usx.atomic.cont1867:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL1865]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT1866]]
+// CHECK: usx.atomic.exit1866:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP946:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP947:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP946]], ptr [[USX_ATOMIC_EXPECTED_PTR1868]], align 2
+// CHECK-NEXT: store i16 [[TMP947]], ptr [[USX_ATOMIC_DESIRED_PTR1869]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1871:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1868]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1872:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1869]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1873:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1871]], i16 [[USX_CMPXCHG_DESIRED1872]] acq_rel acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1874:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1873]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1874]], ptr [[USX_ATOMIC_EXPECTED_PTR1870]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1875:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1873]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1876:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1870]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS1875]], label [[USX_ATOMIC_EXIT1877:%.*]], label [[USX_ATOMIC_CONT1878:%.*]]
+// CHECK: usx.atomic.cont1878:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL1876]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT1877]]
+// CHECK: usx.atomic.exit1877:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP948:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP949:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP948]], ptr [[USX_ATOMIC_EXPECTED_PTR1879]], align 2
+// CHECK-NEXT: store i16 [[TMP949]], ptr [[USX_ATOMIC_DESIRED_PTR1880]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1882:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1879]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1883:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1880]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1884:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1882]], i16 [[USX_CMPXCHG_DESIRED1883]] acq_rel acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1885:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1884]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1885]], ptr [[USX_ATOMIC_EXPECTED_PTR1881]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1886:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1884]], 1
+// CHECK-NEXT: [[TMP950:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS1886]] to i16
+// CHECK-NEXT: store i16 [[TMP950]], ptr [[USR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP951:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP952:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP951]], ptr [[USX_ATOMIC_EXPECTED_PTR1887]], align 2
+// CHECK-NEXT: store i16 [[TMP952]], ptr [[USX_ATOMIC_DESIRED_PTR1888]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1890:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1887]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1891:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1888]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1892:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1890]], i16 [[USX_CMPXCHG_DESIRED1891]] acq_rel acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1893:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1892]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1893]], ptr [[USX_ATOMIC_EXPECTED_PTR1889]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1894:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1892]], 1
+// CHECK-NEXT: [[TMP953:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS1894]] to i16
+// CHECK-NEXT: store i16 [[TMP953]], ptr [[USR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP954:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP955:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP954]], ptr [[USX_ATOMIC_EXPECTED_PTR1895]], align 2
+// CHECK-NEXT: store i16 [[TMP955]], ptr [[USX_ATOMIC_DESIRED_PTR1896]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1898:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1895]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1899:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1896]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1900:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1898]], i16 [[USX_CMPXCHG_DESIRED1899]] acq_rel acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1901:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1900]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1901]], ptr [[USX_ATOMIC_EXPECTED_PTR1897]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1902:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1900]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1903:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1897]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS1902]], label [[USX_ATOMIC_EXIT1904:%.*]], label [[USX_ATOMIC_CONT1905:%.*]]
+// CHECK: usx.atomic.cont1905:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL1903]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT1904]]
+// CHECK: usx.atomic.exit1904:
+// CHECK-NEXT: [[TMP956:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS1902]] to i16
+// CHECK-NEXT: store i16 [[TMP956]], ptr [[USR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP957:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP958:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP957]], ptr [[USX_ATOMIC_EXPECTED_PTR1906]], align 2
+// CHECK-NEXT: store i16 [[TMP958]], ptr [[USX_ATOMIC_DESIRED_PTR1907]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1909:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1906]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1910:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1907]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1911:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1909]], i16 [[USX_CMPXCHG_DESIRED1910]] acq_rel acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1912:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1911]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1912]], ptr [[USX_ATOMIC_EXPECTED_PTR1908]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1913:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1911]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1914:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1908]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS1913]], label [[USX_ATOMIC_EXIT1915:%.*]], label [[USX_ATOMIC_CONT1916:%.*]]
+// CHECK: usx.atomic.cont1916:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL1914]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT1915]]
+// CHECK: usx.atomic.exit1915:
+// CHECK-NEXT: [[TMP959:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS1913]] to i16
+// CHECK-NEXT: store i16 [[TMP959]], ptr [[USR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP960:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP961:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP960]] acquire, align 2
+// CHECK-NEXT: store i16 [[TMP961]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP962:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP963:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP962]] acquire, align 2
+// CHECK-NEXT: store i16 [[TMP963]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP964:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP965:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP964]] acquire, align 2
+// CHECK-NEXT: store i16 [[TMP965]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP966:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP967:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP966]] acquire, align 2
+// CHECK-NEXT: store i16 [[TMP967]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP968:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP969:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP968]], ptr [[USX_ATOMIC_EXPECTED_PTR1917]], align 2
+// CHECK-NEXT: store i16 [[TMP969]], ptr [[USX_ATOMIC_DESIRED_PTR1918]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1920:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1917]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1921:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1918]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1922:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1920]], i16 [[USX_CMPXCHG_DESIRED1921]] acquire acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1923:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1922]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1923]], ptr [[USX_ATOMIC_EXPECTED_PTR1919]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1924:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1922]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1925:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1919]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL1925]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP970:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP971:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP970]], ptr [[USX_ATOMIC_EXPECTED_PTR1926]], align 2
+// CHECK-NEXT: store i16 [[TMP971]], ptr [[USX_ATOMIC_DESIRED_PTR1927]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1929:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1926]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1930:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1927]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1931:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1929]], i16 [[USX_CMPXCHG_DESIRED1930]] acquire acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1932:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1931]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1932]], ptr [[USX_ATOMIC_EXPECTED_PTR1928]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1933:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1931]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1934:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1928]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL1934]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP972:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP973:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP972]] acquire, align 2
+// CHECK-NEXT: [[TMP974:%.*]] = icmp ugt i16 [[TMP973]], [[TMP972]]
+// CHECK-NEXT: [[TMP975:%.*]] = select i1 [[TMP974]], i16 [[TMP972]], i16 [[TMP973]]
+// CHECK-NEXT: store i16 [[TMP975]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP976:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP977:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP976]] acquire, align 2
+// CHECK-NEXT: [[TMP978:%.*]] = icmp ult i16 [[TMP977]], [[TMP976]]
+// CHECK-NEXT: [[TMP979:%.*]] = select i1 [[TMP978]], i16 [[TMP976]], i16 [[TMP977]]
+// CHECK-NEXT: store i16 [[TMP979]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP980:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP981:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP980]] acquire, align 2
+// CHECK-NEXT: [[TMP982:%.*]] = icmp ult i16 [[TMP981]], [[TMP980]]
+// CHECK-NEXT: [[TMP983:%.*]] = select i1 [[TMP982]], i16 [[TMP980]], i16 [[TMP981]]
+// CHECK-NEXT: store i16 [[TMP983]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP984:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP985:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP984]] acquire, align 2
+// CHECK-NEXT: [[TMP986:%.*]] = icmp ugt i16 [[TMP985]], [[TMP984]]
+// CHECK-NEXT: [[TMP987:%.*]] = select i1 [[TMP986]], i16 [[TMP984]], i16 [[TMP985]]
+// CHECK-NEXT: store i16 [[TMP987]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP988:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP989:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP988]], ptr [[USX_ATOMIC_EXPECTED_PTR1935]], align 2
+// CHECK-NEXT: store i16 [[TMP989]], ptr [[USX_ATOMIC_DESIRED_PTR1936]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1938:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1935]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1939:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1936]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1940:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1938]], i16 [[USX_CMPXCHG_DESIRED1939]] acquire acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1941:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1940]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1941]], ptr [[USX_ATOMIC_EXPECTED_PTR1937]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1942:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1940]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1943:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1937]], align 2
+// CHECK-NEXT: [[USX_CAPTURE_CAPTURED1944:%.*]] = select i1 [[USX_CMPXCHG_SUCCESS1942]], i16 [[TMP988]], i16 [[USX_CAPTURE_ACTUAL1943]]
+// CHECK-NEXT: store i16 [[USX_CAPTURE_CAPTURED1944]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP990:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP991:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP990]], ptr [[USX_ATOMIC_EXPECTED_PTR1945]], align 2
+// CHECK-NEXT: store i16 [[TMP991]], ptr [[USX_ATOMIC_DESIRED_PTR1946]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1948:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1945]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1949:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1946]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1950:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1948]], i16 [[USX_CMPXCHG_DESIRED1949]] acquire acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1951:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1950]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1951]], ptr [[USX_ATOMIC_EXPECTED_PTR1947]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1952:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1950]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1953:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1947]], align 2
+// CHECK-NEXT: [[USX_CAPTURE_CAPTURED1954:%.*]] = select i1 [[USX_CMPXCHG_SUCCESS1952]], i16 [[TMP990]], i16 [[USX_CAPTURE_ACTUAL1953]]
+// CHECK-NEXT: store i16 [[USX_CAPTURE_CAPTURED1954]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP992:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP993:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP992]], ptr [[USX_ATOMIC_EXPECTED_PTR1955]], align 2
+// CHECK-NEXT: store i16 [[TMP993]], ptr [[USX_ATOMIC_DESIRED_PTR1956]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1958:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1955]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1959:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1956]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1960:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1958]], i16 [[USX_CMPXCHG_DESIRED1959]] acquire acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1961:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1960]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1961]], ptr [[USX_ATOMIC_EXPECTED_PTR1957]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1962:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1960]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1963:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1957]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS1962]], label [[USX_ATOMIC_EXIT1964:%.*]], label [[USX_ATOMIC_CONT1965:%.*]]
+// CHECK: usx.atomic.cont1965:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL1963]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT1964]]
+// CHECK: usx.atomic.exit1964:
+// CHECK-NEXT: [[TMP994:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP995:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP994]], ptr [[USX_ATOMIC_EXPECTED_PTR1966]], align 2
+// CHECK-NEXT: store i16 [[TMP995]], ptr [[USX_ATOMIC_DESIRED_PTR1967]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1969:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1966]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1970:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1967]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1971:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1969]], i16 [[USX_CMPXCHG_DESIRED1970]] acquire acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1972:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1971]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1972]], ptr [[USX_ATOMIC_EXPECTED_PTR1968]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1973:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1971]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL1974:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1968]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS1973]], label [[USX_ATOMIC_EXIT1975:%.*]], label [[USX_ATOMIC_CONT1976:%.*]]
+// CHECK: usx.atomic.cont1976:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL1974]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT1975]]
+// CHECK: usx.atomic.exit1975:
+// CHECK-NEXT: [[TMP996:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP997:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP996]], ptr [[USX_ATOMIC_EXPECTED_PTR1977]], align 2
+// CHECK-NEXT: store i16 [[TMP997]], ptr [[USX_ATOMIC_DESIRED_PTR1978]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1980:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1977]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1981:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1978]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1982:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1980]], i16 [[USX_CMPXCHG_DESIRED1981]] acquire acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1983:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1982]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1983]], ptr [[USX_ATOMIC_EXPECTED_PTR1979]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1984:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1982]], 1
+// CHECK-NEXT: [[TMP998:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS1984]] to i16
+// CHECK-NEXT: store i16 [[TMP998]], ptr [[USR]], align 2
+// CHECK-NEXT: [[TMP999:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1000:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP999]], ptr [[USX_ATOMIC_EXPECTED_PTR1985]], align 2
+// CHECK-NEXT: store i16 [[TMP1000]], ptr [[USX_ATOMIC_DESIRED_PTR1986]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1988:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1985]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1989:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1986]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1990:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1988]], i16 [[USX_CMPXCHG_DESIRED1989]] acquire acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1991:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1990]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1991]], ptr [[USX_ATOMIC_EXPECTED_PTR1987]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS1992:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1990]], 1
+// CHECK-NEXT: [[TMP1001:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS1992]] to i16
+// CHECK-NEXT: store i16 [[TMP1001]], ptr [[USR]], align 2
+// CHECK-NEXT: [[TMP1002:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1003:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1002]], ptr [[USX_ATOMIC_EXPECTED_PTR1993]], align 2
+// CHECK-NEXT: store i16 [[TMP1003]], ptr [[USX_ATOMIC_DESIRED_PTR1994]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED1996:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1993]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED1997:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR1994]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR1998:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED1996]], i16 [[USX_CMPXCHG_DESIRED1997]] acquire acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV1999:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1998]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV1999]], ptr [[USX_ATOMIC_EXPECTED_PTR1995]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2000:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR1998]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2001:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1995]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS2000]], label [[USX_ATOMIC_EXIT2002:%.*]], label [[USX_ATOMIC_CONT2003:%.*]]
+// CHECK: usx.atomic.cont2003:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2001]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT2002]]
+// CHECK: usx.atomic.exit2002:
+// CHECK-NEXT: [[TMP1004:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS2000]] to i16
+// CHECK-NEXT: store i16 [[TMP1004]], ptr [[USR]], align 2
+// CHECK-NEXT: [[TMP1005:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1006:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1005]], ptr [[USX_ATOMIC_EXPECTED_PTR2004]], align 2
+// CHECK-NEXT: store i16 [[TMP1006]], ptr [[USX_ATOMIC_DESIRED_PTR2005]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2007:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2004]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2008:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2005]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2009:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2007]], i16 [[USX_CMPXCHG_DESIRED2008]] acquire acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2010:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2009]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2010]], ptr [[USX_ATOMIC_EXPECTED_PTR2006]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2011:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2009]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2012:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2006]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS2011]], label [[USX_ATOMIC_EXIT2013:%.*]], label [[USX_ATOMIC_CONT2014:%.*]]
+// CHECK: usx.atomic.cont2014:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2012]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT2013]]
+// CHECK: usx.atomic.exit2013:
+// CHECK-NEXT: [[TMP1007:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS2011]] to i16
+// CHECK-NEXT: store i16 [[TMP1007]], ptr [[USR]], align 2
+// CHECK-NEXT: [[TMP1008:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1009:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1008]] monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP1009]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP1010:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1011:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1010]] monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP1011]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP1012:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1013:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1012]] monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP1013]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP1014:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1015:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1014]] monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP1015]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP1016:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1017:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1016]], ptr [[USX_ATOMIC_EXPECTED_PTR2015]], align 2
+// CHECK-NEXT: store i16 [[TMP1017]], ptr [[USX_ATOMIC_DESIRED_PTR2016]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2018:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2015]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2019:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2016]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2020:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2018]], i16 [[USX_CMPXCHG_DESIRED2019]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2021:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2020]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2021]], ptr [[USX_ATOMIC_EXPECTED_PTR2017]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2022:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2020]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2023:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2017]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2023]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP1018:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1019:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1018]], ptr [[USX_ATOMIC_EXPECTED_PTR2024]], align 2
+// CHECK-NEXT: store i16 [[TMP1019]], ptr [[USX_ATOMIC_DESIRED_PTR2025]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2027:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2024]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2028:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2025]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2029:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2027]], i16 [[USX_CMPXCHG_DESIRED2028]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2030:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2029]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2030]], ptr [[USX_ATOMIC_EXPECTED_PTR2026]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2031:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2029]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2032:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2026]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2032]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP1020:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1021:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1020]] monotonic, align 2
+// CHECK-NEXT: [[TMP1022:%.*]] = icmp ugt i16 [[TMP1021]], [[TMP1020]]
+// CHECK-NEXT: [[TMP1023:%.*]] = select i1 [[TMP1022]], i16 [[TMP1020]], i16 [[TMP1021]]
+// CHECK-NEXT: store i16 [[TMP1023]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP1024:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1025:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1024]] monotonic, align 2
+// CHECK-NEXT: [[TMP1026:%.*]] = icmp ult i16 [[TMP1025]], [[TMP1024]]
+// CHECK-NEXT: [[TMP1027:%.*]] = select i1 [[TMP1026]], i16 [[TMP1024]], i16 [[TMP1025]]
+// CHECK-NEXT: store i16 [[TMP1027]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP1028:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1029:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1028]] monotonic, align 2
+// CHECK-NEXT: [[TMP1030:%.*]] = icmp ult i16 [[TMP1029]], [[TMP1028]]
+// CHECK-NEXT: [[TMP1031:%.*]] = select i1 [[TMP1030]], i16 [[TMP1028]], i16 [[TMP1029]]
+// CHECK-NEXT: store i16 [[TMP1031]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP1032:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1033:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1032]] monotonic, align 2
+// CHECK-NEXT: [[TMP1034:%.*]] = icmp ugt i16 [[TMP1033]], [[TMP1032]]
+// CHECK-NEXT: [[TMP1035:%.*]] = select i1 [[TMP1034]], i16 [[TMP1032]], i16 [[TMP1033]]
+// CHECK-NEXT: store i16 [[TMP1035]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP1036:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1037:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1036]], ptr [[USX_ATOMIC_EXPECTED_PTR2033]], align 2
+// CHECK-NEXT: store i16 [[TMP1037]], ptr [[USX_ATOMIC_DESIRED_PTR2034]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2036:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2033]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2037:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2034]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2038:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2036]], i16 [[USX_CMPXCHG_DESIRED2037]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2039:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2038]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2039]], ptr [[USX_ATOMIC_EXPECTED_PTR2035]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2040:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2038]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2041:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2035]], align 2
+// CHECK-NEXT: [[USX_CAPTURE_CAPTURED2042:%.*]] = select i1 [[USX_CMPXCHG_SUCCESS2040]], i16 [[TMP1036]], i16 [[USX_CAPTURE_ACTUAL2041]]
+// CHECK-NEXT: store i16 [[USX_CAPTURE_CAPTURED2042]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP1038:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1039:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1038]], ptr [[USX_ATOMIC_EXPECTED_PTR2043]], align 2
+// CHECK-NEXT: store i16 [[TMP1039]], ptr [[USX_ATOMIC_DESIRED_PTR2044]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2046:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2043]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2047:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2044]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2048:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2046]], i16 [[USX_CMPXCHG_DESIRED2047]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2049:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2048]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2049]], ptr [[USX_ATOMIC_EXPECTED_PTR2045]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2050:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2048]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2051:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2045]], align 2
+// CHECK-NEXT: [[USX_CAPTURE_CAPTURED2052:%.*]] = select i1 [[USX_CMPXCHG_SUCCESS2050]], i16 [[TMP1038]], i16 [[USX_CAPTURE_ACTUAL2051]]
+// CHECK-NEXT: store i16 [[USX_CAPTURE_CAPTURED2052]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP1040:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1041:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1040]], ptr [[USX_ATOMIC_EXPECTED_PTR2053]], align 2
+// CHECK-NEXT: store i16 [[TMP1041]], ptr [[USX_ATOMIC_DESIRED_PTR2054]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2056:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2053]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2057:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2054]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2058:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2056]], i16 [[USX_CMPXCHG_DESIRED2057]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2059:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2058]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2059]], ptr [[USX_ATOMIC_EXPECTED_PTR2055]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2060:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2058]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2061:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2055]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS2060]], label [[USX_ATOMIC_EXIT2062:%.*]], label [[USX_ATOMIC_CONT2063:%.*]]
+// CHECK: usx.atomic.cont2063:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2061]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT2062]]
+// CHECK: usx.atomic.exit2062:
+// CHECK-NEXT: [[TMP1042:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1043:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1042]], ptr [[USX_ATOMIC_EXPECTED_PTR2064]], align 2
+// CHECK-NEXT: store i16 [[TMP1043]], ptr [[USX_ATOMIC_DESIRED_PTR2065]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2067:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2064]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2068:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2065]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2069:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2067]], i16 [[USX_CMPXCHG_DESIRED2068]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2070:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2069]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2070]], ptr [[USX_ATOMIC_EXPECTED_PTR2066]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2071:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2069]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2072:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2066]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS2071]], label [[USX_ATOMIC_EXIT2073:%.*]], label [[USX_ATOMIC_CONT2074:%.*]]
+// CHECK: usx.atomic.cont2074:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2072]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT2073]]
+// CHECK: usx.atomic.exit2073:
+// CHECK-NEXT: [[TMP1044:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1045:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1044]], ptr [[USX_ATOMIC_EXPECTED_PTR2075]], align 2
+// CHECK-NEXT: store i16 [[TMP1045]], ptr [[USX_ATOMIC_DESIRED_PTR2076]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2078:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2075]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2079:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2076]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2080:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2078]], i16 [[USX_CMPXCHG_DESIRED2079]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2081:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2080]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2081]], ptr [[USX_ATOMIC_EXPECTED_PTR2077]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2082:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2080]], 1
+// CHECK-NEXT: [[TMP1046:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS2082]] to i16
+// CHECK-NEXT: store i16 [[TMP1046]], ptr [[USR]], align 2
+// CHECK-NEXT: [[TMP1047:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1048:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1047]], ptr [[USX_ATOMIC_EXPECTED_PTR2083]], align 2
+// CHECK-NEXT: store i16 [[TMP1048]], ptr [[USX_ATOMIC_DESIRED_PTR2084]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2086:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2083]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2087:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2084]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2088:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2086]], i16 [[USX_CMPXCHG_DESIRED2087]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2089:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2088]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2089]], ptr [[USX_ATOMIC_EXPECTED_PTR2085]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2090:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2088]], 1
+// CHECK-NEXT: [[TMP1049:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS2090]] to i16
+// CHECK-NEXT: store i16 [[TMP1049]], ptr [[USR]], align 2
+// CHECK-NEXT: [[TMP1050:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1051:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1050]], ptr [[USX_ATOMIC_EXPECTED_PTR2091]], align 2
+// CHECK-NEXT: store i16 [[TMP1051]], ptr [[USX_ATOMIC_DESIRED_PTR2092]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2094:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2091]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2095:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2092]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2096:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2094]], i16 [[USX_CMPXCHG_DESIRED2095]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2097:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2096]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2097]], ptr [[USX_ATOMIC_EXPECTED_PTR2093]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2098:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2096]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2099:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2093]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS2098]], label [[USX_ATOMIC_EXIT2100:%.*]], label [[USX_ATOMIC_CONT2101:%.*]]
+// CHECK: usx.atomic.cont2101:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2099]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT2100]]
+// CHECK: usx.atomic.exit2100:
+// CHECK-NEXT: [[TMP1052:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS2098]] to i16
+// CHECK-NEXT: store i16 [[TMP1052]], ptr [[USR]], align 2
+// CHECK-NEXT: [[TMP1053:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1054:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1053]], ptr [[USX_ATOMIC_EXPECTED_PTR2102]], align 2
+// CHECK-NEXT: store i16 [[TMP1054]], ptr [[USX_ATOMIC_DESIRED_PTR2103]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2105:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2102]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2106:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2103]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2107:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2105]], i16 [[USX_CMPXCHG_DESIRED2106]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2108:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2107]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2108]], ptr [[USX_ATOMIC_EXPECTED_PTR2104]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2109:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2107]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2110:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2104]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS2109]], label [[USX_ATOMIC_EXIT2111:%.*]], label [[USX_ATOMIC_CONT2112:%.*]]
+// CHECK: usx.atomic.cont2112:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2110]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT2111]]
+// CHECK: usx.atomic.exit2111:
+// CHECK-NEXT: [[TMP1055:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS2109]] to i16
+// CHECK-NEXT: store i16 [[TMP1055]], ptr [[USR]], align 2
+// CHECK-NEXT: [[TMP1056:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1057:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1056]] release, align 2
+// CHECK-NEXT: store i16 [[TMP1057]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1058:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1059:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1058]] release, align 2
+// CHECK-NEXT: store i16 [[TMP1059]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1060:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1061:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1060]] release, align 2
+// CHECK-NEXT: store i16 [[TMP1061]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1062:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1063:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1062]] release, align 2
+// CHECK-NEXT: store i16 [[TMP1063]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1064:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1065:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1064]], ptr [[USX_ATOMIC_EXPECTED_PTR2113]], align 2
+// CHECK-NEXT: store i16 [[TMP1065]], ptr [[USX_ATOMIC_DESIRED_PTR2114]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2116:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2113]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2117:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2114]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2118:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2116]], i16 [[USX_CMPXCHG_DESIRED2117]] release monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2119:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2118]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2119]], ptr [[USX_ATOMIC_EXPECTED_PTR2115]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2120:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2118]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2121:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2115]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2121]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1066:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1067:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1066]], ptr [[USX_ATOMIC_EXPECTED_PTR2122]], align 2
+// CHECK-NEXT: store i16 [[TMP1067]], ptr [[USX_ATOMIC_DESIRED_PTR2123]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2125:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2122]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2126:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2123]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2127:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2125]], i16 [[USX_CMPXCHG_DESIRED2126]] release monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2128:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2127]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2128]], ptr [[USX_ATOMIC_EXPECTED_PTR2124]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2129:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2127]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2130:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2124]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2130]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1068:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1069:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1068]] release, align 2
+// CHECK-NEXT: [[TMP1070:%.*]] = icmp ugt i16 [[TMP1069]], [[TMP1068]]
+// CHECK-NEXT: [[TMP1071:%.*]] = select i1 [[TMP1070]], i16 [[TMP1068]], i16 [[TMP1069]]
+// CHECK-NEXT: store i16 [[TMP1071]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1072:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1073:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1072]] release, align 2
+// CHECK-NEXT: [[TMP1074:%.*]] = icmp ult i16 [[TMP1073]], [[TMP1072]]
+// CHECK-NEXT: [[TMP1075:%.*]] = select i1 [[TMP1074]], i16 [[TMP1072]], i16 [[TMP1073]]
+// CHECK-NEXT: store i16 [[TMP1075]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1076:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1077:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1076]] release, align 2
+// CHECK-NEXT: [[TMP1078:%.*]] = icmp ult i16 [[TMP1077]], [[TMP1076]]
+// CHECK-NEXT: [[TMP1079:%.*]] = select i1 [[TMP1078]], i16 [[TMP1076]], i16 [[TMP1077]]
+// CHECK-NEXT: store i16 [[TMP1079]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1080:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1081:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1080]] release, align 2
+// CHECK-NEXT: [[TMP1082:%.*]] = icmp ugt i16 [[TMP1081]], [[TMP1080]]
+// CHECK-NEXT: [[TMP1083:%.*]] = select i1 [[TMP1082]], i16 [[TMP1080]], i16 [[TMP1081]]
+// CHECK-NEXT: store i16 [[TMP1083]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1084:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1085:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1084]], ptr [[USX_ATOMIC_EXPECTED_PTR2131]], align 2
+// CHECK-NEXT: store i16 [[TMP1085]], ptr [[USX_ATOMIC_DESIRED_PTR2132]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2134:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2131]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2135:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2132]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2136:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2134]], i16 [[USX_CMPXCHG_DESIRED2135]] release monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2137:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2136]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2137]], ptr [[USX_ATOMIC_EXPECTED_PTR2133]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2138:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2136]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2139:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2133]], align 2
+// CHECK-NEXT: [[USX_CAPTURE_CAPTURED2140:%.*]] = select i1 [[USX_CMPXCHG_SUCCESS2138]], i16 [[TMP1084]], i16 [[USX_CAPTURE_ACTUAL2139]]
+// CHECK-NEXT: store i16 [[USX_CAPTURE_CAPTURED2140]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1086:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1087:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1086]], ptr [[USX_ATOMIC_EXPECTED_PTR2141]], align 2
+// CHECK-NEXT: store i16 [[TMP1087]], ptr [[USX_ATOMIC_DESIRED_PTR2142]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2144:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2141]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2145:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2142]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2146:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2144]], i16 [[USX_CMPXCHG_DESIRED2145]] release monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2147:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2146]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2147]], ptr [[USX_ATOMIC_EXPECTED_PTR2143]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2148:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2146]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2149:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2143]], align 2
+// CHECK-NEXT: [[USX_CAPTURE_CAPTURED2150:%.*]] = select i1 [[USX_CMPXCHG_SUCCESS2148]], i16 [[TMP1086]], i16 [[USX_CAPTURE_ACTUAL2149]]
+// CHECK-NEXT: store i16 [[USX_CAPTURE_CAPTURED2150]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1088:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1089:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1088]], ptr [[USX_ATOMIC_EXPECTED_PTR2151]], align 2
+// CHECK-NEXT: store i16 [[TMP1089]], ptr [[USX_ATOMIC_DESIRED_PTR2152]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2154:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2151]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2155:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2152]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2156:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2154]], i16 [[USX_CMPXCHG_DESIRED2155]] release monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2157:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2156]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2157]], ptr [[USX_ATOMIC_EXPECTED_PTR2153]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2158:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2156]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2159:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2153]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS2158]], label [[USX_ATOMIC_EXIT2160:%.*]], label [[USX_ATOMIC_CONT2161:%.*]]
+// CHECK: usx.atomic.cont2161:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2159]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT2160]]
+// CHECK: usx.atomic.exit2160:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1090:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1091:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1090]], ptr [[USX_ATOMIC_EXPECTED_PTR2162]], align 2
+// CHECK-NEXT: store i16 [[TMP1091]], ptr [[USX_ATOMIC_DESIRED_PTR2163]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2165:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2162]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2166:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2163]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2167:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2165]], i16 [[USX_CMPXCHG_DESIRED2166]] release monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2168:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2167]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2168]], ptr [[USX_ATOMIC_EXPECTED_PTR2164]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2169:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2167]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2170:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2164]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS2169]], label [[USX_ATOMIC_EXIT2171:%.*]], label [[USX_ATOMIC_CONT2172:%.*]]
+// CHECK: usx.atomic.cont2172:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2170]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT2171]]
+// CHECK: usx.atomic.exit2171:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1092:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1093:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1092]], ptr [[USX_ATOMIC_EXPECTED_PTR2173]], align 2
+// CHECK-NEXT: store i16 [[TMP1093]], ptr [[USX_ATOMIC_DESIRED_PTR2174]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2176:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2173]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2177:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2174]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2178:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2176]], i16 [[USX_CMPXCHG_DESIRED2177]] release monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2179:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2178]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2179]], ptr [[USX_ATOMIC_EXPECTED_PTR2175]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2180:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2178]], 1
+// CHECK-NEXT: [[TMP1094:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS2180]] to i16
+// CHECK-NEXT: store i16 [[TMP1094]], ptr [[USR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1095:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1096:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1095]], ptr [[USX_ATOMIC_EXPECTED_PTR2181]], align 2
+// CHECK-NEXT: store i16 [[TMP1096]], ptr [[USX_ATOMIC_DESIRED_PTR2182]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2184:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2181]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2185:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2182]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2186:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2184]], i16 [[USX_CMPXCHG_DESIRED2185]] release monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2187:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2186]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2187]], ptr [[USX_ATOMIC_EXPECTED_PTR2183]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2188:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2186]], 1
+// CHECK-NEXT: [[TMP1097:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS2188]] to i16
+// CHECK-NEXT: store i16 [[TMP1097]], ptr [[USR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1098:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1099:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1098]], ptr [[USX_ATOMIC_EXPECTED_PTR2189]], align 2
+// CHECK-NEXT: store i16 [[TMP1099]], ptr [[USX_ATOMIC_DESIRED_PTR2190]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2192:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2189]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2193:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2190]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2194:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2192]], i16 [[USX_CMPXCHG_DESIRED2193]] release monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2195:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2194]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2195]], ptr [[USX_ATOMIC_EXPECTED_PTR2191]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2196:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2194]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2197:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2191]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS2196]], label [[USX_ATOMIC_EXIT2198:%.*]], label [[USX_ATOMIC_CONT2199:%.*]]
+// CHECK: usx.atomic.cont2199:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2197]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT2198]]
+// CHECK: usx.atomic.exit2198:
+// CHECK-NEXT: [[TMP1100:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS2196]] to i16
+// CHECK-NEXT: store i16 [[TMP1100]], ptr [[USR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1101:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1102:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1101]], ptr [[USX_ATOMIC_EXPECTED_PTR2200]], align 2
+// CHECK-NEXT: store i16 [[TMP1102]], ptr [[USX_ATOMIC_DESIRED_PTR2201]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2203:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2200]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2204:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2201]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2205:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2203]], i16 [[USX_CMPXCHG_DESIRED2204]] release monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2206:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2205]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2206]], ptr [[USX_ATOMIC_EXPECTED_PTR2202]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2207:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2205]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2208:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2202]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS2207]], label [[USX_ATOMIC_EXIT2209:%.*]], label [[USX_ATOMIC_CONT2210:%.*]]
+// CHECK: usx.atomic.cont2210:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2208]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT2209]]
+// CHECK: usx.atomic.exit2209:
+// CHECK-NEXT: [[TMP1103:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS2207]] to i16
+// CHECK-NEXT: store i16 [[TMP1103]], ptr [[USR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1104:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1105:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1104]] seq_cst, align 2
+// CHECK-NEXT: store i16 [[TMP1105]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1106:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1107:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1106]] seq_cst, align 2
+// CHECK-NEXT: store i16 [[TMP1107]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1108:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1109:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1108]] seq_cst, align 2
+// CHECK-NEXT: store i16 [[TMP1109]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1110:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1111:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1110]] seq_cst, align 2
+// CHECK-NEXT: store i16 [[TMP1111]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1112:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1113:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1112]], ptr [[USX_ATOMIC_EXPECTED_PTR2211]], align 2
+// CHECK-NEXT: store i16 [[TMP1113]], ptr [[USX_ATOMIC_DESIRED_PTR2212]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2214:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2211]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2215:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2212]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2216:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2214]], i16 [[USX_CMPXCHG_DESIRED2215]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2217:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2216]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2217]], ptr [[USX_ATOMIC_EXPECTED_PTR2213]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2218:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2216]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2219:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2213]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2219]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1114:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1115:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1114]], ptr [[USX_ATOMIC_EXPECTED_PTR2220]], align 2
+// CHECK-NEXT: store i16 [[TMP1115]], ptr [[USX_ATOMIC_DESIRED_PTR2221]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2223:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2220]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2224:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2221]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2225:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2223]], i16 [[USX_CMPXCHG_DESIRED2224]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2226:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2225]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2226]], ptr [[USX_ATOMIC_EXPECTED_PTR2222]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2227:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2225]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2228:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2222]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2228]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1116:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1117:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1116]] seq_cst, align 2
+// CHECK-NEXT: [[TMP1118:%.*]] = icmp ugt i16 [[TMP1117]], [[TMP1116]]
+// CHECK-NEXT: [[TMP1119:%.*]] = select i1 [[TMP1118]], i16 [[TMP1116]], i16 [[TMP1117]]
+// CHECK-NEXT: store i16 [[TMP1119]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1120:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1121:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1120]] seq_cst, align 2
+// CHECK-NEXT: [[TMP1122:%.*]] = icmp ult i16 [[TMP1121]], [[TMP1120]]
+// CHECK-NEXT: [[TMP1123:%.*]] = select i1 [[TMP1122]], i16 [[TMP1120]], i16 [[TMP1121]]
+// CHECK-NEXT: store i16 [[TMP1123]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1124:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1125:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP1124]] seq_cst, align 2
+// CHECK-NEXT: [[TMP1126:%.*]] = icmp ult i16 [[TMP1125]], [[TMP1124]]
+// CHECK-NEXT: [[TMP1127:%.*]] = select i1 [[TMP1126]], i16 [[TMP1124]], i16 [[TMP1125]]
+// CHECK-NEXT: store i16 [[TMP1127]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1128:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1129:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP1128]] seq_cst, align 2
+// CHECK-NEXT: [[TMP1130:%.*]] = icmp ugt i16 [[TMP1129]], [[TMP1128]]
+// CHECK-NEXT: [[TMP1131:%.*]] = select i1 [[TMP1130]], i16 [[TMP1128]], i16 [[TMP1129]]
+// CHECK-NEXT: store i16 [[TMP1131]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1132:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1133:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1132]], ptr [[USX_ATOMIC_EXPECTED_PTR2229]], align 2
+// CHECK-NEXT: store i16 [[TMP1133]], ptr [[USX_ATOMIC_DESIRED_PTR2230]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2232:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2229]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2233:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2230]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2234:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2232]], i16 [[USX_CMPXCHG_DESIRED2233]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2235:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2234]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2235]], ptr [[USX_ATOMIC_EXPECTED_PTR2231]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2236:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2234]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2237:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2231]], align 2
+// CHECK-NEXT: [[USX_CAPTURE_CAPTURED2238:%.*]] = select i1 [[USX_CMPXCHG_SUCCESS2236]], i16 [[TMP1132]], i16 [[USX_CAPTURE_ACTUAL2237]]
+// CHECK-NEXT: store i16 [[USX_CAPTURE_CAPTURED2238]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1134:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1135:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1134]], ptr [[USX_ATOMIC_EXPECTED_PTR2239]], align 2
+// CHECK-NEXT: store i16 [[TMP1135]], ptr [[USX_ATOMIC_DESIRED_PTR2240]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2242:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2239]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2243:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2240]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2244:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2242]], i16 [[USX_CMPXCHG_DESIRED2243]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2245:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2244]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2245]], ptr [[USX_ATOMIC_EXPECTED_PTR2241]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2246:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2244]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2247:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2241]], align 2
+// CHECK-NEXT: [[USX_CAPTURE_CAPTURED2248:%.*]] = select i1 [[USX_CMPXCHG_SUCCESS2246]], i16 [[TMP1134]], i16 [[USX_CAPTURE_ACTUAL2247]]
+// CHECK-NEXT: store i16 [[USX_CAPTURE_CAPTURED2248]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1136:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1137:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1136]], ptr [[USX_ATOMIC_EXPECTED_PTR2249]], align 2
+// CHECK-NEXT: store i16 [[TMP1137]], ptr [[USX_ATOMIC_DESIRED_PTR2250]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2252:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2249]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2253:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2250]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2254:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2252]], i16 [[USX_CMPXCHG_DESIRED2253]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2255:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2254]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2255]], ptr [[USX_ATOMIC_EXPECTED_PTR2251]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2256:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2254]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2257:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2251]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS2256]], label [[USX_ATOMIC_EXIT2258:%.*]], label [[USX_ATOMIC_CONT2259:%.*]]
+// CHECK: usx.atomic.cont2259:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2257]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT2258]]
+// CHECK: usx.atomic.exit2258:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1138:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1139:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1138]], ptr [[USX_ATOMIC_EXPECTED_PTR2260]], align 2
+// CHECK-NEXT: store i16 [[TMP1139]], ptr [[USX_ATOMIC_DESIRED_PTR2261]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2263:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2260]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2264:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2261]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2265:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2263]], i16 [[USX_CMPXCHG_DESIRED2264]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2266:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2265]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2266]], ptr [[USX_ATOMIC_EXPECTED_PTR2262]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2267:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2265]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2268:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2262]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS2267]], label [[USX_ATOMIC_EXIT2269:%.*]], label [[USX_ATOMIC_CONT2270:%.*]]
+// CHECK: usx.atomic.cont2270:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2268]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT2269]]
+// CHECK: usx.atomic.exit2269:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1140:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1141:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1140]], ptr [[USX_ATOMIC_EXPECTED_PTR2271]], align 2
+// CHECK-NEXT: store i16 [[TMP1141]], ptr [[USX_ATOMIC_DESIRED_PTR2272]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2274:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2271]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2275:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2272]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2276:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2274]], i16 [[USX_CMPXCHG_DESIRED2275]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2277:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2276]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2277]], ptr [[USX_ATOMIC_EXPECTED_PTR2273]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2278:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2276]], 1
+// CHECK-NEXT: [[TMP1142:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS2278]] to i16
+// CHECK-NEXT: store i16 [[TMP1142]], ptr [[USR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1143:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1144:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1143]], ptr [[USX_ATOMIC_EXPECTED_PTR2279]], align 2
+// CHECK-NEXT: store i16 [[TMP1144]], ptr [[USX_ATOMIC_DESIRED_PTR2280]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2282:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2279]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2283:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2280]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2284:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2282]], i16 [[USX_CMPXCHG_DESIRED2283]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2285:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2284]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2285]], ptr [[USX_ATOMIC_EXPECTED_PTR2281]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2286:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2284]], 1
+// CHECK-NEXT: [[TMP1145:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS2286]] to i16
+// CHECK-NEXT: store i16 [[TMP1145]], ptr [[USR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1146:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1147:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1146]], ptr [[USX_ATOMIC_EXPECTED_PTR2287]], align 2
+// CHECK-NEXT: store i16 [[TMP1147]], ptr [[USX_ATOMIC_DESIRED_PTR2288]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2290:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2287]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2291:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2288]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2292:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2290]], i16 [[USX_CMPXCHG_DESIRED2291]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2293:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2292]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2293]], ptr [[USX_ATOMIC_EXPECTED_PTR2289]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2294:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2292]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2295:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2289]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS2294]], label [[USX_ATOMIC_EXIT2296:%.*]], label [[USX_ATOMIC_CONT2297:%.*]]
+// CHECK: usx.atomic.cont2297:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2295]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT2296]]
+// CHECK: usx.atomic.exit2296:
+// CHECK-NEXT: [[TMP1148:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS2294]] to i16
+// CHECK-NEXT: store i16 [[TMP1148]], ptr [[USR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1149:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP1150:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP1149]], ptr [[USX_ATOMIC_EXPECTED_PTR2298]], align 2
+// CHECK-NEXT: store i16 [[TMP1150]], ptr [[USX_ATOMIC_DESIRED_PTR2299]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED2301:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2298]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED2302:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR2299]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR2303:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED2301]], i16 [[USX_CMPXCHG_DESIRED2302]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV2304:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2303]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV2304]], ptr [[USX_ATOMIC_EXPECTED_PTR2300]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS2305:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR2303]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL2306:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2300]], align 2
+// CHECK-NEXT: br i1 [[USX_CMPXCHG_SUCCESS2305]], label [[USX_ATOMIC_EXIT2307:%.*]], label [[USX_ATOMIC_CONT2308:%.*]]
+// CHECK: usx.atomic.cont2308:
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL2306]], ptr [[USV]], align 2
+// CHECK-NEXT: br label [[USX_ATOMIC_EXIT2307]]
+// CHECK: usx.atomic.exit2307:
+// CHECK-NEXT: [[TMP1151:%.*]] = zext i1 [[USX_CMPXCHG_SUCCESS2305]] to i16
+// CHECK-NEXT: store i16 [[TMP1151]], ptr [[USR]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1152:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1153:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1152]] monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP1153]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1154:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1155:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1154]] monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP1155]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1156:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1157:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1156]] monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP1157]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1158:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1159:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1158]] monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP1159]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1160:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1161:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1160]], ptr [[IX_ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: store i32 [[TMP1161]], ptr [[IX_ATOMIC_DESIRED_PTR]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED]], i32 [[IX_CMPXCHG_DESIRED]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV]], ptr [[IX_ATOMIC_EXPECTED_PTR2309]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2309]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1162:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1163:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1162]], ptr [[IX_ATOMIC_EXPECTED_PTR2310]], align 4
+// CHECK-NEXT: store i32 [[TMP1163]], ptr [[IX_ATOMIC_DESIRED_PTR2311]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2313:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2310]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2314:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2311]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2315:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2313]], i32 [[IX_CMPXCHG_DESIRED2314]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2316:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2315]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2316]], ptr [[IX_ATOMIC_EXPECTED_PTR2312]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2317:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2315]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2318:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2312]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2318]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1164:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1165:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1164]] monotonic, align 4
+// CHECK-NEXT: [[TMP1166:%.*]] = icmp sgt i32 [[TMP1165]], [[TMP1164]]
+// CHECK-NEXT: [[TMP1167:%.*]] = select i1 [[TMP1166]], i32 [[TMP1164]], i32 [[TMP1165]]
+// CHECK-NEXT: store i32 [[TMP1167]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1168:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1169:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1168]] monotonic, align 4
+// CHECK-NEXT: [[TMP1170:%.*]] = icmp slt i32 [[TMP1169]], [[TMP1168]]
+// CHECK-NEXT: [[TMP1171:%.*]] = select i1 [[TMP1170]], i32 [[TMP1168]], i32 [[TMP1169]]
+// CHECK-NEXT: store i32 [[TMP1171]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1172:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1173:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1172]] monotonic, align 4
+// CHECK-NEXT: [[TMP1174:%.*]] = icmp slt i32 [[TMP1173]], [[TMP1172]]
+// CHECK-NEXT: [[TMP1175:%.*]] = select i1 [[TMP1174]], i32 [[TMP1172]], i32 [[TMP1173]]
+// CHECK-NEXT: store i32 [[TMP1175]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1176:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1177:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1176]] monotonic, align 4
+// CHECK-NEXT: [[TMP1178:%.*]] = icmp sgt i32 [[TMP1177]], [[TMP1176]]
+// CHECK-NEXT: [[TMP1179:%.*]] = select i1 [[TMP1178]], i32 [[TMP1176]], i32 [[TMP1177]]
+// CHECK-NEXT: store i32 [[TMP1179]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1180:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1181:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1180]], ptr [[IX_ATOMIC_EXPECTED_PTR2319]], align 4
+// CHECK-NEXT: store i32 [[TMP1181]], ptr [[IX_ATOMIC_DESIRED_PTR2320]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2322:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2319]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2323:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2320]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2324:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2322]], i32 [[IX_CMPXCHG_DESIRED2323]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2325:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2324]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2325]], ptr [[IX_ATOMIC_EXPECTED_PTR2321]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2326:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2324]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2327:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2321]], align 4
+// CHECK-NEXT: [[IX_CAPTURE_CAPTURED:%.*]] = select i1 [[IX_CMPXCHG_SUCCESS2326]], i32 [[TMP1180]], i32 [[IX_CAPTURE_ACTUAL2327]]
+// CHECK-NEXT: store i32 [[IX_CAPTURE_CAPTURED]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1182:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1183:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1182]], ptr [[IX_ATOMIC_EXPECTED_PTR2328]], align 4
+// CHECK-NEXT: store i32 [[TMP1183]], ptr [[IX_ATOMIC_DESIRED_PTR2329]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2331:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2328]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2332:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2329]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2333:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2331]], i32 [[IX_CMPXCHG_DESIRED2332]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2334:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2333]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2334]], ptr [[IX_ATOMIC_EXPECTED_PTR2330]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2335:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2333]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2336:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2330]], align 4
+// CHECK-NEXT: [[IX_CAPTURE_CAPTURED2337:%.*]] = select i1 [[IX_CMPXCHG_SUCCESS2335]], i32 [[TMP1182]], i32 [[IX_CAPTURE_ACTUAL2336]]
+// CHECK-NEXT: store i32 [[IX_CAPTURE_CAPTURED2337]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1184:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1185:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1184]], ptr [[IX_ATOMIC_EXPECTED_PTR2338]], align 4
+// CHECK-NEXT: store i32 [[TMP1185]], ptr [[IX_ATOMIC_DESIRED_PTR2339]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2341:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2338]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2342:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2339]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2343:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2341]], i32 [[IX_CMPXCHG_DESIRED2342]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2344:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2343]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2344]], ptr [[IX_ATOMIC_EXPECTED_PTR2340]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2345:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2343]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2346:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2340]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2345]], label [[IX_ATOMIC_EXIT:%.*]], label [[IX_ATOMIC_CONT:%.*]]
// CHECK: ix.atomic.cont:
-// CHECK-NEXT: store i32 [[TMP1919]], ptr [[IV]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2346]], ptr [[IV]], align 4
// CHECK-NEXT: br label [[IX_ATOMIC_EXIT]]
// CHECK: ix.atomic.exit:
-// CHECK-NEXT: [[TMP1921:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1922:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP1923:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1921]], i32 [[TMP1922]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP1924:%.*]] = extractvalue { i32, i1 } [[TMP1923]], 0
-// CHECK-NEXT: [[TMP1925:%.*]] = extractvalue { i32, i1 } [[TMP1923]], 1
-// CHECK-NEXT: br i1 [[TMP1925]], label [[IX_ATOMIC_EXIT185:%.*]], label [[IX_ATOMIC_CONT186:%.*]]
-// CHECK: ix.atomic.cont186:
-// CHECK-NEXT: store i32 [[TMP1924]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT185]]
-// CHECK: ix.atomic.exit185:
-// CHECK-NEXT: [[TMP1926:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1927:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP1928:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1926]], i32 [[TMP1927]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP1929:%.*]] = extractvalue { i32, i1 } [[TMP1928]], 1
-// CHECK-NEXT: [[TMP1930:%.*]] = sext i1 [[TMP1929]] to i32
-// CHECK-NEXT: store i32 [[TMP1930]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP1931:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1932:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP1933:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1931]], i32 [[TMP1932]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP1934:%.*]] = extractvalue { i32, i1 } [[TMP1933]], 1
-// CHECK-NEXT: [[TMP1935:%.*]] = sext i1 [[TMP1934]] to i32
-// CHECK-NEXT: store i32 [[TMP1935]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP1936:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1937:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP1938:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1936]], i32 [[TMP1937]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP1939:%.*]] = extractvalue { i32, i1 } [[TMP1938]], 0
-// CHECK-NEXT: [[TMP1940:%.*]] = extractvalue { i32, i1 } [[TMP1938]], 1
-// CHECK-NEXT: br i1 [[TMP1940]], label [[IX_ATOMIC_EXIT187:%.*]], label [[IX_ATOMIC_CONT188:%.*]]
-// CHECK: ix.atomic.cont188:
-// CHECK-NEXT: store i32 [[TMP1939]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT187]]
-// CHECK: ix.atomic.exit187:
-// CHECK-NEXT: [[TMP1941:%.*]] = extractvalue { i32, i1 } [[TMP1938]], 1
-// CHECK-NEXT: [[TMP1942:%.*]] = sext i1 [[TMP1941]] to i32
-// CHECK-NEXT: store i32 [[TMP1942]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP1943:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1944:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP1945:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1943]], i32 [[TMP1944]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP1946:%.*]] = extractvalue { i32, i1 } [[TMP1945]], 0
-// CHECK-NEXT: [[TMP1947:%.*]] = extractvalue { i32, i1 } [[TMP1945]], 1
-// CHECK-NEXT: br i1 [[TMP1947]], label [[IX_ATOMIC_EXIT189:%.*]], label [[IX_ATOMIC_CONT190:%.*]]
-// CHECK: ix.atomic.cont190:
-// CHECK-NEXT: store i32 [[TMP1946]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT189]]
-// CHECK: ix.atomic.exit189:
-// CHECK-NEXT: [[TMP1948:%.*]] = extractvalue { i32, i1 } [[TMP1945]], 1
-// CHECK-NEXT: [[TMP1949:%.*]] = sext i1 [[TMP1948]] to i32
-// CHECK-NEXT: store i32 [[TMP1949]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP1950:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1951:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1950]] acq_rel, align 4
-// CHECK-NEXT: store i32 [[TMP1951]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1952:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1953:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1952]] acq_rel, align 4
-// CHECK-NEXT: store i32 [[TMP1953]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1954:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1955:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1954]] acq_rel, align 4
-// CHECK-NEXT: store i32 [[TMP1955]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1956:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1957:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1956]] acq_rel, align 4
-// CHECK-NEXT: store i32 [[TMP1957]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1958:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1959:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP1960:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1958]], i32 [[TMP1959]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP1961:%.*]] = extractvalue { i32, i1 } [[TMP1960]], 0
-// CHECK-NEXT: store i32 [[TMP1961]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1962:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1963:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP1964:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1962]], i32 [[TMP1963]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP1965:%.*]] = extractvalue { i32, i1 } [[TMP1964]], 0
-// CHECK-NEXT: store i32 [[TMP1965]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1966:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1967:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1966]] acq_rel, align 4
-// CHECK-NEXT: [[TMP1968:%.*]] = icmp sgt i32 [[TMP1967]], [[TMP1966]]
-// CHECK-NEXT: [[TMP1969:%.*]] = select i1 [[TMP1968]], i32 [[TMP1966]], i32 [[TMP1967]]
-// CHECK-NEXT: store i32 [[TMP1969]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1970:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1971:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1970]] acq_rel, align 4
-// CHECK-NEXT: [[TMP1972:%.*]] = icmp slt i32 [[TMP1971]], [[TMP1970]]
-// CHECK-NEXT: [[TMP1973:%.*]] = select i1 [[TMP1972]], i32 [[TMP1970]], i32 [[TMP1971]]
-// CHECK-NEXT: store i32 [[TMP1973]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1974:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1975:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1974]] acq_rel, align 4
-// CHECK-NEXT: [[TMP1976:%.*]] = icmp slt i32 [[TMP1975]], [[TMP1974]]
-// CHECK-NEXT: [[TMP1977:%.*]] = select i1 [[TMP1976]], i32 [[TMP1974]], i32 [[TMP1975]]
-// CHECK-NEXT: store i32 [[TMP1977]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1978:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1979:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1978]] acq_rel, align 4
-// CHECK-NEXT: [[TMP1980:%.*]] = icmp sgt i32 [[TMP1979]], [[TMP1978]]
-// CHECK-NEXT: [[TMP1981:%.*]] = select i1 [[TMP1980]], i32 [[TMP1978]], i32 [[TMP1979]]
-// CHECK-NEXT: store i32 [[TMP1981]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1982:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1983:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP1984:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1982]], i32 [[TMP1983]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP1985:%.*]] = extractvalue { i32, i1 } [[TMP1984]], 0
-// CHECK-NEXT: [[TMP1986:%.*]] = extractvalue { i32, i1 } [[TMP1984]], 1
-// CHECK-NEXT: [[TMP1987:%.*]] = select i1 [[TMP1986]], i32 [[TMP1982]], i32 [[TMP1985]]
-// CHECK-NEXT: store i32 [[TMP1987]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1988:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1989:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP1990:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1988]], i32 [[TMP1989]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP1991:%.*]] = extractvalue { i32, i1 } [[TMP1990]], 0
-// CHECK-NEXT: [[TMP1992:%.*]] = extractvalue { i32, i1 } [[TMP1990]], 1
-// CHECK-NEXT: [[TMP1993:%.*]] = select i1 [[TMP1992]], i32 [[TMP1988]], i32 [[TMP1991]]
-// CHECK-NEXT: store i32 [[TMP1993]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1994:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP1995:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP1996:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1994]], i32 [[TMP1995]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP1997:%.*]] = extractvalue { i32, i1 } [[TMP1996]], 0
-// CHECK-NEXT: [[TMP1998:%.*]] = extractvalue { i32, i1 } [[TMP1996]], 1
-// CHECK-NEXT: br i1 [[TMP1998]], label [[IX_ATOMIC_EXIT191:%.*]], label [[IX_ATOMIC_CONT192:%.*]]
-// CHECK: ix.atomic.cont192:
-// CHECK-NEXT: store i32 [[TMP1997]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT191]]
-// CHECK: ix.atomic.exit191:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP1999:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2000:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2001:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP1999]], i32 [[TMP2000]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP2002:%.*]] = extractvalue { i32, i1 } [[TMP2001]], 0
-// CHECK-NEXT: [[TMP2003:%.*]] = extractvalue { i32, i1 } [[TMP2001]], 1
-// CHECK-NEXT: br i1 [[TMP2003]], label [[IX_ATOMIC_EXIT193:%.*]], label [[IX_ATOMIC_CONT194:%.*]]
-// CHECK: ix.atomic.cont194:
-// CHECK-NEXT: store i32 [[TMP2002]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT193]]
-// CHECK: ix.atomic.exit193:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2004:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2005:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2006:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2004]], i32 [[TMP2005]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP2007:%.*]] = extractvalue { i32, i1 } [[TMP2006]], 1
-// CHECK-NEXT: [[TMP2008:%.*]] = sext i1 [[TMP2007]] to i32
-// CHECK-NEXT: store i32 [[TMP2008]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2009:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2010:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2011:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2009]], i32 [[TMP2010]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP2012:%.*]] = extractvalue { i32, i1 } [[TMP2011]], 1
-// CHECK-NEXT: [[TMP2013:%.*]] = sext i1 [[TMP2012]] to i32
-// CHECK-NEXT: store i32 [[TMP2013]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2014:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2015:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2016:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2014]], i32 [[TMP2015]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP2017:%.*]] = extractvalue { i32, i1 } [[TMP2016]], 0
-// CHECK-NEXT: [[TMP2018:%.*]] = extractvalue { i32, i1 } [[TMP2016]], 1
-// CHECK-NEXT: br i1 [[TMP2018]], label [[IX_ATOMIC_EXIT195:%.*]], label [[IX_ATOMIC_CONT196:%.*]]
-// CHECK: ix.atomic.cont196:
-// CHECK-NEXT: store i32 [[TMP2017]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT195]]
-// CHECK: ix.atomic.exit195:
-// CHECK-NEXT: [[TMP2019:%.*]] = extractvalue { i32, i1 } [[TMP2016]], 1
-// CHECK-NEXT: [[TMP2020:%.*]] = sext i1 [[TMP2019]] to i32
-// CHECK-NEXT: store i32 [[TMP2020]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2021:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2022:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2023:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2021]], i32 [[TMP2022]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP2024:%.*]] = extractvalue { i32, i1 } [[TMP2023]], 0
-// CHECK-NEXT: [[TMP2025:%.*]] = extractvalue { i32, i1 } [[TMP2023]], 1
-// CHECK-NEXT: br i1 [[TMP2025]], label [[IX_ATOMIC_EXIT197:%.*]], label [[IX_ATOMIC_CONT198:%.*]]
-// CHECK: ix.atomic.cont198:
-// CHECK-NEXT: store i32 [[TMP2024]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT197]]
-// CHECK: ix.atomic.exit197:
-// CHECK-NEXT: [[TMP2026:%.*]] = extractvalue { i32, i1 } [[TMP2023]], 1
-// CHECK-NEXT: [[TMP2027:%.*]] = sext i1 [[TMP2026]] to i32
-// CHECK-NEXT: store i32 [[TMP2027]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2028:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2029:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2028]] acquire, align 4
-// CHECK-NEXT: store i32 [[TMP2029]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2030:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2031:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2030]] acquire, align 4
-// CHECK-NEXT: store i32 [[TMP2031]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2032:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2033:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2032]] acquire, align 4
-// CHECK-NEXT: store i32 [[TMP2033]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2034:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2035:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2034]] acquire, align 4
-// CHECK-NEXT: store i32 [[TMP2035]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2036:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2037:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2038:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2036]], i32 [[TMP2037]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2039:%.*]] = extractvalue { i32, i1 } [[TMP2038]], 0
-// CHECK-NEXT: store i32 [[TMP2039]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2040:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2041:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2042:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2040]], i32 [[TMP2041]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2043:%.*]] = extractvalue { i32, i1 } [[TMP2042]], 0
-// CHECK-NEXT: store i32 [[TMP2043]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2044:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2045:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2044]] acquire, align 4
-// CHECK-NEXT: [[TMP2046:%.*]] = icmp sgt i32 [[TMP2045]], [[TMP2044]]
-// CHECK-NEXT: [[TMP2047:%.*]] = select i1 [[TMP2046]], i32 [[TMP2044]], i32 [[TMP2045]]
-// CHECK-NEXT: store i32 [[TMP2047]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2048:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2049:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2048]] acquire, align 4
-// CHECK-NEXT: [[TMP2050:%.*]] = icmp slt i32 [[TMP2049]], [[TMP2048]]
-// CHECK-NEXT: [[TMP2051:%.*]] = select i1 [[TMP2050]], i32 [[TMP2048]], i32 [[TMP2049]]
-// CHECK-NEXT: store i32 [[TMP2051]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2052:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2053:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2052]] acquire, align 4
-// CHECK-NEXT: [[TMP2054:%.*]] = icmp slt i32 [[TMP2053]], [[TMP2052]]
-// CHECK-NEXT: [[TMP2055:%.*]] = select i1 [[TMP2054]], i32 [[TMP2052]], i32 [[TMP2053]]
-// CHECK-NEXT: store i32 [[TMP2055]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2056:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2057:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2056]] acquire, align 4
-// CHECK-NEXT: [[TMP2058:%.*]] = icmp sgt i32 [[TMP2057]], [[TMP2056]]
-// CHECK-NEXT: [[TMP2059:%.*]] = select i1 [[TMP2058]], i32 [[TMP2056]], i32 [[TMP2057]]
-// CHECK-NEXT: store i32 [[TMP2059]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2060:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2061:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2062:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2060]], i32 [[TMP2061]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2063:%.*]] = extractvalue { i32, i1 } [[TMP2062]], 0
-// CHECK-NEXT: [[TMP2064:%.*]] = extractvalue { i32, i1 } [[TMP2062]], 1
-// CHECK-NEXT: [[TMP2065:%.*]] = select i1 [[TMP2064]], i32 [[TMP2060]], i32 [[TMP2063]]
-// CHECK-NEXT: store i32 [[TMP2065]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2066:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2067:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2068:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2066]], i32 [[TMP2067]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2069:%.*]] = extractvalue { i32, i1 } [[TMP2068]], 0
-// CHECK-NEXT: [[TMP2070:%.*]] = extractvalue { i32, i1 } [[TMP2068]], 1
-// CHECK-NEXT: [[TMP2071:%.*]] = select i1 [[TMP2070]], i32 [[TMP2066]], i32 [[TMP2069]]
-// CHECK-NEXT: store i32 [[TMP2071]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2072:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2073:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2074:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2072]], i32 [[TMP2073]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2075:%.*]] = extractvalue { i32, i1 } [[TMP2074]], 0
-// CHECK-NEXT: [[TMP2076:%.*]] = extractvalue { i32, i1 } [[TMP2074]], 1
-// CHECK-NEXT: br i1 [[TMP2076]], label [[IX_ATOMIC_EXIT199:%.*]], label [[IX_ATOMIC_CONT200:%.*]]
-// CHECK: ix.atomic.cont200:
-// CHECK-NEXT: store i32 [[TMP2075]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT199]]
-// CHECK: ix.atomic.exit199:
-// CHECK-NEXT: [[TMP2077:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2078:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2079:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2077]], i32 [[TMP2078]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2080:%.*]] = extractvalue { i32, i1 } [[TMP2079]], 0
-// CHECK-NEXT: [[TMP2081:%.*]] = extractvalue { i32, i1 } [[TMP2079]], 1
-// CHECK-NEXT: br i1 [[TMP2081]], label [[IX_ATOMIC_EXIT201:%.*]], label [[IX_ATOMIC_CONT202:%.*]]
-// CHECK: ix.atomic.cont202:
-// CHECK-NEXT: store i32 [[TMP2080]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT201]]
-// CHECK: ix.atomic.exit201:
-// CHECK-NEXT: [[TMP2082:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2083:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2084:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2082]], i32 [[TMP2083]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2085:%.*]] = extractvalue { i32, i1 } [[TMP2084]], 1
-// CHECK-NEXT: [[TMP2086:%.*]] = sext i1 [[TMP2085]] to i32
-// CHECK-NEXT: store i32 [[TMP2086]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP2087:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2088:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2089:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2087]], i32 [[TMP2088]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2090:%.*]] = extractvalue { i32, i1 } [[TMP2089]], 1
-// CHECK-NEXT: [[TMP2091:%.*]] = sext i1 [[TMP2090]] to i32
-// CHECK-NEXT: store i32 [[TMP2091]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP2092:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2093:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2094:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2092]], i32 [[TMP2093]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2095:%.*]] = extractvalue { i32, i1 } [[TMP2094]], 0
-// CHECK-NEXT: [[TMP2096:%.*]] = extractvalue { i32, i1 } [[TMP2094]], 1
-// CHECK-NEXT: br i1 [[TMP2096]], label [[IX_ATOMIC_EXIT203:%.*]], label [[IX_ATOMIC_CONT204:%.*]]
-// CHECK: ix.atomic.cont204:
-// CHECK-NEXT: store i32 [[TMP2095]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT203]]
-// CHECK: ix.atomic.exit203:
-// CHECK-NEXT: [[TMP2097:%.*]] = extractvalue { i32, i1 } [[TMP2094]], 1
-// CHECK-NEXT: [[TMP2098:%.*]] = sext i1 [[TMP2097]] to i32
-// CHECK-NEXT: store i32 [[TMP2098]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP2099:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2100:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2101:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2099]], i32 [[TMP2100]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2102:%.*]] = extractvalue { i32, i1 } [[TMP2101]], 0
-// CHECK-NEXT: [[TMP2103:%.*]] = extractvalue { i32, i1 } [[TMP2101]], 1
-// CHECK-NEXT: br i1 [[TMP2103]], label [[IX_ATOMIC_EXIT205:%.*]], label [[IX_ATOMIC_CONT206:%.*]]
-// CHECK: ix.atomic.cont206:
-// CHECK-NEXT: store i32 [[TMP2102]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT205]]
-// CHECK: ix.atomic.exit205:
-// CHECK-NEXT: [[TMP2104:%.*]] = extractvalue { i32, i1 } [[TMP2101]], 1
-// CHECK-NEXT: [[TMP2105:%.*]] = sext i1 [[TMP2104]] to i32
-// CHECK-NEXT: store i32 [[TMP2105]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP2106:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2107:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2106]] monotonic, align 4
-// CHECK-NEXT: store i32 [[TMP2107]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2108:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2109:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2108]] monotonic, align 4
-// CHECK-NEXT: store i32 [[TMP2109]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2110:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2111:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2110]] monotonic, align 4
-// CHECK-NEXT: store i32 [[TMP2111]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2112:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2113:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2112]] monotonic, align 4
-// CHECK-NEXT: store i32 [[TMP2113]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2114:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2115:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2116:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2114]], i32 [[TMP2115]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2117:%.*]] = extractvalue { i32, i1 } [[TMP2116]], 0
-// CHECK-NEXT: store i32 [[TMP2117]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2118:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2119:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2120:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2118]], i32 [[TMP2119]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2121:%.*]] = extractvalue { i32, i1 } [[TMP2120]], 0
-// CHECK-NEXT: store i32 [[TMP2121]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2122:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2123:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2122]] monotonic, align 4
-// CHECK-NEXT: [[TMP2124:%.*]] = icmp sgt i32 [[TMP2123]], [[TMP2122]]
-// CHECK-NEXT: [[TMP2125:%.*]] = select i1 [[TMP2124]], i32 [[TMP2122]], i32 [[TMP2123]]
-// CHECK-NEXT: store i32 [[TMP2125]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2126:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2127:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2126]] monotonic, align 4
-// CHECK-NEXT: [[TMP2128:%.*]] = icmp slt i32 [[TMP2127]], [[TMP2126]]
-// CHECK-NEXT: [[TMP2129:%.*]] = select i1 [[TMP2128]], i32 [[TMP2126]], i32 [[TMP2127]]
-// CHECK-NEXT: store i32 [[TMP2129]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2130:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2131:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2130]] monotonic, align 4
-// CHECK-NEXT: [[TMP2132:%.*]] = icmp slt i32 [[TMP2131]], [[TMP2130]]
-// CHECK-NEXT: [[TMP2133:%.*]] = select i1 [[TMP2132]], i32 [[TMP2130]], i32 [[TMP2131]]
-// CHECK-NEXT: store i32 [[TMP2133]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2134:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2135:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2134]] monotonic, align 4
-// CHECK-NEXT: [[TMP2136:%.*]] = icmp sgt i32 [[TMP2135]], [[TMP2134]]
-// CHECK-NEXT: [[TMP2137:%.*]] = select i1 [[TMP2136]], i32 [[TMP2134]], i32 [[TMP2135]]
-// CHECK-NEXT: store i32 [[TMP2137]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2138:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2139:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2140:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2138]], i32 [[TMP2139]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2141:%.*]] = extractvalue { i32, i1 } [[TMP2140]], 0
-// CHECK-NEXT: [[TMP2142:%.*]] = extractvalue { i32, i1 } [[TMP2140]], 1
-// CHECK-NEXT: [[TMP2143:%.*]] = select i1 [[TMP2142]], i32 [[TMP2138]], i32 [[TMP2141]]
-// CHECK-NEXT: store i32 [[TMP2143]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2144:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2145:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2146:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2144]], i32 [[TMP2145]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2147:%.*]] = extractvalue { i32, i1 } [[TMP2146]], 0
-// CHECK-NEXT: [[TMP2148:%.*]] = extractvalue { i32, i1 } [[TMP2146]], 1
-// CHECK-NEXT: [[TMP2149:%.*]] = select i1 [[TMP2148]], i32 [[TMP2144]], i32 [[TMP2147]]
-// CHECK-NEXT: store i32 [[TMP2149]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP2150:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2151:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2152:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2150]], i32 [[TMP2151]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2153:%.*]] = extractvalue { i32, i1 } [[TMP2152]], 0
-// CHECK-NEXT: [[TMP2154:%.*]] = extractvalue { i32, i1 } [[TMP2152]], 1
-// CHECK-NEXT: br i1 [[TMP2154]], label [[IX_ATOMIC_EXIT207:%.*]], label [[IX_ATOMIC_CONT208:%.*]]
-// CHECK: ix.atomic.cont208:
-// CHECK-NEXT: store i32 [[TMP2153]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT207]]
-// CHECK: ix.atomic.exit207:
-// CHECK-NEXT: [[TMP2155:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2156:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2157:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2155]], i32 [[TMP2156]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2158:%.*]] = extractvalue { i32, i1 } [[TMP2157]], 0
-// CHECK-NEXT: [[TMP2159:%.*]] = extractvalue { i32, i1 } [[TMP2157]], 1
-// CHECK-NEXT: br i1 [[TMP2159]], label [[IX_ATOMIC_EXIT209:%.*]], label [[IX_ATOMIC_CONT210:%.*]]
-// CHECK: ix.atomic.cont210:
-// CHECK-NEXT: store i32 [[TMP2158]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT209]]
-// CHECK: ix.atomic.exit209:
-// CHECK-NEXT: [[TMP2160:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2161:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2162:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2160]], i32 [[TMP2161]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2163:%.*]] = extractvalue { i32, i1 } [[TMP2162]], 1
-// CHECK-NEXT: [[TMP2164:%.*]] = sext i1 [[TMP2163]] to i32
-// CHECK-NEXT: store i32 [[TMP2164]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP2165:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2166:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2167:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2165]], i32 [[TMP2166]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2168:%.*]] = extractvalue { i32, i1 } [[TMP2167]], 1
-// CHECK-NEXT: [[TMP2169:%.*]] = sext i1 [[TMP2168]] to i32
-// CHECK-NEXT: store i32 [[TMP2169]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP2170:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2171:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2172:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2170]], i32 [[TMP2171]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2173:%.*]] = extractvalue { i32, i1 } [[TMP2172]], 0
-// CHECK-NEXT: [[TMP2174:%.*]] = extractvalue { i32, i1 } [[TMP2172]], 1
-// CHECK-NEXT: br i1 [[TMP2174]], label [[IX_ATOMIC_EXIT211:%.*]], label [[IX_ATOMIC_CONT212:%.*]]
-// CHECK: ix.atomic.cont212:
-// CHECK-NEXT: store i32 [[TMP2173]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT211]]
-// CHECK: ix.atomic.exit211:
-// CHECK-NEXT: [[TMP2175:%.*]] = extractvalue { i32, i1 } [[TMP2172]], 1
-// CHECK-NEXT: [[TMP2176:%.*]] = sext i1 [[TMP2175]] to i32
-// CHECK-NEXT: store i32 [[TMP2176]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP2177:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2178:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2179:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2177]], i32 [[TMP2178]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2180:%.*]] = extractvalue { i32, i1 } [[TMP2179]], 0
-// CHECK-NEXT: [[TMP2181:%.*]] = extractvalue { i32, i1 } [[TMP2179]], 1
-// CHECK-NEXT: br i1 [[TMP2181]], label [[IX_ATOMIC_EXIT213:%.*]], label [[IX_ATOMIC_CONT214:%.*]]
-// CHECK: ix.atomic.cont214:
-// CHECK-NEXT: store i32 [[TMP2180]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT213]]
-// CHECK: ix.atomic.exit213:
-// CHECK-NEXT: [[TMP2182:%.*]] = extractvalue { i32, i1 } [[TMP2179]], 1
-// CHECK-NEXT: [[TMP2183:%.*]] = sext i1 [[TMP2182]] to i32
-// CHECK-NEXT: store i32 [[TMP2183]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP2184:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2185:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2184]] release, align 4
-// CHECK-NEXT: store i32 [[TMP2185]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2186:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2187:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2186]] release, align 4
-// CHECK-NEXT: store i32 [[TMP2187]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2188:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2189:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2188]] release, align 4
-// CHECK-NEXT: store i32 [[TMP2189]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2190:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2191:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2190]] release, align 4
-// CHECK-NEXT: store i32 [[TMP2191]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2192:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2193:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2194:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2192]], i32 [[TMP2193]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2195:%.*]] = extractvalue { i32, i1 } [[TMP2194]], 0
-// CHECK-NEXT: store i32 [[TMP2195]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2196:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2197:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2198:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2196]], i32 [[TMP2197]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2199:%.*]] = extractvalue { i32, i1 } [[TMP2198]], 0
-// CHECK-NEXT: store i32 [[TMP2199]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2200:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2201:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2200]] release, align 4
-// CHECK-NEXT: [[TMP2202:%.*]] = icmp sgt i32 [[TMP2201]], [[TMP2200]]
-// CHECK-NEXT: [[TMP2203:%.*]] = select i1 [[TMP2202]], i32 [[TMP2200]], i32 [[TMP2201]]
-// CHECK-NEXT: store i32 [[TMP2203]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2204:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2205:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2204]] release, align 4
-// CHECK-NEXT: [[TMP2206:%.*]] = icmp slt i32 [[TMP2205]], [[TMP2204]]
-// CHECK-NEXT: [[TMP2207:%.*]] = select i1 [[TMP2206]], i32 [[TMP2204]], i32 [[TMP2205]]
-// CHECK-NEXT: store i32 [[TMP2207]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2208:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2209:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2208]] release, align 4
-// CHECK-NEXT: [[TMP2210:%.*]] = icmp slt i32 [[TMP2209]], [[TMP2208]]
-// CHECK-NEXT: [[TMP2211:%.*]] = select i1 [[TMP2210]], i32 [[TMP2208]], i32 [[TMP2209]]
-// CHECK-NEXT: store i32 [[TMP2211]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2212:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2213:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2212]] release, align 4
-// CHECK-NEXT: [[TMP2214:%.*]] = icmp sgt i32 [[TMP2213]], [[TMP2212]]
-// CHECK-NEXT: [[TMP2215:%.*]] = select i1 [[TMP2214]], i32 [[TMP2212]], i32 [[TMP2213]]
-// CHECK-NEXT: store i32 [[TMP2215]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2216:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2217:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2218:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2216]], i32 [[TMP2217]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2219:%.*]] = extractvalue { i32, i1 } [[TMP2218]], 0
-// CHECK-NEXT: [[TMP2220:%.*]] = extractvalue { i32, i1 } [[TMP2218]], 1
-// CHECK-NEXT: [[TMP2221:%.*]] = select i1 [[TMP2220]], i32 [[TMP2216]], i32 [[TMP2219]]
-// CHECK-NEXT: store i32 [[TMP2221]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2222:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2223:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2224:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2222]], i32 [[TMP2223]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2225:%.*]] = extractvalue { i32, i1 } [[TMP2224]], 0
-// CHECK-NEXT: [[TMP2226:%.*]] = extractvalue { i32, i1 } [[TMP2224]], 1
-// CHECK-NEXT: [[TMP2227:%.*]] = select i1 [[TMP2226]], i32 [[TMP2222]], i32 [[TMP2225]]
-// CHECK-NEXT: store i32 [[TMP2227]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2228:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2229:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2230:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2228]], i32 [[TMP2229]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2231:%.*]] = extractvalue { i32, i1 } [[TMP2230]], 0
-// CHECK-NEXT: [[TMP2232:%.*]] = extractvalue { i32, i1 } [[TMP2230]], 1
-// CHECK-NEXT: br i1 [[TMP2232]], label [[IX_ATOMIC_EXIT215:%.*]], label [[IX_ATOMIC_CONT216:%.*]]
-// CHECK: ix.atomic.cont216:
-// CHECK-NEXT: store i32 [[TMP2231]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT215]]
-// CHECK: ix.atomic.exit215:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2233:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2234:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2235:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2233]], i32 [[TMP2234]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2236:%.*]] = extractvalue { i32, i1 } [[TMP2235]], 0
-// CHECK-NEXT: [[TMP2237:%.*]] = extractvalue { i32, i1 } [[TMP2235]], 1
-// CHECK-NEXT: br i1 [[TMP2237]], label [[IX_ATOMIC_EXIT217:%.*]], label [[IX_ATOMIC_CONT218:%.*]]
-// CHECK: ix.atomic.cont218:
-// CHECK-NEXT: store i32 [[TMP2236]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT217]]
-// CHECK: ix.atomic.exit217:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2238:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2239:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2240:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2238]], i32 [[TMP2239]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2241:%.*]] = extractvalue { i32, i1 } [[TMP2240]], 1
-// CHECK-NEXT: [[TMP2242:%.*]] = sext i1 [[TMP2241]] to i32
-// CHECK-NEXT: store i32 [[TMP2242]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2243:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2244:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2245:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2243]], i32 [[TMP2244]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2246:%.*]] = extractvalue { i32, i1 } [[TMP2245]], 1
-// CHECK-NEXT: [[TMP2247:%.*]] = sext i1 [[TMP2246]] to i32
-// CHECK-NEXT: store i32 [[TMP2247]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2248:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2249:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2250:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2248]], i32 [[TMP2249]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2251:%.*]] = extractvalue { i32, i1 } [[TMP2250]], 0
-// CHECK-NEXT: [[TMP2252:%.*]] = extractvalue { i32, i1 } [[TMP2250]], 1
-// CHECK-NEXT: br i1 [[TMP2252]], label [[IX_ATOMIC_EXIT219:%.*]], label [[IX_ATOMIC_CONT220:%.*]]
-// CHECK: ix.atomic.cont220:
-// CHECK-NEXT: store i32 [[TMP2251]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT219]]
-// CHECK: ix.atomic.exit219:
-// CHECK-NEXT: [[TMP2253:%.*]] = extractvalue { i32, i1 } [[TMP2250]], 1
-// CHECK-NEXT: [[TMP2254:%.*]] = sext i1 [[TMP2253]] to i32
-// CHECK-NEXT: store i32 [[TMP2254]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2255:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2256:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2257:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2255]], i32 [[TMP2256]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2258:%.*]] = extractvalue { i32, i1 } [[TMP2257]], 0
-// CHECK-NEXT: [[TMP2259:%.*]] = extractvalue { i32, i1 } [[TMP2257]], 1
-// CHECK-NEXT: br i1 [[TMP2259]], label [[IX_ATOMIC_EXIT221:%.*]], label [[IX_ATOMIC_CONT222:%.*]]
-// CHECK: ix.atomic.cont222:
-// CHECK-NEXT: store i32 [[TMP2258]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT221]]
-// CHECK: ix.atomic.exit221:
-// CHECK-NEXT: [[TMP2260:%.*]] = extractvalue { i32, i1 } [[TMP2257]], 1
-// CHECK-NEXT: [[TMP2261:%.*]] = sext i1 [[TMP2260]] to i32
-// CHECK-NEXT: store i32 [[TMP2261]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2262:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2263:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2262]] seq_cst, align 4
-// CHECK-NEXT: store i32 [[TMP2263]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2264:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2265:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2264]] seq_cst, align 4
-// CHECK-NEXT: store i32 [[TMP2265]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2266:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2267:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2266]] seq_cst, align 4
-// CHECK-NEXT: store i32 [[TMP2267]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2268:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2269:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2268]] seq_cst, align 4
-// CHECK-NEXT: store i32 [[TMP2269]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2270:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2271:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2272:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2270]], i32 [[TMP2271]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2273:%.*]] = extractvalue { i32, i1 } [[TMP2272]], 0
-// CHECK-NEXT: store i32 [[TMP2273]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2274:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2275:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2276:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2274]], i32 [[TMP2275]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2277:%.*]] = extractvalue { i32, i1 } [[TMP2276]], 0
-// CHECK-NEXT: store i32 [[TMP2277]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2278:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2279:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2278]] seq_cst, align 4
-// CHECK-NEXT: [[TMP2280:%.*]] = icmp sgt i32 [[TMP2279]], [[TMP2278]]
-// CHECK-NEXT: [[TMP2281:%.*]] = select i1 [[TMP2280]], i32 [[TMP2278]], i32 [[TMP2279]]
-// CHECK-NEXT: store i32 [[TMP2281]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2282:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2283:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2282]] seq_cst, align 4
-// CHECK-NEXT: [[TMP2284:%.*]] = icmp slt i32 [[TMP2283]], [[TMP2282]]
-// CHECK-NEXT: [[TMP2285:%.*]] = select i1 [[TMP2284]], i32 [[TMP2282]], i32 [[TMP2283]]
-// CHECK-NEXT: store i32 [[TMP2285]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2286:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2287:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP2286]] seq_cst, align 4
-// CHECK-NEXT: [[TMP2288:%.*]] = icmp slt i32 [[TMP2287]], [[TMP2286]]
-// CHECK-NEXT: [[TMP2289:%.*]] = select i1 [[TMP2288]], i32 [[TMP2286]], i32 [[TMP2287]]
-// CHECK-NEXT: store i32 [[TMP2289]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2290:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2291:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP2290]] seq_cst, align 4
-// CHECK-NEXT: [[TMP2292:%.*]] = icmp sgt i32 [[TMP2291]], [[TMP2290]]
-// CHECK-NEXT: [[TMP2293:%.*]] = select i1 [[TMP2292]], i32 [[TMP2290]], i32 [[TMP2291]]
-// CHECK-NEXT: store i32 [[TMP2293]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2294:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2295:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2296:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2294]], i32 [[TMP2295]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2297:%.*]] = extractvalue { i32, i1 } [[TMP2296]], 0
-// CHECK-NEXT: [[TMP2298:%.*]] = extractvalue { i32, i1 } [[TMP2296]], 1
-// CHECK-NEXT: [[TMP2299:%.*]] = select i1 [[TMP2298]], i32 [[TMP2294]], i32 [[TMP2297]]
-// CHECK-NEXT: store i32 [[TMP2299]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2300:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2301:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2302:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2300]], i32 [[TMP2301]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2303:%.*]] = extractvalue { i32, i1 } [[TMP2302]], 0
-// CHECK-NEXT: [[TMP2304:%.*]] = extractvalue { i32, i1 } [[TMP2302]], 1
-// CHECK-NEXT: [[TMP2305:%.*]] = select i1 [[TMP2304]], i32 [[TMP2300]], i32 [[TMP2303]]
-// CHECK-NEXT: store i32 [[TMP2305]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2306:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2307:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2308:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2306]], i32 [[TMP2307]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2309:%.*]] = extractvalue { i32, i1 } [[TMP2308]], 0
-// CHECK-NEXT: [[TMP2310:%.*]] = extractvalue { i32, i1 } [[TMP2308]], 1
-// CHECK-NEXT: br i1 [[TMP2310]], label [[IX_ATOMIC_EXIT223:%.*]], label [[IX_ATOMIC_CONT224:%.*]]
-// CHECK: ix.atomic.cont224:
-// CHECK-NEXT: store i32 [[TMP2309]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT223]]
-// CHECK: ix.atomic.exit223:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2311:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2312:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2313:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2311]], i32 [[TMP2312]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2314:%.*]] = extractvalue { i32, i1 } [[TMP2313]], 0
-// CHECK-NEXT: [[TMP2315:%.*]] = extractvalue { i32, i1 } [[TMP2313]], 1
-// CHECK-NEXT: br i1 [[TMP2315]], label [[IX_ATOMIC_EXIT225:%.*]], label [[IX_ATOMIC_CONT226:%.*]]
-// CHECK: ix.atomic.cont226:
-// CHECK-NEXT: store i32 [[TMP2314]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT225]]
-// CHECK: ix.atomic.exit225:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2316:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2317:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2318:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2316]], i32 [[TMP2317]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2319:%.*]] = extractvalue { i32, i1 } [[TMP2318]], 1
-// CHECK-NEXT: [[TMP2320:%.*]] = sext i1 [[TMP2319]] to i32
-// CHECK-NEXT: store i32 [[TMP2320]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2321:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2322:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2323:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2321]], i32 [[TMP2322]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2324:%.*]] = extractvalue { i32, i1 } [[TMP2323]], 1
-// CHECK-NEXT: [[TMP2325:%.*]] = sext i1 [[TMP2324]] to i32
-// CHECK-NEXT: store i32 [[TMP2325]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2326:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2327:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2328:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2326]], i32 [[TMP2327]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2329:%.*]] = extractvalue { i32, i1 } [[TMP2328]], 0
-// CHECK-NEXT: [[TMP2330:%.*]] = extractvalue { i32, i1 } [[TMP2328]], 1
-// CHECK-NEXT: br i1 [[TMP2330]], label [[IX_ATOMIC_EXIT227:%.*]], label [[IX_ATOMIC_CONT228:%.*]]
-// CHECK: ix.atomic.cont228:
-// CHECK-NEXT: store i32 [[TMP2329]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT227]]
-// CHECK: ix.atomic.exit227:
-// CHECK-NEXT: [[TMP2331:%.*]] = extractvalue { i32, i1 } [[TMP2328]], 1
-// CHECK-NEXT: [[TMP2332:%.*]] = sext i1 [[TMP2331]] to i32
-// CHECK-NEXT: store i32 [[TMP2332]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2333:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP2334:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP2335:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP2333]], i32 [[TMP2334]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2336:%.*]] = extractvalue { i32, i1 } [[TMP2335]], 0
-// CHECK-NEXT: [[TMP2337:%.*]] = extractvalue { i32, i1 } [[TMP2335]], 1
-// CHECK-NEXT: br i1 [[TMP2337]], label [[IX_ATOMIC_EXIT229:%.*]], label [[IX_ATOMIC_CONT230:%.*]]
-// CHECK: ix.atomic.cont230:
-// CHECK-NEXT: store i32 [[TMP2336]], ptr [[IV]], align 4
-// CHECK-NEXT: br label [[IX_ATOMIC_EXIT229]]
-// CHECK: ix.atomic.exit229:
-// CHECK-NEXT: [[TMP2338:%.*]] = extractvalue { i32, i1 } [[TMP2335]], 1
-// CHECK-NEXT: [[TMP2339:%.*]] = sext i1 [[TMP2338]] to i32
-// CHECK-NEXT: store i32 [[TMP2339]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2340:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2341:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2340]] monotonic, align 4
-// CHECK-NEXT: store i32 [[TMP2341]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2342:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2343:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2342]] monotonic, align 4
-// CHECK-NEXT: store i32 [[TMP2343]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2344:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2345:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2344]] monotonic, align 4
-// CHECK-NEXT: store i32 [[TMP2345]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2346:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2347:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2346]] monotonic, align 4
-// CHECK-NEXT: store i32 [[TMP2347]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2348:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2349:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2350:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2348]], i32 [[TMP2349]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2351:%.*]] = extractvalue { i32, i1 } [[TMP2350]], 0
-// CHECK-NEXT: store i32 [[TMP2351]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2352:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2353:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2354:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2352]], i32 [[TMP2353]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2355:%.*]] = extractvalue { i32, i1 } [[TMP2354]], 0
-// CHECK-NEXT: store i32 [[TMP2355]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2356:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2357:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2356]] monotonic, align 4
-// CHECK-NEXT: [[TMP2358:%.*]] = icmp ugt i32 [[TMP2357]], [[TMP2356]]
-// CHECK-NEXT: [[TMP2359:%.*]] = select i1 [[TMP2358]], i32 [[TMP2356]], i32 [[TMP2357]]
-// CHECK-NEXT: store i32 [[TMP2359]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2360:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2361:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2360]] monotonic, align 4
-// CHECK-NEXT: [[TMP2362:%.*]] = icmp ult i32 [[TMP2361]], [[TMP2360]]
-// CHECK-NEXT: [[TMP2363:%.*]] = select i1 [[TMP2362]], i32 [[TMP2360]], i32 [[TMP2361]]
-// CHECK-NEXT: store i32 [[TMP2363]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2364:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2365:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2364]] monotonic, align 4
-// CHECK-NEXT: [[TMP2366:%.*]] = icmp ult i32 [[TMP2365]], [[TMP2364]]
-// CHECK-NEXT: [[TMP2367:%.*]] = select i1 [[TMP2366]], i32 [[TMP2364]], i32 [[TMP2365]]
-// CHECK-NEXT: store i32 [[TMP2367]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2368:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2369:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2368]] monotonic, align 4
-// CHECK-NEXT: [[TMP2370:%.*]] = icmp ugt i32 [[TMP2369]], [[TMP2368]]
-// CHECK-NEXT: [[TMP2371:%.*]] = select i1 [[TMP2370]], i32 [[TMP2368]], i32 [[TMP2369]]
-// CHECK-NEXT: store i32 [[TMP2371]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2372:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2373:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2374:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2372]], i32 [[TMP2373]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2375:%.*]] = extractvalue { i32, i1 } [[TMP2374]], 0
-// CHECK-NEXT: [[TMP2376:%.*]] = extractvalue { i32, i1 } [[TMP2374]], 1
-// CHECK-NEXT: [[TMP2377:%.*]] = select i1 [[TMP2376]], i32 [[TMP2372]], i32 [[TMP2375]]
-// CHECK-NEXT: store i32 [[TMP2377]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2378:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2379:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2380:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2378]], i32 [[TMP2379]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2381:%.*]] = extractvalue { i32, i1 } [[TMP2380]], 0
-// CHECK-NEXT: [[TMP2382:%.*]] = extractvalue { i32, i1 } [[TMP2380]], 1
-// CHECK-NEXT: [[TMP2383:%.*]] = select i1 [[TMP2382]], i32 [[TMP2378]], i32 [[TMP2381]]
-// CHECK-NEXT: store i32 [[TMP2383]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2384:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2385:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2386:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2384]], i32 [[TMP2385]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2387:%.*]] = extractvalue { i32, i1 } [[TMP2386]], 0
-// CHECK-NEXT: [[TMP2388:%.*]] = extractvalue { i32, i1 } [[TMP2386]], 1
-// CHECK-NEXT: br i1 [[TMP2388]], label [[UIX_ATOMIC_EXIT:%.*]], label [[UIX_ATOMIC_CONT:%.*]]
+// CHECK-NEXT: [[TMP1186:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1187:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1186]], ptr [[IX_ATOMIC_EXPECTED_PTR2347]], align 4
+// CHECK-NEXT: store i32 [[TMP1187]], ptr [[IX_ATOMIC_DESIRED_PTR2348]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2350:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2347]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2351:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2348]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2352:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2350]], i32 [[IX_CMPXCHG_DESIRED2351]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2353:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2352]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2353]], ptr [[IX_ATOMIC_EXPECTED_PTR2349]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2354:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2352]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2355:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2349]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2354]], label [[IX_ATOMIC_EXIT2356:%.*]], label [[IX_ATOMIC_CONT2357:%.*]]
+// CHECK: ix.atomic.cont2357:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2355]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2356]]
+// CHECK: ix.atomic.exit2356:
+// CHECK-NEXT: [[TMP1188:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1189:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1188]], ptr [[IX_ATOMIC_EXPECTED_PTR2358]], align 4
+// CHECK-NEXT: store i32 [[TMP1189]], ptr [[IX_ATOMIC_DESIRED_PTR2359]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2361:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2358]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2362:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2359]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2363:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2361]], i32 [[IX_CMPXCHG_DESIRED2362]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2364:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2363]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2364]], ptr [[IX_ATOMIC_EXPECTED_PTR2360]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2365:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2363]], 1
+// CHECK-NEXT: [[TMP1190:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2365]] to i32
+// CHECK-NEXT: store i32 [[TMP1190]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP1191:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1192:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1191]], ptr [[IX_ATOMIC_EXPECTED_PTR2366]], align 4
+// CHECK-NEXT: store i32 [[TMP1192]], ptr [[IX_ATOMIC_DESIRED_PTR2367]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2369:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2366]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2370:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2367]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2371:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2369]], i32 [[IX_CMPXCHG_DESIRED2370]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2372:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2371]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2372]], ptr [[IX_ATOMIC_EXPECTED_PTR2368]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2373:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2371]], 1
+// CHECK-NEXT: [[TMP1193:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2373]] to i32
+// CHECK-NEXT: store i32 [[TMP1193]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP1194:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1195:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1194]], ptr [[IX_ATOMIC_EXPECTED_PTR2374]], align 4
+// CHECK-NEXT: store i32 [[TMP1195]], ptr [[IX_ATOMIC_DESIRED_PTR2375]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2377:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2374]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2378:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2375]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2379:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2377]], i32 [[IX_CMPXCHG_DESIRED2378]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2380:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2379]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2380]], ptr [[IX_ATOMIC_EXPECTED_PTR2376]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2381:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2379]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2382:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2376]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2381]], label [[IX_ATOMIC_EXIT2383:%.*]], label [[IX_ATOMIC_CONT2384:%.*]]
+// CHECK: ix.atomic.cont2384:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2382]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2383]]
+// CHECK: ix.atomic.exit2383:
+// CHECK-NEXT: [[TMP1196:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2381]] to i32
+// CHECK-NEXT: store i32 [[TMP1196]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP1197:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1198:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1197]], ptr [[IX_ATOMIC_EXPECTED_PTR2385]], align 4
+// CHECK-NEXT: store i32 [[TMP1198]], ptr [[IX_ATOMIC_DESIRED_PTR2386]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2388:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2385]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2389:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2386]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2390:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2388]], i32 [[IX_CMPXCHG_DESIRED2389]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2391:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2390]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2391]], ptr [[IX_ATOMIC_EXPECTED_PTR2387]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2392:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2390]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2393:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2387]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2392]], label [[IX_ATOMIC_EXIT2394:%.*]], label [[IX_ATOMIC_CONT2395:%.*]]
+// CHECK: ix.atomic.cont2395:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2393]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2394]]
+// CHECK: ix.atomic.exit2394:
+// CHECK-NEXT: [[TMP1199:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2392]] to i32
+// CHECK-NEXT: store i32 [[TMP1199]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP1200:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1201:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1200]] acq_rel, align 4
+// CHECK-NEXT: store i32 [[TMP1201]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1202:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1203:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1202]] acq_rel, align 4
+// CHECK-NEXT: store i32 [[TMP1203]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1204:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1205:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1204]] acq_rel, align 4
+// CHECK-NEXT: store i32 [[TMP1205]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1206:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1207:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1206]] acq_rel, align 4
+// CHECK-NEXT: store i32 [[TMP1207]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1208:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1209:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1208]], ptr [[IX_ATOMIC_EXPECTED_PTR2396]], align 4
+// CHECK-NEXT: store i32 [[TMP1209]], ptr [[IX_ATOMIC_DESIRED_PTR2397]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2399:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2396]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2400:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2397]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2401:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2399]], i32 [[IX_CMPXCHG_DESIRED2400]] acq_rel acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2402:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2401]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2402]], ptr [[IX_ATOMIC_EXPECTED_PTR2398]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2403:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2401]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2404:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2398]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2404]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1210:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1211:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1210]], ptr [[IX_ATOMIC_EXPECTED_PTR2405]], align 4
+// CHECK-NEXT: store i32 [[TMP1211]], ptr [[IX_ATOMIC_DESIRED_PTR2406]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2408:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2405]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2409:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2406]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2410:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2408]], i32 [[IX_CMPXCHG_DESIRED2409]] acq_rel acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2411:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2410]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2411]], ptr [[IX_ATOMIC_EXPECTED_PTR2407]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2412:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2410]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2413:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2407]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2413]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1212:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1213:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1212]] acq_rel, align 4
+// CHECK-NEXT: [[TMP1214:%.*]] = icmp sgt i32 [[TMP1213]], [[TMP1212]]
+// CHECK-NEXT: [[TMP1215:%.*]] = select i1 [[TMP1214]], i32 [[TMP1212]], i32 [[TMP1213]]
+// CHECK-NEXT: store i32 [[TMP1215]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1216:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1217:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1216]] acq_rel, align 4
+// CHECK-NEXT: [[TMP1218:%.*]] = icmp slt i32 [[TMP1217]], [[TMP1216]]
+// CHECK-NEXT: [[TMP1219:%.*]] = select i1 [[TMP1218]], i32 [[TMP1216]], i32 [[TMP1217]]
+// CHECK-NEXT: store i32 [[TMP1219]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1220:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1221:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1220]] acq_rel, align 4
+// CHECK-NEXT: [[TMP1222:%.*]] = icmp slt i32 [[TMP1221]], [[TMP1220]]
+// CHECK-NEXT: [[TMP1223:%.*]] = select i1 [[TMP1222]], i32 [[TMP1220]], i32 [[TMP1221]]
+// CHECK-NEXT: store i32 [[TMP1223]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1224:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1225:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1224]] acq_rel, align 4
+// CHECK-NEXT: [[TMP1226:%.*]] = icmp sgt i32 [[TMP1225]], [[TMP1224]]
+// CHECK-NEXT: [[TMP1227:%.*]] = select i1 [[TMP1226]], i32 [[TMP1224]], i32 [[TMP1225]]
+// CHECK-NEXT: store i32 [[TMP1227]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1228:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1229:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1228]], ptr [[IX_ATOMIC_EXPECTED_PTR2414]], align 4
+// CHECK-NEXT: store i32 [[TMP1229]], ptr [[IX_ATOMIC_DESIRED_PTR2415]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2417:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2414]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2418:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2415]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2419:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2417]], i32 [[IX_CMPXCHG_DESIRED2418]] acq_rel acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2420:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2419]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2420]], ptr [[IX_ATOMIC_EXPECTED_PTR2416]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2421:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2419]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2422:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2416]], align 4
+// CHECK-NEXT: [[IX_CAPTURE_CAPTURED2423:%.*]] = select i1 [[IX_CMPXCHG_SUCCESS2421]], i32 [[TMP1228]], i32 [[IX_CAPTURE_ACTUAL2422]]
+// CHECK-NEXT: store i32 [[IX_CAPTURE_CAPTURED2423]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1230:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1231:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1230]], ptr [[IX_ATOMIC_EXPECTED_PTR2424]], align 4
+// CHECK-NEXT: store i32 [[TMP1231]], ptr [[IX_ATOMIC_DESIRED_PTR2425]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2427:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2424]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2428:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2425]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2429:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2427]], i32 [[IX_CMPXCHG_DESIRED2428]] acq_rel acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2430:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2429]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2430]], ptr [[IX_ATOMIC_EXPECTED_PTR2426]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2431:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2429]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2432:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2426]], align 4
+// CHECK-NEXT: [[IX_CAPTURE_CAPTURED2433:%.*]] = select i1 [[IX_CMPXCHG_SUCCESS2431]], i32 [[TMP1230]], i32 [[IX_CAPTURE_ACTUAL2432]]
+// CHECK-NEXT: store i32 [[IX_CAPTURE_CAPTURED2433]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1232:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1233:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1232]], ptr [[IX_ATOMIC_EXPECTED_PTR2434]], align 4
+// CHECK-NEXT: store i32 [[TMP1233]], ptr [[IX_ATOMIC_DESIRED_PTR2435]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2437:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2434]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2438:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2435]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2439:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2437]], i32 [[IX_CMPXCHG_DESIRED2438]] acq_rel acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2440:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2439]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2440]], ptr [[IX_ATOMIC_EXPECTED_PTR2436]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2441:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2439]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2442:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2436]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2441]], label [[IX_ATOMIC_EXIT2443:%.*]], label [[IX_ATOMIC_CONT2444:%.*]]
+// CHECK: ix.atomic.cont2444:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2442]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2443]]
+// CHECK: ix.atomic.exit2443:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1234:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1235:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1234]], ptr [[IX_ATOMIC_EXPECTED_PTR2445]], align 4
+// CHECK-NEXT: store i32 [[TMP1235]], ptr [[IX_ATOMIC_DESIRED_PTR2446]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2448:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2445]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2449:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2446]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2450:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2448]], i32 [[IX_CMPXCHG_DESIRED2449]] acq_rel acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2451:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2450]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2451]], ptr [[IX_ATOMIC_EXPECTED_PTR2447]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2452:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2450]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2453:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2447]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2452]], label [[IX_ATOMIC_EXIT2454:%.*]], label [[IX_ATOMIC_CONT2455:%.*]]
+// CHECK: ix.atomic.cont2455:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2453]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2454]]
+// CHECK: ix.atomic.exit2454:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1236:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1237:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1236]], ptr [[IX_ATOMIC_EXPECTED_PTR2456]], align 4
+// CHECK-NEXT: store i32 [[TMP1237]], ptr [[IX_ATOMIC_DESIRED_PTR2457]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2459:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2456]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2460:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2457]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2461:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2459]], i32 [[IX_CMPXCHG_DESIRED2460]] acq_rel acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2462:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2461]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2462]], ptr [[IX_ATOMIC_EXPECTED_PTR2458]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2463:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2461]], 1
+// CHECK-NEXT: [[TMP1238:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2463]] to i32
+// CHECK-NEXT: store i32 [[TMP1238]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1239:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1240:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1239]], ptr [[IX_ATOMIC_EXPECTED_PTR2464]], align 4
+// CHECK-NEXT: store i32 [[TMP1240]], ptr [[IX_ATOMIC_DESIRED_PTR2465]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2467:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2464]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2468:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2465]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2469:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2467]], i32 [[IX_CMPXCHG_DESIRED2468]] acq_rel acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2470:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2469]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2470]], ptr [[IX_ATOMIC_EXPECTED_PTR2466]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2471:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2469]], 1
+// CHECK-NEXT: [[TMP1241:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2471]] to i32
+// CHECK-NEXT: store i32 [[TMP1241]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1242:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1243:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1242]], ptr [[IX_ATOMIC_EXPECTED_PTR2472]], align 4
+// CHECK-NEXT: store i32 [[TMP1243]], ptr [[IX_ATOMIC_DESIRED_PTR2473]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2475:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2472]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2476:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2473]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2477:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2475]], i32 [[IX_CMPXCHG_DESIRED2476]] acq_rel acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2478:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2477]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2478]], ptr [[IX_ATOMIC_EXPECTED_PTR2474]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2479:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2477]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2480:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2474]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2479]], label [[IX_ATOMIC_EXIT2481:%.*]], label [[IX_ATOMIC_CONT2482:%.*]]
+// CHECK: ix.atomic.cont2482:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2480]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2481]]
+// CHECK: ix.atomic.exit2481:
+// CHECK-NEXT: [[TMP1244:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2479]] to i32
+// CHECK-NEXT: store i32 [[TMP1244]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1245:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1246:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1245]], ptr [[IX_ATOMIC_EXPECTED_PTR2483]], align 4
+// CHECK-NEXT: store i32 [[TMP1246]], ptr [[IX_ATOMIC_DESIRED_PTR2484]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2486:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2483]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2487:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2484]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2488:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2486]], i32 [[IX_CMPXCHG_DESIRED2487]] acq_rel acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2489:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2488]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2489]], ptr [[IX_ATOMIC_EXPECTED_PTR2485]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2490:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2488]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2491:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2485]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2490]], label [[IX_ATOMIC_EXIT2492:%.*]], label [[IX_ATOMIC_CONT2493:%.*]]
+// CHECK: ix.atomic.cont2493:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2491]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2492]]
+// CHECK: ix.atomic.exit2492:
+// CHECK-NEXT: [[TMP1247:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2490]] to i32
+// CHECK-NEXT: store i32 [[TMP1247]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1248:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1249:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1248]] acquire, align 4
+// CHECK-NEXT: store i32 [[TMP1249]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1250:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1251:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1250]] acquire, align 4
+// CHECK-NEXT: store i32 [[TMP1251]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1252:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1253:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1252]] acquire, align 4
+// CHECK-NEXT: store i32 [[TMP1253]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1254:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1255:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1254]] acquire, align 4
+// CHECK-NEXT: store i32 [[TMP1255]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1256:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1257:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1256]], ptr [[IX_ATOMIC_EXPECTED_PTR2494]], align 4
+// CHECK-NEXT: store i32 [[TMP1257]], ptr [[IX_ATOMIC_DESIRED_PTR2495]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2497:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2494]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2498:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2495]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2499:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2497]], i32 [[IX_CMPXCHG_DESIRED2498]] acquire acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2500:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2499]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2500]], ptr [[IX_ATOMIC_EXPECTED_PTR2496]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2501:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2499]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2502:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2496]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2502]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1258:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1259:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1258]], ptr [[IX_ATOMIC_EXPECTED_PTR2503]], align 4
+// CHECK-NEXT: store i32 [[TMP1259]], ptr [[IX_ATOMIC_DESIRED_PTR2504]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2506:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2503]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2507:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2504]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2508:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2506]], i32 [[IX_CMPXCHG_DESIRED2507]] acquire acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2509:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2508]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2509]], ptr [[IX_ATOMIC_EXPECTED_PTR2505]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2510:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2508]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2511:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2505]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2511]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1260:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1261:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1260]] acquire, align 4
+// CHECK-NEXT: [[TMP1262:%.*]] = icmp sgt i32 [[TMP1261]], [[TMP1260]]
+// CHECK-NEXT: [[TMP1263:%.*]] = select i1 [[TMP1262]], i32 [[TMP1260]], i32 [[TMP1261]]
+// CHECK-NEXT: store i32 [[TMP1263]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1264:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1265:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1264]] acquire, align 4
+// CHECK-NEXT: [[TMP1266:%.*]] = icmp slt i32 [[TMP1265]], [[TMP1264]]
+// CHECK-NEXT: [[TMP1267:%.*]] = select i1 [[TMP1266]], i32 [[TMP1264]], i32 [[TMP1265]]
+// CHECK-NEXT: store i32 [[TMP1267]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1268:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1269:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1268]] acquire, align 4
+// CHECK-NEXT: [[TMP1270:%.*]] = icmp slt i32 [[TMP1269]], [[TMP1268]]
+// CHECK-NEXT: [[TMP1271:%.*]] = select i1 [[TMP1270]], i32 [[TMP1268]], i32 [[TMP1269]]
+// CHECK-NEXT: store i32 [[TMP1271]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1272:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1273:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1272]] acquire, align 4
+// CHECK-NEXT: [[TMP1274:%.*]] = icmp sgt i32 [[TMP1273]], [[TMP1272]]
+// CHECK-NEXT: [[TMP1275:%.*]] = select i1 [[TMP1274]], i32 [[TMP1272]], i32 [[TMP1273]]
+// CHECK-NEXT: store i32 [[TMP1275]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1276:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1277:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1276]], ptr [[IX_ATOMIC_EXPECTED_PTR2512]], align 4
+// CHECK-NEXT: store i32 [[TMP1277]], ptr [[IX_ATOMIC_DESIRED_PTR2513]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2515:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2512]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2516:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2513]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2517:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2515]], i32 [[IX_CMPXCHG_DESIRED2516]] acquire acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2518:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2517]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2518]], ptr [[IX_ATOMIC_EXPECTED_PTR2514]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2519:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2517]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2520:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2514]], align 4
+// CHECK-NEXT: [[IX_CAPTURE_CAPTURED2521:%.*]] = select i1 [[IX_CMPXCHG_SUCCESS2519]], i32 [[TMP1276]], i32 [[IX_CAPTURE_ACTUAL2520]]
+// CHECK-NEXT: store i32 [[IX_CAPTURE_CAPTURED2521]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1278:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1279:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1278]], ptr [[IX_ATOMIC_EXPECTED_PTR2522]], align 4
+// CHECK-NEXT: store i32 [[TMP1279]], ptr [[IX_ATOMIC_DESIRED_PTR2523]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2525:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2522]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2526:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2523]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2527:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2525]], i32 [[IX_CMPXCHG_DESIRED2526]] acquire acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2528:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2527]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2528]], ptr [[IX_ATOMIC_EXPECTED_PTR2524]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2529:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2527]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2530:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2524]], align 4
+// CHECK-NEXT: [[IX_CAPTURE_CAPTURED2531:%.*]] = select i1 [[IX_CMPXCHG_SUCCESS2529]], i32 [[TMP1278]], i32 [[IX_CAPTURE_ACTUAL2530]]
+// CHECK-NEXT: store i32 [[IX_CAPTURE_CAPTURED2531]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1280:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1281:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1280]], ptr [[IX_ATOMIC_EXPECTED_PTR2532]], align 4
+// CHECK-NEXT: store i32 [[TMP1281]], ptr [[IX_ATOMIC_DESIRED_PTR2533]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2535:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2532]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2536:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2533]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2537:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2535]], i32 [[IX_CMPXCHG_DESIRED2536]] acquire acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2538:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2537]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2538]], ptr [[IX_ATOMIC_EXPECTED_PTR2534]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2539:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2537]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2540:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2534]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2539]], label [[IX_ATOMIC_EXIT2541:%.*]], label [[IX_ATOMIC_CONT2542:%.*]]
+// CHECK: ix.atomic.cont2542:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2540]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2541]]
+// CHECK: ix.atomic.exit2541:
+// CHECK-NEXT: [[TMP1282:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1283:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1282]], ptr [[IX_ATOMIC_EXPECTED_PTR2543]], align 4
+// CHECK-NEXT: store i32 [[TMP1283]], ptr [[IX_ATOMIC_DESIRED_PTR2544]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2546:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2543]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2547:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2544]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2548:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2546]], i32 [[IX_CMPXCHG_DESIRED2547]] acquire acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2549:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2548]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2549]], ptr [[IX_ATOMIC_EXPECTED_PTR2545]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2550:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2548]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2551:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2545]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2550]], label [[IX_ATOMIC_EXIT2552:%.*]], label [[IX_ATOMIC_CONT2553:%.*]]
+// CHECK: ix.atomic.cont2553:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2551]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2552]]
+// CHECK: ix.atomic.exit2552:
+// CHECK-NEXT: [[TMP1284:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1285:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1284]], ptr [[IX_ATOMIC_EXPECTED_PTR2554]], align 4
+// CHECK-NEXT: store i32 [[TMP1285]], ptr [[IX_ATOMIC_DESIRED_PTR2555]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2557:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2554]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2558:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2555]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2559:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2557]], i32 [[IX_CMPXCHG_DESIRED2558]] acquire acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2560:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2559]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2560]], ptr [[IX_ATOMIC_EXPECTED_PTR2556]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2561:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2559]], 1
+// CHECK-NEXT: [[TMP1286:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2561]] to i32
+// CHECK-NEXT: store i32 [[TMP1286]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP1287:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1288:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1287]], ptr [[IX_ATOMIC_EXPECTED_PTR2562]], align 4
+// CHECK-NEXT: store i32 [[TMP1288]], ptr [[IX_ATOMIC_DESIRED_PTR2563]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2565:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2562]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2566:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2563]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2567:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2565]], i32 [[IX_CMPXCHG_DESIRED2566]] acquire acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2568:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2567]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2568]], ptr [[IX_ATOMIC_EXPECTED_PTR2564]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2569:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2567]], 1
+// CHECK-NEXT: [[TMP1289:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2569]] to i32
+// CHECK-NEXT: store i32 [[TMP1289]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP1290:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1291:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1290]], ptr [[IX_ATOMIC_EXPECTED_PTR2570]], align 4
+// CHECK-NEXT: store i32 [[TMP1291]], ptr [[IX_ATOMIC_DESIRED_PTR2571]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2573:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2570]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2574:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2571]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2575:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2573]], i32 [[IX_CMPXCHG_DESIRED2574]] acquire acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2576:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2575]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2576]], ptr [[IX_ATOMIC_EXPECTED_PTR2572]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2577:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2575]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2578:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2572]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2577]], label [[IX_ATOMIC_EXIT2579:%.*]], label [[IX_ATOMIC_CONT2580:%.*]]
+// CHECK: ix.atomic.cont2580:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2578]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2579]]
+// CHECK: ix.atomic.exit2579:
+// CHECK-NEXT: [[TMP1292:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2577]] to i32
+// CHECK-NEXT: store i32 [[TMP1292]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP1293:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1294:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1293]], ptr [[IX_ATOMIC_EXPECTED_PTR2581]], align 4
+// CHECK-NEXT: store i32 [[TMP1294]], ptr [[IX_ATOMIC_DESIRED_PTR2582]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2584:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2581]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2585:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2582]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2586:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2584]], i32 [[IX_CMPXCHG_DESIRED2585]] acquire acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2587:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2586]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2587]], ptr [[IX_ATOMIC_EXPECTED_PTR2583]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2588:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2586]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2589:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2583]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2588]], label [[IX_ATOMIC_EXIT2590:%.*]], label [[IX_ATOMIC_CONT2591:%.*]]
+// CHECK: ix.atomic.cont2591:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2589]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2590]]
+// CHECK: ix.atomic.exit2590:
+// CHECK-NEXT: [[TMP1295:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2588]] to i32
+// CHECK-NEXT: store i32 [[TMP1295]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP1296:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1297:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1296]] monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP1297]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1298:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1299:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1298]] monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP1299]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1300:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1301:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1300]] monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP1301]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1302:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1303:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1302]] monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP1303]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1304:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1305:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1304]], ptr [[IX_ATOMIC_EXPECTED_PTR2592]], align 4
+// CHECK-NEXT: store i32 [[TMP1305]], ptr [[IX_ATOMIC_DESIRED_PTR2593]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2595:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2592]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2596:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2593]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2597:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2595]], i32 [[IX_CMPXCHG_DESIRED2596]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2598:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2597]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2598]], ptr [[IX_ATOMIC_EXPECTED_PTR2594]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2599:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2597]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2600:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2594]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2600]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1306:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1307:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1306]], ptr [[IX_ATOMIC_EXPECTED_PTR2601]], align 4
+// CHECK-NEXT: store i32 [[TMP1307]], ptr [[IX_ATOMIC_DESIRED_PTR2602]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2604:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2601]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2605:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2602]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2606:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2604]], i32 [[IX_CMPXCHG_DESIRED2605]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2607:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2606]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2607]], ptr [[IX_ATOMIC_EXPECTED_PTR2603]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2608:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2606]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2609:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2603]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2609]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1308:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1309:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1308]] monotonic, align 4
+// CHECK-NEXT: [[TMP1310:%.*]] = icmp sgt i32 [[TMP1309]], [[TMP1308]]
+// CHECK-NEXT: [[TMP1311:%.*]] = select i1 [[TMP1310]], i32 [[TMP1308]], i32 [[TMP1309]]
+// CHECK-NEXT: store i32 [[TMP1311]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1312:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1313:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1312]] monotonic, align 4
+// CHECK-NEXT: [[TMP1314:%.*]] = icmp slt i32 [[TMP1313]], [[TMP1312]]
+// CHECK-NEXT: [[TMP1315:%.*]] = select i1 [[TMP1314]], i32 [[TMP1312]], i32 [[TMP1313]]
+// CHECK-NEXT: store i32 [[TMP1315]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1316:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1317:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1316]] monotonic, align 4
+// CHECK-NEXT: [[TMP1318:%.*]] = icmp slt i32 [[TMP1317]], [[TMP1316]]
+// CHECK-NEXT: [[TMP1319:%.*]] = select i1 [[TMP1318]], i32 [[TMP1316]], i32 [[TMP1317]]
+// CHECK-NEXT: store i32 [[TMP1319]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1320:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1321:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1320]] monotonic, align 4
+// CHECK-NEXT: [[TMP1322:%.*]] = icmp sgt i32 [[TMP1321]], [[TMP1320]]
+// CHECK-NEXT: [[TMP1323:%.*]] = select i1 [[TMP1322]], i32 [[TMP1320]], i32 [[TMP1321]]
+// CHECK-NEXT: store i32 [[TMP1323]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1324:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1325:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1324]], ptr [[IX_ATOMIC_EXPECTED_PTR2610]], align 4
+// CHECK-NEXT: store i32 [[TMP1325]], ptr [[IX_ATOMIC_DESIRED_PTR2611]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2613:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2610]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2614:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2611]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2615:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2613]], i32 [[IX_CMPXCHG_DESIRED2614]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2616:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2615]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2616]], ptr [[IX_ATOMIC_EXPECTED_PTR2612]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2617:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2615]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2618:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2612]], align 4
+// CHECK-NEXT: [[IX_CAPTURE_CAPTURED2619:%.*]] = select i1 [[IX_CMPXCHG_SUCCESS2617]], i32 [[TMP1324]], i32 [[IX_CAPTURE_ACTUAL2618]]
+// CHECK-NEXT: store i32 [[IX_CAPTURE_CAPTURED2619]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1326:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1327:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1326]], ptr [[IX_ATOMIC_EXPECTED_PTR2620]], align 4
+// CHECK-NEXT: store i32 [[TMP1327]], ptr [[IX_ATOMIC_DESIRED_PTR2621]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2623:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2620]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2624:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2621]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2625:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2623]], i32 [[IX_CMPXCHG_DESIRED2624]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2626:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2625]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2626]], ptr [[IX_ATOMIC_EXPECTED_PTR2622]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2627:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2625]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2628:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2622]], align 4
+// CHECK-NEXT: [[IX_CAPTURE_CAPTURED2629:%.*]] = select i1 [[IX_CMPXCHG_SUCCESS2627]], i32 [[TMP1326]], i32 [[IX_CAPTURE_ACTUAL2628]]
+// CHECK-NEXT: store i32 [[IX_CAPTURE_CAPTURED2629]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP1328:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1329:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1328]], ptr [[IX_ATOMIC_EXPECTED_PTR2630]], align 4
+// CHECK-NEXT: store i32 [[TMP1329]], ptr [[IX_ATOMIC_DESIRED_PTR2631]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2633:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2630]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2634:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2631]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2635:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2633]], i32 [[IX_CMPXCHG_DESIRED2634]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2636:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2635]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2636]], ptr [[IX_ATOMIC_EXPECTED_PTR2632]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2637:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2635]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2638:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2632]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2637]], label [[IX_ATOMIC_EXIT2639:%.*]], label [[IX_ATOMIC_CONT2640:%.*]]
+// CHECK: ix.atomic.cont2640:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2638]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2639]]
+// CHECK: ix.atomic.exit2639:
+// CHECK-NEXT: [[TMP1330:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1331:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1330]], ptr [[IX_ATOMIC_EXPECTED_PTR2641]], align 4
+// CHECK-NEXT: store i32 [[TMP1331]], ptr [[IX_ATOMIC_DESIRED_PTR2642]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2644:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2641]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2645:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2642]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2646:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2644]], i32 [[IX_CMPXCHG_DESIRED2645]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2647:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2646]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2647]], ptr [[IX_ATOMIC_EXPECTED_PTR2643]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2648:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2646]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2649:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2643]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2648]], label [[IX_ATOMIC_EXIT2650:%.*]], label [[IX_ATOMIC_CONT2651:%.*]]
+// CHECK: ix.atomic.cont2651:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2649]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2650]]
+// CHECK: ix.atomic.exit2650:
+// CHECK-NEXT: [[TMP1332:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1333:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1332]], ptr [[IX_ATOMIC_EXPECTED_PTR2652]], align 4
+// CHECK-NEXT: store i32 [[TMP1333]], ptr [[IX_ATOMIC_DESIRED_PTR2653]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2655:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2652]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2656:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2653]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2657:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2655]], i32 [[IX_CMPXCHG_DESIRED2656]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2658:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2657]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2658]], ptr [[IX_ATOMIC_EXPECTED_PTR2654]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2659:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2657]], 1
+// CHECK-NEXT: [[TMP1334:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2659]] to i32
+// CHECK-NEXT: store i32 [[TMP1334]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP1335:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1336:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1335]], ptr [[IX_ATOMIC_EXPECTED_PTR2660]], align 4
+// CHECK-NEXT: store i32 [[TMP1336]], ptr [[IX_ATOMIC_DESIRED_PTR2661]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2663:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2660]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2664:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2661]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2665:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2663]], i32 [[IX_CMPXCHG_DESIRED2664]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2666:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2665]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2666]], ptr [[IX_ATOMIC_EXPECTED_PTR2662]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2667:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2665]], 1
+// CHECK-NEXT: [[TMP1337:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2667]] to i32
+// CHECK-NEXT: store i32 [[TMP1337]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP1338:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1339:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1338]], ptr [[IX_ATOMIC_EXPECTED_PTR2668]], align 4
+// CHECK-NEXT: store i32 [[TMP1339]], ptr [[IX_ATOMIC_DESIRED_PTR2669]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2671:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2668]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2672:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2669]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2673:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2671]], i32 [[IX_CMPXCHG_DESIRED2672]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2674:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2673]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2674]], ptr [[IX_ATOMIC_EXPECTED_PTR2670]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2675:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2673]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2676:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2670]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2675]], label [[IX_ATOMIC_EXIT2677:%.*]], label [[IX_ATOMIC_CONT2678:%.*]]
+// CHECK: ix.atomic.cont2678:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2676]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2677]]
+// CHECK: ix.atomic.exit2677:
+// CHECK-NEXT: [[TMP1340:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2675]] to i32
+// CHECK-NEXT: store i32 [[TMP1340]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP1341:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1342:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1341]], ptr [[IX_ATOMIC_EXPECTED_PTR2679]], align 4
+// CHECK-NEXT: store i32 [[TMP1342]], ptr [[IX_ATOMIC_DESIRED_PTR2680]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2682:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2679]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2683:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2680]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2684:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2682]], i32 [[IX_CMPXCHG_DESIRED2683]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2685:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2684]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2685]], ptr [[IX_ATOMIC_EXPECTED_PTR2681]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2686:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2684]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2687:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2681]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2686]], label [[IX_ATOMIC_EXIT2688:%.*]], label [[IX_ATOMIC_CONT2689:%.*]]
+// CHECK: ix.atomic.cont2689:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2687]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2688]]
+// CHECK: ix.atomic.exit2688:
+// CHECK-NEXT: [[TMP1343:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2686]] to i32
+// CHECK-NEXT: store i32 [[TMP1343]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP1344:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1345:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1344]] release, align 4
+// CHECK-NEXT: store i32 [[TMP1345]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1346:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1347:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1346]] release, align 4
+// CHECK-NEXT: store i32 [[TMP1347]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1348:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1349:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1348]] release, align 4
+// CHECK-NEXT: store i32 [[TMP1349]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1350:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1351:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1350]] release, align 4
+// CHECK-NEXT: store i32 [[TMP1351]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1352:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1353:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1352]], ptr [[IX_ATOMIC_EXPECTED_PTR2690]], align 4
+// CHECK-NEXT: store i32 [[TMP1353]], ptr [[IX_ATOMIC_DESIRED_PTR2691]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2693:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2690]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2694:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2691]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2695:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2693]], i32 [[IX_CMPXCHG_DESIRED2694]] release monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2696:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2695]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2696]], ptr [[IX_ATOMIC_EXPECTED_PTR2692]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2697:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2695]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2698:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2692]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2698]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1354:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1355:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1354]], ptr [[IX_ATOMIC_EXPECTED_PTR2699]], align 4
+// CHECK-NEXT: store i32 [[TMP1355]], ptr [[IX_ATOMIC_DESIRED_PTR2700]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2702:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2699]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2703:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2700]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2704:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2702]], i32 [[IX_CMPXCHG_DESIRED2703]] release monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2705:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2704]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2705]], ptr [[IX_ATOMIC_EXPECTED_PTR2701]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2706:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2704]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2707:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2701]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2707]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1356:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1357:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1356]] release, align 4
+// CHECK-NEXT: [[TMP1358:%.*]] = icmp sgt i32 [[TMP1357]], [[TMP1356]]
+// CHECK-NEXT: [[TMP1359:%.*]] = select i1 [[TMP1358]], i32 [[TMP1356]], i32 [[TMP1357]]
+// CHECK-NEXT: store i32 [[TMP1359]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1360:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1361:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1360]] release, align 4
+// CHECK-NEXT: [[TMP1362:%.*]] = icmp slt i32 [[TMP1361]], [[TMP1360]]
+// CHECK-NEXT: [[TMP1363:%.*]] = select i1 [[TMP1362]], i32 [[TMP1360]], i32 [[TMP1361]]
+// CHECK-NEXT: store i32 [[TMP1363]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1364:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1365:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1364]] release, align 4
+// CHECK-NEXT: [[TMP1366:%.*]] = icmp slt i32 [[TMP1365]], [[TMP1364]]
+// CHECK-NEXT: [[TMP1367:%.*]] = select i1 [[TMP1366]], i32 [[TMP1364]], i32 [[TMP1365]]
+// CHECK-NEXT: store i32 [[TMP1367]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1368:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1369:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1368]] release, align 4
+// CHECK-NEXT: [[TMP1370:%.*]] = icmp sgt i32 [[TMP1369]], [[TMP1368]]
+// CHECK-NEXT: [[TMP1371:%.*]] = select i1 [[TMP1370]], i32 [[TMP1368]], i32 [[TMP1369]]
+// CHECK-NEXT: store i32 [[TMP1371]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1372:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1373:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1372]], ptr [[IX_ATOMIC_EXPECTED_PTR2708]], align 4
+// CHECK-NEXT: store i32 [[TMP1373]], ptr [[IX_ATOMIC_DESIRED_PTR2709]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2711:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2708]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2712:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2709]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2713:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2711]], i32 [[IX_CMPXCHG_DESIRED2712]] release monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2714:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2713]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2714]], ptr [[IX_ATOMIC_EXPECTED_PTR2710]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2715:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2713]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2716:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2710]], align 4
+// CHECK-NEXT: [[IX_CAPTURE_CAPTURED2717:%.*]] = select i1 [[IX_CMPXCHG_SUCCESS2715]], i32 [[TMP1372]], i32 [[IX_CAPTURE_ACTUAL2716]]
+// CHECK-NEXT: store i32 [[IX_CAPTURE_CAPTURED2717]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1374:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1375:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1374]], ptr [[IX_ATOMIC_EXPECTED_PTR2718]], align 4
+// CHECK-NEXT: store i32 [[TMP1375]], ptr [[IX_ATOMIC_DESIRED_PTR2719]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2721:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2718]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2722:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2719]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2723:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2721]], i32 [[IX_CMPXCHG_DESIRED2722]] release monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2724:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2723]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2724]], ptr [[IX_ATOMIC_EXPECTED_PTR2720]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2725:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2723]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2726:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2720]], align 4
+// CHECK-NEXT: [[IX_CAPTURE_CAPTURED2727:%.*]] = select i1 [[IX_CMPXCHG_SUCCESS2725]], i32 [[TMP1374]], i32 [[IX_CAPTURE_ACTUAL2726]]
+// CHECK-NEXT: store i32 [[IX_CAPTURE_CAPTURED2727]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1376:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1377:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1376]], ptr [[IX_ATOMIC_EXPECTED_PTR2728]], align 4
+// CHECK-NEXT: store i32 [[TMP1377]], ptr [[IX_ATOMIC_DESIRED_PTR2729]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2731:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2728]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2732:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2729]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2733:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2731]], i32 [[IX_CMPXCHG_DESIRED2732]] release monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2734:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2733]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2734]], ptr [[IX_ATOMIC_EXPECTED_PTR2730]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2735:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2733]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2736:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2730]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2735]], label [[IX_ATOMIC_EXIT2737:%.*]], label [[IX_ATOMIC_CONT2738:%.*]]
+// CHECK: ix.atomic.cont2738:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2736]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2737]]
+// CHECK: ix.atomic.exit2737:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1378:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1379:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1378]], ptr [[IX_ATOMIC_EXPECTED_PTR2739]], align 4
+// CHECK-NEXT: store i32 [[TMP1379]], ptr [[IX_ATOMIC_DESIRED_PTR2740]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2742:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2739]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2743:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2740]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2744:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2742]], i32 [[IX_CMPXCHG_DESIRED2743]] release monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2745:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2744]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2745]], ptr [[IX_ATOMIC_EXPECTED_PTR2741]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2746:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2744]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2747:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2741]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2746]], label [[IX_ATOMIC_EXIT2748:%.*]], label [[IX_ATOMIC_CONT2749:%.*]]
+// CHECK: ix.atomic.cont2749:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2747]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2748]]
+// CHECK: ix.atomic.exit2748:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1380:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1381:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1380]], ptr [[IX_ATOMIC_EXPECTED_PTR2750]], align 4
+// CHECK-NEXT: store i32 [[TMP1381]], ptr [[IX_ATOMIC_DESIRED_PTR2751]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2753:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2750]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2754:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2751]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2755:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2753]], i32 [[IX_CMPXCHG_DESIRED2754]] release monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2756:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2755]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2756]], ptr [[IX_ATOMIC_EXPECTED_PTR2752]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2757:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2755]], 1
+// CHECK-NEXT: [[TMP1382:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2757]] to i32
+// CHECK-NEXT: store i32 [[TMP1382]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1383:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1384:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1383]], ptr [[IX_ATOMIC_EXPECTED_PTR2758]], align 4
+// CHECK-NEXT: store i32 [[TMP1384]], ptr [[IX_ATOMIC_DESIRED_PTR2759]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2761:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2758]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2762:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2759]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2763:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2761]], i32 [[IX_CMPXCHG_DESIRED2762]] release monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2764:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2763]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2764]], ptr [[IX_ATOMIC_EXPECTED_PTR2760]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2765:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2763]], 1
+// CHECK-NEXT: [[TMP1385:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2765]] to i32
+// CHECK-NEXT: store i32 [[TMP1385]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1386:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1387:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1386]], ptr [[IX_ATOMIC_EXPECTED_PTR2766]], align 4
+// CHECK-NEXT: store i32 [[TMP1387]], ptr [[IX_ATOMIC_DESIRED_PTR2767]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2769:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2766]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2770:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2767]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2771:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2769]], i32 [[IX_CMPXCHG_DESIRED2770]] release monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2772:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2771]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2772]], ptr [[IX_ATOMIC_EXPECTED_PTR2768]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2773:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2771]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2774:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2768]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2773]], label [[IX_ATOMIC_EXIT2775:%.*]], label [[IX_ATOMIC_CONT2776:%.*]]
+// CHECK: ix.atomic.cont2776:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2774]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2775]]
+// CHECK: ix.atomic.exit2775:
+// CHECK-NEXT: [[TMP1388:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2773]] to i32
+// CHECK-NEXT: store i32 [[TMP1388]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1389:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1390:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1389]], ptr [[IX_ATOMIC_EXPECTED_PTR2777]], align 4
+// CHECK-NEXT: store i32 [[TMP1390]], ptr [[IX_ATOMIC_DESIRED_PTR2778]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2780:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2777]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2781:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2778]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2782:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2780]], i32 [[IX_CMPXCHG_DESIRED2781]] release monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2783:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2782]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2783]], ptr [[IX_ATOMIC_EXPECTED_PTR2779]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2784:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2782]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2785:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2779]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2784]], label [[IX_ATOMIC_EXIT2786:%.*]], label [[IX_ATOMIC_CONT2787:%.*]]
+// CHECK: ix.atomic.cont2787:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2785]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2786]]
+// CHECK: ix.atomic.exit2786:
+// CHECK-NEXT: [[TMP1391:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2784]] to i32
+// CHECK-NEXT: store i32 [[TMP1391]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1392:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1393:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1392]] seq_cst, align 4
+// CHECK-NEXT: store i32 [[TMP1393]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1394:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1395:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1394]] seq_cst, align 4
+// CHECK-NEXT: store i32 [[TMP1395]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1396:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1397:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1396]] seq_cst, align 4
+// CHECK-NEXT: store i32 [[TMP1397]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1398:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1399:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1398]] seq_cst, align 4
+// CHECK-NEXT: store i32 [[TMP1399]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1400:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1401:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1400]], ptr [[IX_ATOMIC_EXPECTED_PTR2788]], align 4
+// CHECK-NEXT: store i32 [[TMP1401]], ptr [[IX_ATOMIC_DESIRED_PTR2789]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2791:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2788]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2792:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2789]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2793:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2791]], i32 [[IX_CMPXCHG_DESIRED2792]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2794:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2793]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2794]], ptr [[IX_ATOMIC_EXPECTED_PTR2790]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2795:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2793]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2796:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2790]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2796]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1402:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1403:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1402]], ptr [[IX_ATOMIC_EXPECTED_PTR2797]], align 4
+// CHECK-NEXT: store i32 [[TMP1403]], ptr [[IX_ATOMIC_DESIRED_PTR2798]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2800:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2797]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2801:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2798]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2802:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2800]], i32 [[IX_CMPXCHG_DESIRED2801]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2803:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2802]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2803]], ptr [[IX_ATOMIC_EXPECTED_PTR2799]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2804:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2802]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2805:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2799]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2805]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1404:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1405:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1404]] seq_cst, align 4
+// CHECK-NEXT: [[TMP1406:%.*]] = icmp sgt i32 [[TMP1405]], [[TMP1404]]
+// CHECK-NEXT: [[TMP1407:%.*]] = select i1 [[TMP1406]], i32 [[TMP1404]], i32 [[TMP1405]]
+// CHECK-NEXT: store i32 [[TMP1407]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1408:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1409:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1408]] seq_cst, align 4
+// CHECK-NEXT: [[TMP1410:%.*]] = icmp slt i32 [[TMP1409]], [[TMP1408]]
+// CHECK-NEXT: [[TMP1411:%.*]] = select i1 [[TMP1410]], i32 [[TMP1408]], i32 [[TMP1409]]
+// CHECK-NEXT: store i32 [[TMP1411]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1412:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1413:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP1412]] seq_cst, align 4
+// CHECK-NEXT: [[TMP1414:%.*]] = icmp slt i32 [[TMP1413]], [[TMP1412]]
+// CHECK-NEXT: [[TMP1415:%.*]] = select i1 [[TMP1414]], i32 [[TMP1412]], i32 [[TMP1413]]
+// CHECK-NEXT: store i32 [[TMP1415]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1416:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1417:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP1416]] seq_cst, align 4
+// CHECK-NEXT: [[TMP1418:%.*]] = icmp sgt i32 [[TMP1417]], [[TMP1416]]
+// CHECK-NEXT: [[TMP1419:%.*]] = select i1 [[TMP1418]], i32 [[TMP1416]], i32 [[TMP1417]]
+// CHECK-NEXT: store i32 [[TMP1419]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1420:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1421:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1420]], ptr [[IX_ATOMIC_EXPECTED_PTR2806]], align 4
+// CHECK-NEXT: store i32 [[TMP1421]], ptr [[IX_ATOMIC_DESIRED_PTR2807]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2809:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2806]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2810:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2807]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2811:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2809]], i32 [[IX_CMPXCHG_DESIRED2810]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2812:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2811]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2812]], ptr [[IX_ATOMIC_EXPECTED_PTR2808]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2813:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2811]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2814:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2808]], align 4
+// CHECK-NEXT: [[IX_CAPTURE_CAPTURED2815:%.*]] = select i1 [[IX_CMPXCHG_SUCCESS2813]], i32 [[TMP1420]], i32 [[IX_CAPTURE_ACTUAL2814]]
+// CHECK-NEXT: store i32 [[IX_CAPTURE_CAPTURED2815]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1422:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1423:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1422]], ptr [[IX_ATOMIC_EXPECTED_PTR2816]], align 4
+// CHECK-NEXT: store i32 [[TMP1423]], ptr [[IX_ATOMIC_DESIRED_PTR2817]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2819:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2816]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2820:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2817]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2821:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2819]], i32 [[IX_CMPXCHG_DESIRED2820]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2822:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2821]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2822]], ptr [[IX_ATOMIC_EXPECTED_PTR2818]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2823:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2821]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2824:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2818]], align 4
+// CHECK-NEXT: [[IX_CAPTURE_CAPTURED2825:%.*]] = select i1 [[IX_CMPXCHG_SUCCESS2823]], i32 [[TMP1422]], i32 [[IX_CAPTURE_ACTUAL2824]]
+// CHECK-NEXT: store i32 [[IX_CAPTURE_CAPTURED2825]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1424:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1425:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1424]], ptr [[IX_ATOMIC_EXPECTED_PTR2826]], align 4
+// CHECK-NEXT: store i32 [[TMP1425]], ptr [[IX_ATOMIC_DESIRED_PTR2827]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2829:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2826]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2830:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2827]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2831:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2829]], i32 [[IX_CMPXCHG_DESIRED2830]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2832:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2831]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2832]], ptr [[IX_ATOMIC_EXPECTED_PTR2828]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2833:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2831]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2834:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2828]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2833]], label [[IX_ATOMIC_EXIT2835:%.*]], label [[IX_ATOMIC_CONT2836:%.*]]
+// CHECK: ix.atomic.cont2836:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2834]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2835]]
+// CHECK: ix.atomic.exit2835:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1426:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1427:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1426]], ptr [[IX_ATOMIC_EXPECTED_PTR2837]], align 4
+// CHECK-NEXT: store i32 [[TMP1427]], ptr [[IX_ATOMIC_DESIRED_PTR2838]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2840:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2837]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2841:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2838]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2842:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2840]], i32 [[IX_CMPXCHG_DESIRED2841]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2843:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2842]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2843]], ptr [[IX_ATOMIC_EXPECTED_PTR2839]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2844:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2842]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2845:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2839]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2844]], label [[IX_ATOMIC_EXIT2846:%.*]], label [[IX_ATOMIC_CONT2847:%.*]]
+// CHECK: ix.atomic.cont2847:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2845]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2846]]
+// CHECK: ix.atomic.exit2846:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1428:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1429:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1428]], ptr [[IX_ATOMIC_EXPECTED_PTR2848]], align 4
+// CHECK-NEXT: store i32 [[TMP1429]], ptr [[IX_ATOMIC_DESIRED_PTR2849]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2851:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2848]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2852:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2849]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2853:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2851]], i32 [[IX_CMPXCHG_DESIRED2852]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2854:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2853]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2854]], ptr [[IX_ATOMIC_EXPECTED_PTR2850]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2855:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2853]], 1
+// CHECK-NEXT: [[TMP1430:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2855]] to i32
+// CHECK-NEXT: store i32 [[TMP1430]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1431:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1432:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1431]], ptr [[IX_ATOMIC_EXPECTED_PTR2856]], align 4
+// CHECK-NEXT: store i32 [[TMP1432]], ptr [[IX_ATOMIC_DESIRED_PTR2857]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2859:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2856]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2860:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2857]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2861:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2859]], i32 [[IX_CMPXCHG_DESIRED2860]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2862:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2861]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2862]], ptr [[IX_ATOMIC_EXPECTED_PTR2858]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2863:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2861]], 1
+// CHECK-NEXT: [[TMP1433:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2863]] to i32
+// CHECK-NEXT: store i32 [[TMP1433]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1434:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1435:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1434]], ptr [[IX_ATOMIC_EXPECTED_PTR2864]], align 4
+// CHECK-NEXT: store i32 [[TMP1435]], ptr [[IX_ATOMIC_DESIRED_PTR2865]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2867:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2864]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2868:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2865]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2869:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2867]], i32 [[IX_CMPXCHG_DESIRED2868]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2870:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2869]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2870]], ptr [[IX_ATOMIC_EXPECTED_PTR2866]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2871:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2869]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2872:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2866]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2871]], label [[IX_ATOMIC_EXIT2873:%.*]], label [[IX_ATOMIC_CONT2874:%.*]]
+// CHECK: ix.atomic.cont2874:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2872]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2873]]
+// CHECK: ix.atomic.exit2873:
+// CHECK-NEXT: [[TMP1436:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2871]] to i32
+// CHECK-NEXT: store i32 [[TMP1436]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1437:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP1438:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP1437]], ptr [[IX_ATOMIC_EXPECTED_PTR2875]], align 4
+// CHECK-NEXT: store i32 [[TMP1438]], ptr [[IX_ATOMIC_DESIRED_PTR2876]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED2878:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2875]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED2879:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR2876]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR2880:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED2878]], i32 [[IX_CMPXCHG_DESIRED2879]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV2881:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2880]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV2881]], ptr [[IX_ATOMIC_EXPECTED_PTR2877]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS2882:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR2880]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL2883:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2877]], align 4
+// CHECK-NEXT: br i1 [[IX_CMPXCHG_SUCCESS2882]], label [[IX_ATOMIC_EXIT2884:%.*]], label [[IX_ATOMIC_CONT2885:%.*]]
+// CHECK: ix.atomic.cont2885:
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL2883]], ptr [[IV]], align 4
+// CHECK-NEXT: br label [[IX_ATOMIC_EXIT2884]]
+// CHECK: ix.atomic.exit2884:
+// CHECK-NEXT: [[TMP1439:%.*]] = sext i1 [[IX_CMPXCHG_SUCCESS2882]] to i32
+// CHECK-NEXT: store i32 [[TMP1439]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1440:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1441:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1440]] monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP1441]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1442:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1443:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1442]] monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP1443]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1444:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1445:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1444]] monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP1445]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1446:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1447:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1446]] monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP1447]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1448:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1449:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1448]], ptr [[UIX_ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: store i32 [[TMP1449]], ptr [[UIX_ATOMIC_DESIRED_PTR]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED]], i32 [[UIX_CMPXCHG_DESIRED]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV]], ptr [[UIX_ATOMIC_EXPECTED_PTR2886]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2886]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1450:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1451:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1450]], ptr [[UIX_ATOMIC_EXPECTED_PTR2887]], align 4
+// CHECK-NEXT: store i32 [[TMP1451]], ptr [[UIX_ATOMIC_DESIRED_PTR2888]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED2890:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2887]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED2891:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR2888]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR2892:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED2890]], i32 [[UIX_CMPXCHG_DESIRED2891]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV2893:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2892]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV2893]], ptr [[UIX_ATOMIC_EXPECTED_PTR2889]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS2894:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2892]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL2895:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2889]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL2895]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1452:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1453:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1452]] monotonic, align 4
+// CHECK-NEXT: [[TMP1454:%.*]] = icmp ugt i32 [[TMP1453]], [[TMP1452]]
+// CHECK-NEXT: [[TMP1455:%.*]] = select i1 [[TMP1454]], i32 [[TMP1452]], i32 [[TMP1453]]
+// CHECK-NEXT: store i32 [[TMP1455]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1456:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1457:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1456]] monotonic, align 4
+// CHECK-NEXT: [[TMP1458:%.*]] = icmp ult i32 [[TMP1457]], [[TMP1456]]
+// CHECK-NEXT: [[TMP1459:%.*]] = select i1 [[TMP1458]], i32 [[TMP1456]], i32 [[TMP1457]]
+// CHECK-NEXT: store i32 [[TMP1459]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1460:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1461:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1460]] monotonic, align 4
+// CHECK-NEXT: [[TMP1462:%.*]] = icmp ult i32 [[TMP1461]], [[TMP1460]]
+// CHECK-NEXT: [[TMP1463:%.*]] = select i1 [[TMP1462]], i32 [[TMP1460]], i32 [[TMP1461]]
+// CHECK-NEXT: store i32 [[TMP1463]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1464:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1465:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1464]] monotonic, align 4
+// CHECK-NEXT: [[TMP1466:%.*]] = icmp ugt i32 [[TMP1465]], [[TMP1464]]
+// CHECK-NEXT: [[TMP1467:%.*]] = select i1 [[TMP1466]], i32 [[TMP1464]], i32 [[TMP1465]]
+// CHECK-NEXT: store i32 [[TMP1467]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1468:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1469:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1468]], ptr [[UIX_ATOMIC_EXPECTED_PTR2896]], align 4
+// CHECK-NEXT: store i32 [[TMP1469]], ptr [[UIX_ATOMIC_DESIRED_PTR2897]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED2899:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2896]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED2900:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR2897]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR2901:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED2899]], i32 [[UIX_CMPXCHG_DESIRED2900]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV2902:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2901]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV2902]], ptr [[UIX_ATOMIC_EXPECTED_PTR2898]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS2903:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2901]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL2904:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2898]], align 4
+// CHECK-NEXT: [[UIX_CAPTURE_CAPTURED:%.*]] = select i1 [[UIX_CMPXCHG_SUCCESS2903]], i32 [[TMP1468]], i32 [[UIX_CAPTURE_ACTUAL2904]]
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_CAPTURED]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1470:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1471:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1470]], ptr [[UIX_ATOMIC_EXPECTED_PTR2905]], align 4
+// CHECK-NEXT: store i32 [[TMP1471]], ptr [[UIX_ATOMIC_DESIRED_PTR2906]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED2908:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2905]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED2909:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR2906]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR2910:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED2908]], i32 [[UIX_CMPXCHG_DESIRED2909]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV2911:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2910]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV2911]], ptr [[UIX_ATOMIC_EXPECTED_PTR2907]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS2912:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2910]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL2913:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2907]], align 4
+// CHECK-NEXT: [[UIX_CAPTURE_CAPTURED2914:%.*]] = select i1 [[UIX_CMPXCHG_SUCCESS2912]], i32 [[TMP1470]], i32 [[UIX_CAPTURE_ACTUAL2913]]
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_CAPTURED2914]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1472:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1473:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1472]], ptr [[UIX_ATOMIC_EXPECTED_PTR2915]], align 4
+// CHECK-NEXT: store i32 [[TMP1473]], ptr [[UIX_ATOMIC_DESIRED_PTR2916]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED2918:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2915]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED2919:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR2916]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR2920:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED2918]], i32 [[UIX_CMPXCHG_DESIRED2919]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV2921:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2920]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV2921]], ptr [[UIX_ATOMIC_EXPECTED_PTR2917]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS2922:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2920]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL2923:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2917]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS2922]], label [[UIX_ATOMIC_EXIT:%.*]], label [[UIX_ATOMIC_CONT:%.*]]
// CHECK: uix.atomic.cont:
-// CHECK-NEXT: store i32 [[TMP2387]], ptr [[UIV]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL2923]], ptr [[UIV]], align 4
// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT]]
// CHECK: uix.atomic.exit:
-// CHECK-NEXT: [[TMP2389:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2390:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2391:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2389]], i32 [[TMP2390]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2392:%.*]] = extractvalue { i32, i1 } [[TMP2391]], 0
-// CHECK-NEXT: [[TMP2393:%.*]] = extractvalue { i32, i1 } [[TMP2391]], 1
-// CHECK-NEXT: br i1 [[TMP2393]], label [[UIX_ATOMIC_EXIT231:%.*]], label [[UIX_ATOMIC_CONT232:%.*]]
-// CHECK: uix.atomic.cont232:
-// CHECK-NEXT: store i32 [[TMP2392]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT231]]
-// CHECK: uix.atomic.exit231:
-// CHECK-NEXT: [[TMP2394:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2395:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2396:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2394]], i32 [[TMP2395]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2397:%.*]] = extractvalue { i32, i1 } [[TMP2396]], 1
-// CHECK-NEXT: [[TMP2398:%.*]] = zext i1 [[TMP2397]] to i32
-// CHECK-NEXT: store i32 [[TMP2398]], ptr [[UIR]], align 4
-// CHECK-NEXT: [[TMP2399:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2400:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2401:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2399]], i32 [[TMP2400]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2402:%.*]] = extractvalue { i32, i1 } [[TMP2401]], 1
-// CHECK-NEXT: [[TMP2403:%.*]] = zext i1 [[TMP2402]] to i32
-// CHECK-NEXT: store i32 [[TMP2403]], ptr [[UIR]], align 4
-// CHECK-NEXT: [[TMP2404:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2405:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2406:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2404]], i32 [[TMP2405]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2407:%.*]] = extractvalue { i32, i1 } [[TMP2406]], 0
-// CHECK-NEXT: [[TMP2408:%.*]] = extractvalue { i32, i1 } [[TMP2406]], 1
-// CHECK-NEXT: br i1 [[TMP2408]], label [[UIX_ATOMIC_EXIT233:%.*]], label [[UIX_ATOMIC_CONT234:%.*]]
-// CHECK: uix.atomic.cont234:
-// CHECK-NEXT: store i32 [[TMP2407]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT233]]
-// CHECK: uix.atomic.exit233:
-// CHECK-NEXT: [[TMP2409:%.*]] = extractvalue { i32, i1 } [[TMP2406]], 1
-// CHECK-NEXT: [[TMP2410:%.*]] = zext i1 [[TMP2409]] to i32
-// CHECK-NEXT: store i32 [[TMP2410]], ptr [[UIR]], align 4
-// CHECK-NEXT: [[TMP2411:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2412:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2413:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2411]], i32 [[TMP2412]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2414:%.*]] = extractvalue { i32, i1 } [[TMP2413]], 0
-// CHECK-NEXT: [[TMP2415:%.*]] = extractvalue { i32, i1 } [[TMP2413]], 1
-// CHECK-NEXT: br i1 [[TMP2415]], label [[UIX_ATOMIC_EXIT235:%.*]], label [[UIX_ATOMIC_CONT236:%.*]]
-// CHECK: uix.atomic.cont236:
-// CHECK-NEXT: store i32 [[TMP2414]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT235]]
-// CHECK: uix.atomic.exit235:
-// CHECK-NEXT: [[TMP2416:%.*]] = extractvalue { i32, i1 } [[TMP2413]], 1
-// CHECK-NEXT: [[TMP2417:%.*]] = zext i1 [[TMP2416]] to i32
-// CHECK-NEXT: store i32 [[TMP2417]], ptr [[UIR]], align 4
-// CHECK-NEXT: [[TMP2418:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2419:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2418]] acq_rel, align 4
-// CHECK-NEXT: store i32 [[TMP2419]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2420:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2421:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2420]] acq_rel, align 4
-// CHECK-NEXT: store i32 [[TMP2421]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2422:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2423:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2422]] acq_rel, align 4
-// CHECK-NEXT: store i32 [[TMP2423]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2424:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2425:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2424]] acq_rel, align 4
-// CHECK-NEXT: store i32 [[TMP2425]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2426:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2427:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2428:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2426]], i32 [[TMP2427]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP2429:%.*]] = extractvalue { i32, i1 } [[TMP2428]], 0
-// CHECK-NEXT: store i32 [[TMP2429]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2430:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2431:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2432:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2430]], i32 [[TMP2431]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP2433:%.*]] = extractvalue { i32, i1 } [[TMP2432]], 0
-// CHECK-NEXT: store i32 [[TMP2433]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2434:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2435:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2434]] acq_rel, align 4
-// CHECK-NEXT: [[TMP2436:%.*]] = icmp ugt i32 [[TMP2435]], [[TMP2434]]
-// CHECK-NEXT: [[TMP2437:%.*]] = select i1 [[TMP2436]], i32 [[TMP2434]], i32 [[TMP2435]]
-// CHECK-NEXT: store i32 [[TMP2437]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2438:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2439:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2438]] acq_rel, align 4
-// CHECK-NEXT: [[TMP2440:%.*]] = icmp ult i32 [[TMP2439]], [[TMP2438]]
-// CHECK-NEXT: [[TMP2441:%.*]] = select i1 [[TMP2440]], i32 [[TMP2438]], i32 [[TMP2439]]
-// CHECK-NEXT: store i32 [[TMP2441]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2442:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2443:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2442]] acq_rel, align 4
-// CHECK-NEXT: [[TMP2444:%.*]] = icmp ult i32 [[TMP2443]], [[TMP2442]]
-// CHECK-NEXT: [[TMP2445:%.*]] = select i1 [[TMP2444]], i32 [[TMP2442]], i32 [[TMP2443]]
-// CHECK-NEXT: store i32 [[TMP2445]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2446:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2447:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2446]] acq_rel, align 4
-// CHECK-NEXT: [[TMP2448:%.*]] = icmp ugt i32 [[TMP2447]], [[TMP2446]]
-// CHECK-NEXT: [[TMP2449:%.*]] = select i1 [[TMP2448]], i32 [[TMP2446]], i32 [[TMP2447]]
-// CHECK-NEXT: store i32 [[TMP2449]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2450:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2451:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2452:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2450]], i32 [[TMP2451]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP2453:%.*]] = extractvalue { i32, i1 } [[TMP2452]], 0
-// CHECK-NEXT: [[TMP2454:%.*]] = extractvalue { i32, i1 } [[TMP2452]], 1
-// CHECK-NEXT: [[TMP2455:%.*]] = select i1 [[TMP2454]], i32 [[TMP2450]], i32 [[TMP2453]]
-// CHECK-NEXT: store i32 [[TMP2455]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2456:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2457:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2458:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2456]], i32 [[TMP2457]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP2459:%.*]] = extractvalue { i32, i1 } [[TMP2458]], 0
-// CHECK-NEXT: [[TMP2460:%.*]] = extractvalue { i32, i1 } [[TMP2458]], 1
-// CHECK-NEXT: [[TMP2461:%.*]] = select i1 [[TMP2460]], i32 [[TMP2456]], i32 [[TMP2459]]
-// CHECK-NEXT: store i32 [[TMP2461]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2462:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2463:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2464:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2462]], i32 [[TMP2463]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP2465:%.*]] = extractvalue { i32, i1 } [[TMP2464]], 0
-// CHECK-NEXT: [[TMP2466:%.*]] = extractvalue { i32, i1 } [[TMP2464]], 1
-// CHECK-NEXT: br i1 [[TMP2466]], label [[UIX_ATOMIC_EXIT237:%.*]], label [[UIX_ATOMIC_CONT238:%.*]]
-// CHECK: uix.atomic.cont238:
-// CHECK-NEXT: store i32 [[TMP2465]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT237]]
-// CHECK: uix.atomic.exit237:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2467:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2468:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2469:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2467]], i32 [[TMP2468]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP2470:%.*]] = extractvalue { i32, i1 } [[TMP2469]], 0
-// CHECK-NEXT: [[TMP2471:%.*]] = extractvalue { i32, i1 } [[TMP2469]], 1
-// CHECK-NEXT: br i1 [[TMP2471]], label [[UIX_ATOMIC_EXIT239:%.*]], label [[UIX_ATOMIC_CONT240:%.*]]
-// CHECK: uix.atomic.cont240:
-// CHECK-NEXT: store i32 [[TMP2470]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT239]]
-// CHECK: uix.atomic.exit239:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2472:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2473:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2474:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2472]], i32 [[TMP2473]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP2475:%.*]] = extractvalue { i32, i1 } [[TMP2474]], 1
-// CHECK-NEXT: [[TMP2476:%.*]] = zext i1 [[TMP2475]] to i32
-// CHECK-NEXT: store i32 [[TMP2476]], ptr [[UIR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2477:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2478:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2479:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2477]], i32 [[TMP2478]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP2480:%.*]] = extractvalue { i32, i1 } [[TMP2479]], 1
-// CHECK-NEXT: [[TMP2481:%.*]] = zext i1 [[TMP2480]] to i32
-// CHECK-NEXT: store i32 [[TMP2481]], ptr [[UIR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2482:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2483:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2484:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2482]], i32 [[TMP2483]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP2485:%.*]] = extractvalue { i32, i1 } [[TMP2484]], 0
-// CHECK-NEXT: [[TMP2486:%.*]] = extractvalue { i32, i1 } [[TMP2484]], 1
-// CHECK-NEXT: br i1 [[TMP2486]], label [[UIX_ATOMIC_EXIT241:%.*]], label [[UIX_ATOMIC_CONT242:%.*]]
-// CHECK: uix.atomic.cont242:
-// CHECK-NEXT: store i32 [[TMP2485]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT241]]
-// CHECK: uix.atomic.exit241:
-// CHECK-NEXT: [[TMP2487:%.*]] = extractvalue { i32, i1 } [[TMP2484]], 1
-// CHECK-NEXT: [[TMP2488:%.*]] = zext i1 [[TMP2487]] to i32
-// CHECK-NEXT: store i32 [[TMP2488]], ptr [[UIR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2489:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2490:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2491:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2489]], i32 [[TMP2490]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP2492:%.*]] = extractvalue { i32, i1 } [[TMP2491]], 0
-// CHECK-NEXT: [[TMP2493:%.*]] = extractvalue { i32, i1 } [[TMP2491]], 1
-// CHECK-NEXT: br i1 [[TMP2493]], label [[UIX_ATOMIC_EXIT243:%.*]], label [[UIX_ATOMIC_CONT244:%.*]]
-// CHECK: uix.atomic.cont244:
-// CHECK-NEXT: store i32 [[TMP2492]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT243]]
-// CHECK: uix.atomic.exit243:
-// CHECK-NEXT: [[TMP2494:%.*]] = extractvalue { i32, i1 } [[TMP2491]], 1
-// CHECK-NEXT: [[TMP2495:%.*]] = zext i1 [[TMP2494]] to i32
-// CHECK-NEXT: store i32 [[TMP2495]], ptr [[UIR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2496:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2497:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2496]] acquire, align 4
-// CHECK-NEXT: store i32 [[TMP2497]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2498:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2499:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2498]] acquire, align 4
-// CHECK-NEXT: store i32 [[TMP2499]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2500:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2501:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2500]] acquire, align 4
-// CHECK-NEXT: store i32 [[TMP2501]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2502:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2503:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2502]] acquire, align 4
-// CHECK-NEXT: store i32 [[TMP2503]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2504:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2505:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2506:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2504]], i32 [[TMP2505]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2507:%.*]] = extractvalue { i32, i1 } [[TMP2506]], 0
-// CHECK-NEXT: store i32 [[TMP2507]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2508:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2509:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2510:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2508]], i32 [[TMP2509]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2511:%.*]] = extractvalue { i32, i1 } [[TMP2510]], 0
-// CHECK-NEXT: store i32 [[TMP2511]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2512:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2513:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2512]] acquire, align 4
-// CHECK-NEXT: [[TMP2514:%.*]] = icmp ugt i32 [[TMP2513]], [[TMP2512]]
-// CHECK-NEXT: [[TMP2515:%.*]] = select i1 [[TMP2514]], i32 [[TMP2512]], i32 [[TMP2513]]
-// CHECK-NEXT: store i32 [[TMP2515]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2516:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2517:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2516]] acquire, align 4
-// CHECK-NEXT: [[TMP2518:%.*]] = icmp ult i32 [[TMP2517]], [[TMP2516]]
-// CHECK-NEXT: [[TMP2519:%.*]] = select i1 [[TMP2518]], i32 [[TMP2516]], i32 [[TMP2517]]
-// CHECK-NEXT: store i32 [[TMP2519]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2520:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2521:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2520]] acquire, align 4
-// CHECK-NEXT: [[TMP2522:%.*]] = icmp ult i32 [[TMP2521]], [[TMP2520]]
-// CHECK-NEXT: [[TMP2523:%.*]] = select i1 [[TMP2522]], i32 [[TMP2520]], i32 [[TMP2521]]
-// CHECK-NEXT: store i32 [[TMP2523]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2524:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2525:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2524]] acquire, align 4
-// CHECK-NEXT: [[TMP2526:%.*]] = icmp ugt i32 [[TMP2525]], [[TMP2524]]
-// CHECK-NEXT: [[TMP2527:%.*]] = select i1 [[TMP2526]], i32 [[TMP2524]], i32 [[TMP2525]]
-// CHECK-NEXT: store i32 [[TMP2527]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2528:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2529:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2530:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2528]], i32 [[TMP2529]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2531:%.*]] = extractvalue { i32, i1 } [[TMP2530]], 0
-// CHECK-NEXT: [[TMP2532:%.*]] = extractvalue { i32, i1 } [[TMP2530]], 1
-// CHECK-NEXT: [[TMP2533:%.*]] = select i1 [[TMP2532]], i32 [[TMP2528]], i32 [[TMP2531]]
-// CHECK-NEXT: store i32 [[TMP2533]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2534:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2535:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2536:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2534]], i32 [[TMP2535]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2537:%.*]] = extractvalue { i32, i1 } [[TMP2536]], 0
-// CHECK-NEXT: [[TMP2538:%.*]] = extractvalue { i32, i1 } [[TMP2536]], 1
-// CHECK-NEXT: [[TMP2539:%.*]] = select i1 [[TMP2538]], i32 [[TMP2534]], i32 [[TMP2537]]
-// CHECK-NEXT: store i32 [[TMP2539]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2540:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2541:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2542:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2540]], i32 [[TMP2541]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2543:%.*]] = extractvalue { i32, i1 } [[TMP2542]], 0
-// CHECK-NEXT: [[TMP2544:%.*]] = extractvalue { i32, i1 } [[TMP2542]], 1
-// CHECK-NEXT: br i1 [[TMP2544]], label [[UIX_ATOMIC_EXIT245:%.*]], label [[UIX_ATOMIC_CONT246:%.*]]
-// CHECK: uix.atomic.cont246:
-// CHECK-NEXT: store i32 [[TMP2543]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT245]]
-// CHECK: uix.atomic.exit245:
-// CHECK-NEXT: [[TMP2545:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2546:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2547:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2545]], i32 [[TMP2546]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2548:%.*]] = extractvalue { i32, i1 } [[TMP2547]], 0
-// CHECK-NEXT: [[TMP2549:%.*]] = extractvalue { i32, i1 } [[TMP2547]], 1
-// CHECK-NEXT: br i1 [[TMP2549]], label [[UIX_ATOMIC_EXIT247:%.*]], label [[UIX_ATOMIC_CONT248:%.*]]
-// CHECK: uix.atomic.cont248:
-// CHECK-NEXT: store i32 [[TMP2548]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT247]]
-// CHECK: uix.atomic.exit247:
-// CHECK-NEXT: [[TMP2550:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2551:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2552:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2550]], i32 [[TMP2551]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2553:%.*]] = extractvalue { i32, i1 } [[TMP2552]], 1
-// CHECK-NEXT: [[TMP2554:%.*]] = zext i1 [[TMP2553]] to i32
-// CHECK-NEXT: store i32 [[TMP2554]], ptr [[UIR]], align 4
-// CHECK-NEXT: [[TMP2555:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2556:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2557:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2555]], i32 [[TMP2556]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2558:%.*]] = extractvalue { i32, i1 } [[TMP2557]], 1
-// CHECK-NEXT: [[TMP2559:%.*]] = zext i1 [[TMP2558]] to i32
-// CHECK-NEXT: store i32 [[TMP2559]], ptr [[UIR]], align 4
-// CHECK-NEXT: [[TMP2560:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2561:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2562:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2560]], i32 [[TMP2561]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2563:%.*]] = extractvalue { i32, i1 } [[TMP2562]], 0
-// CHECK-NEXT: [[TMP2564:%.*]] = extractvalue { i32, i1 } [[TMP2562]], 1
-// CHECK-NEXT: br i1 [[TMP2564]], label [[UIX_ATOMIC_EXIT249:%.*]], label [[UIX_ATOMIC_CONT250:%.*]]
-// CHECK: uix.atomic.cont250:
-// CHECK-NEXT: store i32 [[TMP2563]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT249]]
-// CHECK: uix.atomic.exit249:
-// CHECK-NEXT: [[TMP2565:%.*]] = extractvalue { i32, i1 } [[TMP2562]], 1
-// CHECK-NEXT: [[TMP2566:%.*]] = zext i1 [[TMP2565]] to i32
-// CHECK-NEXT: store i32 [[TMP2566]], ptr [[UIR]], align 4
-// CHECK-NEXT: [[TMP2567:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2568:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2569:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2567]], i32 [[TMP2568]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP2570:%.*]] = extractvalue { i32, i1 } [[TMP2569]], 0
-// CHECK-NEXT: [[TMP2571:%.*]] = extractvalue { i32, i1 } [[TMP2569]], 1
-// CHECK-NEXT: br i1 [[TMP2571]], label [[UIX_ATOMIC_EXIT251:%.*]], label [[UIX_ATOMIC_CONT252:%.*]]
-// CHECK: uix.atomic.cont252:
-// CHECK-NEXT: store i32 [[TMP2570]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT251]]
-// CHECK: uix.atomic.exit251:
-// CHECK-NEXT: [[TMP2572:%.*]] = extractvalue { i32, i1 } [[TMP2569]], 1
-// CHECK-NEXT: [[TMP2573:%.*]] = zext i1 [[TMP2572]] to i32
-// CHECK-NEXT: store i32 [[TMP2573]], ptr [[UIR]], align 4
-// CHECK-NEXT: [[TMP2574:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2575:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2574]] monotonic, align 4
-// CHECK-NEXT: store i32 [[TMP2575]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2576:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2577:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2576]] monotonic, align 4
-// CHECK-NEXT: store i32 [[TMP2577]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2578:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2579:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2578]] monotonic, align 4
-// CHECK-NEXT: store i32 [[TMP2579]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2580:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2581:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2580]] monotonic, align 4
-// CHECK-NEXT: store i32 [[TMP2581]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2582:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2583:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2584:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2582]], i32 [[TMP2583]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2585:%.*]] = extractvalue { i32, i1 } [[TMP2584]], 0
-// CHECK-NEXT: store i32 [[TMP2585]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2586:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2587:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2588:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2586]], i32 [[TMP2587]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2589:%.*]] = extractvalue { i32, i1 } [[TMP2588]], 0
-// CHECK-NEXT: store i32 [[TMP2589]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2590:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2591:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2590]] monotonic, align 4
-// CHECK-NEXT: [[TMP2592:%.*]] = icmp ugt i32 [[TMP2591]], [[TMP2590]]
-// CHECK-NEXT: [[TMP2593:%.*]] = select i1 [[TMP2592]], i32 [[TMP2590]], i32 [[TMP2591]]
-// CHECK-NEXT: store i32 [[TMP2593]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2594:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2595:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2594]] monotonic, align 4
-// CHECK-NEXT: [[TMP2596:%.*]] = icmp ult i32 [[TMP2595]], [[TMP2594]]
-// CHECK-NEXT: [[TMP2597:%.*]] = select i1 [[TMP2596]], i32 [[TMP2594]], i32 [[TMP2595]]
-// CHECK-NEXT: store i32 [[TMP2597]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2598:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2599:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2598]] monotonic, align 4
-// CHECK-NEXT: [[TMP2600:%.*]] = icmp ult i32 [[TMP2599]], [[TMP2598]]
-// CHECK-NEXT: [[TMP2601:%.*]] = select i1 [[TMP2600]], i32 [[TMP2598]], i32 [[TMP2599]]
-// CHECK-NEXT: store i32 [[TMP2601]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2602:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2603:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2602]] monotonic, align 4
-// CHECK-NEXT: [[TMP2604:%.*]] = icmp ugt i32 [[TMP2603]], [[TMP2602]]
-// CHECK-NEXT: [[TMP2605:%.*]] = select i1 [[TMP2604]], i32 [[TMP2602]], i32 [[TMP2603]]
-// CHECK-NEXT: store i32 [[TMP2605]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2606:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2607:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2608:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2606]], i32 [[TMP2607]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2609:%.*]] = extractvalue { i32, i1 } [[TMP2608]], 0
-// CHECK-NEXT: [[TMP2610:%.*]] = extractvalue { i32, i1 } [[TMP2608]], 1
-// CHECK-NEXT: [[TMP2611:%.*]] = select i1 [[TMP2610]], i32 [[TMP2606]], i32 [[TMP2609]]
-// CHECK-NEXT: store i32 [[TMP2611]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2612:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2613:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2614:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2612]], i32 [[TMP2613]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2615:%.*]] = extractvalue { i32, i1 } [[TMP2614]], 0
-// CHECK-NEXT: [[TMP2616:%.*]] = extractvalue { i32, i1 } [[TMP2614]], 1
-// CHECK-NEXT: [[TMP2617:%.*]] = select i1 [[TMP2616]], i32 [[TMP2612]], i32 [[TMP2615]]
-// CHECK-NEXT: store i32 [[TMP2617]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP2618:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2619:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2620:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2618]], i32 [[TMP2619]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2621:%.*]] = extractvalue { i32, i1 } [[TMP2620]], 0
-// CHECK-NEXT: [[TMP2622:%.*]] = extractvalue { i32, i1 } [[TMP2620]], 1
-// CHECK-NEXT: br i1 [[TMP2622]], label [[UIX_ATOMIC_EXIT253:%.*]], label [[UIX_ATOMIC_CONT254:%.*]]
-// CHECK: uix.atomic.cont254:
-// CHECK-NEXT: store i32 [[TMP2621]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT253]]
-// CHECK: uix.atomic.exit253:
-// CHECK-NEXT: [[TMP2623:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2624:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2625:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2623]], i32 [[TMP2624]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2626:%.*]] = extractvalue { i32, i1 } [[TMP2625]], 0
-// CHECK-NEXT: [[TMP2627:%.*]] = extractvalue { i32, i1 } [[TMP2625]], 1
-// CHECK-NEXT: br i1 [[TMP2627]], label [[UIX_ATOMIC_EXIT255:%.*]], label [[UIX_ATOMIC_CONT256:%.*]]
-// CHECK: uix.atomic.cont256:
-// CHECK-NEXT: store i32 [[TMP2626]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT255]]
-// CHECK: uix.atomic.exit255:
-// CHECK-NEXT: [[TMP2628:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2629:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2630:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2628]], i32 [[TMP2629]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2631:%.*]] = extractvalue { i32, i1 } [[TMP2630]], 1
-// CHECK-NEXT: [[TMP2632:%.*]] = zext i1 [[TMP2631]] to i32
-// CHECK-NEXT: store i32 [[TMP2632]], ptr [[UIR]], align 4
-// CHECK-NEXT: [[TMP2633:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2634:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2635:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2633]], i32 [[TMP2634]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2636:%.*]] = extractvalue { i32, i1 } [[TMP2635]], 1
-// CHECK-NEXT: [[TMP2637:%.*]] = zext i1 [[TMP2636]] to i32
-// CHECK-NEXT: store i32 [[TMP2637]], ptr [[UIR]], align 4
-// CHECK-NEXT: [[TMP2638:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2639:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2640:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2638]], i32 [[TMP2639]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2641:%.*]] = extractvalue { i32, i1 } [[TMP2640]], 0
-// CHECK-NEXT: [[TMP2642:%.*]] = extractvalue { i32, i1 } [[TMP2640]], 1
-// CHECK-NEXT: br i1 [[TMP2642]], label [[UIX_ATOMIC_EXIT257:%.*]], label [[UIX_ATOMIC_CONT258:%.*]]
-// CHECK: uix.atomic.cont258:
-// CHECK-NEXT: store i32 [[TMP2641]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT257]]
-// CHECK: uix.atomic.exit257:
-// CHECK-NEXT: [[TMP2643:%.*]] = extractvalue { i32, i1 } [[TMP2640]], 1
-// CHECK-NEXT: [[TMP2644:%.*]] = zext i1 [[TMP2643]] to i32
-// CHECK-NEXT: store i32 [[TMP2644]], ptr [[UIR]], align 4
-// CHECK-NEXT: [[TMP2645:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2646:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2647:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2645]], i32 [[TMP2646]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP2648:%.*]] = extractvalue { i32, i1 } [[TMP2647]], 0
-// CHECK-NEXT: [[TMP2649:%.*]] = extractvalue { i32, i1 } [[TMP2647]], 1
-// CHECK-NEXT: br i1 [[TMP2649]], label [[UIX_ATOMIC_EXIT259:%.*]], label [[UIX_ATOMIC_CONT260:%.*]]
-// CHECK: uix.atomic.cont260:
-// CHECK-NEXT: store i32 [[TMP2648]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT259]]
-// CHECK: uix.atomic.exit259:
-// CHECK-NEXT: [[TMP2650:%.*]] = extractvalue { i32, i1 } [[TMP2647]], 1
-// CHECK-NEXT: [[TMP2651:%.*]] = zext i1 [[TMP2650]] to i32
-// CHECK-NEXT: store i32 [[TMP2651]], ptr [[UIR]], align 4
-// CHECK-NEXT: [[TMP2652:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2653:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2652]] release, align 4
-// CHECK-NEXT: store i32 [[TMP2653]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2654:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2655:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2654]] release, align 4
-// CHECK-NEXT: store i32 [[TMP2655]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2656:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2657:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2656]] release, align 4
-// CHECK-NEXT: store i32 [[TMP2657]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2658:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2659:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2658]] release, align 4
-// CHECK-NEXT: store i32 [[TMP2659]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2660:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2661:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2662:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2660]], i32 [[TMP2661]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2663:%.*]] = extractvalue { i32, i1 } [[TMP2662]], 0
-// CHECK-NEXT: store i32 [[TMP2663]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2664:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2665:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2666:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2664]], i32 [[TMP2665]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2667:%.*]] = extractvalue { i32, i1 } [[TMP2666]], 0
-// CHECK-NEXT: store i32 [[TMP2667]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2668:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2669:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2668]] release, align 4
-// CHECK-NEXT: [[TMP2670:%.*]] = icmp ugt i32 [[TMP2669]], [[TMP2668]]
-// CHECK-NEXT: [[TMP2671:%.*]] = select i1 [[TMP2670]], i32 [[TMP2668]], i32 [[TMP2669]]
-// CHECK-NEXT: store i32 [[TMP2671]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2672:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2673:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2672]] release, align 4
-// CHECK-NEXT: [[TMP2674:%.*]] = icmp ult i32 [[TMP2673]], [[TMP2672]]
-// CHECK-NEXT: [[TMP2675:%.*]] = select i1 [[TMP2674]], i32 [[TMP2672]], i32 [[TMP2673]]
-// CHECK-NEXT: store i32 [[TMP2675]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2676:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2677:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2676]] release, align 4
-// CHECK-NEXT: [[TMP2678:%.*]] = icmp ult i32 [[TMP2677]], [[TMP2676]]
-// CHECK-NEXT: [[TMP2679:%.*]] = select i1 [[TMP2678]], i32 [[TMP2676]], i32 [[TMP2677]]
-// CHECK-NEXT: store i32 [[TMP2679]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2680:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2681:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2680]] release, align 4
-// CHECK-NEXT: [[TMP2682:%.*]] = icmp ugt i32 [[TMP2681]], [[TMP2680]]
-// CHECK-NEXT: [[TMP2683:%.*]] = select i1 [[TMP2682]], i32 [[TMP2680]], i32 [[TMP2681]]
-// CHECK-NEXT: store i32 [[TMP2683]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2684:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2685:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2686:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2684]], i32 [[TMP2685]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2687:%.*]] = extractvalue { i32, i1 } [[TMP2686]], 0
-// CHECK-NEXT: [[TMP2688:%.*]] = extractvalue { i32, i1 } [[TMP2686]], 1
-// CHECK-NEXT: [[TMP2689:%.*]] = select i1 [[TMP2688]], i32 [[TMP2684]], i32 [[TMP2687]]
-// CHECK-NEXT: store i32 [[TMP2689]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2690:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2691:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2692:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2690]], i32 [[TMP2691]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2693:%.*]] = extractvalue { i32, i1 } [[TMP2692]], 0
-// CHECK-NEXT: [[TMP2694:%.*]] = extractvalue { i32, i1 } [[TMP2692]], 1
-// CHECK-NEXT: [[TMP2695:%.*]] = select i1 [[TMP2694]], i32 [[TMP2690]], i32 [[TMP2693]]
-// CHECK-NEXT: store i32 [[TMP2695]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2696:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2697:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2698:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2696]], i32 [[TMP2697]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2699:%.*]] = extractvalue { i32, i1 } [[TMP2698]], 0
-// CHECK-NEXT: [[TMP2700:%.*]] = extractvalue { i32, i1 } [[TMP2698]], 1
-// CHECK-NEXT: br i1 [[TMP2700]], label [[UIX_ATOMIC_EXIT261:%.*]], label [[UIX_ATOMIC_CONT262:%.*]]
-// CHECK: uix.atomic.cont262:
-// CHECK-NEXT: store i32 [[TMP2699]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT261]]
-// CHECK: uix.atomic.exit261:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2701:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2702:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2703:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2701]], i32 [[TMP2702]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2704:%.*]] = extractvalue { i32, i1 } [[TMP2703]], 0
-// CHECK-NEXT: [[TMP2705:%.*]] = extractvalue { i32, i1 } [[TMP2703]], 1
-// CHECK-NEXT: br i1 [[TMP2705]], label [[UIX_ATOMIC_EXIT263:%.*]], label [[UIX_ATOMIC_CONT264:%.*]]
-// CHECK: uix.atomic.cont264:
-// CHECK-NEXT: store i32 [[TMP2704]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT263]]
-// CHECK: uix.atomic.exit263:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2706:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2707:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2708:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2706]], i32 [[TMP2707]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2709:%.*]] = extractvalue { i32, i1 } [[TMP2708]], 1
-// CHECK-NEXT: [[TMP2710:%.*]] = zext i1 [[TMP2709]] to i32
-// CHECK-NEXT: store i32 [[TMP2710]], ptr [[UIR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2711:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2712:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2713:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2711]], i32 [[TMP2712]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2714:%.*]] = extractvalue { i32, i1 } [[TMP2713]], 1
-// CHECK-NEXT: [[TMP2715:%.*]] = zext i1 [[TMP2714]] to i32
-// CHECK-NEXT: store i32 [[TMP2715]], ptr [[UIR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2716:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2717:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2718:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2716]], i32 [[TMP2717]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2719:%.*]] = extractvalue { i32, i1 } [[TMP2718]], 0
-// CHECK-NEXT: [[TMP2720:%.*]] = extractvalue { i32, i1 } [[TMP2718]], 1
-// CHECK-NEXT: br i1 [[TMP2720]], label [[UIX_ATOMIC_EXIT265:%.*]], label [[UIX_ATOMIC_CONT266:%.*]]
-// CHECK: uix.atomic.cont266:
-// CHECK-NEXT: store i32 [[TMP2719]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT265]]
-// CHECK: uix.atomic.exit265:
-// CHECK-NEXT: [[TMP2721:%.*]] = extractvalue { i32, i1 } [[TMP2718]], 1
-// CHECK-NEXT: [[TMP2722:%.*]] = zext i1 [[TMP2721]] to i32
-// CHECK-NEXT: store i32 [[TMP2722]], ptr [[UIR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2723:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2724:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2725:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2723]], i32 [[TMP2724]] release monotonic, align 4
-// CHECK-NEXT: [[TMP2726:%.*]] = extractvalue { i32, i1 } [[TMP2725]], 0
-// CHECK-NEXT: [[TMP2727:%.*]] = extractvalue { i32, i1 } [[TMP2725]], 1
-// CHECK-NEXT: br i1 [[TMP2727]], label [[UIX_ATOMIC_EXIT267:%.*]], label [[UIX_ATOMIC_CONT268:%.*]]
-// CHECK: uix.atomic.cont268:
-// CHECK-NEXT: store i32 [[TMP2726]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT267]]
-// CHECK: uix.atomic.exit267:
-// CHECK-NEXT: [[TMP2728:%.*]] = extractvalue { i32, i1 } [[TMP2725]], 1
-// CHECK-NEXT: [[TMP2729:%.*]] = zext i1 [[TMP2728]] to i32
-// CHECK-NEXT: store i32 [[TMP2729]], ptr [[UIR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2730:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2731:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2730]] seq_cst, align 4
-// CHECK-NEXT: store i32 [[TMP2731]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2732:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2733:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2732]] seq_cst, align 4
-// CHECK-NEXT: store i32 [[TMP2733]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2734:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2735:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2734]] seq_cst, align 4
-// CHECK-NEXT: store i32 [[TMP2735]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2736:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2737:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2736]] seq_cst, align 4
-// CHECK-NEXT: store i32 [[TMP2737]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2738:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2739:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2740:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2738]], i32 [[TMP2739]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2741:%.*]] = extractvalue { i32, i1 } [[TMP2740]], 0
-// CHECK-NEXT: store i32 [[TMP2741]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2742:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2743:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2744:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2742]], i32 [[TMP2743]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2745:%.*]] = extractvalue { i32, i1 } [[TMP2744]], 0
-// CHECK-NEXT: store i32 [[TMP2745]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2746:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2747:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2746]] seq_cst, align 4
-// CHECK-NEXT: [[TMP2748:%.*]] = icmp ugt i32 [[TMP2747]], [[TMP2746]]
-// CHECK-NEXT: [[TMP2749:%.*]] = select i1 [[TMP2748]], i32 [[TMP2746]], i32 [[TMP2747]]
-// CHECK-NEXT: store i32 [[TMP2749]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2750:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2751:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2750]] seq_cst, align 4
-// CHECK-NEXT: [[TMP2752:%.*]] = icmp ult i32 [[TMP2751]], [[TMP2750]]
-// CHECK-NEXT: [[TMP2753:%.*]] = select i1 [[TMP2752]], i32 [[TMP2750]], i32 [[TMP2751]]
-// CHECK-NEXT: store i32 [[TMP2753]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2754:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2755:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP2754]] seq_cst, align 4
-// CHECK-NEXT: [[TMP2756:%.*]] = icmp ult i32 [[TMP2755]], [[TMP2754]]
-// CHECK-NEXT: [[TMP2757:%.*]] = select i1 [[TMP2756]], i32 [[TMP2754]], i32 [[TMP2755]]
-// CHECK-NEXT: store i32 [[TMP2757]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2758:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2759:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP2758]] seq_cst, align 4
-// CHECK-NEXT: [[TMP2760:%.*]] = icmp ugt i32 [[TMP2759]], [[TMP2758]]
-// CHECK-NEXT: [[TMP2761:%.*]] = select i1 [[TMP2760]], i32 [[TMP2758]], i32 [[TMP2759]]
-// CHECK-NEXT: store i32 [[TMP2761]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2762:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2763:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2764:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2762]], i32 [[TMP2763]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2765:%.*]] = extractvalue { i32, i1 } [[TMP2764]], 0
-// CHECK-NEXT: [[TMP2766:%.*]] = extractvalue { i32, i1 } [[TMP2764]], 1
-// CHECK-NEXT: [[TMP2767:%.*]] = select i1 [[TMP2766]], i32 [[TMP2762]], i32 [[TMP2765]]
-// CHECK-NEXT: store i32 [[TMP2767]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2768:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2769:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2770:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2768]], i32 [[TMP2769]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2771:%.*]] = extractvalue { i32, i1 } [[TMP2770]], 0
-// CHECK-NEXT: [[TMP2772:%.*]] = extractvalue { i32, i1 } [[TMP2770]], 1
-// CHECK-NEXT: [[TMP2773:%.*]] = select i1 [[TMP2772]], i32 [[TMP2768]], i32 [[TMP2771]]
-// CHECK-NEXT: store i32 [[TMP2773]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2774:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2775:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2776:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2774]], i32 [[TMP2775]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2777:%.*]] = extractvalue { i32, i1 } [[TMP2776]], 0
-// CHECK-NEXT: [[TMP2778:%.*]] = extractvalue { i32, i1 } [[TMP2776]], 1
-// CHECK-NEXT: br i1 [[TMP2778]], label [[UIX_ATOMIC_EXIT269:%.*]], label [[UIX_ATOMIC_CONT270:%.*]]
-// CHECK: uix.atomic.cont270:
-// CHECK-NEXT: store i32 [[TMP2777]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT269]]
-// CHECK: uix.atomic.exit269:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2779:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2780:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2781:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2779]], i32 [[TMP2780]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2782:%.*]] = extractvalue { i32, i1 } [[TMP2781]], 0
-// CHECK-NEXT: [[TMP2783:%.*]] = extractvalue { i32, i1 } [[TMP2781]], 1
-// CHECK-NEXT: br i1 [[TMP2783]], label [[UIX_ATOMIC_EXIT271:%.*]], label [[UIX_ATOMIC_CONT272:%.*]]
-// CHECK: uix.atomic.cont272:
-// CHECK-NEXT: store i32 [[TMP2782]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT271]]
-// CHECK: uix.atomic.exit271:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2784:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2785:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2786:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2784]], i32 [[TMP2785]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2787:%.*]] = extractvalue { i32, i1 } [[TMP2786]], 1
-// CHECK-NEXT: [[TMP2788:%.*]] = zext i1 [[TMP2787]] to i32
-// CHECK-NEXT: store i32 [[TMP2788]], ptr [[UIR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2789:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2790:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2791:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2789]], i32 [[TMP2790]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2792:%.*]] = extractvalue { i32, i1 } [[TMP2791]], 1
-// CHECK-NEXT: [[TMP2793:%.*]] = zext i1 [[TMP2792]] to i32
-// CHECK-NEXT: store i32 [[TMP2793]], ptr [[UIR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2794:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2795:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2796:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2794]], i32 [[TMP2795]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2797:%.*]] = extractvalue { i32, i1 } [[TMP2796]], 0
-// CHECK-NEXT: [[TMP2798:%.*]] = extractvalue { i32, i1 } [[TMP2796]], 1
-// CHECK-NEXT: br i1 [[TMP2798]], label [[UIX_ATOMIC_EXIT273:%.*]], label [[UIX_ATOMIC_CONT274:%.*]]
-// CHECK: uix.atomic.cont274:
-// CHECK-NEXT: store i32 [[TMP2797]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT273]]
-// CHECK: uix.atomic.exit273:
-// CHECK-NEXT: [[TMP2799:%.*]] = extractvalue { i32, i1 } [[TMP2796]], 1
-// CHECK-NEXT: [[TMP2800:%.*]] = zext i1 [[TMP2799]] to i32
-// CHECK-NEXT: store i32 [[TMP2800]], ptr [[UIR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2801:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP2802:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP2803:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP2801]], i32 [[TMP2802]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP2804:%.*]] = extractvalue { i32, i1 } [[TMP2803]], 0
-// CHECK-NEXT: [[TMP2805:%.*]] = extractvalue { i32, i1 } [[TMP2803]], 1
-// CHECK-NEXT: br i1 [[TMP2805]], label [[UIX_ATOMIC_EXIT275:%.*]], label [[UIX_ATOMIC_CONT276:%.*]]
-// CHECK: uix.atomic.cont276:
-// CHECK-NEXT: store i32 [[TMP2804]], ptr [[UIV]], align 4
-// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT275]]
-// CHECK: uix.atomic.exit275:
-// CHECK-NEXT: [[TMP2806:%.*]] = extractvalue { i32, i1 } [[TMP2803]], 1
-// CHECK-NEXT: [[TMP2807:%.*]] = zext i1 [[TMP2806]] to i32
-// CHECK-NEXT: store i32 [[TMP2807]], ptr [[UIR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2808:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2809:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2808]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP2809]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2810:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2811:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2810]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP2811]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2812:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2813:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2812]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP2813]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2814:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2815:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2814]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP2815]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2816:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2817:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2818:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2816]], i64 [[TMP2817]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP2819:%.*]] = extractvalue { i64, i1 } [[TMP2818]], 0
-// CHECK-NEXT: store i64 [[TMP2819]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2820:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2821:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2822:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2820]], i64 [[TMP2821]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP2823:%.*]] = extractvalue { i64, i1 } [[TMP2822]], 0
-// CHECK-NEXT: store i64 [[TMP2823]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2824:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2825:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2824]] monotonic, align 8
-// CHECK-NEXT: [[TMP2826:%.*]] = icmp sgt i64 [[TMP2825]], [[TMP2824]]
-// CHECK-NEXT: [[TMP2827:%.*]] = select i1 [[TMP2826]], i64 [[TMP2824]], i64 [[TMP2825]]
-// CHECK-NEXT: store i64 [[TMP2827]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2828:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2829:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2828]] monotonic, align 8
-// CHECK-NEXT: [[TMP2830:%.*]] = icmp slt i64 [[TMP2829]], [[TMP2828]]
-// CHECK-NEXT: [[TMP2831:%.*]] = select i1 [[TMP2830]], i64 [[TMP2828]], i64 [[TMP2829]]
-// CHECK-NEXT: store i64 [[TMP2831]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2832:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2833:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2832]] monotonic, align 8
-// CHECK-NEXT: [[TMP2834:%.*]] = icmp slt i64 [[TMP2833]], [[TMP2832]]
-// CHECK-NEXT: [[TMP2835:%.*]] = select i1 [[TMP2834]], i64 [[TMP2832]], i64 [[TMP2833]]
-// CHECK-NEXT: store i64 [[TMP2835]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2836:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2837:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2836]] monotonic, align 8
-// CHECK-NEXT: [[TMP2838:%.*]] = icmp sgt i64 [[TMP2837]], [[TMP2836]]
-// CHECK-NEXT: [[TMP2839:%.*]] = select i1 [[TMP2838]], i64 [[TMP2836]], i64 [[TMP2837]]
-// CHECK-NEXT: store i64 [[TMP2839]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2840:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2841:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2842:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2840]], i64 [[TMP2841]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP2843:%.*]] = extractvalue { i64, i1 } [[TMP2842]], 0
-// CHECK-NEXT: [[TMP2844:%.*]] = extractvalue { i64, i1 } [[TMP2842]], 1
-// CHECK-NEXT: [[TMP2845:%.*]] = select i1 [[TMP2844]], i64 [[TMP2840]], i64 [[TMP2843]]
-// CHECK-NEXT: store i64 [[TMP2845]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2846:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2847:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2848:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2846]], i64 [[TMP2847]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP2849:%.*]] = extractvalue { i64, i1 } [[TMP2848]], 0
-// CHECK-NEXT: [[TMP2850:%.*]] = extractvalue { i64, i1 } [[TMP2848]], 1
-// CHECK-NEXT: [[TMP2851:%.*]] = select i1 [[TMP2850]], i64 [[TMP2846]], i64 [[TMP2849]]
-// CHECK-NEXT: store i64 [[TMP2851]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2852:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2853:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2854:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2852]], i64 [[TMP2853]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP2855:%.*]] = extractvalue { i64, i1 } [[TMP2854]], 0
-// CHECK-NEXT: [[TMP2856:%.*]] = extractvalue { i64, i1 } [[TMP2854]], 1
-// CHECK-NEXT: br i1 [[TMP2856]], label [[LX_ATOMIC_EXIT:%.*]], label [[LX_ATOMIC_CONT:%.*]]
+// CHECK-NEXT: [[TMP1474:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1475:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1474]], ptr [[UIX_ATOMIC_EXPECTED_PTR2924]], align 4
+// CHECK-NEXT: store i32 [[TMP1475]], ptr [[UIX_ATOMIC_DESIRED_PTR2925]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED2927:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2924]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED2928:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR2925]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR2929:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED2927]], i32 [[UIX_CMPXCHG_DESIRED2928]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV2930:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2929]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV2930]], ptr [[UIX_ATOMIC_EXPECTED_PTR2926]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS2931:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2929]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL2932:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2926]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS2931]], label [[UIX_ATOMIC_EXIT2933:%.*]], label [[UIX_ATOMIC_CONT2934:%.*]]
+// CHECK: uix.atomic.cont2934:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL2932]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT2933]]
+// CHECK: uix.atomic.exit2933:
+// CHECK-NEXT: [[TMP1476:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1477:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1476]], ptr [[UIX_ATOMIC_EXPECTED_PTR2935]], align 4
+// CHECK-NEXT: store i32 [[TMP1477]], ptr [[UIX_ATOMIC_DESIRED_PTR2936]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED2938:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2935]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED2939:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR2936]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR2940:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED2938]], i32 [[UIX_CMPXCHG_DESIRED2939]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV2941:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2940]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV2941]], ptr [[UIX_ATOMIC_EXPECTED_PTR2937]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS2942:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2940]], 1
+// CHECK-NEXT: [[TMP1478:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS2942]] to i32
+// CHECK-NEXT: store i32 [[TMP1478]], ptr [[UIR]], align 4
+// CHECK-NEXT: [[TMP1479:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1480:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1479]], ptr [[UIX_ATOMIC_EXPECTED_PTR2943]], align 4
+// CHECK-NEXT: store i32 [[TMP1480]], ptr [[UIX_ATOMIC_DESIRED_PTR2944]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED2946:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2943]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED2947:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR2944]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR2948:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED2946]], i32 [[UIX_CMPXCHG_DESIRED2947]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV2949:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2948]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV2949]], ptr [[UIX_ATOMIC_EXPECTED_PTR2945]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS2950:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2948]], 1
+// CHECK-NEXT: [[TMP1481:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS2950]] to i32
+// CHECK-NEXT: store i32 [[TMP1481]], ptr [[UIR]], align 4
+// CHECK-NEXT: [[TMP1482:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1483:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1482]], ptr [[UIX_ATOMIC_EXPECTED_PTR2951]], align 4
+// CHECK-NEXT: store i32 [[TMP1483]], ptr [[UIX_ATOMIC_DESIRED_PTR2952]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED2954:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2951]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED2955:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR2952]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR2956:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED2954]], i32 [[UIX_CMPXCHG_DESIRED2955]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV2957:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2956]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV2957]], ptr [[UIX_ATOMIC_EXPECTED_PTR2953]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS2958:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2956]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL2959:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2953]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS2958]], label [[UIX_ATOMIC_EXIT2960:%.*]], label [[UIX_ATOMIC_CONT2961:%.*]]
+// CHECK: uix.atomic.cont2961:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL2959]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT2960]]
+// CHECK: uix.atomic.exit2960:
+// CHECK-NEXT: [[TMP1484:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS2958]] to i32
+// CHECK-NEXT: store i32 [[TMP1484]], ptr [[UIR]], align 4
+// CHECK-NEXT: [[TMP1485:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1486:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1485]], ptr [[UIX_ATOMIC_EXPECTED_PTR2962]], align 4
+// CHECK-NEXT: store i32 [[TMP1486]], ptr [[UIX_ATOMIC_DESIRED_PTR2963]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED2965:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2962]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED2966:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR2963]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR2967:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED2965]], i32 [[UIX_CMPXCHG_DESIRED2966]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV2968:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2967]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV2968]], ptr [[UIX_ATOMIC_EXPECTED_PTR2964]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS2969:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2967]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL2970:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2964]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS2969]], label [[UIX_ATOMIC_EXIT2971:%.*]], label [[UIX_ATOMIC_CONT2972:%.*]]
+// CHECK: uix.atomic.cont2972:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL2970]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT2971]]
+// CHECK: uix.atomic.exit2971:
+// CHECK-NEXT: [[TMP1487:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS2969]] to i32
+// CHECK-NEXT: store i32 [[TMP1487]], ptr [[UIR]], align 4
+// CHECK-NEXT: [[TMP1488:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1489:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1488]] acq_rel, align 4
+// CHECK-NEXT: store i32 [[TMP1489]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1490:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1491:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1490]] acq_rel, align 4
+// CHECK-NEXT: store i32 [[TMP1491]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1492:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1493:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1492]] acq_rel, align 4
+// CHECK-NEXT: store i32 [[TMP1493]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1494:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1495:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1494]] acq_rel, align 4
+// CHECK-NEXT: store i32 [[TMP1495]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1496:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1497:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1496]], ptr [[UIX_ATOMIC_EXPECTED_PTR2973]], align 4
+// CHECK-NEXT: store i32 [[TMP1497]], ptr [[UIX_ATOMIC_DESIRED_PTR2974]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED2976:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2973]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED2977:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR2974]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR2978:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED2976]], i32 [[UIX_CMPXCHG_DESIRED2977]] acq_rel acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV2979:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2978]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV2979]], ptr [[UIX_ATOMIC_EXPECTED_PTR2975]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS2980:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2978]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL2981:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2975]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL2981]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1498:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1499:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1498]], ptr [[UIX_ATOMIC_EXPECTED_PTR2982]], align 4
+// CHECK-NEXT: store i32 [[TMP1499]], ptr [[UIX_ATOMIC_DESIRED_PTR2983]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED2985:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2982]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED2986:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR2983]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR2987:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED2985]], i32 [[UIX_CMPXCHG_DESIRED2986]] acq_rel acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV2988:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2987]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV2988]], ptr [[UIX_ATOMIC_EXPECTED_PTR2984]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS2989:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2987]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL2990:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2984]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL2990]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1500:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1501:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1500]] acq_rel, align 4
+// CHECK-NEXT: [[TMP1502:%.*]] = icmp ugt i32 [[TMP1501]], [[TMP1500]]
+// CHECK-NEXT: [[TMP1503:%.*]] = select i1 [[TMP1502]], i32 [[TMP1500]], i32 [[TMP1501]]
+// CHECK-NEXT: store i32 [[TMP1503]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1504:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1505:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1504]] acq_rel, align 4
+// CHECK-NEXT: [[TMP1506:%.*]] = icmp ult i32 [[TMP1505]], [[TMP1504]]
+// CHECK-NEXT: [[TMP1507:%.*]] = select i1 [[TMP1506]], i32 [[TMP1504]], i32 [[TMP1505]]
+// CHECK-NEXT: store i32 [[TMP1507]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1508:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1509:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1508]] acq_rel, align 4
+// CHECK-NEXT: [[TMP1510:%.*]] = icmp ult i32 [[TMP1509]], [[TMP1508]]
+// CHECK-NEXT: [[TMP1511:%.*]] = select i1 [[TMP1510]], i32 [[TMP1508]], i32 [[TMP1509]]
+// CHECK-NEXT: store i32 [[TMP1511]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1512:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1513:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1512]] acq_rel, align 4
+// CHECK-NEXT: [[TMP1514:%.*]] = icmp ugt i32 [[TMP1513]], [[TMP1512]]
+// CHECK-NEXT: [[TMP1515:%.*]] = select i1 [[TMP1514]], i32 [[TMP1512]], i32 [[TMP1513]]
+// CHECK-NEXT: store i32 [[TMP1515]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1516:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1517:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1516]], ptr [[UIX_ATOMIC_EXPECTED_PTR2991]], align 4
+// CHECK-NEXT: store i32 [[TMP1517]], ptr [[UIX_ATOMIC_DESIRED_PTR2992]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED2994:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2991]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED2995:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR2992]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR2996:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED2994]], i32 [[UIX_CMPXCHG_DESIRED2995]] acq_rel acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV2997:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2996]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV2997]], ptr [[UIX_ATOMIC_EXPECTED_PTR2993]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS2998:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR2996]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL2999:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2993]], align 4
+// CHECK-NEXT: [[UIX_CAPTURE_CAPTURED3000:%.*]] = select i1 [[UIX_CMPXCHG_SUCCESS2998]], i32 [[TMP1516]], i32 [[UIX_CAPTURE_ACTUAL2999]]
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_CAPTURED3000]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1518:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1519:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1518]], ptr [[UIX_ATOMIC_EXPECTED_PTR3001]], align 4
+// CHECK-NEXT: store i32 [[TMP1519]], ptr [[UIX_ATOMIC_DESIRED_PTR3002]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3004:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3001]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3005:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3002]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3006:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3004]], i32 [[UIX_CMPXCHG_DESIRED3005]] acq_rel acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3007:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3006]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3007]], ptr [[UIX_ATOMIC_EXPECTED_PTR3003]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3008:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3006]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3009:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3003]], align 4
+// CHECK-NEXT: [[UIX_CAPTURE_CAPTURED3010:%.*]] = select i1 [[UIX_CMPXCHG_SUCCESS3008]], i32 [[TMP1518]], i32 [[UIX_CAPTURE_ACTUAL3009]]
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_CAPTURED3010]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1520:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1521:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1520]], ptr [[UIX_ATOMIC_EXPECTED_PTR3011]], align 4
+// CHECK-NEXT: store i32 [[TMP1521]], ptr [[UIX_ATOMIC_DESIRED_PTR3012]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3014:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3011]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3015:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3012]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3016:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3014]], i32 [[UIX_CMPXCHG_DESIRED3015]] acq_rel acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3017:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3016]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3017]], ptr [[UIX_ATOMIC_EXPECTED_PTR3013]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3018:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3016]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3019:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3013]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3018]], label [[UIX_ATOMIC_EXIT3020:%.*]], label [[UIX_ATOMIC_CONT3021:%.*]]
+// CHECK: uix.atomic.cont3021:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3019]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3020]]
+// CHECK: uix.atomic.exit3020:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1522:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1523:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1522]], ptr [[UIX_ATOMIC_EXPECTED_PTR3022]], align 4
+// CHECK-NEXT: store i32 [[TMP1523]], ptr [[UIX_ATOMIC_DESIRED_PTR3023]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3025:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3022]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3026:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3023]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3027:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3025]], i32 [[UIX_CMPXCHG_DESIRED3026]] acq_rel acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3028:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3027]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3028]], ptr [[UIX_ATOMIC_EXPECTED_PTR3024]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3029:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3027]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3030:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3024]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3029]], label [[UIX_ATOMIC_EXIT3031:%.*]], label [[UIX_ATOMIC_CONT3032:%.*]]
+// CHECK: uix.atomic.cont3032:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3030]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3031]]
+// CHECK: uix.atomic.exit3031:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1524:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1525:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1524]], ptr [[UIX_ATOMIC_EXPECTED_PTR3033]], align 4
+// CHECK-NEXT: store i32 [[TMP1525]], ptr [[UIX_ATOMIC_DESIRED_PTR3034]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3036:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3033]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3037:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3034]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3038:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3036]], i32 [[UIX_CMPXCHG_DESIRED3037]] acq_rel acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3039:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3038]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3039]], ptr [[UIX_ATOMIC_EXPECTED_PTR3035]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3040:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3038]], 1
+// CHECK-NEXT: [[TMP1526:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3040]] to i32
+// CHECK-NEXT: store i32 [[TMP1526]], ptr [[UIR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1527:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1528:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1527]], ptr [[UIX_ATOMIC_EXPECTED_PTR3041]], align 4
+// CHECK-NEXT: store i32 [[TMP1528]], ptr [[UIX_ATOMIC_DESIRED_PTR3042]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3044:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3041]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3045:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3042]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3046:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3044]], i32 [[UIX_CMPXCHG_DESIRED3045]] acq_rel acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3047:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3046]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3047]], ptr [[UIX_ATOMIC_EXPECTED_PTR3043]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3048:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3046]], 1
+// CHECK-NEXT: [[TMP1529:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3048]] to i32
+// CHECK-NEXT: store i32 [[TMP1529]], ptr [[UIR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1530:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1531:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1530]], ptr [[UIX_ATOMIC_EXPECTED_PTR3049]], align 4
+// CHECK-NEXT: store i32 [[TMP1531]], ptr [[UIX_ATOMIC_DESIRED_PTR3050]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3052:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3049]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3053:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3050]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3054:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3052]], i32 [[UIX_CMPXCHG_DESIRED3053]] acq_rel acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3055:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3054]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3055]], ptr [[UIX_ATOMIC_EXPECTED_PTR3051]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3056:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3054]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3057:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3051]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3056]], label [[UIX_ATOMIC_EXIT3058:%.*]], label [[UIX_ATOMIC_CONT3059:%.*]]
+// CHECK: uix.atomic.cont3059:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3057]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3058]]
+// CHECK: uix.atomic.exit3058:
+// CHECK-NEXT: [[TMP1532:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3056]] to i32
+// CHECK-NEXT: store i32 [[TMP1532]], ptr [[UIR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1533:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1534:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1533]], ptr [[UIX_ATOMIC_EXPECTED_PTR3060]], align 4
+// CHECK-NEXT: store i32 [[TMP1534]], ptr [[UIX_ATOMIC_DESIRED_PTR3061]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3063:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3060]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3064:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3061]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3065:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3063]], i32 [[UIX_CMPXCHG_DESIRED3064]] acq_rel acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3066:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3065]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3066]], ptr [[UIX_ATOMIC_EXPECTED_PTR3062]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3067:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3065]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3068:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3062]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3067]], label [[UIX_ATOMIC_EXIT3069:%.*]], label [[UIX_ATOMIC_CONT3070:%.*]]
+// CHECK: uix.atomic.cont3070:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3068]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3069]]
+// CHECK: uix.atomic.exit3069:
+// CHECK-NEXT: [[TMP1535:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3067]] to i32
+// CHECK-NEXT: store i32 [[TMP1535]], ptr [[UIR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1536:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1537:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1536]] acquire, align 4
+// CHECK-NEXT: store i32 [[TMP1537]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1538:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1539:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1538]] acquire, align 4
+// CHECK-NEXT: store i32 [[TMP1539]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1540:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1541:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1540]] acquire, align 4
+// CHECK-NEXT: store i32 [[TMP1541]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1542:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1543:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1542]] acquire, align 4
+// CHECK-NEXT: store i32 [[TMP1543]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1544:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1545:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1544]], ptr [[UIX_ATOMIC_EXPECTED_PTR3071]], align 4
+// CHECK-NEXT: store i32 [[TMP1545]], ptr [[UIX_ATOMIC_DESIRED_PTR3072]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3074:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3071]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3075:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3072]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3076:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3074]], i32 [[UIX_CMPXCHG_DESIRED3075]] acquire acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3077:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3076]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3077]], ptr [[UIX_ATOMIC_EXPECTED_PTR3073]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3078:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3076]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3079:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3073]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3079]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1546:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1547:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1546]], ptr [[UIX_ATOMIC_EXPECTED_PTR3080]], align 4
+// CHECK-NEXT: store i32 [[TMP1547]], ptr [[UIX_ATOMIC_DESIRED_PTR3081]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3083:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3080]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3084:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3081]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3085:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3083]], i32 [[UIX_CMPXCHG_DESIRED3084]] acquire acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3086:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3085]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3086]], ptr [[UIX_ATOMIC_EXPECTED_PTR3082]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3087:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3085]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3088:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3082]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3088]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1548:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1549:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1548]] acquire, align 4
+// CHECK-NEXT: [[TMP1550:%.*]] = icmp ugt i32 [[TMP1549]], [[TMP1548]]
+// CHECK-NEXT: [[TMP1551:%.*]] = select i1 [[TMP1550]], i32 [[TMP1548]], i32 [[TMP1549]]
+// CHECK-NEXT: store i32 [[TMP1551]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1552:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1553:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1552]] acquire, align 4
+// CHECK-NEXT: [[TMP1554:%.*]] = icmp ult i32 [[TMP1553]], [[TMP1552]]
+// CHECK-NEXT: [[TMP1555:%.*]] = select i1 [[TMP1554]], i32 [[TMP1552]], i32 [[TMP1553]]
+// CHECK-NEXT: store i32 [[TMP1555]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1556:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1557:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1556]] acquire, align 4
+// CHECK-NEXT: [[TMP1558:%.*]] = icmp ult i32 [[TMP1557]], [[TMP1556]]
+// CHECK-NEXT: [[TMP1559:%.*]] = select i1 [[TMP1558]], i32 [[TMP1556]], i32 [[TMP1557]]
+// CHECK-NEXT: store i32 [[TMP1559]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1560:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1561:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1560]] acquire, align 4
+// CHECK-NEXT: [[TMP1562:%.*]] = icmp ugt i32 [[TMP1561]], [[TMP1560]]
+// CHECK-NEXT: [[TMP1563:%.*]] = select i1 [[TMP1562]], i32 [[TMP1560]], i32 [[TMP1561]]
+// CHECK-NEXT: store i32 [[TMP1563]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1564:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1565:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1564]], ptr [[UIX_ATOMIC_EXPECTED_PTR3089]], align 4
+// CHECK-NEXT: store i32 [[TMP1565]], ptr [[UIX_ATOMIC_DESIRED_PTR3090]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3092:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3089]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3093:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3090]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3094:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3092]], i32 [[UIX_CMPXCHG_DESIRED3093]] acquire acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3095:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3094]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3095]], ptr [[UIX_ATOMIC_EXPECTED_PTR3091]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3096:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3094]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3097:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3091]], align 4
+// CHECK-NEXT: [[UIX_CAPTURE_CAPTURED3098:%.*]] = select i1 [[UIX_CMPXCHG_SUCCESS3096]], i32 [[TMP1564]], i32 [[UIX_CAPTURE_ACTUAL3097]]
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_CAPTURED3098]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1566:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1567:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1566]], ptr [[UIX_ATOMIC_EXPECTED_PTR3099]], align 4
+// CHECK-NEXT: store i32 [[TMP1567]], ptr [[UIX_ATOMIC_DESIRED_PTR3100]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3102:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3099]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3103:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3100]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3104:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3102]], i32 [[UIX_CMPXCHG_DESIRED3103]] acquire acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3105:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3104]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3105]], ptr [[UIX_ATOMIC_EXPECTED_PTR3101]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3106:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3104]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3107:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3101]], align 4
+// CHECK-NEXT: [[UIX_CAPTURE_CAPTURED3108:%.*]] = select i1 [[UIX_CMPXCHG_SUCCESS3106]], i32 [[TMP1566]], i32 [[UIX_CAPTURE_ACTUAL3107]]
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_CAPTURED3108]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1568:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1569:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1568]], ptr [[UIX_ATOMIC_EXPECTED_PTR3109]], align 4
+// CHECK-NEXT: store i32 [[TMP1569]], ptr [[UIX_ATOMIC_DESIRED_PTR3110]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3112:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3109]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3113:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3110]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3114:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3112]], i32 [[UIX_CMPXCHG_DESIRED3113]] acquire acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3115:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3114]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3115]], ptr [[UIX_ATOMIC_EXPECTED_PTR3111]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3116:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3114]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3117:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3111]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3116]], label [[UIX_ATOMIC_EXIT3118:%.*]], label [[UIX_ATOMIC_CONT3119:%.*]]
+// CHECK: uix.atomic.cont3119:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3117]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3118]]
+// CHECK: uix.atomic.exit3118:
+// CHECK-NEXT: [[TMP1570:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1571:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1570]], ptr [[UIX_ATOMIC_EXPECTED_PTR3120]], align 4
+// CHECK-NEXT: store i32 [[TMP1571]], ptr [[UIX_ATOMIC_DESIRED_PTR3121]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3123:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3120]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3124:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3121]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3125:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3123]], i32 [[UIX_CMPXCHG_DESIRED3124]] acquire acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3126:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3125]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3126]], ptr [[UIX_ATOMIC_EXPECTED_PTR3122]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3127:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3125]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3128:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3122]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3127]], label [[UIX_ATOMIC_EXIT3129:%.*]], label [[UIX_ATOMIC_CONT3130:%.*]]
+// CHECK: uix.atomic.cont3130:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3128]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3129]]
+// CHECK: uix.atomic.exit3129:
+// CHECK-NEXT: [[TMP1572:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1573:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1572]], ptr [[UIX_ATOMIC_EXPECTED_PTR3131]], align 4
+// CHECK-NEXT: store i32 [[TMP1573]], ptr [[UIX_ATOMIC_DESIRED_PTR3132]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3134:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3131]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3135:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3132]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3136:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3134]], i32 [[UIX_CMPXCHG_DESIRED3135]] acquire acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3137:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3136]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3137]], ptr [[UIX_ATOMIC_EXPECTED_PTR3133]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3138:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3136]], 1
+// CHECK-NEXT: [[TMP1574:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3138]] to i32
+// CHECK-NEXT: store i32 [[TMP1574]], ptr [[UIR]], align 4
+// CHECK-NEXT: [[TMP1575:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1576:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1575]], ptr [[UIX_ATOMIC_EXPECTED_PTR3139]], align 4
+// CHECK-NEXT: store i32 [[TMP1576]], ptr [[UIX_ATOMIC_DESIRED_PTR3140]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3142:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3139]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3143:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3140]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3144:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3142]], i32 [[UIX_CMPXCHG_DESIRED3143]] acquire acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3145:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3144]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3145]], ptr [[UIX_ATOMIC_EXPECTED_PTR3141]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3146:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3144]], 1
+// CHECK-NEXT: [[TMP1577:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3146]] to i32
+// CHECK-NEXT: store i32 [[TMP1577]], ptr [[UIR]], align 4
+// CHECK-NEXT: [[TMP1578:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1579:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1578]], ptr [[UIX_ATOMIC_EXPECTED_PTR3147]], align 4
+// CHECK-NEXT: store i32 [[TMP1579]], ptr [[UIX_ATOMIC_DESIRED_PTR3148]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3150:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3147]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3151:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3148]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3152:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3150]], i32 [[UIX_CMPXCHG_DESIRED3151]] acquire acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3153:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3152]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3153]], ptr [[UIX_ATOMIC_EXPECTED_PTR3149]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3154:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3152]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3155:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3149]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3154]], label [[UIX_ATOMIC_EXIT3156:%.*]], label [[UIX_ATOMIC_CONT3157:%.*]]
+// CHECK: uix.atomic.cont3157:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3155]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3156]]
+// CHECK: uix.atomic.exit3156:
+// CHECK-NEXT: [[TMP1580:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3154]] to i32
+// CHECK-NEXT: store i32 [[TMP1580]], ptr [[UIR]], align 4
+// CHECK-NEXT: [[TMP1581:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1582:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1581]], ptr [[UIX_ATOMIC_EXPECTED_PTR3158]], align 4
+// CHECK-NEXT: store i32 [[TMP1582]], ptr [[UIX_ATOMIC_DESIRED_PTR3159]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3161:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3158]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3162:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3159]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3163:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3161]], i32 [[UIX_CMPXCHG_DESIRED3162]] acquire acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3164:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3163]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3164]], ptr [[UIX_ATOMIC_EXPECTED_PTR3160]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3165:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3163]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3166:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3160]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3165]], label [[UIX_ATOMIC_EXIT3167:%.*]], label [[UIX_ATOMIC_CONT3168:%.*]]
+// CHECK: uix.atomic.cont3168:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3166]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3167]]
+// CHECK: uix.atomic.exit3167:
+// CHECK-NEXT: [[TMP1583:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3165]] to i32
+// CHECK-NEXT: store i32 [[TMP1583]], ptr [[UIR]], align 4
+// CHECK-NEXT: [[TMP1584:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1585:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1584]] monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP1585]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1586:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1587:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1586]] monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP1587]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1588:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1589:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1588]] monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP1589]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1590:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1591:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1590]] monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP1591]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1592:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1593:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1592]], ptr [[UIX_ATOMIC_EXPECTED_PTR3169]], align 4
+// CHECK-NEXT: store i32 [[TMP1593]], ptr [[UIX_ATOMIC_DESIRED_PTR3170]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3172:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3169]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3173:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3170]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3174:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3172]], i32 [[UIX_CMPXCHG_DESIRED3173]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3175:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3174]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3175]], ptr [[UIX_ATOMIC_EXPECTED_PTR3171]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3176:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3174]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3177:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3171]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3177]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1594:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1595:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1594]], ptr [[UIX_ATOMIC_EXPECTED_PTR3178]], align 4
+// CHECK-NEXT: store i32 [[TMP1595]], ptr [[UIX_ATOMIC_DESIRED_PTR3179]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3181:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3178]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3182:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3179]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3183:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3181]], i32 [[UIX_CMPXCHG_DESIRED3182]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3184:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3183]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3184]], ptr [[UIX_ATOMIC_EXPECTED_PTR3180]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3185:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3183]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3186:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3180]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3186]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1596:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1597:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1596]] monotonic, align 4
+// CHECK-NEXT: [[TMP1598:%.*]] = icmp ugt i32 [[TMP1597]], [[TMP1596]]
+// CHECK-NEXT: [[TMP1599:%.*]] = select i1 [[TMP1598]], i32 [[TMP1596]], i32 [[TMP1597]]
+// CHECK-NEXT: store i32 [[TMP1599]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1600:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1601:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1600]] monotonic, align 4
+// CHECK-NEXT: [[TMP1602:%.*]] = icmp ult i32 [[TMP1601]], [[TMP1600]]
+// CHECK-NEXT: [[TMP1603:%.*]] = select i1 [[TMP1602]], i32 [[TMP1600]], i32 [[TMP1601]]
+// CHECK-NEXT: store i32 [[TMP1603]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1604:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1605:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1604]] monotonic, align 4
+// CHECK-NEXT: [[TMP1606:%.*]] = icmp ult i32 [[TMP1605]], [[TMP1604]]
+// CHECK-NEXT: [[TMP1607:%.*]] = select i1 [[TMP1606]], i32 [[TMP1604]], i32 [[TMP1605]]
+// CHECK-NEXT: store i32 [[TMP1607]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1608:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1609:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1608]] monotonic, align 4
+// CHECK-NEXT: [[TMP1610:%.*]] = icmp ugt i32 [[TMP1609]], [[TMP1608]]
+// CHECK-NEXT: [[TMP1611:%.*]] = select i1 [[TMP1610]], i32 [[TMP1608]], i32 [[TMP1609]]
+// CHECK-NEXT: store i32 [[TMP1611]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1612:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1613:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1612]], ptr [[UIX_ATOMIC_EXPECTED_PTR3187]], align 4
+// CHECK-NEXT: store i32 [[TMP1613]], ptr [[UIX_ATOMIC_DESIRED_PTR3188]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3190:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3187]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3191:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3188]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3192:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3190]], i32 [[UIX_CMPXCHG_DESIRED3191]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3193:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3192]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3193]], ptr [[UIX_ATOMIC_EXPECTED_PTR3189]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3194:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3192]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3195:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3189]], align 4
+// CHECK-NEXT: [[UIX_CAPTURE_CAPTURED3196:%.*]] = select i1 [[UIX_CMPXCHG_SUCCESS3194]], i32 [[TMP1612]], i32 [[UIX_CAPTURE_ACTUAL3195]]
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_CAPTURED3196]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1614:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1615:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1614]], ptr [[UIX_ATOMIC_EXPECTED_PTR3197]], align 4
+// CHECK-NEXT: store i32 [[TMP1615]], ptr [[UIX_ATOMIC_DESIRED_PTR3198]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3200:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3197]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3201:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3198]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3202:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3200]], i32 [[UIX_CMPXCHG_DESIRED3201]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3203:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3202]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3203]], ptr [[UIX_ATOMIC_EXPECTED_PTR3199]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3204:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3202]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3205:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3199]], align 4
+// CHECK-NEXT: [[UIX_CAPTURE_CAPTURED3206:%.*]] = select i1 [[UIX_CMPXCHG_SUCCESS3204]], i32 [[TMP1614]], i32 [[UIX_CAPTURE_ACTUAL3205]]
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_CAPTURED3206]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP1616:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1617:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1616]], ptr [[UIX_ATOMIC_EXPECTED_PTR3207]], align 4
+// CHECK-NEXT: store i32 [[TMP1617]], ptr [[UIX_ATOMIC_DESIRED_PTR3208]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3210:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3207]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3211:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3208]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3212:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3210]], i32 [[UIX_CMPXCHG_DESIRED3211]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3213:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3212]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3213]], ptr [[UIX_ATOMIC_EXPECTED_PTR3209]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3214:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3212]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3215:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3209]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3214]], label [[UIX_ATOMIC_EXIT3216:%.*]], label [[UIX_ATOMIC_CONT3217:%.*]]
+// CHECK: uix.atomic.cont3217:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3215]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3216]]
+// CHECK: uix.atomic.exit3216:
+// CHECK-NEXT: [[TMP1618:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1619:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1618]], ptr [[UIX_ATOMIC_EXPECTED_PTR3218]], align 4
+// CHECK-NEXT: store i32 [[TMP1619]], ptr [[UIX_ATOMIC_DESIRED_PTR3219]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3221:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3218]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3222:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3219]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3223:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3221]], i32 [[UIX_CMPXCHG_DESIRED3222]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3224:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3223]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3224]], ptr [[UIX_ATOMIC_EXPECTED_PTR3220]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3225:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3223]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3226:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3220]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3225]], label [[UIX_ATOMIC_EXIT3227:%.*]], label [[UIX_ATOMIC_CONT3228:%.*]]
+// CHECK: uix.atomic.cont3228:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3226]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3227]]
+// CHECK: uix.atomic.exit3227:
+// CHECK-NEXT: [[TMP1620:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1621:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1620]], ptr [[UIX_ATOMIC_EXPECTED_PTR3229]], align 4
+// CHECK-NEXT: store i32 [[TMP1621]], ptr [[UIX_ATOMIC_DESIRED_PTR3230]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3232:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3229]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3233:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3230]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3234:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3232]], i32 [[UIX_CMPXCHG_DESIRED3233]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3235:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3234]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3235]], ptr [[UIX_ATOMIC_EXPECTED_PTR3231]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3236:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3234]], 1
+// CHECK-NEXT: [[TMP1622:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3236]] to i32
+// CHECK-NEXT: store i32 [[TMP1622]], ptr [[UIR]], align 4
+// CHECK-NEXT: [[TMP1623:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1624:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1623]], ptr [[UIX_ATOMIC_EXPECTED_PTR3237]], align 4
+// CHECK-NEXT: store i32 [[TMP1624]], ptr [[UIX_ATOMIC_DESIRED_PTR3238]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3240:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3237]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3241:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3238]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3242:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3240]], i32 [[UIX_CMPXCHG_DESIRED3241]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3243:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3242]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3243]], ptr [[UIX_ATOMIC_EXPECTED_PTR3239]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3244:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3242]], 1
+// CHECK-NEXT: [[TMP1625:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3244]] to i32
+// CHECK-NEXT: store i32 [[TMP1625]], ptr [[UIR]], align 4
+// CHECK-NEXT: [[TMP1626:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1627:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1626]], ptr [[UIX_ATOMIC_EXPECTED_PTR3245]], align 4
+// CHECK-NEXT: store i32 [[TMP1627]], ptr [[UIX_ATOMIC_DESIRED_PTR3246]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3248:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3245]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3249:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3246]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3250:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3248]], i32 [[UIX_CMPXCHG_DESIRED3249]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3251:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3250]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3251]], ptr [[UIX_ATOMIC_EXPECTED_PTR3247]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3252:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3250]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3253:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3247]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3252]], label [[UIX_ATOMIC_EXIT3254:%.*]], label [[UIX_ATOMIC_CONT3255:%.*]]
+// CHECK: uix.atomic.cont3255:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3253]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3254]]
+// CHECK: uix.atomic.exit3254:
+// CHECK-NEXT: [[TMP1628:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3252]] to i32
+// CHECK-NEXT: store i32 [[TMP1628]], ptr [[UIR]], align 4
+// CHECK-NEXT: [[TMP1629:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1630:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1629]], ptr [[UIX_ATOMIC_EXPECTED_PTR3256]], align 4
+// CHECK-NEXT: store i32 [[TMP1630]], ptr [[UIX_ATOMIC_DESIRED_PTR3257]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3259:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3256]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3260:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3257]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3261:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3259]], i32 [[UIX_CMPXCHG_DESIRED3260]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3262:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3261]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3262]], ptr [[UIX_ATOMIC_EXPECTED_PTR3258]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3263:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3261]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3264:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3258]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3263]], label [[UIX_ATOMIC_EXIT3265:%.*]], label [[UIX_ATOMIC_CONT3266:%.*]]
+// CHECK: uix.atomic.cont3266:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3264]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3265]]
+// CHECK: uix.atomic.exit3265:
+// CHECK-NEXT: [[TMP1631:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3263]] to i32
+// CHECK-NEXT: store i32 [[TMP1631]], ptr [[UIR]], align 4
+// CHECK-NEXT: [[TMP1632:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1633:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1632]] release, align 4
+// CHECK-NEXT: store i32 [[TMP1633]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1634:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1635:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1634]] release, align 4
+// CHECK-NEXT: store i32 [[TMP1635]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1636:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1637:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1636]] release, align 4
+// CHECK-NEXT: store i32 [[TMP1637]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1638:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1639:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1638]] release, align 4
+// CHECK-NEXT: store i32 [[TMP1639]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1640:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1641:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1640]], ptr [[UIX_ATOMIC_EXPECTED_PTR3267]], align 4
+// CHECK-NEXT: store i32 [[TMP1641]], ptr [[UIX_ATOMIC_DESIRED_PTR3268]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3270:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3267]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3271:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3268]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3272:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3270]], i32 [[UIX_CMPXCHG_DESIRED3271]] release monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3273:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3272]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3273]], ptr [[UIX_ATOMIC_EXPECTED_PTR3269]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3274:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3272]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3275:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3269]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3275]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1642:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1643:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1642]], ptr [[UIX_ATOMIC_EXPECTED_PTR3276]], align 4
+// CHECK-NEXT: store i32 [[TMP1643]], ptr [[UIX_ATOMIC_DESIRED_PTR3277]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3279:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3276]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3280:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3277]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3281:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3279]], i32 [[UIX_CMPXCHG_DESIRED3280]] release monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3282:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3281]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3282]], ptr [[UIX_ATOMIC_EXPECTED_PTR3278]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3283:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3281]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3284:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3278]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3284]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1644:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1645:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1644]] release, align 4
+// CHECK-NEXT: [[TMP1646:%.*]] = icmp ugt i32 [[TMP1645]], [[TMP1644]]
+// CHECK-NEXT: [[TMP1647:%.*]] = select i1 [[TMP1646]], i32 [[TMP1644]], i32 [[TMP1645]]
+// CHECK-NEXT: store i32 [[TMP1647]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1648:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1649:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1648]] release, align 4
+// CHECK-NEXT: [[TMP1650:%.*]] = icmp ult i32 [[TMP1649]], [[TMP1648]]
+// CHECK-NEXT: [[TMP1651:%.*]] = select i1 [[TMP1650]], i32 [[TMP1648]], i32 [[TMP1649]]
+// CHECK-NEXT: store i32 [[TMP1651]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1652:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1653:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1652]] release, align 4
+// CHECK-NEXT: [[TMP1654:%.*]] = icmp ult i32 [[TMP1653]], [[TMP1652]]
+// CHECK-NEXT: [[TMP1655:%.*]] = select i1 [[TMP1654]], i32 [[TMP1652]], i32 [[TMP1653]]
+// CHECK-NEXT: store i32 [[TMP1655]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1656:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1657:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1656]] release, align 4
+// CHECK-NEXT: [[TMP1658:%.*]] = icmp ugt i32 [[TMP1657]], [[TMP1656]]
+// CHECK-NEXT: [[TMP1659:%.*]] = select i1 [[TMP1658]], i32 [[TMP1656]], i32 [[TMP1657]]
+// CHECK-NEXT: store i32 [[TMP1659]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1660:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1661:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1660]], ptr [[UIX_ATOMIC_EXPECTED_PTR3285]], align 4
+// CHECK-NEXT: store i32 [[TMP1661]], ptr [[UIX_ATOMIC_DESIRED_PTR3286]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3288:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3285]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3289:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3286]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3290:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3288]], i32 [[UIX_CMPXCHG_DESIRED3289]] release monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3291:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3290]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3291]], ptr [[UIX_ATOMIC_EXPECTED_PTR3287]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3292:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3290]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3293:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3287]], align 4
+// CHECK-NEXT: [[UIX_CAPTURE_CAPTURED3294:%.*]] = select i1 [[UIX_CMPXCHG_SUCCESS3292]], i32 [[TMP1660]], i32 [[UIX_CAPTURE_ACTUAL3293]]
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_CAPTURED3294]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1662:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1663:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1662]], ptr [[UIX_ATOMIC_EXPECTED_PTR3295]], align 4
+// CHECK-NEXT: store i32 [[TMP1663]], ptr [[UIX_ATOMIC_DESIRED_PTR3296]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3298:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3295]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3299:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3296]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3300:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3298]], i32 [[UIX_CMPXCHG_DESIRED3299]] release monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3301:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3300]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3301]], ptr [[UIX_ATOMIC_EXPECTED_PTR3297]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3302:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3300]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3303:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3297]], align 4
+// CHECK-NEXT: [[UIX_CAPTURE_CAPTURED3304:%.*]] = select i1 [[UIX_CMPXCHG_SUCCESS3302]], i32 [[TMP1662]], i32 [[UIX_CAPTURE_ACTUAL3303]]
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_CAPTURED3304]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1664:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1665:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1664]], ptr [[UIX_ATOMIC_EXPECTED_PTR3305]], align 4
+// CHECK-NEXT: store i32 [[TMP1665]], ptr [[UIX_ATOMIC_DESIRED_PTR3306]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3308:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3305]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3309:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3306]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3310:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3308]], i32 [[UIX_CMPXCHG_DESIRED3309]] release monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3311:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3310]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3311]], ptr [[UIX_ATOMIC_EXPECTED_PTR3307]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3312:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3310]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3313:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3307]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3312]], label [[UIX_ATOMIC_EXIT3314:%.*]], label [[UIX_ATOMIC_CONT3315:%.*]]
+// CHECK: uix.atomic.cont3315:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3313]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3314]]
+// CHECK: uix.atomic.exit3314:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1666:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1667:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1666]], ptr [[UIX_ATOMIC_EXPECTED_PTR3316]], align 4
+// CHECK-NEXT: store i32 [[TMP1667]], ptr [[UIX_ATOMIC_DESIRED_PTR3317]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3319:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3316]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3320:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3317]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3321:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3319]], i32 [[UIX_CMPXCHG_DESIRED3320]] release monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3322:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3321]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3322]], ptr [[UIX_ATOMIC_EXPECTED_PTR3318]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3323:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3321]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3324:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3318]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3323]], label [[UIX_ATOMIC_EXIT3325:%.*]], label [[UIX_ATOMIC_CONT3326:%.*]]
+// CHECK: uix.atomic.cont3326:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3324]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3325]]
+// CHECK: uix.atomic.exit3325:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1668:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1669:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1668]], ptr [[UIX_ATOMIC_EXPECTED_PTR3327]], align 4
+// CHECK-NEXT: store i32 [[TMP1669]], ptr [[UIX_ATOMIC_DESIRED_PTR3328]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3330:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3327]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3331:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3328]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3332:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3330]], i32 [[UIX_CMPXCHG_DESIRED3331]] release monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3333:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3332]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3333]], ptr [[UIX_ATOMIC_EXPECTED_PTR3329]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3334:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3332]], 1
+// CHECK-NEXT: [[TMP1670:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3334]] to i32
+// CHECK-NEXT: store i32 [[TMP1670]], ptr [[UIR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1671:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1672:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1671]], ptr [[UIX_ATOMIC_EXPECTED_PTR3335]], align 4
+// CHECK-NEXT: store i32 [[TMP1672]], ptr [[UIX_ATOMIC_DESIRED_PTR3336]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3338:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3335]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3339:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3336]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3340:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3338]], i32 [[UIX_CMPXCHG_DESIRED3339]] release monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3341:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3340]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3341]], ptr [[UIX_ATOMIC_EXPECTED_PTR3337]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3342:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3340]], 1
+// CHECK-NEXT: [[TMP1673:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3342]] to i32
+// CHECK-NEXT: store i32 [[TMP1673]], ptr [[UIR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1674:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1675:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1674]], ptr [[UIX_ATOMIC_EXPECTED_PTR3343]], align 4
+// CHECK-NEXT: store i32 [[TMP1675]], ptr [[UIX_ATOMIC_DESIRED_PTR3344]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3346:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3343]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3347:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3344]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3348:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3346]], i32 [[UIX_CMPXCHG_DESIRED3347]] release monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3349:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3348]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3349]], ptr [[UIX_ATOMIC_EXPECTED_PTR3345]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3350:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3348]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3351:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3345]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3350]], label [[UIX_ATOMIC_EXIT3352:%.*]], label [[UIX_ATOMIC_CONT3353:%.*]]
+// CHECK: uix.atomic.cont3353:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3351]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3352]]
+// CHECK: uix.atomic.exit3352:
+// CHECK-NEXT: [[TMP1676:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3350]] to i32
+// CHECK-NEXT: store i32 [[TMP1676]], ptr [[UIR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1677:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1678:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1677]], ptr [[UIX_ATOMIC_EXPECTED_PTR3354]], align 4
+// CHECK-NEXT: store i32 [[TMP1678]], ptr [[UIX_ATOMIC_DESIRED_PTR3355]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3357:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3354]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3358:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3355]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3359:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3357]], i32 [[UIX_CMPXCHG_DESIRED3358]] release monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3360:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3359]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3360]], ptr [[UIX_ATOMIC_EXPECTED_PTR3356]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3361:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3359]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3362:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3356]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3361]], label [[UIX_ATOMIC_EXIT3363:%.*]], label [[UIX_ATOMIC_CONT3364:%.*]]
+// CHECK: uix.atomic.cont3364:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3362]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3363]]
+// CHECK: uix.atomic.exit3363:
+// CHECK-NEXT: [[TMP1679:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3361]] to i32
+// CHECK-NEXT: store i32 [[TMP1679]], ptr [[UIR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1680:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1681:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1680]] seq_cst, align 4
+// CHECK-NEXT: store i32 [[TMP1681]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1682:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1683:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1682]] seq_cst, align 4
+// CHECK-NEXT: store i32 [[TMP1683]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1684:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1685:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1684]] seq_cst, align 4
+// CHECK-NEXT: store i32 [[TMP1685]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1686:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1687:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1686]] seq_cst, align 4
+// CHECK-NEXT: store i32 [[TMP1687]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1688:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1689:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1688]], ptr [[UIX_ATOMIC_EXPECTED_PTR3365]], align 4
+// CHECK-NEXT: store i32 [[TMP1689]], ptr [[UIX_ATOMIC_DESIRED_PTR3366]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3368:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3365]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3369:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3366]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3370:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3368]], i32 [[UIX_CMPXCHG_DESIRED3369]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3371:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3370]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3371]], ptr [[UIX_ATOMIC_EXPECTED_PTR3367]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3372:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3370]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3373:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3367]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3373]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1690:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1691:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1690]], ptr [[UIX_ATOMIC_EXPECTED_PTR3374]], align 4
+// CHECK-NEXT: store i32 [[TMP1691]], ptr [[UIX_ATOMIC_DESIRED_PTR3375]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3377:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3374]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3378:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3375]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3379:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3377]], i32 [[UIX_CMPXCHG_DESIRED3378]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3380:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3379]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3380]], ptr [[UIX_ATOMIC_EXPECTED_PTR3376]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3381:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3379]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3382:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3376]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3382]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1692:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1693:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1692]] seq_cst, align 4
+// CHECK-NEXT: [[TMP1694:%.*]] = icmp ugt i32 [[TMP1693]], [[TMP1692]]
+// CHECK-NEXT: [[TMP1695:%.*]] = select i1 [[TMP1694]], i32 [[TMP1692]], i32 [[TMP1693]]
+// CHECK-NEXT: store i32 [[TMP1695]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1696:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1697:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1696]] seq_cst, align 4
+// CHECK-NEXT: [[TMP1698:%.*]] = icmp ult i32 [[TMP1697]], [[TMP1696]]
+// CHECK-NEXT: [[TMP1699:%.*]] = select i1 [[TMP1698]], i32 [[TMP1696]], i32 [[TMP1697]]
+// CHECK-NEXT: store i32 [[TMP1699]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1700:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1701:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP1700]] seq_cst, align 4
+// CHECK-NEXT: [[TMP1702:%.*]] = icmp ult i32 [[TMP1701]], [[TMP1700]]
+// CHECK-NEXT: [[TMP1703:%.*]] = select i1 [[TMP1702]], i32 [[TMP1700]], i32 [[TMP1701]]
+// CHECK-NEXT: store i32 [[TMP1703]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1704:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1705:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP1704]] seq_cst, align 4
+// CHECK-NEXT: [[TMP1706:%.*]] = icmp ugt i32 [[TMP1705]], [[TMP1704]]
+// CHECK-NEXT: [[TMP1707:%.*]] = select i1 [[TMP1706]], i32 [[TMP1704]], i32 [[TMP1705]]
+// CHECK-NEXT: store i32 [[TMP1707]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1708:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1709:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1708]], ptr [[UIX_ATOMIC_EXPECTED_PTR3383]], align 4
+// CHECK-NEXT: store i32 [[TMP1709]], ptr [[UIX_ATOMIC_DESIRED_PTR3384]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3386:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3383]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3387:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3384]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3388:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3386]], i32 [[UIX_CMPXCHG_DESIRED3387]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3389:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3388]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3389]], ptr [[UIX_ATOMIC_EXPECTED_PTR3385]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3390:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3388]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3391:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3385]], align 4
+// CHECK-NEXT: [[UIX_CAPTURE_CAPTURED3392:%.*]] = select i1 [[UIX_CMPXCHG_SUCCESS3390]], i32 [[TMP1708]], i32 [[UIX_CAPTURE_ACTUAL3391]]
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_CAPTURED3392]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1710:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1711:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1710]], ptr [[UIX_ATOMIC_EXPECTED_PTR3393]], align 4
+// CHECK-NEXT: store i32 [[TMP1711]], ptr [[UIX_ATOMIC_DESIRED_PTR3394]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3396:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3393]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3397:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3394]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3398:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3396]], i32 [[UIX_CMPXCHG_DESIRED3397]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3399:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3398]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3399]], ptr [[UIX_ATOMIC_EXPECTED_PTR3395]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3400:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3398]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3401:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3395]], align 4
+// CHECK-NEXT: [[UIX_CAPTURE_CAPTURED3402:%.*]] = select i1 [[UIX_CMPXCHG_SUCCESS3400]], i32 [[TMP1710]], i32 [[UIX_CAPTURE_ACTUAL3401]]
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_CAPTURED3402]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1712:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1713:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1712]], ptr [[UIX_ATOMIC_EXPECTED_PTR3403]], align 4
+// CHECK-NEXT: store i32 [[TMP1713]], ptr [[UIX_ATOMIC_DESIRED_PTR3404]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3406:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3403]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3407:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3404]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3408:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3406]], i32 [[UIX_CMPXCHG_DESIRED3407]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3409:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3408]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3409]], ptr [[UIX_ATOMIC_EXPECTED_PTR3405]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3410:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3408]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3411:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3405]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3410]], label [[UIX_ATOMIC_EXIT3412:%.*]], label [[UIX_ATOMIC_CONT3413:%.*]]
+// CHECK: uix.atomic.cont3413:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3411]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3412]]
+// CHECK: uix.atomic.exit3412:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1714:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1715:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1714]], ptr [[UIX_ATOMIC_EXPECTED_PTR3414]], align 4
+// CHECK-NEXT: store i32 [[TMP1715]], ptr [[UIX_ATOMIC_DESIRED_PTR3415]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3417:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3414]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3418:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3415]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3419:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3417]], i32 [[UIX_CMPXCHG_DESIRED3418]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3420:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3419]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3420]], ptr [[UIX_ATOMIC_EXPECTED_PTR3416]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3421:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3419]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3422:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3416]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3421]], label [[UIX_ATOMIC_EXIT3423:%.*]], label [[UIX_ATOMIC_CONT3424:%.*]]
+// CHECK: uix.atomic.cont3424:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3422]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3423]]
+// CHECK: uix.atomic.exit3423:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1716:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1717:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1716]], ptr [[UIX_ATOMIC_EXPECTED_PTR3425]], align 4
+// CHECK-NEXT: store i32 [[TMP1717]], ptr [[UIX_ATOMIC_DESIRED_PTR3426]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3428:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3425]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3429:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3426]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3430:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3428]], i32 [[UIX_CMPXCHG_DESIRED3429]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3431:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3430]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3431]], ptr [[UIX_ATOMIC_EXPECTED_PTR3427]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3432:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3430]], 1
+// CHECK-NEXT: [[TMP1718:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3432]] to i32
+// CHECK-NEXT: store i32 [[TMP1718]], ptr [[UIR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1719:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1720:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1719]], ptr [[UIX_ATOMIC_EXPECTED_PTR3433]], align 4
+// CHECK-NEXT: store i32 [[TMP1720]], ptr [[UIX_ATOMIC_DESIRED_PTR3434]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3436:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3433]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3437:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3434]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3438:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3436]], i32 [[UIX_CMPXCHG_DESIRED3437]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3439:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3438]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3439]], ptr [[UIX_ATOMIC_EXPECTED_PTR3435]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3440:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3438]], 1
+// CHECK-NEXT: [[TMP1721:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3440]] to i32
+// CHECK-NEXT: store i32 [[TMP1721]], ptr [[UIR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1722:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1723:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1722]], ptr [[UIX_ATOMIC_EXPECTED_PTR3441]], align 4
+// CHECK-NEXT: store i32 [[TMP1723]], ptr [[UIX_ATOMIC_DESIRED_PTR3442]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3444:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3441]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3445:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3442]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3446:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3444]], i32 [[UIX_CMPXCHG_DESIRED3445]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3447:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3446]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3447]], ptr [[UIX_ATOMIC_EXPECTED_PTR3443]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3448:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3446]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3449:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3443]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3448]], label [[UIX_ATOMIC_EXIT3450:%.*]], label [[UIX_ATOMIC_CONT3451:%.*]]
+// CHECK: uix.atomic.cont3451:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3449]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3450]]
+// CHECK: uix.atomic.exit3450:
+// CHECK-NEXT: [[TMP1724:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3448]] to i32
+// CHECK-NEXT: store i32 [[TMP1724]], ptr [[UIR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1725:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP1726:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP1725]], ptr [[UIX_ATOMIC_EXPECTED_PTR3452]], align 4
+// CHECK-NEXT: store i32 [[TMP1726]], ptr [[UIX_ATOMIC_DESIRED_PTR3453]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED3455:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3452]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED3456:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3453]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR3457:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED3455]], i32 [[UIX_CMPXCHG_DESIRED3456]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV3458:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3457]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV3458]], ptr [[UIX_ATOMIC_EXPECTED_PTR3454]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS3459:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR3457]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL3460:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR3454]], align 4
+// CHECK-NEXT: br i1 [[UIX_CMPXCHG_SUCCESS3459]], label [[UIX_ATOMIC_EXIT3461:%.*]], label [[UIX_ATOMIC_CONT3462:%.*]]
+// CHECK: uix.atomic.cont3462:
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL3460]], ptr [[UIV]], align 4
+// CHECK-NEXT: br label [[UIX_ATOMIC_EXIT3461]]
+// CHECK: uix.atomic.exit3461:
+// CHECK-NEXT: [[TMP1727:%.*]] = zext i1 [[UIX_CMPXCHG_SUCCESS3459]] to i32
+// CHECK-NEXT: store i32 [[TMP1727]], ptr [[UIR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1728:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1729:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1728]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP1729]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1730:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1731:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1730]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP1731]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1732:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1733:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1732]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP1733]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1734:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1735:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1734]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP1735]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1736:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1737:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1736]], ptr [[LX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: store i64 [[TMP1737]], ptr [[LX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED]], i64 [[LX_CMPXCHG_DESIRED]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV]], ptr [[LX_ATOMIC_EXPECTED_PTR3463]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3463]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1738:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1739:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1738]], ptr [[LX_ATOMIC_EXPECTED_PTR3464]], align 8
+// CHECK-NEXT: store i64 [[TMP1739]], ptr [[LX_ATOMIC_DESIRED_PTR3465]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3467:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3464]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3468:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3465]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3469:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3467]], i64 [[LX_CMPXCHG_DESIRED3468]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3470:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3469]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3470]], ptr [[LX_ATOMIC_EXPECTED_PTR3466]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3471:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3469]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3472:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3466]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3472]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1740:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1741:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1740]] monotonic, align 8
+// CHECK-NEXT: [[TMP1742:%.*]] = icmp sgt i64 [[TMP1741]], [[TMP1740]]
+// CHECK-NEXT: [[TMP1743:%.*]] = select i1 [[TMP1742]], i64 [[TMP1740]], i64 [[TMP1741]]
+// CHECK-NEXT: store i64 [[TMP1743]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1744:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1745:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1744]] monotonic, align 8
+// CHECK-NEXT: [[TMP1746:%.*]] = icmp slt i64 [[TMP1745]], [[TMP1744]]
+// CHECK-NEXT: [[TMP1747:%.*]] = select i1 [[TMP1746]], i64 [[TMP1744]], i64 [[TMP1745]]
+// CHECK-NEXT: store i64 [[TMP1747]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1748:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1749:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1748]] monotonic, align 8
+// CHECK-NEXT: [[TMP1750:%.*]] = icmp slt i64 [[TMP1749]], [[TMP1748]]
+// CHECK-NEXT: [[TMP1751:%.*]] = select i1 [[TMP1750]], i64 [[TMP1748]], i64 [[TMP1749]]
+// CHECK-NEXT: store i64 [[TMP1751]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1752:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1753:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1752]] monotonic, align 8
+// CHECK-NEXT: [[TMP1754:%.*]] = icmp sgt i64 [[TMP1753]], [[TMP1752]]
+// CHECK-NEXT: [[TMP1755:%.*]] = select i1 [[TMP1754]], i64 [[TMP1752]], i64 [[TMP1753]]
+// CHECK-NEXT: store i64 [[TMP1755]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1756:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1757:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1756]], ptr [[LX_ATOMIC_EXPECTED_PTR3473]], align 8
+// CHECK-NEXT: store i64 [[TMP1757]], ptr [[LX_ATOMIC_DESIRED_PTR3474]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3476:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3473]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3477:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3474]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3478:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3476]], i64 [[LX_CMPXCHG_DESIRED3477]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3479:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3478]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3479]], ptr [[LX_ATOMIC_EXPECTED_PTR3475]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3480:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3478]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3481:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3475]], align 8
+// CHECK-NEXT: [[LX_CAPTURE_CAPTURED:%.*]] = select i1 [[LX_CMPXCHG_SUCCESS3480]], i64 [[TMP1756]], i64 [[LX_CAPTURE_ACTUAL3481]]
+// CHECK-NEXT: store i64 [[LX_CAPTURE_CAPTURED]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1758:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1759:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1758]], ptr [[LX_ATOMIC_EXPECTED_PTR3482]], align 8
+// CHECK-NEXT: store i64 [[TMP1759]], ptr [[LX_ATOMIC_DESIRED_PTR3483]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3485:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3482]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3486:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3483]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3487:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3485]], i64 [[LX_CMPXCHG_DESIRED3486]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3488:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3487]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3488]], ptr [[LX_ATOMIC_EXPECTED_PTR3484]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3489:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3487]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3490:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3484]], align 8
+// CHECK-NEXT: [[LX_CAPTURE_CAPTURED3491:%.*]] = select i1 [[LX_CMPXCHG_SUCCESS3489]], i64 [[TMP1758]], i64 [[LX_CAPTURE_ACTUAL3490]]
+// CHECK-NEXT: store i64 [[LX_CAPTURE_CAPTURED3491]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1760:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1761:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1760]], ptr [[LX_ATOMIC_EXPECTED_PTR3492]], align 8
+// CHECK-NEXT: store i64 [[TMP1761]], ptr [[LX_ATOMIC_DESIRED_PTR3493]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3495:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3492]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3496:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3493]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3497:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3495]], i64 [[LX_CMPXCHG_DESIRED3496]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3498:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3497]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3498]], ptr [[LX_ATOMIC_EXPECTED_PTR3494]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3499:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3497]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3500:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3494]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3499]], label [[LX_ATOMIC_EXIT:%.*]], label [[LX_ATOMIC_CONT:%.*]]
// CHECK: lx.atomic.cont:
-// CHECK-NEXT: store i64 [[TMP2855]], ptr [[LV]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3500]], ptr [[LV]], align 8
// CHECK-NEXT: br label [[LX_ATOMIC_EXIT]]
// CHECK: lx.atomic.exit:
-// CHECK-NEXT: [[TMP2857:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2858:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2859:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2857]], i64 [[TMP2858]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP2860:%.*]] = extractvalue { i64, i1 } [[TMP2859]], 0
-// CHECK-NEXT: [[TMP2861:%.*]] = extractvalue { i64, i1 } [[TMP2859]], 1
-// CHECK-NEXT: br i1 [[TMP2861]], label [[LX_ATOMIC_EXIT277:%.*]], label [[LX_ATOMIC_CONT278:%.*]]
-// CHECK: lx.atomic.cont278:
-// CHECK-NEXT: store i64 [[TMP2860]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT277]]
-// CHECK: lx.atomic.exit277:
-// CHECK-NEXT: [[TMP2862:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2863:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2864:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2862]], i64 [[TMP2863]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP2865:%.*]] = extractvalue { i64, i1 } [[TMP2864]], 1
-// CHECK-NEXT: [[TMP2866:%.*]] = sext i1 [[TMP2865]] to i64
-// CHECK-NEXT: store i64 [[TMP2866]], ptr [[LR]], align 8
-// CHECK-NEXT: [[TMP2867:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2868:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2869:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2867]], i64 [[TMP2868]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP2870:%.*]] = extractvalue { i64, i1 } [[TMP2869]], 1
-// CHECK-NEXT: [[TMP2871:%.*]] = sext i1 [[TMP2870]] to i64
-// CHECK-NEXT: store i64 [[TMP2871]], ptr [[LR]], align 8
-// CHECK-NEXT: [[TMP2872:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2873:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2874:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2872]], i64 [[TMP2873]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP2875:%.*]] = extractvalue { i64, i1 } [[TMP2874]], 0
-// CHECK-NEXT: [[TMP2876:%.*]] = extractvalue { i64, i1 } [[TMP2874]], 1
-// CHECK-NEXT: br i1 [[TMP2876]], label [[LX_ATOMIC_EXIT279:%.*]], label [[LX_ATOMIC_CONT280:%.*]]
-// CHECK: lx.atomic.cont280:
-// CHECK-NEXT: store i64 [[TMP2875]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT279]]
-// CHECK: lx.atomic.exit279:
-// CHECK-NEXT: [[TMP2877:%.*]] = extractvalue { i64, i1 } [[TMP2874]], 1
-// CHECK-NEXT: [[TMP2878:%.*]] = sext i1 [[TMP2877]] to i64
-// CHECK-NEXT: store i64 [[TMP2878]], ptr [[LR]], align 8
-// CHECK-NEXT: [[TMP2879:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2880:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2881:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2879]], i64 [[TMP2880]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP2882:%.*]] = extractvalue { i64, i1 } [[TMP2881]], 0
-// CHECK-NEXT: [[TMP2883:%.*]] = extractvalue { i64, i1 } [[TMP2881]], 1
-// CHECK-NEXT: br i1 [[TMP2883]], label [[LX_ATOMIC_EXIT281:%.*]], label [[LX_ATOMIC_CONT282:%.*]]
-// CHECK: lx.atomic.cont282:
-// CHECK-NEXT: store i64 [[TMP2882]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT281]]
-// CHECK: lx.atomic.exit281:
-// CHECK-NEXT: [[TMP2884:%.*]] = extractvalue { i64, i1 } [[TMP2881]], 1
-// CHECK-NEXT: [[TMP2885:%.*]] = sext i1 [[TMP2884]] to i64
-// CHECK-NEXT: store i64 [[TMP2885]], ptr [[LR]], align 8
-// CHECK-NEXT: [[TMP2886:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2887:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2886]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP2887]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2888:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2889:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2888]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP2889]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2890:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2891:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2890]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP2891]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2892:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2893:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2892]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP2893]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2894:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2895:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2896:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2894]], i64 [[TMP2895]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP2897:%.*]] = extractvalue { i64, i1 } [[TMP2896]], 0
-// CHECK-NEXT: store i64 [[TMP2897]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2898:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2899:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2900:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2898]], i64 [[TMP2899]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP2901:%.*]] = extractvalue { i64, i1 } [[TMP2900]], 0
-// CHECK-NEXT: store i64 [[TMP2901]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2902:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2903:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2902]] acq_rel, align 8
-// CHECK-NEXT: [[TMP2904:%.*]] = icmp sgt i64 [[TMP2903]], [[TMP2902]]
-// CHECK-NEXT: [[TMP2905:%.*]] = select i1 [[TMP2904]], i64 [[TMP2902]], i64 [[TMP2903]]
-// CHECK-NEXT: store i64 [[TMP2905]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2906:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2907:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2906]] acq_rel, align 8
-// CHECK-NEXT: [[TMP2908:%.*]] = icmp slt i64 [[TMP2907]], [[TMP2906]]
-// CHECK-NEXT: [[TMP2909:%.*]] = select i1 [[TMP2908]], i64 [[TMP2906]], i64 [[TMP2907]]
-// CHECK-NEXT: store i64 [[TMP2909]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2910:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2911:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2910]] acq_rel, align 8
-// CHECK-NEXT: [[TMP2912:%.*]] = icmp slt i64 [[TMP2911]], [[TMP2910]]
-// CHECK-NEXT: [[TMP2913:%.*]] = select i1 [[TMP2912]], i64 [[TMP2910]], i64 [[TMP2911]]
-// CHECK-NEXT: store i64 [[TMP2913]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2914:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2915:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2914]] acq_rel, align 8
-// CHECK-NEXT: [[TMP2916:%.*]] = icmp sgt i64 [[TMP2915]], [[TMP2914]]
-// CHECK-NEXT: [[TMP2917:%.*]] = select i1 [[TMP2916]], i64 [[TMP2914]], i64 [[TMP2915]]
-// CHECK-NEXT: store i64 [[TMP2917]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2918:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2919:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2920:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2918]], i64 [[TMP2919]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP2921:%.*]] = extractvalue { i64, i1 } [[TMP2920]], 0
-// CHECK-NEXT: [[TMP2922:%.*]] = extractvalue { i64, i1 } [[TMP2920]], 1
-// CHECK-NEXT: [[TMP2923:%.*]] = select i1 [[TMP2922]], i64 [[TMP2918]], i64 [[TMP2921]]
-// CHECK-NEXT: store i64 [[TMP2923]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2924:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2925:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2926:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2924]], i64 [[TMP2925]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP2927:%.*]] = extractvalue { i64, i1 } [[TMP2926]], 0
-// CHECK-NEXT: [[TMP2928:%.*]] = extractvalue { i64, i1 } [[TMP2926]], 1
-// CHECK-NEXT: [[TMP2929:%.*]] = select i1 [[TMP2928]], i64 [[TMP2924]], i64 [[TMP2927]]
-// CHECK-NEXT: store i64 [[TMP2929]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2930:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2931:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2932:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2930]], i64 [[TMP2931]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP2933:%.*]] = extractvalue { i64, i1 } [[TMP2932]], 0
-// CHECK-NEXT: [[TMP2934:%.*]] = extractvalue { i64, i1 } [[TMP2932]], 1
-// CHECK-NEXT: br i1 [[TMP2934]], label [[LX_ATOMIC_EXIT283:%.*]], label [[LX_ATOMIC_CONT284:%.*]]
-// CHECK: lx.atomic.cont284:
-// CHECK-NEXT: store i64 [[TMP2933]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT283]]
-// CHECK: lx.atomic.exit283:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2935:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2936:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2937:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2935]], i64 [[TMP2936]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP2938:%.*]] = extractvalue { i64, i1 } [[TMP2937]], 0
-// CHECK-NEXT: [[TMP2939:%.*]] = extractvalue { i64, i1 } [[TMP2937]], 1
-// CHECK-NEXT: br i1 [[TMP2939]], label [[LX_ATOMIC_EXIT285:%.*]], label [[LX_ATOMIC_CONT286:%.*]]
-// CHECK: lx.atomic.cont286:
-// CHECK-NEXT: store i64 [[TMP2938]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT285]]
-// CHECK: lx.atomic.exit285:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2940:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2941:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2942:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2940]], i64 [[TMP2941]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP2943:%.*]] = extractvalue { i64, i1 } [[TMP2942]], 1
-// CHECK-NEXT: [[TMP2944:%.*]] = sext i1 [[TMP2943]] to i64
-// CHECK-NEXT: store i64 [[TMP2944]], ptr [[LR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2945:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2946:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2947:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2945]], i64 [[TMP2946]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP2948:%.*]] = extractvalue { i64, i1 } [[TMP2947]], 1
-// CHECK-NEXT: [[TMP2949:%.*]] = sext i1 [[TMP2948]] to i64
-// CHECK-NEXT: store i64 [[TMP2949]], ptr [[LR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2950:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2951:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2952:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2950]], i64 [[TMP2951]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP2953:%.*]] = extractvalue { i64, i1 } [[TMP2952]], 0
-// CHECK-NEXT: [[TMP2954:%.*]] = extractvalue { i64, i1 } [[TMP2952]], 1
-// CHECK-NEXT: br i1 [[TMP2954]], label [[LX_ATOMIC_EXIT287:%.*]], label [[LX_ATOMIC_CONT288:%.*]]
-// CHECK: lx.atomic.cont288:
-// CHECK-NEXT: store i64 [[TMP2953]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT287]]
-// CHECK: lx.atomic.exit287:
-// CHECK-NEXT: [[TMP2955:%.*]] = extractvalue { i64, i1 } [[TMP2952]], 1
-// CHECK-NEXT: [[TMP2956:%.*]] = sext i1 [[TMP2955]] to i64
-// CHECK-NEXT: store i64 [[TMP2956]], ptr [[LR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2957:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2958:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2959:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2957]], i64 [[TMP2958]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP2960:%.*]] = extractvalue { i64, i1 } [[TMP2959]], 0
-// CHECK-NEXT: [[TMP2961:%.*]] = extractvalue { i64, i1 } [[TMP2959]], 1
-// CHECK-NEXT: br i1 [[TMP2961]], label [[LX_ATOMIC_EXIT289:%.*]], label [[LX_ATOMIC_CONT290:%.*]]
-// CHECK: lx.atomic.cont290:
-// CHECK-NEXT: store i64 [[TMP2960]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT289]]
-// CHECK: lx.atomic.exit289:
-// CHECK-NEXT: [[TMP2962:%.*]] = extractvalue { i64, i1 } [[TMP2959]], 1
-// CHECK-NEXT: [[TMP2963:%.*]] = sext i1 [[TMP2962]] to i64
-// CHECK-NEXT: store i64 [[TMP2963]], ptr [[LR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP2964:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2965:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2964]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP2965]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2966:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2967:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2966]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP2967]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2968:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2969:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2968]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP2969]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2970:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2971:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2970]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP2971]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2972:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2973:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2974:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2972]], i64 [[TMP2973]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP2975:%.*]] = extractvalue { i64, i1 } [[TMP2974]], 0
-// CHECK-NEXT: store i64 [[TMP2975]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2976:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2977:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2978:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2976]], i64 [[TMP2977]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP2979:%.*]] = extractvalue { i64, i1 } [[TMP2978]], 0
-// CHECK-NEXT: store i64 [[TMP2979]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2980:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2981:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2980]] acquire, align 8
-// CHECK-NEXT: [[TMP2982:%.*]] = icmp sgt i64 [[TMP2981]], [[TMP2980]]
-// CHECK-NEXT: [[TMP2983:%.*]] = select i1 [[TMP2982]], i64 [[TMP2980]], i64 [[TMP2981]]
-// CHECK-NEXT: store i64 [[TMP2983]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2984:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2985:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2984]] acquire, align 8
-// CHECK-NEXT: [[TMP2986:%.*]] = icmp slt i64 [[TMP2985]], [[TMP2984]]
-// CHECK-NEXT: [[TMP2987:%.*]] = select i1 [[TMP2986]], i64 [[TMP2984]], i64 [[TMP2985]]
-// CHECK-NEXT: store i64 [[TMP2987]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2988:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2989:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP2988]] acquire, align 8
-// CHECK-NEXT: [[TMP2990:%.*]] = icmp slt i64 [[TMP2989]], [[TMP2988]]
-// CHECK-NEXT: [[TMP2991:%.*]] = select i1 [[TMP2990]], i64 [[TMP2988]], i64 [[TMP2989]]
-// CHECK-NEXT: store i64 [[TMP2991]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2992:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2993:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP2992]] acquire, align 8
-// CHECK-NEXT: [[TMP2994:%.*]] = icmp sgt i64 [[TMP2993]], [[TMP2992]]
-// CHECK-NEXT: [[TMP2995:%.*]] = select i1 [[TMP2994]], i64 [[TMP2992]], i64 [[TMP2993]]
-// CHECK-NEXT: store i64 [[TMP2995]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP2996:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP2997:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP2998:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP2996]], i64 [[TMP2997]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP2999:%.*]] = extractvalue { i64, i1 } [[TMP2998]], 0
-// CHECK-NEXT: [[TMP3000:%.*]] = extractvalue { i64, i1 } [[TMP2998]], 1
-// CHECK-NEXT: [[TMP3001:%.*]] = select i1 [[TMP3000]], i64 [[TMP2996]], i64 [[TMP2999]]
-// CHECK-NEXT: store i64 [[TMP3001]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP3002:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3003:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3004:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3002]], i64 [[TMP3003]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3005:%.*]] = extractvalue { i64, i1 } [[TMP3004]], 0
-// CHECK-NEXT: [[TMP3006:%.*]] = extractvalue { i64, i1 } [[TMP3004]], 1
-// CHECK-NEXT: [[TMP3007:%.*]] = select i1 [[TMP3006]], i64 [[TMP3002]], i64 [[TMP3005]]
-// CHECK-NEXT: store i64 [[TMP3007]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP3008:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3009:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3010:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3008]], i64 [[TMP3009]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3011:%.*]] = extractvalue { i64, i1 } [[TMP3010]], 0
-// CHECK-NEXT: [[TMP3012:%.*]] = extractvalue { i64, i1 } [[TMP3010]], 1
-// CHECK-NEXT: br i1 [[TMP3012]], label [[LX_ATOMIC_EXIT291:%.*]], label [[LX_ATOMIC_CONT292:%.*]]
-// CHECK: lx.atomic.cont292:
-// CHECK-NEXT: store i64 [[TMP3011]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT291]]
-// CHECK: lx.atomic.exit291:
-// CHECK-NEXT: [[TMP3013:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3014:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3015:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3013]], i64 [[TMP3014]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3016:%.*]] = extractvalue { i64, i1 } [[TMP3015]], 0
-// CHECK-NEXT: [[TMP3017:%.*]] = extractvalue { i64, i1 } [[TMP3015]], 1
-// CHECK-NEXT: br i1 [[TMP3017]], label [[LX_ATOMIC_EXIT293:%.*]], label [[LX_ATOMIC_CONT294:%.*]]
-// CHECK: lx.atomic.cont294:
-// CHECK-NEXT: store i64 [[TMP3016]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT293]]
-// CHECK: lx.atomic.exit293:
-// CHECK-NEXT: [[TMP3018:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3019:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3020:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3018]], i64 [[TMP3019]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3021:%.*]] = extractvalue { i64, i1 } [[TMP3020]], 1
-// CHECK-NEXT: [[TMP3022:%.*]] = sext i1 [[TMP3021]] to i64
-// CHECK-NEXT: store i64 [[TMP3022]], ptr [[LR]], align 8
-// CHECK-NEXT: [[TMP3023:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3024:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3025:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3023]], i64 [[TMP3024]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3026:%.*]] = extractvalue { i64, i1 } [[TMP3025]], 1
-// CHECK-NEXT: [[TMP3027:%.*]] = sext i1 [[TMP3026]] to i64
-// CHECK-NEXT: store i64 [[TMP3027]], ptr [[LR]], align 8
-// CHECK-NEXT: [[TMP3028:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3029:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3030:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3028]], i64 [[TMP3029]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3031:%.*]] = extractvalue { i64, i1 } [[TMP3030]], 0
-// CHECK-NEXT: [[TMP3032:%.*]] = extractvalue { i64, i1 } [[TMP3030]], 1
-// CHECK-NEXT: br i1 [[TMP3032]], label [[LX_ATOMIC_EXIT295:%.*]], label [[LX_ATOMIC_CONT296:%.*]]
-// CHECK: lx.atomic.cont296:
-// CHECK-NEXT: store i64 [[TMP3031]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT295]]
-// CHECK: lx.atomic.exit295:
-// CHECK-NEXT: [[TMP3033:%.*]] = extractvalue { i64, i1 } [[TMP3030]], 1
-// CHECK-NEXT: [[TMP3034:%.*]] = sext i1 [[TMP3033]] to i64
-// CHECK-NEXT: store i64 [[TMP3034]], ptr [[LR]], align 8
-// CHECK-NEXT: [[TMP3035:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3036:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3037:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3035]], i64 [[TMP3036]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3038:%.*]] = extractvalue { i64, i1 } [[TMP3037]], 0
-// CHECK-NEXT: [[TMP3039:%.*]] = extractvalue { i64, i1 } [[TMP3037]], 1
-// CHECK-NEXT: br i1 [[TMP3039]], label [[LX_ATOMIC_EXIT297:%.*]], label [[LX_ATOMIC_CONT298:%.*]]
-// CHECK: lx.atomic.cont298:
-// CHECK-NEXT: store i64 [[TMP3038]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT297]]
-// CHECK: lx.atomic.exit297:
-// CHECK-NEXT: [[TMP3040:%.*]] = extractvalue { i64, i1 } [[TMP3037]], 1
-// CHECK-NEXT: [[TMP3041:%.*]] = sext i1 [[TMP3040]] to i64
-// CHECK-NEXT: store i64 [[TMP3041]], ptr [[LR]], align 8
-// CHECK-NEXT: [[TMP3042:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3043:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3042]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3043]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP3044:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3045:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3044]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3045]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP3046:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3047:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3046]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3047]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP3048:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3049:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3048]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3049]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP3050:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3051:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3052:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3050]], i64 [[TMP3051]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3053:%.*]] = extractvalue { i64, i1 } [[TMP3052]], 0
-// CHECK-NEXT: store i64 [[TMP3053]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP3054:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3055:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3056:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3054]], i64 [[TMP3055]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3057:%.*]] = extractvalue { i64, i1 } [[TMP3056]], 0
-// CHECK-NEXT: store i64 [[TMP3057]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP3058:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3059:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3058]] monotonic, align 8
-// CHECK-NEXT: [[TMP3060:%.*]] = icmp sgt i64 [[TMP3059]], [[TMP3058]]
-// CHECK-NEXT: [[TMP3061:%.*]] = select i1 [[TMP3060]], i64 [[TMP3058]], i64 [[TMP3059]]
-// CHECK-NEXT: store i64 [[TMP3061]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP3062:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3063:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3062]] monotonic, align 8
-// CHECK-NEXT: [[TMP3064:%.*]] = icmp slt i64 [[TMP3063]], [[TMP3062]]
-// CHECK-NEXT: [[TMP3065:%.*]] = select i1 [[TMP3064]], i64 [[TMP3062]], i64 [[TMP3063]]
-// CHECK-NEXT: store i64 [[TMP3065]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP3066:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3067:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3066]] monotonic, align 8
-// CHECK-NEXT: [[TMP3068:%.*]] = icmp slt i64 [[TMP3067]], [[TMP3066]]
-// CHECK-NEXT: [[TMP3069:%.*]] = select i1 [[TMP3068]], i64 [[TMP3066]], i64 [[TMP3067]]
-// CHECK-NEXT: store i64 [[TMP3069]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP3070:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3071:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3070]] monotonic, align 8
-// CHECK-NEXT: [[TMP3072:%.*]] = icmp sgt i64 [[TMP3071]], [[TMP3070]]
-// CHECK-NEXT: [[TMP3073:%.*]] = select i1 [[TMP3072]], i64 [[TMP3070]], i64 [[TMP3071]]
-// CHECK-NEXT: store i64 [[TMP3073]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP3074:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3075:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3076:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3074]], i64 [[TMP3075]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3077:%.*]] = extractvalue { i64, i1 } [[TMP3076]], 0
-// CHECK-NEXT: [[TMP3078:%.*]] = extractvalue { i64, i1 } [[TMP3076]], 1
-// CHECK-NEXT: [[TMP3079:%.*]] = select i1 [[TMP3078]], i64 [[TMP3074]], i64 [[TMP3077]]
-// CHECK-NEXT: store i64 [[TMP3079]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP3080:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3081:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3082:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3080]], i64 [[TMP3081]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3083:%.*]] = extractvalue { i64, i1 } [[TMP3082]], 0
-// CHECK-NEXT: [[TMP3084:%.*]] = extractvalue { i64, i1 } [[TMP3082]], 1
-// CHECK-NEXT: [[TMP3085:%.*]] = select i1 [[TMP3084]], i64 [[TMP3080]], i64 [[TMP3083]]
-// CHECK-NEXT: store i64 [[TMP3085]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP3086:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3087:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3088:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3086]], i64 [[TMP3087]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3089:%.*]] = extractvalue { i64, i1 } [[TMP3088]], 0
-// CHECK-NEXT: [[TMP3090:%.*]] = extractvalue { i64, i1 } [[TMP3088]], 1
-// CHECK-NEXT: br i1 [[TMP3090]], label [[LX_ATOMIC_EXIT299:%.*]], label [[LX_ATOMIC_CONT300:%.*]]
-// CHECK: lx.atomic.cont300:
-// CHECK-NEXT: store i64 [[TMP3089]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT299]]
-// CHECK: lx.atomic.exit299:
-// CHECK-NEXT: [[TMP3091:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3092:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3093:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3091]], i64 [[TMP3092]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3094:%.*]] = extractvalue { i64, i1 } [[TMP3093]], 0
-// CHECK-NEXT: [[TMP3095:%.*]] = extractvalue { i64, i1 } [[TMP3093]], 1
-// CHECK-NEXT: br i1 [[TMP3095]], label [[LX_ATOMIC_EXIT301:%.*]], label [[LX_ATOMIC_CONT302:%.*]]
-// CHECK: lx.atomic.cont302:
-// CHECK-NEXT: store i64 [[TMP3094]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT301]]
-// CHECK: lx.atomic.exit301:
-// CHECK-NEXT: [[TMP3096:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3097:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3098:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3096]], i64 [[TMP3097]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3099:%.*]] = extractvalue { i64, i1 } [[TMP3098]], 1
-// CHECK-NEXT: [[TMP3100:%.*]] = sext i1 [[TMP3099]] to i64
-// CHECK-NEXT: store i64 [[TMP3100]], ptr [[LR]], align 8
-// CHECK-NEXT: [[TMP3101:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3102:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3103:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3101]], i64 [[TMP3102]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3104:%.*]] = extractvalue { i64, i1 } [[TMP3103]], 1
-// CHECK-NEXT: [[TMP3105:%.*]] = sext i1 [[TMP3104]] to i64
-// CHECK-NEXT: store i64 [[TMP3105]], ptr [[LR]], align 8
-// CHECK-NEXT: [[TMP3106:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3107:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3108:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3106]], i64 [[TMP3107]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3109:%.*]] = extractvalue { i64, i1 } [[TMP3108]], 0
-// CHECK-NEXT: [[TMP3110:%.*]] = extractvalue { i64, i1 } [[TMP3108]], 1
-// CHECK-NEXT: br i1 [[TMP3110]], label [[LX_ATOMIC_EXIT303:%.*]], label [[LX_ATOMIC_CONT304:%.*]]
-// CHECK: lx.atomic.cont304:
-// CHECK-NEXT: store i64 [[TMP3109]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT303]]
-// CHECK: lx.atomic.exit303:
-// CHECK-NEXT: [[TMP3111:%.*]] = extractvalue { i64, i1 } [[TMP3108]], 1
-// CHECK-NEXT: [[TMP3112:%.*]] = sext i1 [[TMP3111]] to i64
-// CHECK-NEXT: store i64 [[TMP3112]], ptr [[LR]], align 8
-// CHECK-NEXT: [[TMP3113:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3114:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3115:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3113]], i64 [[TMP3114]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3116:%.*]] = extractvalue { i64, i1 } [[TMP3115]], 0
-// CHECK-NEXT: [[TMP3117:%.*]] = extractvalue { i64, i1 } [[TMP3115]], 1
-// CHECK-NEXT: br i1 [[TMP3117]], label [[LX_ATOMIC_EXIT305:%.*]], label [[LX_ATOMIC_CONT306:%.*]]
-// CHECK: lx.atomic.cont306:
-// CHECK-NEXT: store i64 [[TMP3116]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT305]]
-// CHECK: lx.atomic.exit305:
-// CHECK-NEXT: [[TMP3118:%.*]] = extractvalue { i64, i1 } [[TMP3115]], 1
-// CHECK-NEXT: [[TMP3119:%.*]] = sext i1 [[TMP3118]] to i64
-// CHECK-NEXT: store i64 [[TMP3119]], ptr [[LR]], align 8
-// CHECK-NEXT: [[TMP3120:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3121:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3120]] release, align 8
-// CHECK-NEXT: store i64 [[TMP3121]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3122:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3123:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3122]] release, align 8
-// CHECK-NEXT: store i64 [[TMP3123]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3124:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3125:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3124]] release, align 8
-// CHECK-NEXT: store i64 [[TMP3125]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3126:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3127:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3126]] release, align 8
-// CHECK-NEXT: store i64 [[TMP3127]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3128:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3129:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3130:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3128]], i64 [[TMP3129]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3131:%.*]] = extractvalue { i64, i1 } [[TMP3130]], 0
-// CHECK-NEXT: store i64 [[TMP3131]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3132:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3133:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3134:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3132]], i64 [[TMP3133]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3135:%.*]] = extractvalue { i64, i1 } [[TMP3134]], 0
-// CHECK-NEXT: store i64 [[TMP3135]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3136:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3137:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3136]] release, align 8
-// CHECK-NEXT: [[TMP3138:%.*]] = icmp sgt i64 [[TMP3137]], [[TMP3136]]
-// CHECK-NEXT: [[TMP3139:%.*]] = select i1 [[TMP3138]], i64 [[TMP3136]], i64 [[TMP3137]]
-// CHECK-NEXT: store i64 [[TMP3139]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3140:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3141:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3140]] release, align 8
-// CHECK-NEXT: [[TMP3142:%.*]] = icmp slt i64 [[TMP3141]], [[TMP3140]]
-// CHECK-NEXT: [[TMP3143:%.*]] = select i1 [[TMP3142]], i64 [[TMP3140]], i64 [[TMP3141]]
-// CHECK-NEXT: store i64 [[TMP3143]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3144:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3145:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3144]] release, align 8
-// CHECK-NEXT: [[TMP3146:%.*]] = icmp slt i64 [[TMP3145]], [[TMP3144]]
-// CHECK-NEXT: [[TMP3147:%.*]] = select i1 [[TMP3146]], i64 [[TMP3144]], i64 [[TMP3145]]
-// CHECK-NEXT: store i64 [[TMP3147]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3148:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3149:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3148]] release, align 8
-// CHECK-NEXT: [[TMP3150:%.*]] = icmp sgt i64 [[TMP3149]], [[TMP3148]]
-// CHECK-NEXT: [[TMP3151:%.*]] = select i1 [[TMP3150]], i64 [[TMP3148]], i64 [[TMP3149]]
-// CHECK-NEXT: store i64 [[TMP3151]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3152:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3153:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3154:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3152]], i64 [[TMP3153]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3155:%.*]] = extractvalue { i64, i1 } [[TMP3154]], 0
-// CHECK-NEXT: [[TMP3156:%.*]] = extractvalue { i64, i1 } [[TMP3154]], 1
-// CHECK-NEXT: [[TMP3157:%.*]] = select i1 [[TMP3156]], i64 [[TMP3152]], i64 [[TMP3155]]
-// CHECK-NEXT: store i64 [[TMP3157]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3158:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3159:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3160:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3158]], i64 [[TMP3159]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3161:%.*]] = extractvalue { i64, i1 } [[TMP3160]], 0
-// CHECK-NEXT: [[TMP3162:%.*]] = extractvalue { i64, i1 } [[TMP3160]], 1
-// CHECK-NEXT: [[TMP3163:%.*]] = select i1 [[TMP3162]], i64 [[TMP3158]], i64 [[TMP3161]]
-// CHECK-NEXT: store i64 [[TMP3163]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3164:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3165:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3166:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3164]], i64 [[TMP3165]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3167:%.*]] = extractvalue { i64, i1 } [[TMP3166]], 0
-// CHECK-NEXT: [[TMP3168:%.*]] = extractvalue { i64, i1 } [[TMP3166]], 1
-// CHECK-NEXT: br i1 [[TMP3168]], label [[LX_ATOMIC_EXIT307:%.*]], label [[LX_ATOMIC_CONT308:%.*]]
-// CHECK: lx.atomic.cont308:
-// CHECK-NEXT: store i64 [[TMP3167]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT307]]
-// CHECK: lx.atomic.exit307:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3169:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3170:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3171:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3169]], i64 [[TMP3170]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3172:%.*]] = extractvalue { i64, i1 } [[TMP3171]], 0
-// CHECK-NEXT: [[TMP3173:%.*]] = extractvalue { i64, i1 } [[TMP3171]], 1
-// CHECK-NEXT: br i1 [[TMP3173]], label [[LX_ATOMIC_EXIT309:%.*]], label [[LX_ATOMIC_CONT310:%.*]]
-// CHECK: lx.atomic.cont310:
-// CHECK-NEXT: store i64 [[TMP3172]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT309]]
-// CHECK: lx.atomic.exit309:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3174:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3175:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3176:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3174]], i64 [[TMP3175]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3177:%.*]] = extractvalue { i64, i1 } [[TMP3176]], 1
-// CHECK-NEXT: [[TMP3178:%.*]] = sext i1 [[TMP3177]] to i64
-// CHECK-NEXT: store i64 [[TMP3178]], ptr [[LR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3179:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3180:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3181:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3179]], i64 [[TMP3180]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3182:%.*]] = extractvalue { i64, i1 } [[TMP3181]], 1
-// CHECK-NEXT: [[TMP3183:%.*]] = sext i1 [[TMP3182]] to i64
-// CHECK-NEXT: store i64 [[TMP3183]], ptr [[LR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3184:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3185:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3186:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3184]], i64 [[TMP3185]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3187:%.*]] = extractvalue { i64, i1 } [[TMP3186]], 0
-// CHECK-NEXT: [[TMP3188:%.*]] = extractvalue { i64, i1 } [[TMP3186]], 1
-// CHECK-NEXT: br i1 [[TMP3188]], label [[LX_ATOMIC_EXIT311:%.*]], label [[LX_ATOMIC_CONT312:%.*]]
-// CHECK: lx.atomic.cont312:
-// CHECK-NEXT: store i64 [[TMP3187]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT311]]
-// CHECK: lx.atomic.exit311:
-// CHECK-NEXT: [[TMP3189:%.*]] = extractvalue { i64, i1 } [[TMP3186]], 1
-// CHECK-NEXT: [[TMP3190:%.*]] = sext i1 [[TMP3189]] to i64
-// CHECK-NEXT: store i64 [[TMP3190]], ptr [[LR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3191:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3192:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3193:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3191]], i64 [[TMP3192]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3194:%.*]] = extractvalue { i64, i1 } [[TMP3193]], 0
-// CHECK-NEXT: [[TMP3195:%.*]] = extractvalue { i64, i1 } [[TMP3193]], 1
-// CHECK-NEXT: br i1 [[TMP3195]], label [[LX_ATOMIC_EXIT313:%.*]], label [[LX_ATOMIC_CONT314:%.*]]
-// CHECK: lx.atomic.cont314:
-// CHECK-NEXT: store i64 [[TMP3194]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT313]]
-// CHECK: lx.atomic.exit313:
-// CHECK-NEXT: [[TMP3196:%.*]] = extractvalue { i64, i1 } [[TMP3193]], 1
-// CHECK-NEXT: [[TMP3197:%.*]] = sext i1 [[TMP3196]] to i64
-// CHECK-NEXT: store i64 [[TMP3197]], ptr [[LR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3198:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3199:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3198]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP3199]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3200:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3201:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3200]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP3201]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3202:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3203:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3202]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP3203]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3204:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3205:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3204]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP3205]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3206:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3207:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3208:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3206]], i64 [[TMP3207]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3209:%.*]] = extractvalue { i64, i1 } [[TMP3208]], 0
-// CHECK-NEXT: store i64 [[TMP3209]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3210:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3211:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3212:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3210]], i64 [[TMP3211]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3213:%.*]] = extractvalue { i64, i1 } [[TMP3212]], 0
-// CHECK-NEXT: store i64 [[TMP3213]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3214:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3215:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3214]] seq_cst, align 8
-// CHECK-NEXT: [[TMP3216:%.*]] = icmp sgt i64 [[TMP3215]], [[TMP3214]]
-// CHECK-NEXT: [[TMP3217:%.*]] = select i1 [[TMP3216]], i64 [[TMP3214]], i64 [[TMP3215]]
-// CHECK-NEXT: store i64 [[TMP3217]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3218:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3219:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3218]] seq_cst, align 8
-// CHECK-NEXT: [[TMP3220:%.*]] = icmp slt i64 [[TMP3219]], [[TMP3218]]
-// CHECK-NEXT: [[TMP3221:%.*]] = select i1 [[TMP3220]], i64 [[TMP3218]], i64 [[TMP3219]]
-// CHECK-NEXT: store i64 [[TMP3221]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3222:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3223:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP3222]] seq_cst, align 8
-// CHECK-NEXT: [[TMP3224:%.*]] = icmp slt i64 [[TMP3223]], [[TMP3222]]
-// CHECK-NEXT: [[TMP3225:%.*]] = select i1 [[TMP3224]], i64 [[TMP3222]], i64 [[TMP3223]]
-// CHECK-NEXT: store i64 [[TMP3225]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3226:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3227:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP3226]] seq_cst, align 8
-// CHECK-NEXT: [[TMP3228:%.*]] = icmp sgt i64 [[TMP3227]], [[TMP3226]]
-// CHECK-NEXT: [[TMP3229:%.*]] = select i1 [[TMP3228]], i64 [[TMP3226]], i64 [[TMP3227]]
-// CHECK-NEXT: store i64 [[TMP3229]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3230:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3231:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3232:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3230]], i64 [[TMP3231]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3233:%.*]] = extractvalue { i64, i1 } [[TMP3232]], 0
-// CHECK-NEXT: [[TMP3234:%.*]] = extractvalue { i64, i1 } [[TMP3232]], 1
-// CHECK-NEXT: [[TMP3235:%.*]] = select i1 [[TMP3234]], i64 [[TMP3230]], i64 [[TMP3233]]
-// CHECK-NEXT: store i64 [[TMP3235]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3236:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3237:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3238:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3236]], i64 [[TMP3237]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3239:%.*]] = extractvalue { i64, i1 } [[TMP3238]], 0
-// CHECK-NEXT: [[TMP3240:%.*]] = extractvalue { i64, i1 } [[TMP3238]], 1
-// CHECK-NEXT: [[TMP3241:%.*]] = select i1 [[TMP3240]], i64 [[TMP3236]], i64 [[TMP3239]]
-// CHECK-NEXT: store i64 [[TMP3241]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3242:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3243:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3244:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3242]], i64 [[TMP3243]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3245:%.*]] = extractvalue { i64, i1 } [[TMP3244]], 0
-// CHECK-NEXT: [[TMP3246:%.*]] = extractvalue { i64, i1 } [[TMP3244]], 1
-// CHECK-NEXT: br i1 [[TMP3246]], label [[LX_ATOMIC_EXIT315:%.*]], label [[LX_ATOMIC_CONT316:%.*]]
-// CHECK: lx.atomic.cont316:
-// CHECK-NEXT: store i64 [[TMP3245]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT315]]
-// CHECK: lx.atomic.exit315:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3247:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3248:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3249:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3247]], i64 [[TMP3248]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3250:%.*]] = extractvalue { i64, i1 } [[TMP3249]], 0
-// CHECK-NEXT: [[TMP3251:%.*]] = extractvalue { i64, i1 } [[TMP3249]], 1
-// CHECK-NEXT: br i1 [[TMP3251]], label [[LX_ATOMIC_EXIT317:%.*]], label [[LX_ATOMIC_CONT318:%.*]]
-// CHECK: lx.atomic.cont318:
-// CHECK-NEXT: store i64 [[TMP3250]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT317]]
-// CHECK: lx.atomic.exit317:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3252:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3253:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3254:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3252]], i64 [[TMP3253]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3255:%.*]] = extractvalue { i64, i1 } [[TMP3254]], 1
-// CHECK-NEXT: [[TMP3256:%.*]] = sext i1 [[TMP3255]] to i64
-// CHECK-NEXT: store i64 [[TMP3256]], ptr [[LR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3257:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3258:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3259:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3257]], i64 [[TMP3258]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3260:%.*]] = extractvalue { i64, i1 } [[TMP3259]], 1
-// CHECK-NEXT: [[TMP3261:%.*]] = sext i1 [[TMP3260]] to i64
-// CHECK-NEXT: store i64 [[TMP3261]], ptr [[LR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3262:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3263:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3264:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3262]], i64 [[TMP3263]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3265:%.*]] = extractvalue { i64, i1 } [[TMP3264]], 0
-// CHECK-NEXT: [[TMP3266:%.*]] = extractvalue { i64, i1 } [[TMP3264]], 1
-// CHECK-NEXT: br i1 [[TMP3266]], label [[LX_ATOMIC_EXIT319:%.*]], label [[LX_ATOMIC_CONT320:%.*]]
-// CHECK: lx.atomic.cont320:
-// CHECK-NEXT: store i64 [[TMP3265]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT319]]
-// CHECK: lx.atomic.exit319:
-// CHECK-NEXT: [[TMP3267:%.*]] = extractvalue { i64, i1 } [[TMP3264]], 1
-// CHECK-NEXT: [[TMP3268:%.*]] = sext i1 [[TMP3267]] to i64
-// CHECK-NEXT: store i64 [[TMP3268]], ptr [[LR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3269:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP3270:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP3271:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP3269]], i64 [[TMP3270]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3272:%.*]] = extractvalue { i64, i1 } [[TMP3271]], 0
-// CHECK-NEXT: [[TMP3273:%.*]] = extractvalue { i64, i1 } [[TMP3271]], 1
-// CHECK-NEXT: br i1 [[TMP3273]], label [[LX_ATOMIC_EXIT321:%.*]], label [[LX_ATOMIC_CONT322:%.*]]
-// CHECK: lx.atomic.cont322:
-// CHECK-NEXT: store i64 [[TMP3272]], ptr [[LV]], align 8
-// CHECK-NEXT: br label [[LX_ATOMIC_EXIT321]]
-// CHECK: lx.atomic.exit321:
-// CHECK-NEXT: [[TMP3274:%.*]] = extractvalue { i64, i1 } [[TMP3271]], 1
-// CHECK-NEXT: [[TMP3275:%.*]] = sext i1 [[TMP3274]] to i64
-// CHECK-NEXT: store i64 [[TMP3275]], ptr [[LR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3276:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3277:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3276]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3277]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3278:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3279:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3278]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3279]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3280:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3281:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3280]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3281]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3282:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3283:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3282]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3283]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3284:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3285:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3286:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3284]], i64 [[TMP3285]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3287:%.*]] = extractvalue { i64, i1 } [[TMP3286]], 0
-// CHECK-NEXT: store i64 [[TMP3287]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3288:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3289:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3290:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3288]], i64 [[TMP3289]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3291:%.*]] = extractvalue { i64, i1 } [[TMP3290]], 0
-// CHECK-NEXT: store i64 [[TMP3291]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3292:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3293:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3292]] monotonic, align 8
-// CHECK-NEXT: [[TMP3294:%.*]] = icmp ugt i64 [[TMP3293]], [[TMP3292]]
-// CHECK-NEXT: [[TMP3295:%.*]] = select i1 [[TMP3294]], i64 [[TMP3292]], i64 [[TMP3293]]
-// CHECK-NEXT: store i64 [[TMP3295]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3296:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3297:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3296]] monotonic, align 8
-// CHECK-NEXT: [[TMP3298:%.*]] = icmp ult i64 [[TMP3297]], [[TMP3296]]
-// CHECK-NEXT: [[TMP3299:%.*]] = select i1 [[TMP3298]], i64 [[TMP3296]], i64 [[TMP3297]]
-// CHECK-NEXT: store i64 [[TMP3299]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3300:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3301:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3300]] monotonic, align 8
-// CHECK-NEXT: [[TMP3302:%.*]] = icmp ult i64 [[TMP3301]], [[TMP3300]]
-// CHECK-NEXT: [[TMP3303:%.*]] = select i1 [[TMP3302]], i64 [[TMP3300]], i64 [[TMP3301]]
-// CHECK-NEXT: store i64 [[TMP3303]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3304:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3305:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3304]] monotonic, align 8
-// CHECK-NEXT: [[TMP3306:%.*]] = icmp ugt i64 [[TMP3305]], [[TMP3304]]
-// CHECK-NEXT: [[TMP3307:%.*]] = select i1 [[TMP3306]], i64 [[TMP3304]], i64 [[TMP3305]]
-// CHECK-NEXT: store i64 [[TMP3307]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3308:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3309:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3310:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3308]], i64 [[TMP3309]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3311:%.*]] = extractvalue { i64, i1 } [[TMP3310]], 0
-// CHECK-NEXT: [[TMP3312:%.*]] = extractvalue { i64, i1 } [[TMP3310]], 1
-// CHECK-NEXT: [[TMP3313:%.*]] = select i1 [[TMP3312]], i64 [[TMP3308]], i64 [[TMP3311]]
-// CHECK-NEXT: store i64 [[TMP3313]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3314:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3315:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3316:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3314]], i64 [[TMP3315]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3317:%.*]] = extractvalue { i64, i1 } [[TMP3316]], 0
-// CHECK-NEXT: [[TMP3318:%.*]] = extractvalue { i64, i1 } [[TMP3316]], 1
-// CHECK-NEXT: [[TMP3319:%.*]] = select i1 [[TMP3318]], i64 [[TMP3314]], i64 [[TMP3317]]
-// CHECK-NEXT: store i64 [[TMP3319]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3320:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3321:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3322:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3320]], i64 [[TMP3321]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3323:%.*]] = extractvalue { i64, i1 } [[TMP3322]], 0
-// CHECK-NEXT: [[TMP3324:%.*]] = extractvalue { i64, i1 } [[TMP3322]], 1
-// CHECK-NEXT: br i1 [[TMP3324]], label [[ULX_ATOMIC_EXIT:%.*]], label [[ULX_ATOMIC_CONT:%.*]]
+// CHECK-NEXT: [[TMP1762:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1763:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1762]], ptr [[LX_ATOMIC_EXPECTED_PTR3501]], align 8
+// CHECK-NEXT: store i64 [[TMP1763]], ptr [[LX_ATOMIC_DESIRED_PTR3502]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3504:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3501]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3505:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3502]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3506:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3504]], i64 [[LX_CMPXCHG_DESIRED3505]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3507:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3506]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3507]], ptr [[LX_ATOMIC_EXPECTED_PTR3503]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3508:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3506]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3509:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3503]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3508]], label [[LX_ATOMIC_EXIT3510:%.*]], label [[LX_ATOMIC_CONT3511:%.*]]
+// CHECK: lx.atomic.cont3511:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3509]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3510]]
+// CHECK: lx.atomic.exit3510:
+// CHECK-NEXT: [[TMP1764:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1765:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1764]], ptr [[LX_ATOMIC_EXPECTED_PTR3512]], align 8
+// CHECK-NEXT: store i64 [[TMP1765]], ptr [[LX_ATOMIC_DESIRED_PTR3513]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3515:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3512]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3516:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3513]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3517:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3515]], i64 [[LX_CMPXCHG_DESIRED3516]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3518:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3517]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3518]], ptr [[LX_ATOMIC_EXPECTED_PTR3514]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3519:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3517]], 1
+// CHECK-NEXT: [[TMP1766:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3519]] to i64
+// CHECK-NEXT: store i64 [[TMP1766]], ptr [[LR]], align 8
+// CHECK-NEXT: [[TMP1767:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1768:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1767]], ptr [[LX_ATOMIC_EXPECTED_PTR3520]], align 8
+// CHECK-NEXT: store i64 [[TMP1768]], ptr [[LX_ATOMIC_DESIRED_PTR3521]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3523:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3520]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3524:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3521]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3525:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3523]], i64 [[LX_CMPXCHG_DESIRED3524]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3526:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3525]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3526]], ptr [[LX_ATOMIC_EXPECTED_PTR3522]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3527:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3525]], 1
+// CHECK-NEXT: [[TMP1769:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3527]] to i64
+// CHECK-NEXT: store i64 [[TMP1769]], ptr [[LR]], align 8
+// CHECK-NEXT: [[TMP1770:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1771:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1770]], ptr [[LX_ATOMIC_EXPECTED_PTR3528]], align 8
+// CHECK-NEXT: store i64 [[TMP1771]], ptr [[LX_ATOMIC_DESIRED_PTR3529]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3531:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3528]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3532:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3529]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3533:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3531]], i64 [[LX_CMPXCHG_DESIRED3532]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3534:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3533]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3534]], ptr [[LX_ATOMIC_EXPECTED_PTR3530]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3535:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3533]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3536:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3530]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3535]], label [[LX_ATOMIC_EXIT3537:%.*]], label [[LX_ATOMIC_CONT3538:%.*]]
+// CHECK: lx.atomic.cont3538:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3536]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3537]]
+// CHECK: lx.atomic.exit3537:
+// CHECK-NEXT: [[TMP1772:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3535]] to i64
+// CHECK-NEXT: store i64 [[TMP1772]], ptr [[LR]], align 8
+// CHECK-NEXT: [[TMP1773:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1774:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1773]], ptr [[LX_ATOMIC_EXPECTED_PTR3539]], align 8
+// CHECK-NEXT: store i64 [[TMP1774]], ptr [[LX_ATOMIC_DESIRED_PTR3540]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3542:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3539]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3543:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3540]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3544:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3542]], i64 [[LX_CMPXCHG_DESIRED3543]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3545:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3544]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3545]], ptr [[LX_ATOMIC_EXPECTED_PTR3541]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3546:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3544]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3547:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3541]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3546]], label [[LX_ATOMIC_EXIT3548:%.*]], label [[LX_ATOMIC_CONT3549:%.*]]
+// CHECK: lx.atomic.cont3549:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3547]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3548]]
+// CHECK: lx.atomic.exit3548:
+// CHECK-NEXT: [[TMP1775:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3546]] to i64
+// CHECK-NEXT: store i64 [[TMP1775]], ptr [[LR]], align 8
+// CHECK-NEXT: [[TMP1776:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1777:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1776]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP1777]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1778:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1779:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1778]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP1779]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1780:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1781:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1780]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP1781]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1782:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1783:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1782]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP1783]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1784:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1785:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1784]], ptr [[LX_ATOMIC_EXPECTED_PTR3550]], align 8
+// CHECK-NEXT: store i64 [[TMP1785]], ptr [[LX_ATOMIC_DESIRED_PTR3551]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3553:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3550]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3554:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3551]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3555:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3553]], i64 [[LX_CMPXCHG_DESIRED3554]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3556:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3555]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3556]], ptr [[LX_ATOMIC_EXPECTED_PTR3552]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3557:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3555]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3558:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3552]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3558]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1786:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1787:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1786]], ptr [[LX_ATOMIC_EXPECTED_PTR3559]], align 8
+// CHECK-NEXT: store i64 [[TMP1787]], ptr [[LX_ATOMIC_DESIRED_PTR3560]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3562:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3559]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3563:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3560]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3564:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3562]], i64 [[LX_CMPXCHG_DESIRED3563]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3565:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3564]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3565]], ptr [[LX_ATOMIC_EXPECTED_PTR3561]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3566:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3564]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3567:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3561]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3567]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1788:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1789:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1788]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1790:%.*]] = icmp sgt i64 [[TMP1789]], [[TMP1788]]
+// CHECK-NEXT: [[TMP1791:%.*]] = select i1 [[TMP1790]], i64 [[TMP1788]], i64 [[TMP1789]]
+// CHECK-NEXT: store i64 [[TMP1791]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1792:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1793:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1792]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1794:%.*]] = icmp slt i64 [[TMP1793]], [[TMP1792]]
+// CHECK-NEXT: [[TMP1795:%.*]] = select i1 [[TMP1794]], i64 [[TMP1792]], i64 [[TMP1793]]
+// CHECK-NEXT: store i64 [[TMP1795]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1796:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1797:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1796]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1798:%.*]] = icmp slt i64 [[TMP1797]], [[TMP1796]]
+// CHECK-NEXT: [[TMP1799:%.*]] = select i1 [[TMP1798]], i64 [[TMP1796]], i64 [[TMP1797]]
+// CHECK-NEXT: store i64 [[TMP1799]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1800:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1801:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1800]] acq_rel, align 8
+// CHECK-NEXT: [[TMP1802:%.*]] = icmp sgt i64 [[TMP1801]], [[TMP1800]]
+// CHECK-NEXT: [[TMP1803:%.*]] = select i1 [[TMP1802]], i64 [[TMP1800]], i64 [[TMP1801]]
+// CHECK-NEXT: store i64 [[TMP1803]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1804:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1805:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1804]], ptr [[LX_ATOMIC_EXPECTED_PTR3568]], align 8
+// CHECK-NEXT: store i64 [[TMP1805]], ptr [[LX_ATOMIC_DESIRED_PTR3569]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3571:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3568]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3572:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3569]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3573:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3571]], i64 [[LX_CMPXCHG_DESIRED3572]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3574:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3573]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3574]], ptr [[LX_ATOMIC_EXPECTED_PTR3570]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3575:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3573]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3576:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3570]], align 8
+// CHECK-NEXT: [[LX_CAPTURE_CAPTURED3577:%.*]] = select i1 [[LX_CMPXCHG_SUCCESS3575]], i64 [[TMP1804]], i64 [[LX_CAPTURE_ACTUAL3576]]
+// CHECK-NEXT: store i64 [[LX_CAPTURE_CAPTURED3577]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1806:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1807:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1806]], ptr [[LX_ATOMIC_EXPECTED_PTR3578]], align 8
+// CHECK-NEXT: store i64 [[TMP1807]], ptr [[LX_ATOMIC_DESIRED_PTR3579]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3581:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3578]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3582:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3579]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3583:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3581]], i64 [[LX_CMPXCHG_DESIRED3582]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3584:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3583]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3584]], ptr [[LX_ATOMIC_EXPECTED_PTR3580]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3585:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3583]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3586:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3580]], align 8
+// CHECK-NEXT: [[LX_CAPTURE_CAPTURED3587:%.*]] = select i1 [[LX_CMPXCHG_SUCCESS3585]], i64 [[TMP1806]], i64 [[LX_CAPTURE_ACTUAL3586]]
+// CHECK-NEXT: store i64 [[LX_CAPTURE_CAPTURED3587]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1808:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1809:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1808]], ptr [[LX_ATOMIC_EXPECTED_PTR3588]], align 8
+// CHECK-NEXT: store i64 [[TMP1809]], ptr [[LX_ATOMIC_DESIRED_PTR3589]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3591:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3588]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3592:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3589]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3593:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3591]], i64 [[LX_CMPXCHG_DESIRED3592]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3594:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3593]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3594]], ptr [[LX_ATOMIC_EXPECTED_PTR3590]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3595:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3593]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3596:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3590]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3595]], label [[LX_ATOMIC_EXIT3597:%.*]], label [[LX_ATOMIC_CONT3598:%.*]]
+// CHECK: lx.atomic.cont3598:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3596]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3597]]
+// CHECK: lx.atomic.exit3597:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1810:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1811:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1810]], ptr [[LX_ATOMIC_EXPECTED_PTR3599]], align 8
+// CHECK-NEXT: store i64 [[TMP1811]], ptr [[LX_ATOMIC_DESIRED_PTR3600]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3602:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3599]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3603:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3600]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3604:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3602]], i64 [[LX_CMPXCHG_DESIRED3603]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3605:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3604]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3605]], ptr [[LX_ATOMIC_EXPECTED_PTR3601]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3606:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3604]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3607:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3601]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3606]], label [[LX_ATOMIC_EXIT3608:%.*]], label [[LX_ATOMIC_CONT3609:%.*]]
+// CHECK: lx.atomic.cont3609:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3607]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3608]]
+// CHECK: lx.atomic.exit3608:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1812:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1813:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1812]], ptr [[LX_ATOMIC_EXPECTED_PTR3610]], align 8
+// CHECK-NEXT: store i64 [[TMP1813]], ptr [[LX_ATOMIC_DESIRED_PTR3611]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3613:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3610]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3614:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3611]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3615:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3613]], i64 [[LX_CMPXCHG_DESIRED3614]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3616:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3615]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3616]], ptr [[LX_ATOMIC_EXPECTED_PTR3612]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3617:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3615]], 1
+// CHECK-NEXT: [[TMP1814:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3617]] to i64
+// CHECK-NEXT: store i64 [[TMP1814]], ptr [[LR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1815:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1816:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1815]], ptr [[LX_ATOMIC_EXPECTED_PTR3618]], align 8
+// CHECK-NEXT: store i64 [[TMP1816]], ptr [[LX_ATOMIC_DESIRED_PTR3619]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3621:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3618]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3622:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3619]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3623:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3621]], i64 [[LX_CMPXCHG_DESIRED3622]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3624:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3623]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3624]], ptr [[LX_ATOMIC_EXPECTED_PTR3620]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3625:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3623]], 1
+// CHECK-NEXT: [[TMP1817:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3625]] to i64
+// CHECK-NEXT: store i64 [[TMP1817]], ptr [[LR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1818:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1819:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1818]], ptr [[LX_ATOMIC_EXPECTED_PTR3626]], align 8
+// CHECK-NEXT: store i64 [[TMP1819]], ptr [[LX_ATOMIC_DESIRED_PTR3627]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3629:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3626]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3630:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3627]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3631:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3629]], i64 [[LX_CMPXCHG_DESIRED3630]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3632:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3631]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3632]], ptr [[LX_ATOMIC_EXPECTED_PTR3628]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3633:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3631]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3634:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3628]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3633]], label [[LX_ATOMIC_EXIT3635:%.*]], label [[LX_ATOMIC_CONT3636:%.*]]
+// CHECK: lx.atomic.cont3636:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3634]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3635]]
+// CHECK: lx.atomic.exit3635:
+// CHECK-NEXT: [[TMP1820:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3633]] to i64
+// CHECK-NEXT: store i64 [[TMP1820]], ptr [[LR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1821:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1822:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1821]], ptr [[LX_ATOMIC_EXPECTED_PTR3637]], align 8
+// CHECK-NEXT: store i64 [[TMP1822]], ptr [[LX_ATOMIC_DESIRED_PTR3638]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3640:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3637]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3641:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3638]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3642:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3640]], i64 [[LX_CMPXCHG_DESIRED3641]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3643:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3642]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3643]], ptr [[LX_ATOMIC_EXPECTED_PTR3639]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3644:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3642]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3645:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3639]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3644]], label [[LX_ATOMIC_EXIT3646:%.*]], label [[LX_ATOMIC_CONT3647:%.*]]
+// CHECK: lx.atomic.cont3647:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3645]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3646]]
+// CHECK: lx.atomic.exit3646:
+// CHECK-NEXT: [[TMP1823:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3644]] to i64
+// CHECK-NEXT: store i64 [[TMP1823]], ptr [[LR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1824:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1825:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1824]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP1825]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1826:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1827:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1826]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP1827]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1828:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1829:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1828]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP1829]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1830:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1831:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1830]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP1831]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1832:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1833:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1832]], ptr [[LX_ATOMIC_EXPECTED_PTR3648]], align 8
+// CHECK-NEXT: store i64 [[TMP1833]], ptr [[LX_ATOMIC_DESIRED_PTR3649]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3651:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3648]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3652:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3649]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3653:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3651]], i64 [[LX_CMPXCHG_DESIRED3652]] acquire acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3654:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3653]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3654]], ptr [[LX_ATOMIC_EXPECTED_PTR3650]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3655:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3653]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3656:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3650]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3656]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1834:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1835:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1834]], ptr [[LX_ATOMIC_EXPECTED_PTR3657]], align 8
+// CHECK-NEXT: store i64 [[TMP1835]], ptr [[LX_ATOMIC_DESIRED_PTR3658]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3660:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3657]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3661:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3658]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3662:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3660]], i64 [[LX_CMPXCHG_DESIRED3661]] acquire acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3663:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3662]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3663]], ptr [[LX_ATOMIC_EXPECTED_PTR3659]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3664:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3662]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3665:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3659]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3665]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1836:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1837:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1836]] acquire, align 8
+// CHECK-NEXT: [[TMP1838:%.*]] = icmp sgt i64 [[TMP1837]], [[TMP1836]]
+// CHECK-NEXT: [[TMP1839:%.*]] = select i1 [[TMP1838]], i64 [[TMP1836]], i64 [[TMP1837]]
+// CHECK-NEXT: store i64 [[TMP1839]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1840:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1841:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1840]] acquire, align 8
+// CHECK-NEXT: [[TMP1842:%.*]] = icmp slt i64 [[TMP1841]], [[TMP1840]]
+// CHECK-NEXT: [[TMP1843:%.*]] = select i1 [[TMP1842]], i64 [[TMP1840]], i64 [[TMP1841]]
+// CHECK-NEXT: store i64 [[TMP1843]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1844:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1845:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1844]] acquire, align 8
+// CHECK-NEXT: [[TMP1846:%.*]] = icmp slt i64 [[TMP1845]], [[TMP1844]]
+// CHECK-NEXT: [[TMP1847:%.*]] = select i1 [[TMP1846]], i64 [[TMP1844]], i64 [[TMP1845]]
+// CHECK-NEXT: store i64 [[TMP1847]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1848:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1849:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1848]] acquire, align 8
+// CHECK-NEXT: [[TMP1850:%.*]] = icmp sgt i64 [[TMP1849]], [[TMP1848]]
+// CHECK-NEXT: [[TMP1851:%.*]] = select i1 [[TMP1850]], i64 [[TMP1848]], i64 [[TMP1849]]
+// CHECK-NEXT: store i64 [[TMP1851]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1852:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1853:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1852]], ptr [[LX_ATOMIC_EXPECTED_PTR3666]], align 8
+// CHECK-NEXT: store i64 [[TMP1853]], ptr [[LX_ATOMIC_DESIRED_PTR3667]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3669:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3666]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3670:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3667]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3671:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3669]], i64 [[LX_CMPXCHG_DESIRED3670]] acquire acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3672:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3671]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3672]], ptr [[LX_ATOMIC_EXPECTED_PTR3668]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3673:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3671]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3674:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3668]], align 8
+// CHECK-NEXT: [[LX_CAPTURE_CAPTURED3675:%.*]] = select i1 [[LX_CMPXCHG_SUCCESS3673]], i64 [[TMP1852]], i64 [[LX_CAPTURE_ACTUAL3674]]
+// CHECK-NEXT: store i64 [[LX_CAPTURE_CAPTURED3675]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1854:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1855:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1854]], ptr [[LX_ATOMIC_EXPECTED_PTR3676]], align 8
+// CHECK-NEXT: store i64 [[TMP1855]], ptr [[LX_ATOMIC_DESIRED_PTR3677]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3679:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3676]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3680:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3677]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3681:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3679]], i64 [[LX_CMPXCHG_DESIRED3680]] acquire acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3682:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3681]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3682]], ptr [[LX_ATOMIC_EXPECTED_PTR3678]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3683:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3681]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3684:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3678]], align 8
+// CHECK-NEXT: [[LX_CAPTURE_CAPTURED3685:%.*]] = select i1 [[LX_CMPXCHG_SUCCESS3683]], i64 [[TMP1854]], i64 [[LX_CAPTURE_ACTUAL3684]]
+// CHECK-NEXT: store i64 [[LX_CAPTURE_CAPTURED3685]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1856:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1857:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1856]], ptr [[LX_ATOMIC_EXPECTED_PTR3686]], align 8
+// CHECK-NEXT: store i64 [[TMP1857]], ptr [[LX_ATOMIC_DESIRED_PTR3687]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3689:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3686]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3690:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3687]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3691:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3689]], i64 [[LX_CMPXCHG_DESIRED3690]] acquire acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3692:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3691]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3692]], ptr [[LX_ATOMIC_EXPECTED_PTR3688]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3693:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3691]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3694:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3688]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3693]], label [[LX_ATOMIC_EXIT3695:%.*]], label [[LX_ATOMIC_CONT3696:%.*]]
+// CHECK: lx.atomic.cont3696:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3694]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3695]]
+// CHECK: lx.atomic.exit3695:
+// CHECK-NEXT: [[TMP1858:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1859:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1858]], ptr [[LX_ATOMIC_EXPECTED_PTR3697]], align 8
+// CHECK-NEXT: store i64 [[TMP1859]], ptr [[LX_ATOMIC_DESIRED_PTR3698]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3700:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3697]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3701:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3698]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3702:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3700]], i64 [[LX_CMPXCHG_DESIRED3701]] acquire acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3703:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3702]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3703]], ptr [[LX_ATOMIC_EXPECTED_PTR3699]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3704:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3702]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3705:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3699]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3704]], label [[LX_ATOMIC_EXIT3706:%.*]], label [[LX_ATOMIC_CONT3707:%.*]]
+// CHECK: lx.atomic.cont3707:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3705]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3706]]
+// CHECK: lx.atomic.exit3706:
+// CHECK-NEXT: [[TMP1860:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1861:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1860]], ptr [[LX_ATOMIC_EXPECTED_PTR3708]], align 8
+// CHECK-NEXT: store i64 [[TMP1861]], ptr [[LX_ATOMIC_DESIRED_PTR3709]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3711:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3708]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3712:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3709]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3713:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3711]], i64 [[LX_CMPXCHG_DESIRED3712]] acquire acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3714:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3713]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3714]], ptr [[LX_ATOMIC_EXPECTED_PTR3710]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3715:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3713]], 1
+// CHECK-NEXT: [[TMP1862:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3715]] to i64
+// CHECK-NEXT: store i64 [[TMP1862]], ptr [[LR]], align 8
+// CHECK-NEXT: [[TMP1863:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1864:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1863]], ptr [[LX_ATOMIC_EXPECTED_PTR3716]], align 8
+// CHECK-NEXT: store i64 [[TMP1864]], ptr [[LX_ATOMIC_DESIRED_PTR3717]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3719:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3716]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3720:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3717]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3721:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3719]], i64 [[LX_CMPXCHG_DESIRED3720]] acquire acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3722:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3721]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3722]], ptr [[LX_ATOMIC_EXPECTED_PTR3718]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3723:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3721]], 1
+// CHECK-NEXT: [[TMP1865:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3723]] to i64
+// CHECK-NEXT: store i64 [[TMP1865]], ptr [[LR]], align 8
+// CHECK-NEXT: [[TMP1866:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1867:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1866]], ptr [[LX_ATOMIC_EXPECTED_PTR3724]], align 8
+// CHECK-NEXT: store i64 [[TMP1867]], ptr [[LX_ATOMIC_DESIRED_PTR3725]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3727:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3724]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3728:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3725]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3729:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3727]], i64 [[LX_CMPXCHG_DESIRED3728]] acquire acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3730:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3729]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3730]], ptr [[LX_ATOMIC_EXPECTED_PTR3726]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3731:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3729]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3732:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3726]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3731]], label [[LX_ATOMIC_EXIT3733:%.*]], label [[LX_ATOMIC_CONT3734:%.*]]
+// CHECK: lx.atomic.cont3734:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3732]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3733]]
+// CHECK: lx.atomic.exit3733:
+// CHECK-NEXT: [[TMP1868:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3731]] to i64
+// CHECK-NEXT: store i64 [[TMP1868]], ptr [[LR]], align 8
+// CHECK-NEXT: [[TMP1869:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1870:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1869]], ptr [[LX_ATOMIC_EXPECTED_PTR3735]], align 8
+// CHECK-NEXT: store i64 [[TMP1870]], ptr [[LX_ATOMIC_DESIRED_PTR3736]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3738:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3735]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3739:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3736]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3740:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3738]], i64 [[LX_CMPXCHG_DESIRED3739]] acquire acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3741:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3740]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3741]], ptr [[LX_ATOMIC_EXPECTED_PTR3737]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3742:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3740]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3743:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3737]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3742]], label [[LX_ATOMIC_EXIT3744:%.*]], label [[LX_ATOMIC_CONT3745:%.*]]
+// CHECK: lx.atomic.cont3745:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3743]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3744]]
+// CHECK: lx.atomic.exit3744:
+// CHECK-NEXT: [[TMP1871:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3742]] to i64
+// CHECK-NEXT: store i64 [[TMP1871]], ptr [[LR]], align 8
+// CHECK-NEXT: [[TMP1872:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1873:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1872]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP1873]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1874:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1875:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1874]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP1875]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1876:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1877:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1876]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP1877]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1878:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1879:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1878]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP1879]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1880:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1881:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1880]], ptr [[LX_ATOMIC_EXPECTED_PTR3746]], align 8
+// CHECK-NEXT: store i64 [[TMP1881]], ptr [[LX_ATOMIC_DESIRED_PTR3747]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3749:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3746]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3750:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3747]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3751:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3749]], i64 [[LX_CMPXCHG_DESIRED3750]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3752:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3751]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3752]], ptr [[LX_ATOMIC_EXPECTED_PTR3748]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3753:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3751]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3754:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3748]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3754]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1882:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1883:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1882]], ptr [[LX_ATOMIC_EXPECTED_PTR3755]], align 8
+// CHECK-NEXT: store i64 [[TMP1883]], ptr [[LX_ATOMIC_DESIRED_PTR3756]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3758:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3755]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3759:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3756]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3760:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3758]], i64 [[LX_CMPXCHG_DESIRED3759]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3761:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3760]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3761]], ptr [[LX_ATOMIC_EXPECTED_PTR3757]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3762:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3760]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3763:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3757]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3763]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1884:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1885:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1884]] monotonic, align 8
+// CHECK-NEXT: [[TMP1886:%.*]] = icmp sgt i64 [[TMP1885]], [[TMP1884]]
+// CHECK-NEXT: [[TMP1887:%.*]] = select i1 [[TMP1886]], i64 [[TMP1884]], i64 [[TMP1885]]
+// CHECK-NEXT: store i64 [[TMP1887]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1888:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1889:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1888]] monotonic, align 8
+// CHECK-NEXT: [[TMP1890:%.*]] = icmp slt i64 [[TMP1889]], [[TMP1888]]
+// CHECK-NEXT: [[TMP1891:%.*]] = select i1 [[TMP1890]], i64 [[TMP1888]], i64 [[TMP1889]]
+// CHECK-NEXT: store i64 [[TMP1891]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1892:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1893:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1892]] monotonic, align 8
+// CHECK-NEXT: [[TMP1894:%.*]] = icmp slt i64 [[TMP1893]], [[TMP1892]]
+// CHECK-NEXT: [[TMP1895:%.*]] = select i1 [[TMP1894]], i64 [[TMP1892]], i64 [[TMP1893]]
+// CHECK-NEXT: store i64 [[TMP1895]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1896:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1897:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1896]] monotonic, align 8
+// CHECK-NEXT: [[TMP1898:%.*]] = icmp sgt i64 [[TMP1897]], [[TMP1896]]
+// CHECK-NEXT: [[TMP1899:%.*]] = select i1 [[TMP1898]], i64 [[TMP1896]], i64 [[TMP1897]]
+// CHECK-NEXT: store i64 [[TMP1899]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1900:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1901:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1900]], ptr [[LX_ATOMIC_EXPECTED_PTR3764]], align 8
+// CHECK-NEXT: store i64 [[TMP1901]], ptr [[LX_ATOMIC_DESIRED_PTR3765]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3767:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3764]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3768:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3765]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3769:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3767]], i64 [[LX_CMPXCHG_DESIRED3768]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3770:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3769]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3770]], ptr [[LX_ATOMIC_EXPECTED_PTR3766]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3771:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3769]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3772:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3766]], align 8
+// CHECK-NEXT: [[LX_CAPTURE_CAPTURED3773:%.*]] = select i1 [[LX_CMPXCHG_SUCCESS3771]], i64 [[TMP1900]], i64 [[LX_CAPTURE_ACTUAL3772]]
+// CHECK-NEXT: store i64 [[LX_CAPTURE_CAPTURED3773]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1902:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1903:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1902]], ptr [[LX_ATOMIC_EXPECTED_PTR3774]], align 8
+// CHECK-NEXT: store i64 [[TMP1903]], ptr [[LX_ATOMIC_DESIRED_PTR3775]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3777:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3774]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3778:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3775]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3779:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3777]], i64 [[LX_CMPXCHG_DESIRED3778]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3780:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3779]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3780]], ptr [[LX_ATOMIC_EXPECTED_PTR3776]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3781:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3779]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3782:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3776]], align 8
+// CHECK-NEXT: [[LX_CAPTURE_CAPTURED3783:%.*]] = select i1 [[LX_CMPXCHG_SUCCESS3781]], i64 [[TMP1902]], i64 [[LX_CAPTURE_ACTUAL3782]]
+// CHECK-NEXT: store i64 [[LX_CAPTURE_CAPTURED3783]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP1904:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1905:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1904]], ptr [[LX_ATOMIC_EXPECTED_PTR3784]], align 8
+// CHECK-NEXT: store i64 [[TMP1905]], ptr [[LX_ATOMIC_DESIRED_PTR3785]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3787:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3784]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3788:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3785]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3789:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3787]], i64 [[LX_CMPXCHG_DESIRED3788]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3790:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3789]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3790]], ptr [[LX_ATOMIC_EXPECTED_PTR3786]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3791:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3789]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3792:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3786]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3791]], label [[LX_ATOMIC_EXIT3793:%.*]], label [[LX_ATOMIC_CONT3794:%.*]]
+// CHECK: lx.atomic.cont3794:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3792]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3793]]
+// CHECK: lx.atomic.exit3793:
+// CHECK-NEXT: [[TMP1906:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1907:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1906]], ptr [[LX_ATOMIC_EXPECTED_PTR3795]], align 8
+// CHECK-NEXT: store i64 [[TMP1907]], ptr [[LX_ATOMIC_DESIRED_PTR3796]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3798:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3795]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3799:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3796]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3800:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3798]], i64 [[LX_CMPXCHG_DESIRED3799]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3801:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3800]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3801]], ptr [[LX_ATOMIC_EXPECTED_PTR3797]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3802:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3800]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3803:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3797]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3802]], label [[LX_ATOMIC_EXIT3804:%.*]], label [[LX_ATOMIC_CONT3805:%.*]]
+// CHECK: lx.atomic.cont3805:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3803]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3804]]
+// CHECK: lx.atomic.exit3804:
+// CHECK-NEXT: [[TMP1908:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1909:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1908]], ptr [[LX_ATOMIC_EXPECTED_PTR3806]], align 8
+// CHECK-NEXT: store i64 [[TMP1909]], ptr [[LX_ATOMIC_DESIRED_PTR3807]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3809:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3806]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3810:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3807]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3811:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3809]], i64 [[LX_CMPXCHG_DESIRED3810]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3812:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3811]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3812]], ptr [[LX_ATOMIC_EXPECTED_PTR3808]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3813:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3811]], 1
+// CHECK-NEXT: [[TMP1910:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3813]] to i64
+// CHECK-NEXT: store i64 [[TMP1910]], ptr [[LR]], align 8
+// CHECK-NEXT: [[TMP1911:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1912:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1911]], ptr [[LX_ATOMIC_EXPECTED_PTR3814]], align 8
+// CHECK-NEXT: store i64 [[TMP1912]], ptr [[LX_ATOMIC_DESIRED_PTR3815]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3817:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3814]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3818:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3815]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3819:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3817]], i64 [[LX_CMPXCHG_DESIRED3818]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3820:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3819]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3820]], ptr [[LX_ATOMIC_EXPECTED_PTR3816]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3821:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3819]], 1
+// CHECK-NEXT: [[TMP1913:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3821]] to i64
+// CHECK-NEXT: store i64 [[TMP1913]], ptr [[LR]], align 8
+// CHECK-NEXT: [[TMP1914:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1915:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1914]], ptr [[LX_ATOMIC_EXPECTED_PTR3822]], align 8
+// CHECK-NEXT: store i64 [[TMP1915]], ptr [[LX_ATOMIC_DESIRED_PTR3823]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3825:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3822]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3826:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3823]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3827:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3825]], i64 [[LX_CMPXCHG_DESIRED3826]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3828:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3827]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3828]], ptr [[LX_ATOMIC_EXPECTED_PTR3824]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3829:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3827]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3830:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3824]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3829]], label [[LX_ATOMIC_EXIT3831:%.*]], label [[LX_ATOMIC_CONT3832:%.*]]
+// CHECK: lx.atomic.cont3832:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3830]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3831]]
+// CHECK: lx.atomic.exit3831:
+// CHECK-NEXT: [[TMP1916:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3829]] to i64
+// CHECK-NEXT: store i64 [[TMP1916]], ptr [[LR]], align 8
+// CHECK-NEXT: [[TMP1917:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1918:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1917]], ptr [[LX_ATOMIC_EXPECTED_PTR3833]], align 8
+// CHECK-NEXT: store i64 [[TMP1918]], ptr [[LX_ATOMIC_DESIRED_PTR3834]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3836:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3833]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3837:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3834]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3838:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3836]], i64 [[LX_CMPXCHG_DESIRED3837]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3839:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3838]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3839]], ptr [[LX_ATOMIC_EXPECTED_PTR3835]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3840:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3838]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3841:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3835]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3840]], label [[LX_ATOMIC_EXIT3842:%.*]], label [[LX_ATOMIC_CONT3843:%.*]]
+// CHECK: lx.atomic.cont3843:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3841]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3842]]
+// CHECK: lx.atomic.exit3842:
+// CHECK-NEXT: [[TMP1919:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3840]] to i64
+// CHECK-NEXT: store i64 [[TMP1919]], ptr [[LR]], align 8
+// CHECK-NEXT: [[TMP1920:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1921:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1920]] release, align 8
+// CHECK-NEXT: store i64 [[TMP1921]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1922:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1923:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1922]] release, align 8
+// CHECK-NEXT: store i64 [[TMP1923]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1924:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1925:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1924]] release, align 8
+// CHECK-NEXT: store i64 [[TMP1925]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1926:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1927:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1926]] release, align 8
+// CHECK-NEXT: store i64 [[TMP1927]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1928:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1929:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1928]], ptr [[LX_ATOMIC_EXPECTED_PTR3844]], align 8
+// CHECK-NEXT: store i64 [[TMP1929]], ptr [[LX_ATOMIC_DESIRED_PTR3845]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3847:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3844]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3848:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3845]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3849:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3847]], i64 [[LX_CMPXCHG_DESIRED3848]] release monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3850:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3849]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3850]], ptr [[LX_ATOMIC_EXPECTED_PTR3846]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3851:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3849]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3852:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3846]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3852]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1930:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1931:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1930]], ptr [[LX_ATOMIC_EXPECTED_PTR3853]], align 8
+// CHECK-NEXT: store i64 [[TMP1931]], ptr [[LX_ATOMIC_DESIRED_PTR3854]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3856:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3853]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3857:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3854]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3858:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3856]], i64 [[LX_CMPXCHG_DESIRED3857]] release monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3859:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3858]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3859]], ptr [[LX_ATOMIC_EXPECTED_PTR3855]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3860:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3858]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3861:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3855]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3861]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1932:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1933:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1932]] release, align 8
+// CHECK-NEXT: [[TMP1934:%.*]] = icmp sgt i64 [[TMP1933]], [[TMP1932]]
+// CHECK-NEXT: [[TMP1935:%.*]] = select i1 [[TMP1934]], i64 [[TMP1932]], i64 [[TMP1933]]
+// CHECK-NEXT: store i64 [[TMP1935]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1936:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1937:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1936]] release, align 8
+// CHECK-NEXT: [[TMP1938:%.*]] = icmp slt i64 [[TMP1937]], [[TMP1936]]
+// CHECK-NEXT: [[TMP1939:%.*]] = select i1 [[TMP1938]], i64 [[TMP1936]], i64 [[TMP1937]]
+// CHECK-NEXT: store i64 [[TMP1939]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1940:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1941:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1940]] release, align 8
+// CHECK-NEXT: [[TMP1942:%.*]] = icmp slt i64 [[TMP1941]], [[TMP1940]]
+// CHECK-NEXT: [[TMP1943:%.*]] = select i1 [[TMP1942]], i64 [[TMP1940]], i64 [[TMP1941]]
+// CHECK-NEXT: store i64 [[TMP1943]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1944:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1945:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1944]] release, align 8
+// CHECK-NEXT: [[TMP1946:%.*]] = icmp sgt i64 [[TMP1945]], [[TMP1944]]
+// CHECK-NEXT: [[TMP1947:%.*]] = select i1 [[TMP1946]], i64 [[TMP1944]], i64 [[TMP1945]]
+// CHECK-NEXT: store i64 [[TMP1947]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1948:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1949:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1948]], ptr [[LX_ATOMIC_EXPECTED_PTR3862]], align 8
+// CHECK-NEXT: store i64 [[TMP1949]], ptr [[LX_ATOMIC_DESIRED_PTR3863]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3865:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3862]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3866:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3863]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3867:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3865]], i64 [[LX_CMPXCHG_DESIRED3866]] release monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3868:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3867]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3868]], ptr [[LX_ATOMIC_EXPECTED_PTR3864]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3869:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3867]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3870:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3864]], align 8
+// CHECK-NEXT: [[LX_CAPTURE_CAPTURED3871:%.*]] = select i1 [[LX_CMPXCHG_SUCCESS3869]], i64 [[TMP1948]], i64 [[LX_CAPTURE_ACTUAL3870]]
+// CHECK-NEXT: store i64 [[LX_CAPTURE_CAPTURED3871]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1950:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1951:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1950]], ptr [[LX_ATOMIC_EXPECTED_PTR3872]], align 8
+// CHECK-NEXT: store i64 [[TMP1951]], ptr [[LX_ATOMIC_DESIRED_PTR3873]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3875:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3872]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3876:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3873]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3877:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3875]], i64 [[LX_CMPXCHG_DESIRED3876]] release monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3878:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3877]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3878]], ptr [[LX_ATOMIC_EXPECTED_PTR3874]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3879:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3877]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3880:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3874]], align 8
+// CHECK-NEXT: [[LX_CAPTURE_CAPTURED3881:%.*]] = select i1 [[LX_CMPXCHG_SUCCESS3879]], i64 [[TMP1950]], i64 [[LX_CAPTURE_ACTUAL3880]]
+// CHECK-NEXT: store i64 [[LX_CAPTURE_CAPTURED3881]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1952:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1953:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1952]], ptr [[LX_ATOMIC_EXPECTED_PTR3882]], align 8
+// CHECK-NEXT: store i64 [[TMP1953]], ptr [[LX_ATOMIC_DESIRED_PTR3883]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3885:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3882]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3886:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3883]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3887:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3885]], i64 [[LX_CMPXCHG_DESIRED3886]] release monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3888:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3887]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3888]], ptr [[LX_ATOMIC_EXPECTED_PTR3884]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3889:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3887]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3890:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3884]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3889]], label [[LX_ATOMIC_EXIT3891:%.*]], label [[LX_ATOMIC_CONT3892:%.*]]
+// CHECK: lx.atomic.cont3892:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3890]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3891]]
+// CHECK: lx.atomic.exit3891:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1954:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1955:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1954]], ptr [[LX_ATOMIC_EXPECTED_PTR3893]], align 8
+// CHECK-NEXT: store i64 [[TMP1955]], ptr [[LX_ATOMIC_DESIRED_PTR3894]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3896:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3893]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3897:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3894]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3898:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3896]], i64 [[LX_CMPXCHG_DESIRED3897]] release monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3899:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3898]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3899]], ptr [[LX_ATOMIC_EXPECTED_PTR3895]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3900:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3898]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3901:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3895]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3900]], label [[LX_ATOMIC_EXIT3902:%.*]], label [[LX_ATOMIC_CONT3903:%.*]]
+// CHECK: lx.atomic.cont3903:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3901]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3902]]
+// CHECK: lx.atomic.exit3902:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1956:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1957:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1956]], ptr [[LX_ATOMIC_EXPECTED_PTR3904]], align 8
+// CHECK-NEXT: store i64 [[TMP1957]], ptr [[LX_ATOMIC_DESIRED_PTR3905]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3907:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3904]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3908:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3905]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3909:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3907]], i64 [[LX_CMPXCHG_DESIRED3908]] release monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3910:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3909]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3910]], ptr [[LX_ATOMIC_EXPECTED_PTR3906]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3911:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3909]], 1
+// CHECK-NEXT: [[TMP1958:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3911]] to i64
+// CHECK-NEXT: store i64 [[TMP1958]], ptr [[LR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1959:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1960:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1959]], ptr [[LX_ATOMIC_EXPECTED_PTR3912]], align 8
+// CHECK-NEXT: store i64 [[TMP1960]], ptr [[LX_ATOMIC_DESIRED_PTR3913]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3915:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3912]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3916:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3913]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3917:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3915]], i64 [[LX_CMPXCHG_DESIRED3916]] release monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3918:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3917]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3918]], ptr [[LX_ATOMIC_EXPECTED_PTR3914]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3919:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3917]], 1
+// CHECK-NEXT: [[TMP1961:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3919]] to i64
+// CHECK-NEXT: store i64 [[TMP1961]], ptr [[LR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1962:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1963:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1962]], ptr [[LX_ATOMIC_EXPECTED_PTR3920]], align 8
+// CHECK-NEXT: store i64 [[TMP1963]], ptr [[LX_ATOMIC_DESIRED_PTR3921]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3923:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3920]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3924:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3921]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3925:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3923]], i64 [[LX_CMPXCHG_DESIRED3924]] release monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3926:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3925]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3926]], ptr [[LX_ATOMIC_EXPECTED_PTR3922]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3927:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3925]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3928:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3922]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3927]], label [[LX_ATOMIC_EXIT3929:%.*]], label [[LX_ATOMIC_CONT3930:%.*]]
+// CHECK: lx.atomic.cont3930:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3928]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3929]]
+// CHECK: lx.atomic.exit3929:
+// CHECK-NEXT: [[TMP1964:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3927]] to i64
+// CHECK-NEXT: store i64 [[TMP1964]], ptr [[LR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1965:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1966:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1965]], ptr [[LX_ATOMIC_EXPECTED_PTR3931]], align 8
+// CHECK-NEXT: store i64 [[TMP1966]], ptr [[LX_ATOMIC_DESIRED_PTR3932]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3934:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3931]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3935:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3932]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3936:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3934]], i64 [[LX_CMPXCHG_DESIRED3935]] release monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3937:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3936]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3937]], ptr [[LX_ATOMIC_EXPECTED_PTR3933]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3938:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3936]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3939:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3933]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3938]], label [[LX_ATOMIC_EXIT3940:%.*]], label [[LX_ATOMIC_CONT3941:%.*]]
+// CHECK: lx.atomic.cont3941:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3939]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3940]]
+// CHECK: lx.atomic.exit3940:
+// CHECK-NEXT: [[TMP1967:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS3938]] to i64
+// CHECK-NEXT: store i64 [[TMP1967]], ptr [[LR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1968:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1969:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1968]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP1969]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1970:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1971:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1970]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP1971]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1972:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1973:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1972]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP1973]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1974:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1975:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1974]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP1975]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1976:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1977:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1976]], ptr [[LX_ATOMIC_EXPECTED_PTR3942]], align 8
+// CHECK-NEXT: store i64 [[TMP1977]], ptr [[LX_ATOMIC_DESIRED_PTR3943]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3945:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3942]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3946:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3943]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3947:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3945]], i64 [[LX_CMPXCHG_DESIRED3946]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3948:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3947]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3948]], ptr [[LX_ATOMIC_EXPECTED_PTR3944]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3949:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3947]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3950:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3944]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3950]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1978:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1979:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1978]], ptr [[LX_ATOMIC_EXPECTED_PTR3951]], align 8
+// CHECK-NEXT: store i64 [[TMP1979]], ptr [[LX_ATOMIC_DESIRED_PTR3952]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3954:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3951]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3955:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3952]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3956:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3954]], i64 [[LX_CMPXCHG_DESIRED3955]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3957:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3956]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3957]], ptr [[LX_ATOMIC_EXPECTED_PTR3953]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3958:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3956]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3959:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3953]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3959]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1980:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1981:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1980]] seq_cst, align 8
+// CHECK-NEXT: [[TMP1982:%.*]] = icmp sgt i64 [[TMP1981]], [[TMP1980]]
+// CHECK-NEXT: [[TMP1983:%.*]] = select i1 [[TMP1982]], i64 [[TMP1980]], i64 [[TMP1981]]
+// CHECK-NEXT: store i64 [[TMP1983]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1984:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1985:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1984]] seq_cst, align 8
+// CHECK-NEXT: [[TMP1986:%.*]] = icmp slt i64 [[TMP1985]], [[TMP1984]]
+// CHECK-NEXT: [[TMP1987:%.*]] = select i1 [[TMP1986]], i64 [[TMP1984]], i64 [[TMP1985]]
+// CHECK-NEXT: store i64 [[TMP1987]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1988:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1989:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP1988]] seq_cst, align 8
+// CHECK-NEXT: [[TMP1990:%.*]] = icmp slt i64 [[TMP1989]], [[TMP1988]]
+// CHECK-NEXT: [[TMP1991:%.*]] = select i1 [[TMP1990]], i64 [[TMP1988]], i64 [[TMP1989]]
+// CHECK-NEXT: store i64 [[TMP1991]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1992:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1993:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP1992]] seq_cst, align 8
+// CHECK-NEXT: [[TMP1994:%.*]] = icmp sgt i64 [[TMP1993]], [[TMP1992]]
+// CHECK-NEXT: [[TMP1995:%.*]] = select i1 [[TMP1994]], i64 [[TMP1992]], i64 [[TMP1993]]
+// CHECK-NEXT: store i64 [[TMP1995]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1996:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1997:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1996]], ptr [[LX_ATOMIC_EXPECTED_PTR3960]], align 8
+// CHECK-NEXT: store i64 [[TMP1997]], ptr [[LX_ATOMIC_DESIRED_PTR3961]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3963:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3960]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3964:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3961]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3965:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3963]], i64 [[LX_CMPXCHG_DESIRED3964]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3966:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3965]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3966]], ptr [[LX_ATOMIC_EXPECTED_PTR3962]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3967:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3965]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3968:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3962]], align 8
+// CHECK-NEXT: [[LX_CAPTURE_CAPTURED3969:%.*]] = select i1 [[LX_CMPXCHG_SUCCESS3967]], i64 [[TMP1996]], i64 [[LX_CAPTURE_ACTUAL3968]]
+// CHECK-NEXT: store i64 [[LX_CAPTURE_CAPTURED3969]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP1998:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP1999:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP1998]], ptr [[LX_ATOMIC_EXPECTED_PTR3970]], align 8
+// CHECK-NEXT: store i64 [[TMP1999]], ptr [[LX_ATOMIC_DESIRED_PTR3971]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3973:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3970]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3974:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3971]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3975:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3973]], i64 [[LX_CMPXCHG_DESIRED3974]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3976:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3975]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3976]], ptr [[LX_ATOMIC_EXPECTED_PTR3972]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3977:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3975]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3978:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3972]], align 8
+// CHECK-NEXT: [[LX_CAPTURE_CAPTURED3979:%.*]] = select i1 [[LX_CMPXCHG_SUCCESS3977]], i64 [[TMP1998]], i64 [[LX_CAPTURE_ACTUAL3978]]
+// CHECK-NEXT: store i64 [[LX_CAPTURE_CAPTURED3979]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2000:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP2001:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP2000]], ptr [[LX_ATOMIC_EXPECTED_PTR3980]], align 8
+// CHECK-NEXT: store i64 [[TMP2001]], ptr [[LX_ATOMIC_DESIRED_PTR3981]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3983:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3980]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3984:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3981]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3985:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3983]], i64 [[LX_CMPXCHG_DESIRED3984]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3986:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3985]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3986]], ptr [[LX_ATOMIC_EXPECTED_PTR3982]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3987:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3985]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3988:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3982]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3987]], label [[LX_ATOMIC_EXIT3989:%.*]], label [[LX_ATOMIC_CONT3990:%.*]]
+// CHECK: lx.atomic.cont3990:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3988]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT3989]]
+// CHECK: lx.atomic.exit3989:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2002:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP2003:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP2002]], ptr [[LX_ATOMIC_EXPECTED_PTR3991]], align 8
+// CHECK-NEXT: store i64 [[TMP2003]], ptr [[LX_ATOMIC_DESIRED_PTR3992]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED3994:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3991]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED3995:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3992]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR3996:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED3994]], i64 [[LX_CMPXCHG_DESIRED3995]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV3997:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3996]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV3997]], ptr [[LX_ATOMIC_EXPECTED_PTR3993]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS3998:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR3996]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL3999:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR3993]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS3998]], label [[LX_ATOMIC_EXIT4000:%.*]], label [[LX_ATOMIC_CONT4001:%.*]]
+// CHECK: lx.atomic.cont4001:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL3999]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT4000]]
+// CHECK: lx.atomic.exit4000:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2004:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP2005:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP2004]], ptr [[LX_ATOMIC_EXPECTED_PTR4002]], align 8
+// CHECK-NEXT: store i64 [[TMP2005]], ptr [[LX_ATOMIC_DESIRED_PTR4003]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED4005:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR4002]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED4006:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR4003]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR4007:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED4005]], i64 [[LX_CMPXCHG_DESIRED4006]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV4008:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR4007]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV4008]], ptr [[LX_ATOMIC_EXPECTED_PTR4004]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS4009:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR4007]], 1
+// CHECK-NEXT: [[TMP2006:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS4009]] to i64
+// CHECK-NEXT: store i64 [[TMP2006]], ptr [[LR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2007:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP2008:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP2007]], ptr [[LX_ATOMIC_EXPECTED_PTR4010]], align 8
+// CHECK-NEXT: store i64 [[TMP2008]], ptr [[LX_ATOMIC_DESIRED_PTR4011]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED4013:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR4010]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED4014:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR4011]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR4015:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED4013]], i64 [[LX_CMPXCHG_DESIRED4014]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV4016:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR4015]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV4016]], ptr [[LX_ATOMIC_EXPECTED_PTR4012]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS4017:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR4015]], 1
+// CHECK-NEXT: [[TMP2009:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS4017]] to i64
+// CHECK-NEXT: store i64 [[TMP2009]], ptr [[LR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2010:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP2011:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP2010]], ptr [[LX_ATOMIC_EXPECTED_PTR4018]], align 8
+// CHECK-NEXT: store i64 [[TMP2011]], ptr [[LX_ATOMIC_DESIRED_PTR4019]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED4021:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR4018]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED4022:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR4019]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR4023:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED4021]], i64 [[LX_CMPXCHG_DESIRED4022]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV4024:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR4023]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV4024]], ptr [[LX_ATOMIC_EXPECTED_PTR4020]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS4025:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR4023]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL4026:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR4020]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS4025]], label [[LX_ATOMIC_EXIT4027:%.*]], label [[LX_ATOMIC_CONT4028:%.*]]
+// CHECK: lx.atomic.cont4028:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL4026]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT4027]]
+// CHECK: lx.atomic.exit4027:
+// CHECK-NEXT: [[TMP2012:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS4025]] to i64
+// CHECK-NEXT: store i64 [[TMP2012]], ptr [[LR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2013:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP2014:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP2013]], ptr [[LX_ATOMIC_EXPECTED_PTR4029]], align 8
+// CHECK-NEXT: store i64 [[TMP2014]], ptr [[LX_ATOMIC_DESIRED_PTR4030]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED4032:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR4029]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED4033:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR4030]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR4034:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED4032]], i64 [[LX_CMPXCHG_DESIRED4033]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV4035:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR4034]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV4035]], ptr [[LX_ATOMIC_EXPECTED_PTR4031]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS4036:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR4034]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL4037:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR4031]], align 8
+// CHECK-NEXT: br i1 [[LX_CMPXCHG_SUCCESS4036]], label [[LX_ATOMIC_EXIT4038:%.*]], label [[LX_ATOMIC_CONT4039:%.*]]
+// CHECK: lx.atomic.cont4039:
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL4037]], ptr [[LV]], align 8
+// CHECK-NEXT: br label [[LX_ATOMIC_EXIT4038]]
+// CHECK: lx.atomic.exit4038:
+// CHECK-NEXT: [[TMP2015:%.*]] = sext i1 [[LX_CMPXCHG_SUCCESS4036]] to i64
+// CHECK-NEXT: store i64 [[TMP2015]], ptr [[LR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2016:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2017:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2016]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2017]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2018:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2019:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2018]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2019]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2020:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2021:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2020]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2021]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2022:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2023:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2022]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2023]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2024:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2025:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2024]], ptr [[ULX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: store i64 [[TMP2025]], ptr [[ULX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED]], i64 [[ULX_CMPXCHG_DESIRED]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV]], ptr [[ULX_ATOMIC_EXPECTED_PTR4040]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4040]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2026:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2027:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2026]], ptr [[ULX_ATOMIC_EXPECTED_PTR4041]], align 8
+// CHECK-NEXT: store i64 [[TMP2027]], ptr [[ULX_ATOMIC_DESIRED_PTR4042]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4044:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4041]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4045:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4042]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4046:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4044]], i64 [[ULX_CMPXCHG_DESIRED4045]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4047:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4046]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4047]], ptr [[ULX_ATOMIC_EXPECTED_PTR4043]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4048:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4046]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4049:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4043]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4049]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2028:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2029:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2028]] monotonic, align 8
+// CHECK-NEXT: [[TMP2030:%.*]] = icmp ugt i64 [[TMP2029]], [[TMP2028]]
+// CHECK-NEXT: [[TMP2031:%.*]] = select i1 [[TMP2030]], i64 [[TMP2028]], i64 [[TMP2029]]
+// CHECK-NEXT: store i64 [[TMP2031]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2032:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2033:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2032]] monotonic, align 8
+// CHECK-NEXT: [[TMP2034:%.*]] = icmp ult i64 [[TMP2033]], [[TMP2032]]
+// CHECK-NEXT: [[TMP2035:%.*]] = select i1 [[TMP2034]], i64 [[TMP2032]], i64 [[TMP2033]]
+// CHECK-NEXT: store i64 [[TMP2035]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2036:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2037:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2036]] monotonic, align 8
+// CHECK-NEXT: [[TMP2038:%.*]] = icmp ult i64 [[TMP2037]], [[TMP2036]]
+// CHECK-NEXT: [[TMP2039:%.*]] = select i1 [[TMP2038]], i64 [[TMP2036]], i64 [[TMP2037]]
+// CHECK-NEXT: store i64 [[TMP2039]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2040:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2041:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2040]] monotonic, align 8
+// CHECK-NEXT: [[TMP2042:%.*]] = icmp ugt i64 [[TMP2041]], [[TMP2040]]
+// CHECK-NEXT: [[TMP2043:%.*]] = select i1 [[TMP2042]], i64 [[TMP2040]], i64 [[TMP2041]]
+// CHECK-NEXT: store i64 [[TMP2043]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2044:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2045:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2044]], ptr [[ULX_ATOMIC_EXPECTED_PTR4050]], align 8
+// CHECK-NEXT: store i64 [[TMP2045]], ptr [[ULX_ATOMIC_DESIRED_PTR4051]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4053:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4050]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4054:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4051]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4055:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4053]], i64 [[ULX_CMPXCHG_DESIRED4054]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4056:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4055]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4056]], ptr [[ULX_ATOMIC_EXPECTED_PTR4052]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4057:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4055]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4058:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4052]], align 8
+// CHECK-NEXT: [[ULX_CAPTURE_CAPTURED:%.*]] = select i1 [[ULX_CMPXCHG_SUCCESS4057]], i64 [[TMP2044]], i64 [[ULX_CAPTURE_ACTUAL4058]]
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_CAPTURED]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2046:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2047:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2046]], ptr [[ULX_ATOMIC_EXPECTED_PTR4059]], align 8
+// CHECK-NEXT: store i64 [[TMP2047]], ptr [[ULX_ATOMIC_DESIRED_PTR4060]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4062:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4059]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4063:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4060]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4064:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4062]], i64 [[ULX_CMPXCHG_DESIRED4063]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4065:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4064]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4065]], ptr [[ULX_ATOMIC_EXPECTED_PTR4061]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4066:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4064]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4067:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4061]], align 8
+// CHECK-NEXT: [[ULX_CAPTURE_CAPTURED4068:%.*]] = select i1 [[ULX_CMPXCHG_SUCCESS4066]], i64 [[TMP2046]], i64 [[ULX_CAPTURE_ACTUAL4067]]
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_CAPTURED4068]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2048:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2049:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2048]], ptr [[ULX_ATOMIC_EXPECTED_PTR4069]], align 8
+// CHECK-NEXT: store i64 [[TMP2049]], ptr [[ULX_ATOMIC_DESIRED_PTR4070]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4072:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4069]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4073:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4070]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4074:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4072]], i64 [[ULX_CMPXCHG_DESIRED4073]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4075:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4074]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4075]], ptr [[ULX_ATOMIC_EXPECTED_PTR4071]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4076:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4074]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4077:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4071]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4076]], label [[ULX_ATOMIC_EXIT:%.*]], label [[ULX_ATOMIC_CONT:%.*]]
// CHECK: ulx.atomic.cont:
-// CHECK-NEXT: store i64 [[TMP3323]], ptr [[ULV]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4077]], ptr [[ULV]], align 8
// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT]]
// CHECK: ulx.atomic.exit:
-// CHECK-NEXT: [[TMP3325:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3326:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3327:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3325]], i64 [[TMP3326]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3328:%.*]] = extractvalue { i64, i1 } [[TMP3327]], 0
-// CHECK-NEXT: [[TMP3329:%.*]] = extractvalue { i64, i1 } [[TMP3327]], 1
-// CHECK-NEXT: br i1 [[TMP3329]], label [[ULX_ATOMIC_EXIT323:%.*]], label [[ULX_ATOMIC_CONT324:%.*]]
-// CHECK: ulx.atomic.cont324:
-// CHECK-NEXT: store i64 [[TMP3328]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT323]]
-// CHECK: ulx.atomic.exit323:
-// CHECK-NEXT: [[TMP3330:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3331:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3332:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3330]], i64 [[TMP3331]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3333:%.*]] = extractvalue { i64, i1 } [[TMP3332]], 1
-// CHECK-NEXT: [[TMP3334:%.*]] = zext i1 [[TMP3333]] to i64
-// CHECK-NEXT: store i64 [[TMP3334]], ptr [[ULR]], align 8
-// CHECK-NEXT: [[TMP3335:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3336:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3337:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3335]], i64 [[TMP3336]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3338:%.*]] = extractvalue { i64, i1 } [[TMP3337]], 1
-// CHECK-NEXT: [[TMP3339:%.*]] = zext i1 [[TMP3338]] to i64
-// CHECK-NEXT: store i64 [[TMP3339]], ptr [[ULR]], align 8
-// CHECK-NEXT: [[TMP3340:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3341:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3342:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3340]], i64 [[TMP3341]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3343:%.*]] = extractvalue { i64, i1 } [[TMP3342]], 0
-// CHECK-NEXT: [[TMP3344:%.*]] = extractvalue { i64, i1 } [[TMP3342]], 1
-// CHECK-NEXT: br i1 [[TMP3344]], label [[ULX_ATOMIC_EXIT325:%.*]], label [[ULX_ATOMIC_CONT326:%.*]]
-// CHECK: ulx.atomic.cont326:
-// CHECK-NEXT: store i64 [[TMP3343]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT325]]
-// CHECK: ulx.atomic.exit325:
-// CHECK-NEXT: [[TMP3345:%.*]] = extractvalue { i64, i1 } [[TMP3342]], 1
-// CHECK-NEXT: [[TMP3346:%.*]] = zext i1 [[TMP3345]] to i64
-// CHECK-NEXT: store i64 [[TMP3346]], ptr [[ULR]], align 8
-// CHECK-NEXT: [[TMP3347:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3348:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3349:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3347]], i64 [[TMP3348]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3350:%.*]] = extractvalue { i64, i1 } [[TMP3349]], 0
-// CHECK-NEXT: [[TMP3351:%.*]] = extractvalue { i64, i1 } [[TMP3349]], 1
-// CHECK-NEXT: br i1 [[TMP3351]], label [[ULX_ATOMIC_EXIT327:%.*]], label [[ULX_ATOMIC_CONT328:%.*]]
-// CHECK: ulx.atomic.cont328:
-// CHECK-NEXT: store i64 [[TMP3350]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT327]]
-// CHECK: ulx.atomic.exit327:
-// CHECK-NEXT: [[TMP3352:%.*]] = extractvalue { i64, i1 } [[TMP3349]], 1
-// CHECK-NEXT: [[TMP3353:%.*]] = zext i1 [[TMP3352]] to i64
-// CHECK-NEXT: store i64 [[TMP3353]], ptr [[ULR]], align 8
-// CHECK-NEXT: [[TMP3354:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3355:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3354]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP3355]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3356:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3357:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3356]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP3357]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3358:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3359:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3358]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP3359]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3360:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3361:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3360]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP3361]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3362:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3363:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3364:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3362]], i64 [[TMP3363]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3365:%.*]] = extractvalue { i64, i1 } [[TMP3364]], 0
-// CHECK-NEXT: store i64 [[TMP3365]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3366:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3367:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3368:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3366]], i64 [[TMP3367]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3369:%.*]] = extractvalue { i64, i1 } [[TMP3368]], 0
-// CHECK-NEXT: store i64 [[TMP3369]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3370:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3371:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3370]] acq_rel, align 8
-// CHECK-NEXT: [[TMP3372:%.*]] = icmp ugt i64 [[TMP3371]], [[TMP3370]]
-// CHECK-NEXT: [[TMP3373:%.*]] = select i1 [[TMP3372]], i64 [[TMP3370]], i64 [[TMP3371]]
-// CHECK-NEXT: store i64 [[TMP3373]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3374:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3375:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3374]] acq_rel, align 8
-// CHECK-NEXT: [[TMP3376:%.*]] = icmp ult i64 [[TMP3375]], [[TMP3374]]
-// CHECK-NEXT: [[TMP3377:%.*]] = select i1 [[TMP3376]], i64 [[TMP3374]], i64 [[TMP3375]]
-// CHECK-NEXT: store i64 [[TMP3377]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3378:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3379:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3378]] acq_rel, align 8
-// CHECK-NEXT: [[TMP3380:%.*]] = icmp ult i64 [[TMP3379]], [[TMP3378]]
-// CHECK-NEXT: [[TMP3381:%.*]] = select i1 [[TMP3380]], i64 [[TMP3378]], i64 [[TMP3379]]
-// CHECK-NEXT: store i64 [[TMP3381]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3382:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3383:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3382]] acq_rel, align 8
-// CHECK-NEXT: [[TMP3384:%.*]] = icmp ugt i64 [[TMP3383]], [[TMP3382]]
-// CHECK-NEXT: [[TMP3385:%.*]] = select i1 [[TMP3384]], i64 [[TMP3382]], i64 [[TMP3383]]
-// CHECK-NEXT: store i64 [[TMP3385]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3386:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3387:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3388:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3386]], i64 [[TMP3387]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3389:%.*]] = extractvalue { i64, i1 } [[TMP3388]], 0
-// CHECK-NEXT: [[TMP3390:%.*]] = extractvalue { i64, i1 } [[TMP3388]], 1
-// CHECK-NEXT: [[TMP3391:%.*]] = select i1 [[TMP3390]], i64 [[TMP3386]], i64 [[TMP3389]]
-// CHECK-NEXT: store i64 [[TMP3391]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3392:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3393:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3394:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3392]], i64 [[TMP3393]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3395:%.*]] = extractvalue { i64, i1 } [[TMP3394]], 0
-// CHECK-NEXT: [[TMP3396:%.*]] = extractvalue { i64, i1 } [[TMP3394]], 1
-// CHECK-NEXT: [[TMP3397:%.*]] = select i1 [[TMP3396]], i64 [[TMP3392]], i64 [[TMP3395]]
-// CHECK-NEXT: store i64 [[TMP3397]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3398:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3399:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3400:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3398]], i64 [[TMP3399]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3401:%.*]] = extractvalue { i64, i1 } [[TMP3400]], 0
-// CHECK-NEXT: [[TMP3402:%.*]] = extractvalue { i64, i1 } [[TMP3400]], 1
-// CHECK-NEXT: br i1 [[TMP3402]], label [[ULX_ATOMIC_EXIT329:%.*]], label [[ULX_ATOMIC_CONT330:%.*]]
-// CHECK: ulx.atomic.cont330:
-// CHECK-NEXT: store i64 [[TMP3401]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT329]]
-// CHECK: ulx.atomic.exit329:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3403:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3404:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3405:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3403]], i64 [[TMP3404]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3406:%.*]] = extractvalue { i64, i1 } [[TMP3405]], 0
-// CHECK-NEXT: [[TMP3407:%.*]] = extractvalue { i64, i1 } [[TMP3405]], 1
-// CHECK-NEXT: br i1 [[TMP3407]], label [[ULX_ATOMIC_EXIT331:%.*]], label [[ULX_ATOMIC_CONT332:%.*]]
-// CHECK: ulx.atomic.cont332:
-// CHECK-NEXT: store i64 [[TMP3406]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT331]]
-// CHECK: ulx.atomic.exit331:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3408:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3409:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3410:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3408]], i64 [[TMP3409]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3411:%.*]] = extractvalue { i64, i1 } [[TMP3410]], 1
-// CHECK-NEXT: [[TMP3412:%.*]] = zext i1 [[TMP3411]] to i64
-// CHECK-NEXT: store i64 [[TMP3412]], ptr [[ULR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3413:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3414:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3415:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3413]], i64 [[TMP3414]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3416:%.*]] = extractvalue { i64, i1 } [[TMP3415]], 1
-// CHECK-NEXT: [[TMP3417:%.*]] = zext i1 [[TMP3416]] to i64
-// CHECK-NEXT: store i64 [[TMP3417]], ptr [[ULR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3418:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3419:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3420:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3418]], i64 [[TMP3419]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3421:%.*]] = extractvalue { i64, i1 } [[TMP3420]], 0
-// CHECK-NEXT: [[TMP3422:%.*]] = extractvalue { i64, i1 } [[TMP3420]], 1
-// CHECK-NEXT: br i1 [[TMP3422]], label [[ULX_ATOMIC_EXIT333:%.*]], label [[ULX_ATOMIC_CONT334:%.*]]
-// CHECK: ulx.atomic.cont334:
-// CHECK-NEXT: store i64 [[TMP3421]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT333]]
-// CHECK: ulx.atomic.exit333:
-// CHECK-NEXT: [[TMP3423:%.*]] = extractvalue { i64, i1 } [[TMP3420]], 1
-// CHECK-NEXT: [[TMP3424:%.*]] = zext i1 [[TMP3423]] to i64
-// CHECK-NEXT: store i64 [[TMP3424]], ptr [[ULR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3425:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3426:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3427:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3425]], i64 [[TMP3426]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3428:%.*]] = extractvalue { i64, i1 } [[TMP3427]], 0
-// CHECK-NEXT: [[TMP3429:%.*]] = extractvalue { i64, i1 } [[TMP3427]], 1
-// CHECK-NEXT: br i1 [[TMP3429]], label [[ULX_ATOMIC_EXIT335:%.*]], label [[ULX_ATOMIC_CONT336:%.*]]
-// CHECK: ulx.atomic.cont336:
-// CHECK-NEXT: store i64 [[TMP3428]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT335]]
-// CHECK: ulx.atomic.exit335:
-// CHECK-NEXT: [[TMP3430:%.*]] = extractvalue { i64, i1 } [[TMP3427]], 1
-// CHECK-NEXT: [[TMP3431:%.*]] = zext i1 [[TMP3430]] to i64
-// CHECK-NEXT: store i64 [[TMP3431]], ptr [[ULR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3432:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3433:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3432]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP3433]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3434:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3435:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3434]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP3435]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3436:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3437:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3436]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP3437]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3438:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3439:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3438]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP3439]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3440:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3441:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3442:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3440]], i64 [[TMP3441]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3443:%.*]] = extractvalue { i64, i1 } [[TMP3442]], 0
-// CHECK-NEXT: store i64 [[TMP3443]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3444:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3445:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3446:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3444]], i64 [[TMP3445]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3447:%.*]] = extractvalue { i64, i1 } [[TMP3446]], 0
-// CHECK-NEXT: store i64 [[TMP3447]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3448:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3449:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3448]] acquire, align 8
-// CHECK-NEXT: [[TMP3450:%.*]] = icmp ugt i64 [[TMP3449]], [[TMP3448]]
-// CHECK-NEXT: [[TMP3451:%.*]] = select i1 [[TMP3450]], i64 [[TMP3448]], i64 [[TMP3449]]
-// CHECK-NEXT: store i64 [[TMP3451]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3452:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3453:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3452]] acquire, align 8
-// CHECK-NEXT: [[TMP3454:%.*]] = icmp ult i64 [[TMP3453]], [[TMP3452]]
-// CHECK-NEXT: [[TMP3455:%.*]] = select i1 [[TMP3454]], i64 [[TMP3452]], i64 [[TMP3453]]
-// CHECK-NEXT: store i64 [[TMP3455]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3456:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3457:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3456]] acquire, align 8
-// CHECK-NEXT: [[TMP3458:%.*]] = icmp ult i64 [[TMP3457]], [[TMP3456]]
-// CHECK-NEXT: [[TMP3459:%.*]] = select i1 [[TMP3458]], i64 [[TMP3456]], i64 [[TMP3457]]
-// CHECK-NEXT: store i64 [[TMP3459]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3460:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3461:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3460]] acquire, align 8
-// CHECK-NEXT: [[TMP3462:%.*]] = icmp ugt i64 [[TMP3461]], [[TMP3460]]
-// CHECK-NEXT: [[TMP3463:%.*]] = select i1 [[TMP3462]], i64 [[TMP3460]], i64 [[TMP3461]]
-// CHECK-NEXT: store i64 [[TMP3463]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3464:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3465:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3466:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3464]], i64 [[TMP3465]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3467:%.*]] = extractvalue { i64, i1 } [[TMP3466]], 0
-// CHECK-NEXT: [[TMP3468:%.*]] = extractvalue { i64, i1 } [[TMP3466]], 1
-// CHECK-NEXT: [[TMP3469:%.*]] = select i1 [[TMP3468]], i64 [[TMP3464]], i64 [[TMP3467]]
-// CHECK-NEXT: store i64 [[TMP3469]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3470:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3471:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3472:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3470]], i64 [[TMP3471]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3473:%.*]] = extractvalue { i64, i1 } [[TMP3472]], 0
-// CHECK-NEXT: [[TMP3474:%.*]] = extractvalue { i64, i1 } [[TMP3472]], 1
-// CHECK-NEXT: [[TMP3475:%.*]] = select i1 [[TMP3474]], i64 [[TMP3470]], i64 [[TMP3473]]
-// CHECK-NEXT: store i64 [[TMP3475]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3476:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3477:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3478:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3476]], i64 [[TMP3477]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3479:%.*]] = extractvalue { i64, i1 } [[TMP3478]], 0
-// CHECK-NEXT: [[TMP3480:%.*]] = extractvalue { i64, i1 } [[TMP3478]], 1
-// CHECK-NEXT: br i1 [[TMP3480]], label [[ULX_ATOMIC_EXIT337:%.*]], label [[ULX_ATOMIC_CONT338:%.*]]
-// CHECK: ulx.atomic.cont338:
-// CHECK-NEXT: store i64 [[TMP3479]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT337]]
-// CHECK: ulx.atomic.exit337:
-// CHECK-NEXT: [[TMP3481:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3482:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3483:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3481]], i64 [[TMP3482]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3484:%.*]] = extractvalue { i64, i1 } [[TMP3483]], 0
-// CHECK-NEXT: [[TMP3485:%.*]] = extractvalue { i64, i1 } [[TMP3483]], 1
-// CHECK-NEXT: br i1 [[TMP3485]], label [[ULX_ATOMIC_EXIT339:%.*]], label [[ULX_ATOMIC_CONT340:%.*]]
-// CHECK: ulx.atomic.cont340:
-// CHECK-NEXT: store i64 [[TMP3484]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT339]]
-// CHECK: ulx.atomic.exit339:
-// CHECK-NEXT: [[TMP3486:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3487:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3488:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3486]], i64 [[TMP3487]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3489:%.*]] = extractvalue { i64, i1 } [[TMP3488]], 1
-// CHECK-NEXT: [[TMP3490:%.*]] = zext i1 [[TMP3489]] to i64
-// CHECK-NEXT: store i64 [[TMP3490]], ptr [[ULR]], align 8
-// CHECK-NEXT: [[TMP3491:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3492:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3493:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3491]], i64 [[TMP3492]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3494:%.*]] = extractvalue { i64, i1 } [[TMP3493]], 1
-// CHECK-NEXT: [[TMP3495:%.*]] = zext i1 [[TMP3494]] to i64
-// CHECK-NEXT: store i64 [[TMP3495]], ptr [[ULR]], align 8
-// CHECK-NEXT: [[TMP3496:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3497:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3498:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3496]], i64 [[TMP3497]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3499:%.*]] = extractvalue { i64, i1 } [[TMP3498]], 0
-// CHECK-NEXT: [[TMP3500:%.*]] = extractvalue { i64, i1 } [[TMP3498]], 1
-// CHECK-NEXT: br i1 [[TMP3500]], label [[ULX_ATOMIC_EXIT341:%.*]], label [[ULX_ATOMIC_CONT342:%.*]]
-// CHECK: ulx.atomic.cont342:
-// CHECK-NEXT: store i64 [[TMP3499]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT341]]
-// CHECK: ulx.atomic.exit341:
-// CHECK-NEXT: [[TMP3501:%.*]] = extractvalue { i64, i1 } [[TMP3498]], 1
-// CHECK-NEXT: [[TMP3502:%.*]] = zext i1 [[TMP3501]] to i64
-// CHECK-NEXT: store i64 [[TMP3502]], ptr [[ULR]], align 8
-// CHECK-NEXT: [[TMP3503:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3504:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3505:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3503]], i64 [[TMP3504]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3506:%.*]] = extractvalue { i64, i1 } [[TMP3505]], 0
-// CHECK-NEXT: [[TMP3507:%.*]] = extractvalue { i64, i1 } [[TMP3505]], 1
-// CHECK-NEXT: br i1 [[TMP3507]], label [[ULX_ATOMIC_EXIT343:%.*]], label [[ULX_ATOMIC_CONT344:%.*]]
-// CHECK: ulx.atomic.cont344:
-// CHECK-NEXT: store i64 [[TMP3506]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT343]]
-// CHECK: ulx.atomic.exit343:
-// CHECK-NEXT: [[TMP3508:%.*]] = extractvalue { i64, i1 } [[TMP3505]], 1
-// CHECK-NEXT: [[TMP3509:%.*]] = zext i1 [[TMP3508]] to i64
-// CHECK-NEXT: store i64 [[TMP3509]], ptr [[ULR]], align 8
-// CHECK-NEXT: [[TMP3510:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3511:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3510]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3511]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3512:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3513:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3512]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3513]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3514:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3515:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3514]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3515]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3516:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3517:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3516]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3517]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3518:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3519:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3520:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3518]], i64 [[TMP3519]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3521:%.*]] = extractvalue { i64, i1 } [[TMP3520]], 0
-// CHECK-NEXT: store i64 [[TMP3521]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3522:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3523:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3524:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3522]], i64 [[TMP3523]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3525:%.*]] = extractvalue { i64, i1 } [[TMP3524]], 0
-// CHECK-NEXT: store i64 [[TMP3525]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3526:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3527:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3526]] monotonic, align 8
-// CHECK-NEXT: [[TMP3528:%.*]] = icmp ugt i64 [[TMP3527]], [[TMP3526]]
-// CHECK-NEXT: [[TMP3529:%.*]] = select i1 [[TMP3528]], i64 [[TMP3526]], i64 [[TMP3527]]
-// CHECK-NEXT: store i64 [[TMP3529]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3530:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3531:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3530]] monotonic, align 8
-// CHECK-NEXT: [[TMP3532:%.*]] = icmp ult i64 [[TMP3531]], [[TMP3530]]
-// CHECK-NEXT: [[TMP3533:%.*]] = select i1 [[TMP3532]], i64 [[TMP3530]], i64 [[TMP3531]]
-// CHECK-NEXT: store i64 [[TMP3533]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3534:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3535:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3534]] monotonic, align 8
-// CHECK-NEXT: [[TMP3536:%.*]] = icmp ult i64 [[TMP3535]], [[TMP3534]]
-// CHECK-NEXT: [[TMP3537:%.*]] = select i1 [[TMP3536]], i64 [[TMP3534]], i64 [[TMP3535]]
-// CHECK-NEXT: store i64 [[TMP3537]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3538:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3539:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3538]] monotonic, align 8
-// CHECK-NEXT: [[TMP3540:%.*]] = icmp ugt i64 [[TMP3539]], [[TMP3538]]
-// CHECK-NEXT: [[TMP3541:%.*]] = select i1 [[TMP3540]], i64 [[TMP3538]], i64 [[TMP3539]]
-// CHECK-NEXT: store i64 [[TMP3541]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3542:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3543:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3544:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3542]], i64 [[TMP3543]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3545:%.*]] = extractvalue { i64, i1 } [[TMP3544]], 0
-// CHECK-NEXT: [[TMP3546:%.*]] = extractvalue { i64, i1 } [[TMP3544]], 1
-// CHECK-NEXT: [[TMP3547:%.*]] = select i1 [[TMP3546]], i64 [[TMP3542]], i64 [[TMP3545]]
-// CHECK-NEXT: store i64 [[TMP3547]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3548:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3549:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3550:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3548]], i64 [[TMP3549]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3551:%.*]] = extractvalue { i64, i1 } [[TMP3550]], 0
-// CHECK-NEXT: [[TMP3552:%.*]] = extractvalue { i64, i1 } [[TMP3550]], 1
-// CHECK-NEXT: [[TMP3553:%.*]] = select i1 [[TMP3552]], i64 [[TMP3548]], i64 [[TMP3551]]
-// CHECK-NEXT: store i64 [[TMP3553]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP3554:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3555:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3556:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3554]], i64 [[TMP3555]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3557:%.*]] = extractvalue { i64, i1 } [[TMP3556]], 0
-// CHECK-NEXT: [[TMP3558:%.*]] = extractvalue { i64, i1 } [[TMP3556]], 1
-// CHECK-NEXT: br i1 [[TMP3558]], label [[ULX_ATOMIC_EXIT345:%.*]], label [[ULX_ATOMIC_CONT346:%.*]]
-// CHECK: ulx.atomic.cont346:
-// CHECK-NEXT: store i64 [[TMP3557]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT345]]
-// CHECK: ulx.atomic.exit345:
-// CHECK-NEXT: [[TMP3559:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3560:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3561:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3559]], i64 [[TMP3560]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3562:%.*]] = extractvalue { i64, i1 } [[TMP3561]], 0
-// CHECK-NEXT: [[TMP3563:%.*]] = extractvalue { i64, i1 } [[TMP3561]], 1
-// CHECK-NEXT: br i1 [[TMP3563]], label [[ULX_ATOMIC_EXIT347:%.*]], label [[ULX_ATOMIC_CONT348:%.*]]
-// CHECK: ulx.atomic.cont348:
-// CHECK-NEXT: store i64 [[TMP3562]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT347]]
-// CHECK: ulx.atomic.exit347:
-// CHECK-NEXT: [[TMP3564:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3565:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3566:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3564]], i64 [[TMP3565]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3567:%.*]] = extractvalue { i64, i1 } [[TMP3566]], 1
-// CHECK-NEXT: [[TMP3568:%.*]] = zext i1 [[TMP3567]] to i64
-// CHECK-NEXT: store i64 [[TMP3568]], ptr [[ULR]], align 8
-// CHECK-NEXT: [[TMP3569:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3570:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3571:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3569]], i64 [[TMP3570]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3572:%.*]] = extractvalue { i64, i1 } [[TMP3571]], 1
-// CHECK-NEXT: [[TMP3573:%.*]] = zext i1 [[TMP3572]] to i64
-// CHECK-NEXT: store i64 [[TMP3573]], ptr [[ULR]], align 8
-// CHECK-NEXT: [[TMP3574:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3575:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3576:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3574]], i64 [[TMP3575]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3577:%.*]] = extractvalue { i64, i1 } [[TMP3576]], 0
-// CHECK-NEXT: [[TMP3578:%.*]] = extractvalue { i64, i1 } [[TMP3576]], 1
-// CHECK-NEXT: br i1 [[TMP3578]], label [[ULX_ATOMIC_EXIT349:%.*]], label [[ULX_ATOMIC_CONT350:%.*]]
-// CHECK: ulx.atomic.cont350:
-// CHECK-NEXT: store i64 [[TMP3577]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT349]]
-// CHECK: ulx.atomic.exit349:
-// CHECK-NEXT: [[TMP3579:%.*]] = extractvalue { i64, i1 } [[TMP3576]], 1
-// CHECK-NEXT: [[TMP3580:%.*]] = zext i1 [[TMP3579]] to i64
-// CHECK-NEXT: store i64 [[TMP3580]], ptr [[ULR]], align 8
-// CHECK-NEXT: [[TMP3581:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3582:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3583:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3581]], i64 [[TMP3582]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3584:%.*]] = extractvalue { i64, i1 } [[TMP3583]], 0
-// CHECK-NEXT: [[TMP3585:%.*]] = extractvalue { i64, i1 } [[TMP3583]], 1
-// CHECK-NEXT: br i1 [[TMP3585]], label [[ULX_ATOMIC_EXIT351:%.*]], label [[ULX_ATOMIC_CONT352:%.*]]
-// CHECK: ulx.atomic.cont352:
-// CHECK-NEXT: store i64 [[TMP3584]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT351]]
-// CHECK: ulx.atomic.exit351:
-// CHECK-NEXT: [[TMP3586:%.*]] = extractvalue { i64, i1 } [[TMP3583]], 1
-// CHECK-NEXT: [[TMP3587:%.*]] = zext i1 [[TMP3586]] to i64
-// CHECK-NEXT: store i64 [[TMP3587]], ptr [[ULR]], align 8
-// CHECK-NEXT: [[TMP3588:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3589:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3588]] release, align 8
-// CHECK-NEXT: store i64 [[TMP3589]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3590:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3591:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3590]] release, align 8
-// CHECK-NEXT: store i64 [[TMP3591]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3592:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3593:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3592]] release, align 8
-// CHECK-NEXT: store i64 [[TMP3593]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3594:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3595:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3594]] release, align 8
-// CHECK-NEXT: store i64 [[TMP3595]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3596:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3597:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3598:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3596]], i64 [[TMP3597]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3599:%.*]] = extractvalue { i64, i1 } [[TMP3598]], 0
-// CHECK-NEXT: store i64 [[TMP3599]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3600:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3601:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3602:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3600]], i64 [[TMP3601]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3603:%.*]] = extractvalue { i64, i1 } [[TMP3602]], 0
-// CHECK-NEXT: store i64 [[TMP3603]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3604:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3605:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3604]] release, align 8
-// CHECK-NEXT: [[TMP3606:%.*]] = icmp ugt i64 [[TMP3605]], [[TMP3604]]
-// CHECK-NEXT: [[TMP3607:%.*]] = select i1 [[TMP3606]], i64 [[TMP3604]], i64 [[TMP3605]]
-// CHECK-NEXT: store i64 [[TMP3607]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3608:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3609:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3608]] release, align 8
-// CHECK-NEXT: [[TMP3610:%.*]] = icmp ult i64 [[TMP3609]], [[TMP3608]]
-// CHECK-NEXT: [[TMP3611:%.*]] = select i1 [[TMP3610]], i64 [[TMP3608]], i64 [[TMP3609]]
-// CHECK-NEXT: store i64 [[TMP3611]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3612:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3613:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3612]] release, align 8
-// CHECK-NEXT: [[TMP3614:%.*]] = icmp ult i64 [[TMP3613]], [[TMP3612]]
-// CHECK-NEXT: [[TMP3615:%.*]] = select i1 [[TMP3614]], i64 [[TMP3612]], i64 [[TMP3613]]
-// CHECK-NEXT: store i64 [[TMP3615]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3616:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3617:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3616]] release, align 8
-// CHECK-NEXT: [[TMP3618:%.*]] = icmp ugt i64 [[TMP3617]], [[TMP3616]]
-// CHECK-NEXT: [[TMP3619:%.*]] = select i1 [[TMP3618]], i64 [[TMP3616]], i64 [[TMP3617]]
-// CHECK-NEXT: store i64 [[TMP3619]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3620:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3621:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3622:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3620]], i64 [[TMP3621]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3623:%.*]] = extractvalue { i64, i1 } [[TMP3622]], 0
-// CHECK-NEXT: [[TMP3624:%.*]] = extractvalue { i64, i1 } [[TMP3622]], 1
-// CHECK-NEXT: [[TMP3625:%.*]] = select i1 [[TMP3624]], i64 [[TMP3620]], i64 [[TMP3623]]
-// CHECK-NEXT: store i64 [[TMP3625]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3626:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3627:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3628:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3626]], i64 [[TMP3627]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3629:%.*]] = extractvalue { i64, i1 } [[TMP3628]], 0
-// CHECK-NEXT: [[TMP3630:%.*]] = extractvalue { i64, i1 } [[TMP3628]], 1
-// CHECK-NEXT: [[TMP3631:%.*]] = select i1 [[TMP3630]], i64 [[TMP3626]], i64 [[TMP3629]]
-// CHECK-NEXT: store i64 [[TMP3631]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3632:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3633:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3634:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3632]], i64 [[TMP3633]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3635:%.*]] = extractvalue { i64, i1 } [[TMP3634]], 0
-// CHECK-NEXT: [[TMP3636:%.*]] = extractvalue { i64, i1 } [[TMP3634]], 1
-// CHECK-NEXT: br i1 [[TMP3636]], label [[ULX_ATOMIC_EXIT353:%.*]], label [[ULX_ATOMIC_CONT354:%.*]]
-// CHECK: ulx.atomic.cont354:
-// CHECK-NEXT: store i64 [[TMP3635]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT353]]
-// CHECK: ulx.atomic.exit353:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3637:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3638:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3639:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3637]], i64 [[TMP3638]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3640:%.*]] = extractvalue { i64, i1 } [[TMP3639]], 0
-// CHECK-NEXT: [[TMP3641:%.*]] = extractvalue { i64, i1 } [[TMP3639]], 1
-// CHECK-NEXT: br i1 [[TMP3641]], label [[ULX_ATOMIC_EXIT355:%.*]], label [[ULX_ATOMIC_CONT356:%.*]]
-// CHECK: ulx.atomic.cont356:
-// CHECK-NEXT: store i64 [[TMP3640]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT355]]
-// CHECK: ulx.atomic.exit355:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3642:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3643:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3644:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3642]], i64 [[TMP3643]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3645:%.*]] = extractvalue { i64, i1 } [[TMP3644]], 1
-// CHECK-NEXT: [[TMP3646:%.*]] = zext i1 [[TMP3645]] to i64
-// CHECK-NEXT: store i64 [[TMP3646]], ptr [[ULR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3647:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3648:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3649:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3647]], i64 [[TMP3648]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3650:%.*]] = extractvalue { i64, i1 } [[TMP3649]], 1
-// CHECK-NEXT: [[TMP3651:%.*]] = zext i1 [[TMP3650]] to i64
-// CHECK-NEXT: store i64 [[TMP3651]], ptr [[ULR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3652:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3653:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3654:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3652]], i64 [[TMP3653]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3655:%.*]] = extractvalue { i64, i1 } [[TMP3654]], 0
-// CHECK-NEXT: [[TMP3656:%.*]] = extractvalue { i64, i1 } [[TMP3654]], 1
-// CHECK-NEXT: br i1 [[TMP3656]], label [[ULX_ATOMIC_EXIT357:%.*]], label [[ULX_ATOMIC_CONT358:%.*]]
-// CHECK: ulx.atomic.cont358:
-// CHECK-NEXT: store i64 [[TMP3655]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT357]]
-// CHECK: ulx.atomic.exit357:
-// CHECK-NEXT: [[TMP3657:%.*]] = extractvalue { i64, i1 } [[TMP3654]], 1
-// CHECK-NEXT: [[TMP3658:%.*]] = zext i1 [[TMP3657]] to i64
-// CHECK-NEXT: store i64 [[TMP3658]], ptr [[ULR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3659:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3660:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3661:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3659]], i64 [[TMP3660]] release monotonic, align 8
-// CHECK-NEXT: [[TMP3662:%.*]] = extractvalue { i64, i1 } [[TMP3661]], 0
-// CHECK-NEXT: [[TMP3663:%.*]] = extractvalue { i64, i1 } [[TMP3661]], 1
-// CHECK-NEXT: br i1 [[TMP3663]], label [[ULX_ATOMIC_EXIT359:%.*]], label [[ULX_ATOMIC_CONT360:%.*]]
-// CHECK: ulx.atomic.cont360:
-// CHECK-NEXT: store i64 [[TMP3662]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT359]]
-// CHECK: ulx.atomic.exit359:
-// CHECK-NEXT: [[TMP3664:%.*]] = extractvalue { i64, i1 } [[TMP3661]], 1
-// CHECK-NEXT: [[TMP3665:%.*]] = zext i1 [[TMP3664]] to i64
-// CHECK-NEXT: store i64 [[TMP3665]], ptr [[ULR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3666:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3667:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3666]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP3667]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3668:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3669:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3668]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP3669]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3670:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3671:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3670]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP3671]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3672:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3673:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3672]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP3673]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3674:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3675:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3676:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3674]], i64 [[TMP3675]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3677:%.*]] = extractvalue { i64, i1 } [[TMP3676]], 0
-// CHECK-NEXT: store i64 [[TMP3677]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3678:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3679:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3680:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3678]], i64 [[TMP3679]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3681:%.*]] = extractvalue { i64, i1 } [[TMP3680]], 0
-// CHECK-NEXT: store i64 [[TMP3681]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3682:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3683:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3682]] seq_cst, align 8
-// CHECK-NEXT: [[TMP3684:%.*]] = icmp ugt i64 [[TMP3683]], [[TMP3682]]
-// CHECK-NEXT: [[TMP3685:%.*]] = select i1 [[TMP3684]], i64 [[TMP3682]], i64 [[TMP3683]]
-// CHECK-NEXT: store i64 [[TMP3685]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3686:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3687:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3686]] seq_cst, align 8
-// CHECK-NEXT: [[TMP3688:%.*]] = icmp ult i64 [[TMP3687]], [[TMP3686]]
-// CHECK-NEXT: [[TMP3689:%.*]] = select i1 [[TMP3688]], i64 [[TMP3686]], i64 [[TMP3687]]
-// CHECK-NEXT: store i64 [[TMP3689]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3690:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3691:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP3690]] seq_cst, align 8
-// CHECK-NEXT: [[TMP3692:%.*]] = icmp ult i64 [[TMP3691]], [[TMP3690]]
-// CHECK-NEXT: [[TMP3693:%.*]] = select i1 [[TMP3692]], i64 [[TMP3690]], i64 [[TMP3691]]
-// CHECK-NEXT: store i64 [[TMP3693]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3694:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3695:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP3694]] seq_cst, align 8
-// CHECK-NEXT: [[TMP3696:%.*]] = icmp ugt i64 [[TMP3695]], [[TMP3694]]
-// CHECK-NEXT: [[TMP3697:%.*]] = select i1 [[TMP3696]], i64 [[TMP3694]], i64 [[TMP3695]]
-// CHECK-NEXT: store i64 [[TMP3697]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3698:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3699:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3700:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3698]], i64 [[TMP3699]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3701:%.*]] = extractvalue { i64, i1 } [[TMP3700]], 0
-// CHECK-NEXT: [[TMP3702:%.*]] = extractvalue { i64, i1 } [[TMP3700]], 1
-// CHECK-NEXT: [[TMP3703:%.*]] = select i1 [[TMP3702]], i64 [[TMP3698]], i64 [[TMP3701]]
-// CHECK-NEXT: store i64 [[TMP3703]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3704:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3705:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3706:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3704]], i64 [[TMP3705]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3707:%.*]] = extractvalue { i64, i1 } [[TMP3706]], 0
-// CHECK-NEXT: [[TMP3708:%.*]] = extractvalue { i64, i1 } [[TMP3706]], 1
-// CHECK-NEXT: [[TMP3709:%.*]] = select i1 [[TMP3708]], i64 [[TMP3704]], i64 [[TMP3707]]
-// CHECK-NEXT: store i64 [[TMP3709]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3710:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3711:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3712:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3710]], i64 [[TMP3711]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3713:%.*]] = extractvalue { i64, i1 } [[TMP3712]], 0
-// CHECK-NEXT: [[TMP3714:%.*]] = extractvalue { i64, i1 } [[TMP3712]], 1
-// CHECK-NEXT: br i1 [[TMP3714]], label [[ULX_ATOMIC_EXIT361:%.*]], label [[ULX_ATOMIC_CONT362:%.*]]
-// CHECK: ulx.atomic.cont362:
-// CHECK-NEXT: store i64 [[TMP3713]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT361]]
-// CHECK: ulx.atomic.exit361:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3715:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3716:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3717:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3715]], i64 [[TMP3716]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3718:%.*]] = extractvalue { i64, i1 } [[TMP3717]], 0
-// CHECK-NEXT: [[TMP3719:%.*]] = extractvalue { i64, i1 } [[TMP3717]], 1
-// CHECK-NEXT: br i1 [[TMP3719]], label [[ULX_ATOMIC_EXIT363:%.*]], label [[ULX_ATOMIC_CONT364:%.*]]
-// CHECK: ulx.atomic.cont364:
-// CHECK-NEXT: store i64 [[TMP3718]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT363]]
-// CHECK: ulx.atomic.exit363:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3720:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3721:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3722:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3720]], i64 [[TMP3721]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3723:%.*]] = extractvalue { i64, i1 } [[TMP3722]], 1
-// CHECK-NEXT: [[TMP3724:%.*]] = zext i1 [[TMP3723]] to i64
-// CHECK-NEXT: store i64 [[TMP3724]], ptr [[ULR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3725:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3726:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3727:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3725]], i64 [[TMP3726]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3728:%.*]] = extractvalue { i64, i1 } [[TMP3727]], 1
-// CHECK-NEXT: [[TMP3729:%.*]] = zext i1 [[TMP3728]] to i64
-// CHECK-NEXT: store i64 [[TMP3729]], ptr [[ULR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3730:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3731:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3732:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3730]], i64 [[TMP3731]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3733:%.*]] = extractvalue { i64, i1 } [[TMP3732]], 0
-// CHECK-NEXT: [[TMP3734:%.*]] = extractvalue { i64, i1 } [[TMP3732]], 1
-// CHECK-NEXT: br i1 [[TMP3734]], label [[ULX_ATOMIC_EXIT365:%.*]], label [[ULX_ATOMIC_CONT366:%.*]]
-// CHECK: ulx.atomic.cont366:
-// CHECK-NEXT: store i64 [[TMP3733]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT365]]
-// CHECK: ulx.atomic.exit365:
-// CHECK-NEXT: [[TMP3735:%.*]] = extractvalue { i64, i1 } [[TMP3732]], 1
-// CHECK-NEXT: [[TMP3736:%.*]] = zext i1 [[TMP3735]] to i64
-// CHECK-NEXT: store i64 [[TMP3736]], ptr [[ULR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3737:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP3738:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP3739:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP3737]], i64 [[TMP3738]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP3740:%.*]] = extractvalue { i64, i1 } [[TMP3739]], 0
-// CHECK-NEXT: [[TMP3741:%.*]] = extractvalue { i64, i1 } [[TMP3739]], 1
-// CHECK-NEXT: br i1 [[TMP3741]], label [[ULX_ATOMIC_EXIT367:%.*]], label [[ULX_ATOMIC_CONT368:%.*]]
-// CHECK: ulx.atomic.cont368:
-// CHECK-NEXT: store i64 [[TMP3740]], ptr [[ULV]], align 8
-// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT367]]
-// CHECK: ulx.atomic.exit367:
-// CHECK-NEXT: [[TMP3742:%.*]] = extractvalue { i64, i1 } [[TMP3739]], 1
-// CHECK-NEXT: [[TMP3743:%.*]] = zext i1 [[TMP3742]] to i64
-// CHECK-NEXT: store i64 [[TMP3743]], ptr [[ULR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3744:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3745:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3744]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3745]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3746:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3747:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3746]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3747]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3748:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3749:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3748]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3749]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3750:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3751:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3750]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3751]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3752:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3753:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3754:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3752]], i64 [[TMP3753]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3755:%.*]] = extractvalue { i64, i1 } [[TMP3754]], 0
-// CHECK-NEXT: store i64 [[TMP3755]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3756:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3757:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3758:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3756]], i64 [[TMP3757]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3759:%.*]] = extractvalue { i64, i1 } [[TMP3758]], 0
-// CHECK-NEXT: store i64 [[TMP3759]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3760:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3761:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3760]] monotonic, align 8
-// CHECK-NEXT: [[TMP3762:%.*]] = icmp sgt i64 [[TMP3761]], [[TMP3760]]
-// CHECK-NEXT: [[TMP3763:%.*]] = select i1 [[TMP3762]], i64 [[TMP3760]], i64 [[TMP3761]]
-// CHECK-NEXT: store i64 [[TMP3763]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3764:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3765:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3764]] monotonic, align 8
-// CHECK-NEXT: [[TMP3766:%.*]] = icmp slt i64 [[TMP3765]], [[TMP3764]]
-// CHECK-NEXT: [[TMP3767:%.*]] = select i1 [[TMP3766]], i64 [[TMP3764]], i64 [[TMP3765]]
-// CHECK-NEXT: store i64 [[TMP3767]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3768:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3769:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3768]] monotonic, align 8
-// CHECK-NEXT: [[TMP3770:%.*]] = icmp slt i64 [[TMP3769]], [[TMP3768]]
-// CHECK-NEXT: [[TMP3771:%.*]] = select i1 [[TMP3770]], i64 [[TMP3768]], i64 [[TMP3769]]
-// CHECK-NEXT: store i64 [[TMP3771]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3772:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3773:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3772]] monotonic, align 8
-// CHECK-NEXT: [[TMP3774:%.*]] = icmp sgt i64 [[TMP3773]], [[TMP3772]]
-// CHECK-NEXT: [[TMP3775:%.*]] = select i1 [[TMP3774]], i64 [[TMP3772]], i64 [[TMP3773]]
-// CHECK-NEXT: store i64 [[TMP3775]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3776:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3777:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3778:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3776]], i64 [[TMP3777]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3779:%.*]] = extractvalue { i64, i1 } [[TMP3778]], 0
-// CHECK-NEXT: [[TMP3780:%.*]] = extractvalue { i64, i1 } [[TMP3778]], 1
-// CHECK-NEXT: [[TMP3781:%.*]] = select i1 [[TMP3780]], i64 [[TMP3776]], i64 [[TMP3779]]
-// CHECK-NEXT: store i64 [[TMP3781]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3782:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3783:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3784:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3782]], i64 [[TMP3783]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3785:%.*]] = extractvalue { i64, i1 } [[TMP3784]], 0
-// CHECK-NEXT: [[TMP3786:%.*]] = extractvalue { i64, i1 } [[TMP3784]], 1
-// CHECK-NEXT: [[TMP3787:%.*]] = select i1 [[TMP3786]], i64 [[TMP3782]], i64 [[TMP3785]]
-// CHECK-NEXT: store i64 [[TMP3787]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3788:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3789:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3790:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3788]], i64 [[TMP3789]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3791:%.*]] = extractvalue { i64, i1 } [[TMP3790]], 0
-// CHECK-NEXT: [[TMP3792:%.*]] = extractvalue { i64, i1 } [[TMP3790]], 1
-// CHECK-NEXT: br i1 [[TMP3792]], label [[LLX_ATOMIC_EXIT:%.*]], label [[LLX_ATOMIC_CONT:%.*]]
+// CHECK-NEXT: [[TMP2050:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2051:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2050]], ptr [[ULX_ATOMIC_EXPECTED_PTR4078]], align 8
+// CHECK-NEXT: store i64 [[TMP2051]], ptr [[ULX_ATOMIC_DESIRED_PTR4079]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4081:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4078]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4082:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4079]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4083:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4081]], i64 [[ULX_CMPXCHG_DESIRED4082]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4084:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4083]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4084]], ptr [[ULX_ATOMIC_EXPECTED_PTR4080]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4085:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4083]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4086:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4080]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4085]], label [[ULX_ATOMIC_EXIT4087:%.*]], label [[ULX_ATOMIC_CONT4088:%.*]]
+// CHECK: ulx.atomic.cont4088:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4086]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4087]]
+// CHECK: ulx.atomic.exit4087:
+// CHECK-NEXT: [[TMP2052:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2053:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2052]], ptr [[ULX_ATOMIC_EXPECTED_PTR4089]], align 8
+// CHECK-NEXT: store i64 [[TMP2053]], ptr [[ULX_ATOMIC_DESIRED_PTR4090]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4092:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4089]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4093:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4090]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4094:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4092]], i64 [[ULX_CMPXCHG_DESIRED4093]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4095:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4094]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4095]], ptr [[ULX_ATOMIC_EXPECTED_PTR4091]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4096:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4094]], 1
+// CHECK-NEXT: [[TMP2054:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4096]] to i64
+// CHECK-NEXT: store i64 [[TMP2054]], ptr [[ULR]], align 8
+// CHECK-NEXT: [[TMP2055:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2056:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2055]], ptr [[ULX_ATOMIC_EXPECTED_PTR4097]], align 8
+// CHECK-NEXT: store i64 [[TMP2056]], ptr [[ULX_ATOMIC_DESIRED_PTR4098]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4100:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4097]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4101:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4098]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4102:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4100]], i64 [[ULX_CMPXCHG_DESIRED4101]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4103:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4102]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4103]], ptr [[ULX_ATOMIC_EXPECTED_PTR4099]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4104:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4102]], 1
+// CHECK-NEXT: [[TMP2057:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4104]] to i64
+// CHECK-NEXT: store i64 [[TMP2057]], ptr [[ULR]], align 8
+// CHECK-NEXT: [[TMP2058:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2059:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2058]], ptr [[ULX_ATOMIC_EXPECTED_PTR4105]], align 8
+// CHECK-NEXT: store i64 [[TMP2059]], ptr [[ULX_ATOMIC_DESIRED_PTR4106]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4108:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4105]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4109:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4106]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4110:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4108]], i64 [[ULX_CMPXCHG_DESIRED4109]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4111:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4110]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4111]], ptr [[ULX_ATOMIC_EXPECTED_PTR4107]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4112:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4110]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4113:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4107]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4112]], label [[ULX_ATOMIC_EXIT4114:%.*]], label [[ULX_ATOMIC_CONT4115:%.*]]
+// CHECK: ulx.atomic.cont4115:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4113]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4114]]
+// CHECK: ulx.atomic.exit4114:
+// CHECK-NEXT: [[TMP2060:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4112]] to i64
+// CHECK-NEXT: store i64 [[TMP2060]], ptr [[ULR]], align 8
+// CHECK-NEXT: [[TMP2061:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2062:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2061]], ptr [[ULX_ATOMIC_EXPECTED_PTR4116]], align 8
+// CHECK-NEXT: store i64 [[TMP2062]], ptr [[ULX_ATOMIC_DESIRED_PTR4117]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4119:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4116]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4120:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4117]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4121:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4119]], i64 [[ULX_CMPXCHG_DESIRED4120]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4122:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4121]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4122]], ptr [[ULX_ATOMIC_EXPECTED_PTR4118]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4123:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4121]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4124:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4118]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4123]], label [[ULX_ATOMIC_EXIT4125:%.*]], label [[ULX_ATOMIC_CONT4126:%.*]]
+// CHECK: ulx.atomic.cont4126:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4124]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4125]]
+// CHECK: ulx.atomic.exit4125:
+// CHECK-NEXT: [[TMP2063:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4123]] to i64
+// CHECK-NEXT: store i64 [[TMP2063]], ptr [[ULR]], align 8
+// CHECK-NEXT: [[TMP2064:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2065:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2064]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP2065]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2066:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2067:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2066]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP2067]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2068:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2069:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2068]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP2069]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2070:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2071:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2070]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP2071]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2072:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2073:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2072]], ptr [[ULX_ATOMIC_EXPECTED_PTR4127]], align 8
+// CHECK-NEXT: store i64 [[TMP2073]], ptr [[ULX_ATOMIC_DESIRED_PTR4128]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4130:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4127]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4131:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4128]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4132:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4130]], i64 [[ULX_CMPXCHG_DESIRED4131]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4133:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4132]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4133]], ptr [[ULX_ATOMIC_EXPECTED_PTR4129]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4134:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4132]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4135:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4129]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4135]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2074:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2075:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2074]], ptr [[ULX_ATOMIC_EXPECTED_PTR4136]], align 8
+// CHECK-NEXT: store i64 [[TMP2075]], ptr [[ULX_ATOMIC_DESIRED_PTR4137]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4139:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4136]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4140:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4137]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4141:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4139]], i64 [[ULX_CMPXCHG_DESIRED4140]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4142:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4141]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4142]], ptr [[ULX_ATOMIC_EXPECTED_PTR4138]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4143:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4141]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4144:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4138]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4144]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2076:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2077:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2076]] acq_rel, align 8
+// CHECK-NEXT: [[TMP2078:%.*]] = icmp ugt i64 [[TMP2077]], [[TMP2076]]
+// CHECK-NEXT: [[TMP2079:%.*]] = select i1 [[TMP2078]], i64 [[TMP2076]], i64 [[TMP2077]]
+// CHECK-NEXT: store i64 [[TMP2079]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2080:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2081:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2080]] acq_rel, align 8
+// CHECK-NEXT: [[TMP2082:%.*]] = icmp ult i64 [[TMP2081]], [[TMP2080]]
+// CHECK-NEXT: [[TMP2083:%.*]] = select i1 [[TMP2082]], i64 [[TMP2080]], i64 [[TMP2081]]
+// CHECK-NEXT: store i64 [[TMP2083]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2084:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2085:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2084]] acq_rel, align 8
+// CHECK-NEXT: [[TMP2086:%.*]] = icmp ult i64 [[TMP2085]], [[TMP2084]]
+// CHECK-NEXT: [[TMP2087:%.*]] = select i1 [[TMP2086]], i64 [[TMP2084]], i64 [[TMP2085]]
+// CHECK-NEXT: store i64 [[TMP2087]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2088:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2089:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2088]] acq_rel, align 8
+// CHECK-NEXT: [[TMP2090:%.*]] = icmp ugt i64 [[TMP2089]], [[TMP2088]]
+// CHECK-NEXT: [[TMP2091:%.*]] = select i1 [[TMP2090]], i64 [[TMP2088]], i64 [[TMP2089]]
+// CHECK-NEXT: store i64 [[TMP2091]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2092:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2093:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2092]], ptr [[ULX_ATOMIC_EXPECTED_PTR4145]], align 8
+// CHECK-NEXT: store i64 [[TMP2093]], ptr [[ULX_ATOMIC_DESIRED_PTR4146]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4148:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4145]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4149:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4146]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4150:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4148]], i64 [[ULX_CMPXCHG_DESIRED4149]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4151:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4150]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4151]], ptr [[ULX_ATOMIC_EXPECTED_PTR4147]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4152:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4150]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4153:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4147]], align 8
+// CHECK-NEXT: [[ULX_CAPTURE_CAPTURED4154:%.*]] = select i1 [[ULX_CMPXCHG_SUCCESS4152]], i64 [[TMP2092]], i64 [[ULX_CAPTURE_ACTUAL4153]]
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_CAPTURED4154]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2094:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2095:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2094]], ptr [[ULX_ATOMIC_EXPECTED_PTR4155]], align 8
+// CHECK-NEXT: store i64 [[TMP2095]], ptr [[ULX_ATOMIC_DESIRED_PTR4156]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4158:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4155]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4159:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4156]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4160:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4158]], i64 [[ULX_CMPXCHG_DESIRED4159]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4161:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4160]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4161]], ptr [[ULX_ATOMIC_EXPECTED_PTR4157]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4162:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4160]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4163:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4157]], align 8
+// CHECK-NEXT: [[ULX_CAPTURE_CAPTURED4164:%.*]] = select i1 [[ULX_CMPXCHG_SUCCESS4162]], i64 [[TMP2094]], i64 [[ULX_CAPTURE_ACTUAL4163]]
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_CAPTURED4164]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2096:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2097:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2096]], ptr [[ULX_ATOMIC_EXPECTED_PTR4165]], align 8
+// CHECK-NEXT: store i64 [[TMP2097]], ptr [[ULX_ATOMIC_DESIRED_PTR4166]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4168:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4165]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4169:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4166]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4170:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4168]], i64 [[ULX_CMPXCHG_DESIRED4169]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4171:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4170]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4171]], ptr [[ULX_ATOMIC_EXPECTED_PTR4167]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4172:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4170]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4173:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4167]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4172]], label [[ULX_ATOMIC_EXIT4174:%.*]], label [[ULX_ATOMIC_CONT4175:%.*]]
+// CHECK: ulx.atomic.cont4175:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4173]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4174]]
+// CHECK: ulx.atomic.exit4174:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2098:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2099:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2098]], ptr [[ULX_ATOMIC_EXPECTED_PTR4176]], align 8
+// CHECK-NEXT: store i64 [[TMP2099]], ptr [[ULX_ATOMIC_DESIRED_PTR4177]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4179:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4176]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4180:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4177]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4181:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4179]], i64 [[ULX_CMPXCHG_DESIRED4180]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4182:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4181]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4182]], ptr [[ULX_ATOMIC_EXPECTED_PTR4178]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4183:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4181]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4184:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4178]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4183]], label [[ULX_ATOMIC_EXIT4185:%.*]], label [[ULX_ATOMIC_CONT4186:%.*]]
+// CHECK: ulx.atomic.cont4186:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4184]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4185]]
+// CHECK: ulx.atomic.exit4185:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2100:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2101:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2100]], ptr [[ULX_ATOMIC_EXPECTED_PTR4187]], align 8
+// CHECK-NEXT: store i64 [[TMP2101]], ptr [[ULX_ATOMIC_DESIRED_PTR4188]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4190:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4187]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4191:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4188]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4192:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4190]], i64 [[ULX_CMPXCHG_DESIRED4191]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4193:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4192]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4193]], ptr [[ULX_ATOMIC_EXPECTED_PTR4189]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4194:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4192]], 1
+// CHECK-NEXT: [[TMP2102:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4194]] to i64
+// CHECK-NEXT: store i64 [[TMP2102]], ptr [[ULR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2103:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2104:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2103]], ptr [[ULX_ATOMIC_EXPECTED_PTR4195]], align 8
+// CHECK-NEXT: store i64 [[TMP2104]], ptr [[ULX_ATOMIC_DESIRED_PTR4196]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4198:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4195]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4199:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4196]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4200:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4198]], i64 [[ULX_CMPXCHG_DESIRED4199]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4201:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4200]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4201]], ptr [[ULX_ATOMIC_EXPECTED_PTR4197]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4202:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4200]], 1
+// CHECK-NEXT: [[TMP2105:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4202]] to i64
+// CHECK-NEXT: store i64 [[TMP2105]], ptr [[ULR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2106:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2107:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2106]], ptr [[ULX_ATOMIC_EXPECTED_PTR4203]], align 8
+// CHECK-NEXT: store i64 [[TMP2107]], ptr [[ULX_ATOMIC_DESIRED_PTR4204]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4206:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4203]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4207:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4204]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4208:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4206]], i64 [[ULX_CMPXCHG_DESIRED4207]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4209:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4208]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4209]], ptr [[ULX_ATOMIC_EXPECTED_PTR4205]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4210:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4208]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4211:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4205]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4210]], label [[ULX_ATOMIC_EXIT4212:%.*]], label [[ULX_ATOMIC_CONT4213:%.*]]
+// CHECK: ulx.atomic.cont4213:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4211]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4212]]
+// CHECK: ulx.atomic.exit4212:
+// CHECK-NEXT: [[TMP2108:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4210]] to i64
+// CHECK-NEXT: store i64 [[TMP2108]], ptr [[ULR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2109:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2110:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2109]], ptr [[ULX_ATOMIC_EXPECTED_PTR4214]], align 8
+// CHECK-NEXT: store i64 [[TMP2110]], ptr [[ULX_ATOMIC_DESIRED_PTR4215]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4217:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4214]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4218:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4215]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4219:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4217]], i64 [[ULX_CMPXCHG_DESIRED4218]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4220:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4219]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4220]], ptr [[ULX_ATOMIC_EXPECTED_PTR4216]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4221:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4219]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4222:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4216]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4221]], label [[ULX_ATOMIC_EXIT4223:%.*]], label [[ULX_ATOMIC_CONT4224:%.*]]
+// CHECK: ulx.atomic.cont4224:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4222]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4223]]
+// CHECK: ulx.atomic.exit4223:
+// CHECK-NEXT: [[TMP2111:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4221]] to i64
+// CHECK-NEXT: store i64 [[TMP2111]], ptr [[ULR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2112:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2113:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2112]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP2113]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2114:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2115:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2114]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP2115]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2116:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2117:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2116]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP2117]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2118:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2119:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2118]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP2119]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2120:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2121:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2120]], ptr [[ULX_ATOMIC_EXPECTED_PTR4225]], align 8
+// CHECK-NEXT: store i64 [[TMP2121]], ptr [[ULX_ATOMIC_DESIRED_PTR4226]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4228:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4225]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4229:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4226]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4230:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4228]], i64 [[ULX_CMPXCHG_DESIRED4229]] acquire acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4231:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4230]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4231]], ptr [[ULX_ATOMIC_EXPECTED_PTR4227]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4232:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4230]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4233:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4227]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4233]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2122:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2123:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2122]], ptr [[ULX_ATOMIC_EXPECTED_PTR4234]], align 8
+// CHECK-NEXT: store i64 [[TMP2123]], ptr [[ULX_ATOMIC_DESIRED_PTR4235]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4237:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4234]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4238:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4235]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4239:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4237]], i64 [[ULX_CMPXCHG_DESIRED4238]] acquire acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4240:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4239]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4240]], ptr [[ULX_ATOMIC_EXPECTED_PTR4236]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4241:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4239]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4242:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4236]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4242]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2124:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2125:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2124]] acquire, align 8
+// CHECK-NEXT: [[TMP2126:%.*]] = icmp ugt i64 [[TMP2125]], [[TMP2124]]
+// CHECK-NEXT: [[TMP2127:%.*]] = select i1 [[TMP2126]], i64 [[TMP2124]], i64 [[TMP2125]]
+// CHECK-NEXT: store i64 [[TMP2127]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2128:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2129:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2128]] acquire, align 8
+// CHECK-NEXT: [[TMP2130:%.*]] = icmp ult i64 [[TMP2129]], [[TMP2128]]
+// CHECK-NEXT: [[TMP2131:%.*]] = select i1 [[TMP2130]], i64 [[TMP2128]], i64 [[TMP2129]]
+// CHECK-NEXT: store i64 [[TMP2131]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2132:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2133:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2132]] acquire, align 8
+// CHECK-NEXT: [[TMP2134:%.*]] = icmp ult i64 [[TMP2133]], [[TMP2132]]
+// CHECK-NEXT: [[TMP2135:%.*]] = select i1 [[TMP2134]], i64 [[TMP2132]], i64 [[TMP2133]]
+// CHECK-NEXT: store i64 [[TMP2135]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2136:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2137:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2136]] acquire, align 8
+// CHECK-NEXT: [[TMP2138:%.*]] = icmp ugt i64 [[TMP2137]], [[TMP2136]]
+// CHECK-NEXT: [[TMP2139:%.*]] = select i1 [[TMP2138]], i64 [[TMP2136]], i64 [[TMP2137]]
+// CHECK-NEXT: store i64 [[TMP2139]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2140:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2141:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2140]], ptr [[ULX_ATOMIC_EXPECTED_PTR4243]], align 8
+// CHECK-NEXT: store i64 [[TMP2141]], ptr [[ULX_ATOMIC_DESIRED_PTR4244]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4246:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4243]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4247:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4244]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4248:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4246]], i64 [[ULX_CMPXCHG_DESIRED4247]] acquire acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4249:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4248]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4249]], ptr [[ULX_ATOMIC_EXPECTED_PTR4245]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4250:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4248]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4251:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4245]], align 8
+// CHECK-NEXT: [[ULX_CAPTURE_CAPTURED4252:%.*]] = select i1 [[ULX_CMPXCHG_SUCCESS4250]], i64 [[TMP2140]], i64 [[ULX_CAPTURE_ACTUAL4251]]
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_CAPTURED4252]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2142:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2143:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2142]], ptr [[ULX_ATOMIC_EXPECTED_PTR4253]], align 8
+// CHECK-NEXT: store i64 [[TMP2143]], ptr [[ULX_ATOMIC_DESIRED_PTR4254]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4256:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4253]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4257:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4254]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4258:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4256]], i64 [[ULX_CMPXCHG_DESIRED4257]] acquire acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4259:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4258]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4259]], ptr [[ULX_ATOMIC_EXPECTED_PTR4255]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4260:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4258]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4261:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4255]], align 8
+// CHECK-NEXT: [[ULX_CAPTURE_CAPTURED4262:%.*]] = select i1 [[ULX_CMPXCHG_SUCCESS4260]], i64 [[TMP2142]], i64 [[ULX_CAPTURE_ACTUAL4261]]
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_CAPTURED4262]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2144:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2145:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2144]], ptr [[ULX_ATOMIC_EXPECTED_PTR4263]], align 8
+// CHECK-NEXT: store i64 [[TMP2145]], ptr [[ULX_ATOMIC_DESIRED_PTR4264]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4266:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4263]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4267:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4264]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4268:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4266]], i64 [[ULX_CMPXCHG_DESIRED4267]] acquire acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4269:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4268]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4269]], ptr [[ULX_ATOMIC_EXPECTED_PTR4265]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4270:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4268]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4271:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4265]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4270]], label [[ULX_ATOMIC_EXIT4272:%.*]], label [[ULX_ATOMIC_CONT4273:%.*]]
+// CHECK: ulx.atomic.cont4273:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4271]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4272]]
+// CHECK: ulx.atomic.exit4272:
+// CHECK-NEXT: [[TMP2146:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2147:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2146]], ptr [[ULX_ATOMIC_EXPECTED_PTR4274]], align 8
+// CHECK-NEXT: store i64 [[TMP2147]], ptr [[ULX_ATOMIC_DESIRED_PTR4275]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4277:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4274]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4278:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4275]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4279:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4277]], i64 [[ULX_CMPXCHG_DESIRED4278]] acquire acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4280:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4279]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4280]], ptr [[ULX_ATOMIC_EXPECTED_PTR4276]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4281:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4279]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4282:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4276]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4281]], label [[ULX_ATOMIC_EXIT4283:%.*]], label [[ULX_ATOMIC_CONT4284:%.*]]
+// CHECK: ulx.atomic.cont4284:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4282]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4283]]
+// CHECK: ulx.atomic.exit4283:
+// CHECK-NEXT: [[TMP2148:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2149:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2148]], ptr [[ULX_ATOMIC_EXPECTED_PTR4285]], align 8
+// CHECK-NEXT: store i64 [[TMP2149]], ptr [[ULX_ATOMIC_DESIRED_PTR4286]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4288:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4285]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4289:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4286]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4290:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4288]], i64 [[ULX_CMPXCHG_DESIRED4289]] acquire acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4291:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4290]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4291]], ptr [[ULX_ATOMIC_EXPECTED_PTR4287]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4292:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4290]], 1
+// CHECK-NEXT: [[TMP2150:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4292]] to i64
+// CHECK-NEXT: store i64 [[TMP2150]], ptr [[ULR]], align 8
+// CHECK-NEXT: [[TMP2151:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2152:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2151]], ptr [[ULX_ATOMIC_EXPECTED_PTR4293]], align 8
+// CHECK-NEXT: store i64 [[TMP2152]], ptr [[ULX_ATOMIC_DESIRED_PTR4294]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4296:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4293]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4297:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4294]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4298:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4296]], i64 [[ULX_CMPXCHG_DESIRED4297]] acquire acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4299:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4298]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4299]], ptr [[ULX_ATOMIC_EXPECTED_PTR4295]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4300:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4298]], 1
+// CHECK-NEXT: [[TMP2153:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4300]] to i64
+// CHECK-NEXT: store i64 [[TMP2153]], ptr [[ULR]], align 8
+// CHECK-NEXT: [[TMP2154:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2155:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2154]], ptr [[ULX_ATOMIC_EXPECTED_PTR4301]], align 8
+// CHECK-NEXT: store i64 [[TMP2155]], ptr [[ULX_ATOMIC_DESIRED_PTR4302]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4304:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4301]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4305:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4302]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4306:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4304]], i64 [[ULX_CMPXCHG_DESIRED4305]] acquire acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4307:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4306]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4307]], ptr [[ULX_ATOMIC_EXPECTED_PTR4303]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4308:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4306]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4309:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4303]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4308]], label [[ULX_ATOMIC_EXIT4310:%.*]], label [[ULX_ATOMIC_CONT4311:%.*]]
+// CHECK: ulx.atomic.cont4311:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4309]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4310]]
+// CHECK: ulx.atomic.exit4310:
+// CHECK-NEXT: [[TMP2156:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4308]] to i64
+// CHECK-NEXT: store i64 [[TMP2156]], ptr [[ULR]], align 8
+// CHECK-NEXT: [[TMP2157:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2158:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2157]], ptr [[ULX_ATOMIC_EXPECTED_PTR4312]], align 8
+// CHECK-NEXT: store i64 [[TMP2158]], ptr [[ULX_ATOMIC_DESIRED_PTR4313]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4315:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4312]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4316:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4313]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4317:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4315]], i64 [[ULX_CMPXCHG_DESIRED4316]] acquire acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4318:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4317]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4318]], ptr [[ULX_ATOMIC_EXPECTED_PTR4314]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4319:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4317]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4320:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4314]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4319]], label [[ULX_ATOMIC_EXIT4321:%.*]], label [[ULX_ATOMIC_CONT4322:%.*]]
+// CHECK: ulx.atomic.cont4322:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4320]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4321]]
+// CHECK: ulx.atomic.exit4321:
+// CHECK-NEXT: [[TMP2159:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4319]] to i64
+// CHECK-NEXT: store i64 [[TMP2159]], ptr [[ULR]], align 8
+// CHECK-NEXT: [[TMP2160:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2161:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2160]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2161]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2162:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2163:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2162]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2163]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2164:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2165:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2164]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2165]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2166:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2167:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2166]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2167]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2168:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2169:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2168]], ptr [[ULX_ATOMIC_EXPECTED_PTR4323]], align 8
+// CHECK-NEXT: store i64 [[TMP2169]], ptr [[ULX_ATOMIC_DESIRED_PTR4324]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4326:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4323]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4327:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4324]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4328:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4326]], i64 [[ULX_CMPXCHG_DESIRED4327]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4329:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4328]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4329]], ptr [[ULX_ATOMIC_EXPECTED_PTR4325]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4330:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4328]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4331:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4325]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4331]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2170:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2171:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2170]], ptr [[ULX_ATOMIC_EXPECTED_PTR4332]], align 8
+// CHECK-NEXT: store i64 [[TMP2171]], ptr [[ULX_ATOMIC_DESIRED_PTR4333]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4335:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4332]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4336:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4333]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4337:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4335]], i64 [[ULX_CMPXCHG_DESIRED4336]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4338:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4337]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4338]], ptr [[ULX_ATOMIC_EXPECTED_PTR4334]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4339:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4337]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4340:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4334]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4340]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2172:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2173:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2172]] monotonic, align 8
+// CHECK-NEXT: [[TMP2174:%.*]] = icmp ugt i64 [[TMP2173]], [[TMP2172]]
+// CHECK-NEXT: [[TMP2175:%.*]] = select i1 [[TMP2174]], i64 [[TMP2172]], i64 [[TMP2173]]
+// CHECK-NEXT: store i64 [[TMP2175]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2176:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2177:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2176]] monotonic, align 8
+// CHECK-NEXT: [[TMP2178:%.*]] = icmp ult i64 [[TMP2177]], [[TMP2176]]
+// CHECK-NEXT: [[TMP2179:%.*]] = select i1 [[TMP2178]], i64 [[TMP2176]], i64 [[TMP2177]]
+// CHECK-NEXT: store i64 [[TMP2179]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2180:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2181:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2180]] monotonic, align 8
+// CHECK-NEXT: [[TMP2182:%.*]] = icmp ult i64 [[TMP2181]], [[TMP2180]]
+// CHECK-NEXT: [[TMP2183:%.*]] = select i1 [[TMP2182]], i64 [[TMP2180]], i64 [[TMP2181]]
+// CHECK-NEXT: store i64 [[TMP2183]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2184:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2185:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2184]] monotonic, align 8
+// CHECK-NEXT: [[TMP2186:%.*]] = icmp ugt i64 [[TMP2185]], [[TMP2184]]
+// CHECK-NEXT: [[TMP2187:%.*]] = select i1 [[TMP2186]], i64 [[TMP2184]], i64 [[TMP2185]]
+// CHECK-NEXT: store i64 [[TMP2187]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2188:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2189:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2188]], ptr [[ULX_ATOMIC_EXPECTED_PTR4341]], align 8
+// CHECK-NEXT: store i64 [[TMP2189]], ptr [[ULX_ATOMIC_DESIRED_PTR4342]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4344:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4341]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4345:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4342]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4346:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4344]], i64 [[ULX_CMPXCHG_DESIRED4345]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4347:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4346]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4347]], ptr [[ULX_ATOMIC_EXPECTED_PTR4343]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4348:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4346]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4349:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4343]], align 8
+// CHECK-NEXT: [[ULX_CAPTURE_CAPTURED4350:%.*]] = select i1 [[ULX_CMPXCHG_SUCCESS4348]], i64 [[TMP2188]], i64 [[ULX_CAPTURE_ACTUAL4349]]
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_CAPTURED4350]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2190:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2191:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2190]], ptr [[ULX_ATOMIC_EXPECTED_PTR4351]], align 8
+// CHECK-NEXT: store i64 [[TMP2191]], ptr [[ULX_ATOMIC_DESIRED_PTR4352]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4354:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4351]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4355:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4352]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4356:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4354]], i64 [[ULX_CMPXCHG_DESIRED4355]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4357:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4356]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4357]], ptr [[ULX_ATOMIC_EXPECTED_PTR4353]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4358:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4356]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4359:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4353]], align 8
+// CHECK-NEXT: [[ULX_CAPTURE_CAPTURED4360:%.*]] = select i1 [[ULX_CMPXCHG_SUCCESS4358]], i64 [[TMP2190]], i64 [[ULX_CAPTURE_ACTUAL4359]]
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_CAPTURED4360]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP2192:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2193:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2192]], ptr [[ULX_ATOMIC_EXPECTED_PTR4361]], align 8
+// CHECK-NEXT: store i64 [[TMP2193]], ptr [[ULX_ATOMIC_DESIRED_PTR4362]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4364:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4361]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4365:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4362]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4366:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4364]], i64 [[ULX_CMPXCHG_DESIRED4365]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4367:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4366]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4367]], ptr [[ULX_ATOMIC_EXPECTED_PTR4363]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4368:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4366]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4369:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4363]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4368]], label [[ULX_ATOMIC_EXIT4370:%.*]], label [[ULX_ATOMIC_CONT4371:%.*]]
+// CHECK: ulx.atomic.cont4371:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4369]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4370]]
+// CHECK: ulx.atomic.exit4370:
+// CHECK-NEXT: [[TMP2194:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2195:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2194]], ptr [[ULX_ATOMIC_EXPECTED_PTR4372]], align 8
+// CHECK-NEXT: store i64 [[TMP2195]], ptr [[ULX_ATOMIC_DESIRED_PTR4373]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4375:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4372]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4376:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4373]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4377:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4375]], i64 [[ULX_CMPXCHG_DESIRED4376]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4378:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4377]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4378]], ptr [[ULX_ATOMIC_EXPECTED_PTR4374]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4379:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4377]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4380:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4374]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4379]], label [[ULX_ATOMIC_EXIT4381:%.*]], label [[ULX_ATOMIC_CONT4382:%.*]]
+// CHECK: ulx.atomic.cont4382:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4380]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4381]]
+// CHECK: ulx.atomic.exit4381:
+// CHECK-NEXT: [[TMP2196:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2197:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2196]], ptr [[ULX_ATOMIC_EXPECTED_PTR4383]], align 8
+// CHECK-NEXT: store i64 [[TMP2197]], ptr [[ULX_ATOMIC_DESIRED_PTR4384]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4386:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4383]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4387:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4384]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4388:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4386]], i64 [[ULX_CMPXCHG_DESIRED4387]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4389:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4388]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4389]], ptr [[ULX_ATOMIC_EXPECTED_PTR4385]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4390:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4388]], 1
+// CHECK-NEXT: [[TMP2198:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4390]] to i64
+// CHECK-NEXT: store i64 [[TMP2198]], ptr [[ULR]], align 8
+// CHECK-NEXT: [[TMP2199:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2200:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2199]], ptr [[ULX_ATOMIC_EXPECTED_PTR4391]], align 8
+// CHECK-NEXT: store i64 [[TMP2200]], ptr [[ULX_ATOMIC_DESIRED_PTR4392]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4394:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4391]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4395:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4392]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4396:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4394]], i64 [[ULX_CMPXCHG_DESIRED4395]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4397:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4396]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4397]], ptr [[ULX_ATOMIC_EXPECTED_PTR4393]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4398:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4396]], 1
+// CHECK-NEXT: [[TMP2201:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4398]] to i64
+// CHECK-NEXT: store i64 [[TMP2201]], ptr [[ULR]], align 8
+// CHECK-NEXT: [[TMP2202:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2203:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2202]], ptr [[ULX_ATOMIC_EXPECTED_PTR4399]], align 8
+// CHECK-NEXT: store i64 [[TMP2203]], ptr [[ULX_ATOMIC_DESIRED_PTR4400]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4402:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4399]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4403:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4400]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4404:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4402]], i64 [[ULX_CMPXCHG_DESIRED4403]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4405:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4404]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4405]], ptr [[ULX_ATOMIC_EXPECTED_PTR4401]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4406:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4404]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4407:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4401]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4406]], label [[ULX_ATOMIC_EXIT4408:%.*]], label [[ULX_ATOMIC_CONT4409:%.*]]
+// CHECK: ulx.atomic.cont4409:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4407]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4408]]
+// CHECK: ulx.atomic.exit4408:
+// CHECK-NEXT: [[TMP2204:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4406]] to i64
+// CHECK-NEXT: store i64 [[TMP2204]], ptr [[ULR]], align 8
+// CHECK-NEXT: [[TMP2205:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2206:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2205]], ptr [[ULX_ATOMIC_EXPECTED_PTR4410]], align 8
+// CHECK-NEXT: store i64 [[TMP2206]], ptr [[ULX_ATOMIC_DESIRED_PTR4411]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4413:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4410]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4414:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4411]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4415:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4413]], i64 [[ULX_CMPXCHG_DESIRED4414]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4416:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4415]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4416]], ptr [[ULX_ATOMIC_EXPECTED_PTR4412]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4417:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4415]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4418:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4412]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4417]], label [[ULX_ATOMIC_EXIT4419:%.*]], label [[ULX_ATOMIC_CONT4420:%.*]]
+// CHECK: ulx.atomic.cont4420:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4418]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4419]]
+// CHECK: ulx.atomic.exit4419:
+// CHECK-NEXT: [[TMP2207:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4417]] to i64
+// CHECK-NEXT: store i64 [[TMP2207]], ptr [[ULR]], align 8
+// CHECK-NEXT: [[TMP2208:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2209:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2208]] release, align 8
+// CHECK-NEXT: store i64 [[TMP2209]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2210:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2211:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2210]] release, align 8
+// CHECK-NEXT: store i64 [[TMP2211]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2212:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2213:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2212]] release, align 8
+// CHECK-NEXT: store i64 [[TMP2213]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2214:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2215:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2214]] release, align 8
+// CHECK-NEXT: store i64 [[TMP2215]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2216:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2217:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2216]], ptr [[ULX_ATOMIC_EXPECTED_PTR4421]], align 8
+// CHECK-NEXT: store i64 [[TMP2217]], ptr [[ULX_ATOMIC_DESIRED_PTR4422]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4424:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4421]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4425:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4422]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4426:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4424]], i64 [[ULX_CMPXCHG_DESIRED4425]] release monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4427:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4426]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4427]], ptr [[ULX_ATOMIC_EXPECTED_PTR4423]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4428:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4426]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4429:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4423]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4429]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2218:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2219:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2218]], ptr [[ULX_ATOMIC_EXPECTED_PTR4430]], align 8
+// CHECK-NEXT: store i64 [[TMP2219]], ptr [[ULX_ATOMIC_DESIRED_PTR4431]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4433:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4430]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4434:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4431]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4435:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4433]], i64 [[ULX_CMPXCHG_DESIRED4434]] release monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4436:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4435]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4436]], ptr [[ULX_ATOMIC_EXPECTED_PTR4432]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4437:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4435]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4438:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4432]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4438]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2220:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2221:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2220]] release, align 8
+// CHECK-NEXT: [[TMP2222:%.*]] = icmp ugt i64 [[TMP2221]], [[TMP2220]]
+// CHECK-NEXT: [[TMP2223:%.*]] = select i1 [[TMP2222]], i64 [[TMP2220]], i64 [[TMP2221]]
+// CHECK-NEXT: store i64 [[TMP2223]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2224:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2225:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2224]] release, align 8
+// CHECK-NEXT: [[TMP2226:%.*]] = icmp ult i64 [[TMP2225]], [[TMP2224]]
+// CHECK-NEXT: [[TMP2227:%.*]] = select i1 [[TMP2226]], i64 [[TMP2224]], i64 [[TMP2225]]
+// CHECK-NEXT: store i64 [[TMP2227]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2228:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2229:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2228]] release, align 8
+// CHECK-NEXT: [[TMP2230:%.*]] = icmp ult i64 [[TMP2229]], [[TMP2228]]
+// CHECK-NEXT: [[TMP2231:%.*]] = select i1 [[TMP2230]], i64 [[TMP2228]], i64 [[TMP2229]]
+// CHECK-NEXT: store i64 [[TMP2231]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2232:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2233:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2232]] release, align 8
+// CHECK-NEXT: [[TMP2234:%.*]] = icmp ugt i64 [[TMP2233]], [[TMP2232]]
+// CHECK-NEXT: [[TMP2235:%.*]] = select i1 [[TMP2234]], i64 [[TMP2232]], i64 [[TMP2233]]
+// CHECK-NEXT: store i64 [[TMP2235]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2236:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2237:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2236]], ptr [[ULX_ATOMIC_EXPECTED_PTR4439]], align 8
+// CHECK-NEXT: store i64 [[TMP2237]], ptr [[ULX_ATOMIC_DESIRED_PTR4440]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4442:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4439]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4443:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4440]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4444:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4442]], i64 [[ULX_CMPXCHG_DESIRED4443]] release monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4445:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4444]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4445]], ptr [[ULX_ATOMIC_EXPECTED_PTR4441]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4446:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4444]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4447:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4441]], align 8
+// CHECK-NEXT: [[ULX_CAPTURE_CAPTURED4448:%.*]] = select i1 [[ULX_CMPXCHG_SUCCESS4446]], i64 [[TMP2236]], i64 [[ULX_CAPTURE_ACTUAL4447]]
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_CAPTURED4448]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2238:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2239:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2238]], ptr [[ULX_ATOMIC_EXPECTED_PTR4449]], align 8
+// CHECK-NEXT: store i64 [[TMP2239]], ptr [[ULX_ATOMIC_DESIRED_PTR4450]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4452:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4449]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4453:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4450]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4454:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4452]], i64 [[ULX_CMPXCHG_DESIRED4453]] release monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4455:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4454]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4455]], ptr [[ULX_ATOMIC_EXPECTED_PTR4451]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4456:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4454]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4457:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4451]], align 8
+// CHECK-NEXT: [[ULX_CAPTURE_CAPTURED4458:%.*]] = select i1 [[ULX_CMPXCHG_SUCCESS4456]], i64 [[TMP2238]], i64 [[ULX_CAPTURE_ACTUAL4457]]
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_CAPTURED4458]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2240:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2241:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2240]], ptr [[ULX_ATOMIC_EXPECTED_PTR4459]], align 8
+// CHECK-NEXT: store i64 [[TMP2241]], ptr [[ULX_ATOMIC_DESIRED_PTR4460]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4462:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4459]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4463:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4460]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4464:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4462]], i64 [[ULX_CMPXCHG_DESIRED4463]] release monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4465:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4464]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4465]], ptr [[ULX_ATOMIC_EXPECTED_PTR4461]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4466:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4464]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4467:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4461]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4466]], label [[ULX_ATOMIC_EXIT4468:%.*]], label [[ULX_ATOMIC_CONT4469:%.*]]
+// CHECK: ulx.atomic.cont4469:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4467]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4468]]
+// CHECK: ulx.atomic.exit4468:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2242:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2243:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2242]], ptr [[ULX_ATOMIC_EXPECTED_PTR4470]], align 8
+// CHECK-NEXT: store i64 [[TMP2243]], ptr [[ULX_ATOMIC_DESIRED_PTR4471]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4473:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4470]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4474:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4471]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4475:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4473]], i64 [[ULX_CMPXCHG_DESIRED4474]] release monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4476:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4475]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4476]], ptr [[ULX_ATOMIC_EXPECTED_PTR4472]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4477:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4475]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4478:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4472]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4477]], label [[ULX_ATOMIC_EXIT4479:%.*]], label [[ULX_ATOMIC_CONT4480:%.*]]
+// CHECK: ulx.atomic.cont4480:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4478]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4479]]
+// CHECK: ulx.atomic.exit4479:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2244:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2245:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2244]], ptr [[ULX_ATOMIC_EXPECTED_PTR4481]], align 8
+// CHECK-NEXT: store i64 [[TMP2245]], ptr [[ULX_ATOMIC_DESIRED_PTR4482]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4484:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4481]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4485:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4482]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4486:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4484]], i64 [[ULX_CMPXCHG_DESIRED4485]] release monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4487:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4486]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4487]], ptr [[ULX_ATOMIC_EXPECTED_PTR4483]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4488:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4486]], 1
+// CHECK-NEXT: [[TMP2246:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4488]] to i64
+// CHECK-NEXT: store i64 [[TMP2246]], ptr [[ULR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2247:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2248:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2247]], ptr [[ULX_ATOMIC_EXPECTED_PTR4489]], align 8
+// CHECK-NEXT: store i64 [[TMP2248]], ptr [[ULX_ATOMIC_DESIRED_PTR4490]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4492:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4489]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4493:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4490]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4494:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4492]], i64 [[ULX_CMPXCHG_DESIRED4493]] release monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4495:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4494]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4495]], ptr [[ULX_ATOMIC_EXPECTED_PTR4491]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4496:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4494]], 1
+// CHECK-NEXT: [[TMP2249:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4496]] to i64
+// CHECK-NEXT: store i64 [[TMP2249]], ptr [[ULR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2250:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2251:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2250]], ptr [[ULX_ATOMIC_EXPECTED_PTR4497]], align 8
+// CHECK-NEXT: store i64 [[TMP2251]], ptr [[ULX_ATOMIC_DESIRED_PTR4498]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4500:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4497]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4501:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4498]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4502:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4500]], i64 [[ULX_CMPXCHG_DESIRED4501]] release monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4503:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4502]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4503]], ptr [[ULX_ATOMIC_EXPECTED_PTR4499]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4504:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4502]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4505:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4499]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4504]], label [[ULX_ATOMIC_EXIT4506:%.*]], label [[ULX_ATOMIC_CONT4507:%.*]]
+// CHECK: ulx.atomic.cont4507:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4505]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4506]]
+// CHECK: ulx.atomic.exit4506:
+// CHECK-NEXT: [[TMP2252:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4504]] to i64
+// CHECK-NEXT: store i64 [[TMP2252]], ptr [[ULR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2253:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2254:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2253]], ptr [[ULX_ATOMIC_EXPECTED_PTR4508]], align 8
+// CHECK-NEXT: store i64 [[TMP2254]], ptr [[ULX_ATOMIC_DESIRED_PTR4509]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4511:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4508]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4512:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4509]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4513:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4511]], i64 [[ULX_CMPXCHG_DESIRED4512]] release monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4514:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4513]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4514]], ptr [[ULX_ATOMIC_EXPECTED_PTR4510]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4515:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4513]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4516:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4510]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4515]], label [[ULX_ATOMIC_EXIT4517:%.*]], label [[ULX_ATOMIC_CONT4518:%.*]]
+// CHECK: ulx.atomic.cont4518:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4516]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4517]]
+// CHECK: ulx.atomic.exit4517:
+// CHECK-NEXT: [[TMP2255:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4515]] to i64
+// CHECK-NEXT: store i64 [[TMP2255]], ptr [[ULR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2256:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2257:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2256]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP2257]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2258:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2259:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2258]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP2259]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2260:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2261:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2260]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP2261]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2262:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2263:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2262]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP2263]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2264:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2265:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2264]], ptr [[ULX_ATOMIC_EXPECTED_PTR4519]], align 8
+// CHECK-NEXT: store i64 [[TMP2265]], ptr [[ULX_ATOMIC_DESIRED_PTR4520]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4522:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4519]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4523:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4520]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4524:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4522]], i64 [[ULX_CMPXCHG_DESIRED4523]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4525:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4524]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4525]], ptr [[ULX_ATOMIC_EXPECTED_PTR4521]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4526:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4524]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4527:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4521]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4527]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2266:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2267:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2266]], ptr [[ULX_ATOMIC_EXPECTED_PTR4528]], align 8
+// CHECK-NEXT: store i64 [[TMP2267]], ptr [[ULX_ATOMIC_DESIRED_PTR4529]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4531:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4528]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4532:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4529]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4533:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4531]], i64 [[ULX_CMPXCHG_DESIRED4532]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4534:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4533]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4534]], ptr [[ULX_ATOMIC_EXPECTED_PTR4530]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4535:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4533]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4536:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4530]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4536]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2268:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2269:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2268]] seq_cst, align 8
+// CHECK-NEXT: [[TMP2270:%.*]] = icmp ugt i64 [[TMP2269]], [[TMP2268]]
+// CHECK-NEXT: [[TMP2271:%.*]] = select i1 [[TMP2270]], i64 [[TMP2268]], i64 [[TMP2269]]
+// CHECK-NEXT: store i64 [[TMP2271]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2272:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2273:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2272]] seq_cst, align 8
+// CHECK-NEXT: [[TMP2274:%.*]] = icmp ult i64 [[TMP2273]], [[TMP2272]]
+// CHECK-NEXT: [[TMP2275:%.*]] = select i1 [[TMP2274]], i64 [[TMP2272]], i64 [[TMP2273]]
+// CHECK-NEXT: store i64 [[TMP2275]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2276:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2277:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP2276]] seq_cst, align 8
+// CHECK-NEXT: [[TMP2278:%.*]] = icmp ult i64 [[TMP2277]], [[TMP2276]]
+// CHECK-NEXT: [[TMP2279:%.*]] = select i1 [[TMP2278]], i64 [[TMP2276]], i64 [[TMP2277]]
+// CHECK-NEXT: store i64 [[TMP2279]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2280:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2281:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP2280]] seq_cst, align 8
+// CHECK-NEXT: [[TMP2282:%.*]] = icmp ugt i64 [[TMP2281]], [[TMP2280]]
+// CHECK-NEXT: [[TMP2283:%.*]] = select i1 [[TMP2282]], i64 [[TMP2280]], i64 [[TMP2281]]
+// CHECK-NEXT: store i64 [[TMP2283]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2284:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2285:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2284]], ptr [[ULX_ATOMIC_EXPECTED_PTR4537]], align 8
+// CHECK-NEXT: store i64 [[TMP2285]], ptr [[ULX_ATOMIC_DESIRED_PTR4538]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4540:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4537]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4541:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4538]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4542:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4540]], i64 [[ULX_CMPXCHG_DESIRED4541]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4543:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4542]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4543]], ptr [[ULX_ATOMIC_EXPECTED_PTR4539]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4544:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4542]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4545:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4539]], align 8
+// CHECK-NEXT: [[ULX_CAPTURE_CAPTURED4546:%.*]] = select i1 [[ULX_CMPXCHG_SUCCESS4544]], i64 [[TMP2284]], i64 [[ULX_CAPTURE_ACTUAL4545]]
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_CAPTURED4546]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2286:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2287:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2286]], ptr [[ULX_ATOMIC_EXPECTED_PTR4547]], align 8
+// CHECK-NEXT: store i64 [[TMP2287]], ptr [[ULX_ATOMIC_DESIRED_PTR4548]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4550:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4547]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4551:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4548]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4552:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4550]], i64 [[ULX_CMPXCHG_DESIRED4551]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4553:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4552]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4553]], ptr [[ULX_ATOMIC_EXPECTED_PTR4549]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4554:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4552]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4555:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4549]], align 8
+// CHECK-NEXT: [[ULX_CAPTURE_CAPTURED4556:%.*]] = select i1 [[ULX_CMPXCHG_SUCCESS4554]], i64 [[TMP2286]], i64 [[ULX_CAPTURE_ACTUAL4555]]
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_CAPTURED4556]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2288:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2289:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2288]], ptr [[ULX_ATOMIC_EXPECTED_PTR4557]], align 8
+// CHECK-NEXT: store i64 [[TMP2289]], ptr [[ULX_ATOMIC_DESIRED_PTR4558]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4560:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4557]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4561:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4558]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4562:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4560]], i64 [[ULX_CMPXCHG_DESIRED4561]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4563:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4562]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4563]], ptr [[ULX_ATOMIC_EXPECTED_PTR4559]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4564:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4562]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4565:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4559]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4564]], label [[ULX_ATOMIC_EXIT4566:%.*]], label [[ULX_ATOMIC_CONT4567:%.*]]
+// CHECK: ulx.atomic.cont4567:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4565]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4566]]
+// CHECK: ulx.atomic.exit4566:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2290:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2291:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2290]], ptr [[ULX_ATOMIC_EXPECTED_PTR4568]], align 8
+// CHECK-NEXT: store i64 [[TMP2291]], ptr [[ULX_ATOMIC_DESIRED_PTR4569]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4571:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4568]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4572:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4569]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4573:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4571]], i64 [[ULX_CMPXCHG_DESIRED4572]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4574:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4573]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4574]], ptr [[ULX_ATOMIC_EXPECTED_PTR4570]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4575:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4573]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4576:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4570]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4575]], label [[ULX_ATOMIC_EXIT4577:%.*]], label [[ULX_ATOMIC_CONT4578:%.*]]
+// CHECK: ulx.atomic.cont4578:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4576]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4577]]
+// CHECK: ulx.atomic.exit4577:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2292:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2293:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2292]], ptr [[ULX_ATOMIC_EXPECTED_PTR4579]], align 8
+// CHECK-NEXT: store i64 [[TMP2293]], ptr [[ULX_ATOMIC_DESIRED_PTR4580]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4582:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4579]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4583:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4580]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4584:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4582]], i64 [[ULX_CMPXCHG_DESIRED4583]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4585:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4584]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4585]], ptr [[ULX_ATOMIC_EXPECTED_PTR4581]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4586:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4584]], 1
+// CHECK-NEXT: [[TMP2294:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4586]] to i64
+// CHECK-NEXT: store i64 [[TMP2294]], ptr [[ULR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2295:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2296:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2295]], ptr [[ULX_ATOMIC_EXPECTED_PTR4587]], align 8
+// CHECK-NEXT: store i64 [[TMP2296]], ptr [[ULX_ATOMIC_DESIRED_PTR4588]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4590:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4587]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4591:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4588]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4592:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4590]], i64 [[ULX_CMPXCHG_DESIRED4591]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4593:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4592]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4593]], ptr [[ULX_ATOMIC_EXPECTED_PTR4589]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4594:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4592]], 1
+// CHECK-NEXT: [[TMP2297:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4594]] to i64
+// CHECK-NEXT: store i64 [[TMP2297]], ptr [[ULR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2298:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2299:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2298]], ptr [[ULX_ATOMIC_EXPECTED_PTR4595]], align 8
+// CHECK-NEXT: store i64 [[TMP2299]], ptr [[ULX_ATOMIC_DESIRED_PTR4596]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4598:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4595]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4599:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4596]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4600:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4598]], i64 [[ULX_CMPXCHG_DESIRED4599]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4601:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4600]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4601]], ptr [[ULX_ATOMIC_EXPECTED_PTR4597]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4602:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4600]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4603:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4597]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4602]], label [[ULX_ATOMIC_EXIT4604:%.*]], label [[ULX_ATOMIC_CONT4605:%.*]]
+// CHECK: ulx.atomic.cont4605:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4603]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4604]]
+// CHECK: ulx.atomic.exit4604:
+// CHECK-NEXT: [[TMP2300:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4602]] to i64
+// CHECK-NEXT: store i64 [[TMP2300]], ptr [[ULR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2301:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP2302:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP2301]], ptr [[ULX_ATOMIC_EXPECTED_PTR4606]], align 8
+// CHECK-NEXT: store i64 [[TMP2302]], ptr [[ULX_ATOMIC_DESIRED_PTR4607]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED4609:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4606]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED4610:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR4607]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR4611:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED4609]], i64 [[ULX_CMPXCHG_DESIRED4610]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV4612:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4611]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV4612]], ptr [[ULX_ATOMIC_EXPECTED_PTR4608]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS4613:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR4611]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL4614:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4608]], align 8
+// CHECK-NEXT: br i1 [[ULX_CMPXCHG_SUCCESS4613]], label [[ULX_ATOMIC_EXIT4615:%.*]], label [[ULX_ATOMIC_CONT4616:%.*]]
+// CHECK: ulx.atomic.cont4616:
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL4614]], ptr [[ULV]], align 8
+// CHECK-NEXT: br label [[ULX_ATOMIC_EXIT4615]]
+// CHECK: ulx.atomic.exit4615:
+// CHECK-NEXT: [[TMP2303:%.*]] = zext i1 [[ULX_CMPXCHG_SUCCESS4613]] to i64
+// CHECK-NEXT: store i64 [[TMP2303]], ptr [[ULR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2304:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2305:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2304]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2305]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2306:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2307:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2306]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2307]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2308:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2309:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2308]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2309]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2310:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2311:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2310]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2311]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2312:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2313:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2312]], ptr [[LLX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: store i64 [[TMP2313]], ptr [[LLX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED]], i64 [[LLX_CMPXCHG_DESIRED]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV]], ptr [[LLX_ATOMIC_EXPECTED_PTR4617]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4617]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2314:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2315:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2314]], ptr [[LLX_ATOMIC_EXPECTED_PTR4618]], align 8
+// CHECK-NEXT: store i64 [[TMP2315]], ptr [[LLX_ATOMIC_DESIRED_PTR4619]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4621:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4618]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4622:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4619]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4623:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4621]], i64 [[LLX_CMPXCHG_DESIRED4622]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4624:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4623]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4624]], ptr [[LLX_ATOMIC_EXPECTED_PTR4620]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4625:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4623]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4626:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4620]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4626]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2316:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2317:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2316]] monotonic, align 8
+// CHECK-NEXT: [[TMP2318:%.*]] = icmp sgt i64 [[TMP2317]], [[TMP2316]]
+// CHECK-NEXT: [[TMP2319:%.*]] = select i1 [[TMP2318]], i64 [[TMP2316]], i64 [[TMP2317]]
+// CHECK-NEXT: store i64 [[TMP2319]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2320:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2321:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2320]] monotonic, align 8
+// CHECK-NEXT: [[TMP2322:%.*]] = icmp slt i64 [[TMP2321]], [[TMP2320]]
+// CHECK-NEXT: [[TMP2323:%.*]] = select i1 [[TMP2322]], i64 [[TMP2320]], i64 [[TMP2321]]
+// CHECK-NEXT: store i64 [[TMP2323]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2324:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2325:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2324]] monotonic, align 8
+// CHECK-NEXT: [[TMP2326:%.*]] = icmp slt i64 [[TMP2325]], [[TMP2324]]
+// CHECK-NEXT: [[TMP2327:%.*]] = select i1 [[TMP2326]], i64 [[TMP2324]], i64 [[TMP2325]]
+// CHECK-NEXT: store i64 [[TMP2327]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2328:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2329:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2328]] monotonic, align 8
+// CHECK-NEXT: [[TMP2330:%.*]] = icmp sgt i64 [[TMP2329]], [[TMP2328]]
+// CHECK-NEXT: [[TMP2331:%.*]] = select i1 [[TMP2330]], i64 [[TMP2328]], i64 [[TMP2329]]
+// CHECK-NEXT: store i64 [[TMP2331]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2332:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2333:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2332]], ptr [[LLX_ATOMIC_EXPECTED_PTR4627]], align 8
+// CHECK-NEXT: store i64 [[TMP2333]], ptr [[LLX_ATOMIC_DESIRED_PTR4628]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4630:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4627]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4631:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4628]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4632:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4630]], i64 [[LLX_CMPXCHG_DESIRED4631]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4633:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4632]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4633]], ptr [[LLX_ATOMIC_EXPECTED_PTR4629]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4634:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4632]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4635:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4629]], align 8
+// CHECK-NEXT: [[LLX_CAPTURE_CAPTURED:%.*]] = select i1 [[LLX_CMPXCHG_SUCCESS4634]], i64 [[TMP2332]], i64 [[LLX_CAPTURE_ACTUAL4635]]
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_CAPTURED]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2334:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2335:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2334]], ptr [[LLX_ATOMIC_EXPECTED_PTR4636]], align 8
+// CHECK-NEXT: store i64 [[TMP2335]], ptr [[LLX_ATOMIC_DESIRED_PTR4637]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4639:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4636]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4640:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4637]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4641:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4639]], i64 [[LLX_CMPXCHG_DESIRED4640]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4642:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4641]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4642]], ptr [[LLX_ATOMIC_EXPECTED_PTR4638]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4643:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4641]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4644:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4638]], align 8
+// CHECK-NEXT: [[LLX_CAPTURE_CAPTURED4645:%.*]] = select i1 [[LLX_CMPXCHG_SUCCESS4643]], i64 [[TMP2334]], i64 [[LLX_CAPTURE_ACTUAL4644]]
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_CAPTURED4645]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2336:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2337:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2336]], ptr [[LLX_ATOMIC_EXPECTED_PTR4646]], align 8
+// CHECK-NEXT: store i64 [[TMP2337]], ptr [[LLX_ATOMIC_DESIRED_PTR4647]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4649:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4646]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4650:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4647]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4651:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4649]], i64 [[LLX_CMPXCHG_DESIRED4650]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4652:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4651]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4652]], ptr [[LLX_ATOMIC_EXPECTED_PTR4648]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4653:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4651]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4654:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4648]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS4653]], label [[LLX_ATOMIC_EXIT:%.*]], label [[LLX_ATOMIC_CONT:%.*]]
// CHECK: llx.atomic.cont:
-// CHECK-NEXT: store i64 [[TMP3791]], ptr [[LLV]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4654]], ptr [[LLV]], align 8
// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT]]
// CHECK: llx.atomic.exit:
-// CHECK-NEXT: [[TMP3793:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3794:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3795:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3793]], i64 [[TMP3794]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3796:%.*]] = extractvalue { i64, i1 } [[TMP3795]], 0
-// CHECK-NEXT: [[TMP3797:%.*]] = extractvalue { i64, i1 } [[TMP3795]], 1
-// CHECK-NEXT: br i1 [[TMP3797]], label [[LLX_ATOMIC_EXIT369:%.*]], label [[LLX_ATOMIC_CONT370:%.*]]
-// CHECK: llx.atomic.cont370:
-// CHECK-NEXT: store i64 [[TMP3796]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT369]]
-// CHECK: llx.atomic.exit369:
-// CHECK-NEXT: [[TMP3798:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3799:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3800:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3798]], i64 [[TMP3799]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3801:%.*]] = extractvalue { i64, i1 } [[TMP3800]], 1
-// CHECK-NEXT: [[TMP3802:%.*]] = sext i1 [[TMP3801]] to i64
-// CHECK-NEXT: store i64 [[TMP3802]], ptr [[LLR]], align 8
-// CHECK-NEXT: [[TMP3803:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3804:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3805:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3803]], i64 [[TMP3804]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3806:%.*]] = extractvalue { i64, i1 } [[TMP3805]], 1
-// CHECK-NEXT: [[TMP3807:%.*]] = sext i1 [[TMP3806]] to i64
-// CHECK-NEXT: store i64 [[TMP3807]], ptr [[LLR]], align 8
-// CHECK-NEXT: [[TMP3808:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3809:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3810:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3808]], i64 [[TMP3809]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3811:%.*]] = extractvalue { i64, i1 } [[TMP3810]], 0
-// CHECK-NEXT: [[TMP3812:%.*]] = extractvalue { i64, i1 } [[TMP3810]], 1
-// CHECK-NEXT: br i1 [[TMP3812]], label [[LLX_ATOMIC_EXIT371:%.*]], label [[LLX_ATOMIC_CONT372:%.*]]
-// CHECK: llx.atomic.cont372:
-// CHECK-NEXT: store i64 [[TMP3811]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT371]]
-// CHECK: llx.atomic.exit371:
-// CHECK-NEXT: [[TMP3813:%.*]] = extractvalue { i64, i1 } [[TMP3810]], 1
-// CHECK-NEXT: [[TMP3814:%.*]] = sext i1 [[TMP3813]] to i64
-// CHECK-NEXT: store i64 [[TMP3814]], ptr [[LLR]], align 8
-// CHECK-NEXT: [[TMP3815:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3816:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3817:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3815]], i64 [[TMP3816]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3818:%.*]] = extractvalue { i64, i1 } [[TMP3817]], 0
-// CHECK-NEXT: [[TMP3819:%.*]] = extractvalue { i64, i1 } [[TMP3817]], 1
-// CHECK-NEXT: br i1 [[TMP3819]], label [[LLX_ATOMIC_EXIT373:%.*]], label [[LLX_ATOMIC_CONT374:%.*]]
-// CHECK: llx.atomic.cont374:
-// CHECK-NEXT: store i64 [[TMP3818]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT373]]
-// CHECK: llx.atomic.exit373:
-// CHECK-NEXT: [[TMP3820:%.*]] = extractvalue { i64, i1 } [[TMP3817]], 1
-// CHECK-NEXT: [[TMP3821:%.*]] = sext i1 [[TMP3820]] to i64
-// CHECK-NEXT: store i64 [[TMP3821]], ptr [[LLR]], align 8
-// CHECK-NEXT: [[TMP3822:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3823:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3822]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP3823]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3824:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3825:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3824]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP3825]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3826:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3827:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3826]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP3827]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3828:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3829:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3828]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP3829]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3830:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3831:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3832:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3830]], i64 [[TMP3831]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3833:%.*]] = extractvalue { i64, i1 } [[TMP3832]], 0
-// CHECK-NEXT: store i64 [[TMP3833]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3834:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3835:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3836:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3834]], i64 [[TMP3835]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3837:%.*]] = extractvalue { i64, i1 } [[TMP3836]], 0
-// CHECK-NEXT: store i64 [[TMP3837]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3838:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3839:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3838]] acq_rel, align 8
-// CHECK-NEXT: [[TMP3840:%.*]] = icmp sgt i64 [[TMP3839]], [[TMP3838]]
-// CHECK-NEXT: [[TMP3841:%.*]] = select i1 [[TMP3840]], i64 [[TMP3838]], i64 [[TMP3839]]
-// CHECK-NEXT: store i64 [[TMP3841]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3842:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3843:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3842]] acq_rel, align 8
-// CHECK-NEXT: [[TMP3844:%.*]] = icmp slt i64 [[TMP3843]], [[TMP3842]]
-// CHECK-NEXT: [[TMP3845:%.*]] = select i1 [[TMP3844]], i64 [[TMP3842]], i64 [[TMP3843]]
-// CHECK-NEXT: store i64 [[TMP3845]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3846:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3847:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3846]] acq_rel, align 8
-// CHECK-NEXT: [[TMP3848:%.*]] = icmp slt i64 [[TMP3847]], [[TMP3846]]
-// CHECK-NEXT: [[TMP3849:%.*]] = select i1 [[TMP3848]], i64 [[TMP3846]], i64 [[TMP3847]]
-// CHECK-NEXT: store i64 [[TMP3849]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3850:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3851:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3850]] acq_rel, align 8
-// CHECK-NEXT: [[TMP3852:%.*]] = icmp sgt i64 [[TMP3851]], [[TMP3850]]
-// CHECK-NEXT: [[TMP3853:%.*]] = select i1 [[TMP3852]], i64 [[TMP3850]], i64 [[TMP3851]]
-// CHECK-NEXT: store i64 [[TMP3853]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3854:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3855:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3856:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3854]], i64 [[TMP3855]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3857:%.*]] = extractvalue { i64, i1 } [[TMP3856]], 0
-// CHECK-NEXT: [[TMP3858:%.*]] = extractvalue { i64, i1 } [[TMP3856]], 1
-// CHECK-NEXT: [[TMP3859:%.*]] = select i1 [[TMP3858]], i64 [[TMP3854]], i64 [[TMP3857]]
-// CHECK-NEXT: store i64 [[TMP3859]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3860:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3861:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3862:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3860]], i64 [[TMP3861]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3863:%.*]] = extractvalue { i64, i1 } [[TMP3862]], 0
-// CHECK-NEXT: [[TMP3864:%.*]] = extractvalue { i64, i1 } [[TMP3862]], 1
-// CHECK-NEXT: [[TMP3865:%.*]] = select i1 [[TMP3864]], i64 [[TMP3860]], i64 [[TMP3863]]
-// CHECK-NEXT: store i64 [[TMP3865]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3866:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3867:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3868:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3866]], i64 [[TMP3867]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3869:%.*]] = extractvalue { i64, i1 } [[TMP3868]], 0
-// CHECK-NEXT: [[TMP3870:%.*]] = extractvalue { i64, i1 } [[TMP3868]], 1
-// CHECK-NEXT: br i1 [[TMP3870]], label [[LLX_ATOMIC_EXIT375:%.*]], label [[LLX_ATOMIC_CONT376:%.*]]
-// CHECK: llx.atomic.cont376:
-// CHECK-NEXT: store i64 [[TMP3869]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT375]]
-// CHECK: llx.atomic.exit375:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3871:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3872:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3873:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3871]], i64 [[TMP3872]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3874:%.*]] = extractvalue { i64, i1 } [[TMP3873]], 0
-// CHECK-NEXT: [[TMP3875:%.*]] = extractvalue { i64, i1 } [[TMP3873]], 1
-// CHECK-NEXT: br i1 [[TMP3875]], label [[LLX_ATOMIC_EXIT377:%.*]], label [[LLX_ATOMIC_CONT378:%.*]]
-// CHECK: llx.atomic.cont378:
-// CHECK-NEXT: store i64 [[TMP3874]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT377]]
-// CHECK: llx.atomic.exit377:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3876:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3877:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3878:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3876]], i64 [[TMP3877]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3879:%.*]] = extractvalue { i64, i1 } [[TMP3878]], 1
-// CHECK-NEXT: [[TMP3880:%.*]] = sext i1 [[TMP3879]] to i64
-// CHECK-NEXT: store i64 [[TMP3880]], ptr [[LLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3881:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3882:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3883:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3881]], i64 [[TMP3882]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3884:%.*]] = extractvalue { i64, i1 } [[TMP3883]], 1
-// CHECK-NEXT: [[TMP3885:%.*]] = sext i1 [[TMP3884]] to i64
-// CHECK-NEXT: store i64 [[TMP3885]], ptr [[LLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3886:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3887:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3888:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3886]], i64 [[TMP3887]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3889:%.*]] = extractvalue { i64, i1 } [[TMP3888]], 0
-// CHECK-NEXT: [[TMP3890:%.*]] = extractvalue { i64, i1 } [[TMP3888]], 1
-// CHECK-NEXT: br i1 [[TMP3890]], label [[LLX_ATOMIC_EXIT379:%.*]], label [[LLX_ATOMIC_CONT380:%.*]]
-// CHECK: llx.atomic.cont380:
-// CHECK-NEXT: store i64 [[TMP3889]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT379]]
-// CHECK: llx.atomic.exit379:
-// CHECK-NEXT: [[TMP3891:%.*]] = extractvalue { i64, i1 } [[TMP3888]], 1
-// CHECK-NEXT: [[TMP3892:%.*]] = sext i1 [[TMP3891]] to i64
-// CHECK-NEXT: store i64 [[TMP3892]], ptr [[LLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3893:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3894:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3895:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3893]], i64 [[TMP3894]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP3896:%.*]] = extractvalue { i64, i1 } [[TMP3895]], 0
-// CHECK-NEXT: [[TMP3897:%.*]] = extractvalue { i64, i1 } [[TMP3895]], 1
-// CHECK-NEXT: br i1 [[TMP3897]], label [[LLX_ATOMIC_EXIT381:%.*]], label [[LLX_ATOMIC_CONT382:%.*]]
-// CHECK: llx.atomic.cont382:
-// CHECK-NEXT: store i64 [[TMP3896]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT381]]
-// CHECK: llx.atomic.exit381:
-// CHECK-NEXT: [[TMP3898:%.*]] = extractvalue { i64, i1 } [[TMP3895]], 1
-// CHECK-NEXT: [[TMP3899:%.*]] = sext i1 [[TMP3898]] to i64
-// CHECK-NEXT: store i64 [[TMP3899]], ptr [[LLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP3900:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3901:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3900]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP3901]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3902:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3903:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3902]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP3903]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3904:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3905:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3904]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP3905]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3906:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3907:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3906]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP3907]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3908:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3909:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3910:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3908]], i64 [[TMP3909]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3911:%.*]] = extractvalue { i64, i1 } [[TMP3910]], 0
-// CHECK-NEXT: store i64 [[TMP3911]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3912:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3913:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3914:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3912]], i64 [[TMP3913]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3915:%.*]] = extractvalue { i64, i1 } [[TMP3914]], 0
-// CHECK-NEXT: store i64 [[TMP3915]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3916:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3917:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3916]] acquire, align 8
-// CHECK-NEXT: [[TMP3918:%.*]] = icmp sgt i64 [[TMP3917]], [[TMP3916]]
-// CHECK-NEXT: [[TMP3919:%.*]] = select i1 [[TMP3918]], i64 [[TMP3916]], i64 [[TMP3917]]
-// CHECK-NEXT: store i64 [[TMP3919]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3920:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3921:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3920]] acquire, align 8
-// CHECK-NEXT: [[TMP3922:%.*]] = icmp slt i64 [[TMP3921]], [[TMP3920]]
-// CHECK-NEXT: [[TMP3923:%.*]] = select i1 [[TMP3922]], i64 [[TMP3920]], i64 [[TMP3921]]
-// CHECK-NEXT: store i64 [[TMP3923]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3924:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3925:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3924]] acquire, align 8
-// CHECK-NEXT: [[TMP3926:%.*]] = icmp slt i64 [[TMP3925]], [[TMP3924]]
-// CHECK-NEXT: [[TMP3927:%.*]] = select i1 [[TMP3926]], i64 [[TMP3924]], i64 [[TMP3925]]
-// CHECK-NEXT: store i64 [[TMP3927]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3928:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3929:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3928]] acquire, align 8
-// CHECK-NEXT: [[TMP3930:%.*]] = icmp sgt i64 [[TMP3929]], [[TMP3928]]
-// CHECK-NEXT: [[TMP3931:%.*]] = select i1 [[TMP3930]], i64 [[TMP3928]], i64 [[TMP3929]]
-// CHECK-NEXT: store i64 [[TMP3931]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3932:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3933:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3934:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3932]], i64 [[TMP3933]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3935:%.*]] = extractvalue { i64, i1 } [[TMP3934]], 0
-// CHECK-NEXT: [[TMP3936:%.*]] = extractvalue { i64, i1 } [[TMP3934]], 1
-// CHECK-NEXT: [[TMP3937:%.*]] = select i1 [[TMP3936]], i64 [[TMP3932]], i64 [[TMP3935]]
-// CHECK-NEXT: store i64 [[TMP3937]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3938:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3939:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3940:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3938]], i64 [[TMP3939]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3941:%.*]] = extractvalue { i64, i1 } [[TMP3940]], 0
-// CHECK-NEXT: [[TMP3942:%.*]] = extractvalue { i64, i1 } [[TMP3940]], 1
-// CHECK-NEXT: [[TMP3943:%.*]] = select i1 [[TMP3942]], i64 [[TMP3938]], i64 [[TMP3941]]
-// CHECK-NEXT: store i64 [[TMP3943]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3944:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3945:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3946:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3944]], i64 [[TMP3945]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3947:%.*]] = extractvalue { i64, i1 } [[TMP3946]], 0
-// CHECK-NEXT: [[TMP3948:%.*]] = extractvalue { i64, i1 } [[TMP3946]], 1
-// CHECK-NEXT: br i1 [[TMP3948]], label [[LLX_ATOMIC_EXIT383:%.*]], label [[LLX_ATOMIC_CONT384:%.*]]
-// CHECK: llx.atomic.cont384:
-// CHECK-NEXT: store i64 [[TMP3947]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT383]]
-// CHECK: llx.atomic.exit383:
-// CHECK-NEXT: [[TMP3949:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3950:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3951:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3949]], i64 [[TMP3950]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3952:%.*]] = extractvalue { i64, i1 } [[TMP3951]], 0
-// CHECK-NEXT: [[TMP3953:%.*]] = extractvalue { i64, i1 } [[TMP3951]], 1
-// CHECK-NEXT: br i1 [[TMP3953]], label [[LLX_ATOMIC_EXIT385:%.*]], label [[LLX_ATOMIC_CONT386:%.*]]
-// CHECK: llx.atomic.cont386:
-// CHECK-NEXT: store i64 [[TMP3952]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT385]]
-// CHECK: llx.atomic.exit385:
-// CHECK-NEXT: [[TMP3954:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3955:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3956:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3954]], i64 [[TMP3955]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3957:%.*]] = extractvalue { i64, i1 } [[TMP3956]], 1
-// CHECK-NEXT: [[TMP3958:%.*]] = sext i1 [[TMP3957]] to i64
-// CHECK-NEXT: store i64 [[TMP3958]], ptr [[LLR]], align 8
-// CHECK-NEXT: [[TMP3959:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3960:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3961:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3959]], i64 [[TMP3960]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3962:%.*]] = extractvalue { i64, i1 } [[TMP3961]], 1
-// CHECK-NEXT: [[TMP3963:%.*]] = sext i1 [[TMP3962]] to i64
-// CHECK-NEXT: store i64 [[TMP3963]], ptr [[LLR]], align 8
-// CHECK-NEXT: [[TMP3964:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3965:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3966:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3964]], i64 [[TMP3965]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3967:%.*]] = extractvalue { i64, i1 } [[TMP3966]], 0
-// CHECK-NEXT: [[TMP3968:%.*]] = extractvalue { i64, i1 } [[TMP3966]], 1
-// CHECK-NEXT: br i1 [[TMP3968]], label [[LLX_ATOMIC_EXIT387:%.*]], label [[LLX_ATOMIC_CONT388:%.*]]
-// CHECK: llx.atomic.cont388:
-// CHECK-NEXT: store i64 [[TMP3967]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT387]]
-// CHECK: llx.atomic.exit387:
-// CHECK-NEXT: [[TMP3969:%.*]] = extractvalue { i64, i1 } [[TMP3966]], 1
-// CHECK-NEXT: [[TMP3970:%.*]] = sext i1 [[TMP3969]] to i64
-// CHECK-NEXT: store i64 [[TMP3970]], ptr [[LLR]], align 8
-// CHECK-NEXT: [[TMP3971:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3972:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3973:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3971]], i64 [[TMP3972]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP3974:%.*]] = extractvalue { i64, i1 } [[TMP3973]], 0
-// CHECK-NEXT: [[TMP3975:%.*]] = extractvalue { i64, i1 } [[TMP3973]], 1
-// CHECK-NEXT: br i1 [[TMP3975]], label [[LLX_ATOMIC_EXIT389:%.*]], label [[LLX_ATOMIC_CONT390:%.*]]
-// CHECK: llx.atomic.cont390:
-// CHECK-NEXT: store i64 [[TMP3974]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT389]]
-// CHECK: llx.atomic.exit389:
-// CHECK-NEXT: [[TMP3976:%.*]] = extractvalue { i64, i1 } [[TMP3973]], 1
-// CHECK-NEXT: [[TMP3977:%.*]] = sext i1 [[TMP3976]] to i64
-// CHECK-NEXT: store i64 [[TMP3977]], ptr [[LLR]], align 8
-// CHECK-NEXT: [[TMP3978:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3979:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3978]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3979]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3980:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3981:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3980]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3981]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3982:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3983:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3982]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3983]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3984:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3985:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3984]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP3985]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3986:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3987:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3988:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3986]], i64 [[TMP3987]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3989:%.*]] = extractvalue { i64, i1 } [[TMP3988]], 0
-// CHECK-NEXT: store i64 [[TMP3989]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3990:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3991:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP3992:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP3990]], i64 [[TMP3991]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP3993:%.*]] = extractvalue { i64, i1 } [[TMP3992]], 0
-// CHECK-NEXT: store i64 [[TMP3993]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3994:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3995:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP3994]] monotonic, align 8
-// CHECK-NEXT: [[TMP3996:%.*]] = icmp sgt i64 [[TMP3995]], [[TMP3994]]
-// CHECK-NEXT: [[TMP3997:%.*]] = select i1 [[TMP3996]], i64 [[TMP3994]], i64 [[TMP3995]]
-// CHECK-NEXT: store i64 [[TMP3997]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP3998:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP3999:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP3998]] monotonic, align 8
-// CHECK-NEXT: [[TMP4000:%.*]] = icmp slt i64 [[TMP3999]], [[TMP3998]]
-// CHECK-NEXT: [[TMP4001:%.*]] = select i1 [[TMP4000]], i64 [[TMP3998]], i64 [[TMP3999]]
-// CHECK-NEXT: store i64 [[TMP4001]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP4002:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4003:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4002]] monotonic, align 8
-// CHECK-NEXT: [[TMP4004:%.*]] = icmp slt i64 [[TMP4003]], [[TMP4002]]
-// CHECK-NEXT: [[TMP4005:%.*]] = select i1 [[TMP4004]], i64 [[TMP4002]], i64 [[TMP4003]]
-// CHECK-NEXT: store i64 [[TMP4005]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP4006:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4007:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4006]] monotonic, align 8
-// CHECK-NEXT: [[TMP4008:%.*]] = icmp sgt i64 [[TMP4007]], [[TMP4006]]
-// CHECK-NEXT: [[TMP4009:%.*]] = select i1 [[TMP4008]], i64 [[TMP4006]], i64 [[TMP4007]]
-// CHECK-NEXT: store i64 [[TMP4009]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP4010:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4011:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4012:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4010]], i64 [[TMP4011]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4013:%.*]] = extractvalue { i64, i1 } [[TMP4012]], 0
-// CHECK-NEXT: [[TMP4014:%.*]] = extractvalue { i64, i1 } [[TMP4012]], 1
-// CHECK-NEXT: [[TMP4015:%.*]] = select i1 [[TMP4014]], i64 [[TMP4010]], i64 [[TMP4013]]
-// CHECK-NEXT: store i64 [[TMP4015]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP4016:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4017:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4018:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4016]], i64 [[TMP4017]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4019:%.*]] = extractvalue { i64, i1 } [[TMP4018]], 0
-// CHECK-NEXT: [[TMP4020:%.*]] = extractvalue { i64, i1 } [[TMP4018]], 1
-// CHECK-NEXT: [[TMP4021:%.*]] = select i1 [[TMP4020]], i64 [[TMP4016]], i64 [[TMP4019]]
-// CHECK-NEXT: store i64 [[TMP4021]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP4022:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4023:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4024:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4022]], i64 [[TMP4023]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4025:%.*]] = extractvalue { i64, i1 } [[TMP4024]], 0
-// CHECK-NEXT: [[TMP4026:%.*]] = extractvalue { i64, i1 } [[TMP4024]], 1
-// CHECK-NEXT: br i1 [[TMP4026]], label [[LLX_ATOMIC_EXIT391:%.*]], label [[LLX_ATOMIC_CONT392:%.*]]
-// CHECK: llx.atomic.cont392:
-// CHECK-NEXT: store i64 [[TMP4025]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT391]]
-// CHECK: llx.atomic.exit391:
-// CHECK-NEXT: [[TMP4027:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4028:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4029:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4027]], i64 [[TMP4028]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4030:%.*]] = extractvalue { i64, i1 } [[TMP4029]], 0
-// CHECK-NEXT: [[TMP4031:%.*]] = extractvalue { i64, i1 } [[TMP4029]], 1
-// CHECK-NEXT: br i1 [[TMP4031]], label [[LLX_ATOMIC_EXIT393:%.*]], label [[LLX_ATOMIC_CONT394:%.*]]
-// CHECK: llx.atomic.cont394:
-// CHECK-NEXT: store i64 [[TMP4030]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT393]]
-// CHECK: llx.atomic.exit393:
-// CHECK-NEXT: [[TMP4032:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4033:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4034:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4032]], i64 [[TMP4033]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4035:%.*]] = extractvalue { i64, i1 } [[TMP4034]], 1
-// CHECK-NEXT: [[TMP4036:%.*]] = sext i1 [[TMP4035]] to i64
-// CHECK-NEXT: store i64 [[TMP4036]], ptr [[LLR]], align 8
-// CHECK-NEXT: [[TMP4037:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4038:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4039:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4037]], i64 [[TMP4038]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4040:%.*]] = extractvalue { i64, i1 } [[TMP4039]], 1
-// CHECK-NEXT: [[TMP4041:%.*]] = sext i1 [[TMP4040]] to i64
-// CHECK-NEXT: store i64 [[TMP4041]], ptr [[LLR]], align 8
-// CHECK-NEXT: [[TMP4042:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4043:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4044:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4042]], i64 [[TMP4043]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4045:%.*]] = extractvalue { i64, i1 } [[TMP4044]], 0
-// CHECK-NEXT: [[TMP4046:%.*]] = extractvalue { i64, i1 } [[TMP4044]], 1
-// CHECK-NEXT: br i1 [[TMP4046]], label [[LLX_ATOMIC_EXIT395:%.*]], label [[LLX_ATOMIC_CONT396:%.*]]
-// CHECK: llx.atomic.cont396:
-// CHECK-NEXT: store i64 [[TMP4045]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT395]]
-// CHECK: llx.atomic.exit395:
-// CHECK-NEXT: [[TMP4047:%.*]] = extractvalue { i64, i1 } [[TMP4044]], 1
-// CHECK-NEXT: [[TMP4048:%.*]] = sext i1 [[TMP4047]] to i64
-// CHECK-NEXT: store i64 [[TMP4048]], ptr [[LLR]], align 8
-// CHECK-NEXT: [[TMP4049:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4050:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4051:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4049]], i64 [[TMP4050]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4052:%.*]] = extractvalue { i64, i1 } [[TMP4051]], 0
-// CHECK-NEXT: [[TMP4053:%.*]] = extractvalue { i64, i1 } [[TMP4051]], 1
-// CHECK-NEXT: br i1 [[TMP4053]], label [[LLX_ATOMIC_EXIT397:%.*]], label [[LLX_ATOMIC_CONT398:%.*]]
-// CHECK: llx.atomic.cont398:
-// CHECK-NEXT: store i64 [[TMP4052]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT397]]
-// CHECK: llx.atomic.exit397:
-// CHECK-NEXT: [[TMP4054:%.*]] = extractvalue { i64, i1 } [[TMP4051]], 1
-// CHECK-NEXT: [[TMP4055:%.*]] = sext i1 [[TMP4054]] to i64
-// CHECK-NEXT: store i64 [[TMP4055]], ptr [[LLR]], align 8
-// CHECK-NEXT: [[TMP4056:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4057:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4056]] release, align 8
-// CHECK-NEXT: store i64 [[TMP4057]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4058:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4059:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4058]] release, align 8
-// CHECK-NEXT: store i64 [[TMP4059]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4060:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4061:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4060]] release, align 8
-// CHECK-NEXT: store i64 [[TMP4061]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4062:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4063:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4062]] release, align 8
-// CHECK-NEXT: store i64 [[TMP4063]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4064:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4065:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4066:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4064]], i64 [[TMP4065]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4067:%.*]] = extractvalue { i64, i1 } [[TMP4066]], 0
-// CHECK-NEXT: store i64 [[TMP4067]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4068:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4069:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4070:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4068]], i64 [[TMP4069]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4071:%.*]] = extractvalue { i64, i1 } [[TMP4070]], 0
-// CHECK-NEXT: store i64 [[TMP4071]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4072:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4073:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4072]] release, align 8
-// CHECK-NEXT: [[TMP4074:%.*]] = icmp sgt i64 [[TMP4073]], [[TMP4072]]
-// CHECK-NEXT: [[TMP4075:%.*]] = select i1 [[TMP4074]], i64 [[TMP4072]], i64 [[TMP4073]]
-// CHECK-NEXT: store i64 [[TMP4075]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4076:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4077:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4076]] release, align 8
-// CHECK-NEXT: [[TMP4078:%.*]] = icmp slt i64 [[TMP4077]], [[TMP4076]]
-// CHECK-NEXT: [[TMP4079:%.*]] = select i1 [[TMP4078]], i64 [[TMP4076]], i64 [[TMP4077]]
-// CHECK-NEXT: store i64 [[TMP4079]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4080:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4081:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4080]] release, align 8
-// CHECK-NEXT: [[TMP4082:%.*]] = icmp slt i64 [[TMP4081]], [[TMP4080]]
-// CHECK-NEXT: [[TMP4083:%.*]] = select i1 [[TMP4082]], i64 [[TMP4080]], i64 [[TMP4081]]
-// CHECK-NEXT: store i64 [[TMP4083]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4084:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4085:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4084]] release, align 8
-// CHECK-NEXT: [[TMP4086:%.*]] = icmp sgt i64 [[TMP4085]], [[TMP4084]]
-// CHECK-NEXT: [[TMP4087:%.*]] = select i1 [[TMP4086]], i64 [[TMP4084]], i64 [[TMP4085]]
-// CHECK-NEXT: store i64 [[TMP4087]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4088:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4089:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4090:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4088]], i64 [[TMP4089]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4091:%.*]] = extractvalue { i64, i1 } [[TMP4090]], 0
-// CHECK-NEXT: [[TMP4092:%.*]] = extractvalue { i64, i1 } [[TMP4090]], 1
-// CHECK-NEXT: [[TMP4093:%.*]] = select i1 [[TMP4092]], i64 [[TMP4088]], i64 [[TMP4091]]
-// CHECK-NEXT: store i64 [[TMP4093]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4094:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4095:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4096:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4094]], i64 [[TMP4095]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4097:%.*]] = extractvalue { i64, i1 } [[TMP4096]], 0
-// CHECK-NEXT: [[TMP4098:%.*]] = extractvalue { i64, i1 } [[TMP4096]], 1
-// CHECK-NEXT: [[TMP4099:%.*]] = select i1 [[TMP4098]], i64 [[TMP4094]], i64 [[TMP4097]]
-// CHECK-NEXT: store i64 [[TMP4099]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4100:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4101:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4102:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4100]], i64 [[TMP4101]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4103:%.*]] = extractvalue { i64, i1 } [[TMP4102]], 0
-// CHECK-NEXT: [[TMP4104:%.*]] = extractvalue { i64, i1 } [[TMP4102]], 1
-// CHECK-NEXT: br i1 [[TMP4104]], label [[LLX_ATOMIC_EXIT399:%.*]], label [[LLX_ATOMIC_CONT400:%.*]]
-// CHECK: llx.atomic.cont400:
-// CHECK-NEXT: store i64 [[TMP4103]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT399]]
-// CHECK: llx.atomic.exit399:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4105:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4106:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4107:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4105]], i64 [[TMP4106]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4108:%.*]] = extractvalue { i64, i1 } [[TMP4107]], 0
-// CHECK-NEXT: [[TMP4109:%.*]] = extractvalue { i64, i1 } [[TMP4107]], 1
-// CHECK-NEXT: br i1 [[TMP4109]], label [[LLX_ATOMIC_EXIT401:%.*]], label [[LLX_ATOMIC_CONT402:%.*]]
-// CHECK: llx.atomic.cont402:
-// CHECK-NEXT: store i64 [[TMP4108]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT401]]
-// CHECK: llx.atomic.exit401:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4110:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4111:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4112:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4110]], i64 [[TMP4111]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4113:%.*]] = extractvalue { i64, i1 } [[TMP4112]], 1
-// CHECK-NEXT: [[TMP4114:%.*]] = sext i1 [[TMP4113]] to i64
-// CHECK-NEXT: store i64 [[TMP4114]], ptr [[LLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4115:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4116:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4117:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4115]], i64 [[TMP4116]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4118:%.*]] = extractvalue { i64, i1 } [[TMP4117]], 1
-// CHECK-NEXT: [[TMP4119:%.*]] = sext i1 [[TMP4118]] to i64
-// CHECK-NEXT: store i64 [[TMP4119]], ptr [[LLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4120:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4121:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4122:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4120]], i64 [[TMP4121]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4123:%.*]] = extractvalue { i64, i1 } [[TMP4122]], 0
-// CHECK-NEXT: [[TMP4124:%.*]] = extractvalue { i64, i1 } [[TMP4122]], 1
-// CHECK-NEXT: br i1 [[TMP4124]], label [[LLX_ATOMIC_EXIT403:%.*]], label [[LLX_ATOMIC_CONT404:%.*]]
-// CHECK: llx.atomic.cont404:
-// CHECK-NEXT: store i64 [[TMP4123]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT403]]
-// CHECK: llx.atomic.exit403:
-// CHECK-NEXT: [[TMP4125:%.*]] = extractvalue { i64, i1 } [[TMP4122]], 1
-// CHECK-NEXT: [[TMP4126:%.*]] = sext i1 [[TMP4125]] to i64
-// CHECK-NEXT: store i64 [[TMP4126]], ptr [[LLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4127:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4128:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4129:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4127]], i64 [[TMP4128]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4130:%.*]] = extractvalue { i64, i1 } [[TMP4129]], 0
-// CHECK-NEXT: [[TMP4131:%.*]] = extractvalue { i64, i1 } [[TMP4129]], 1
-// CHECK-NEXT: br i1 [[TMP4131]], label [[LLX_ATOMIC_EXIT405:%.*]], label [[LLX_ATOMIC_CONT406:%.*]]
-// CHECK: llx.atomic.cont406:
-// CHECK-NEXT: store i64 [[TMP4130]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT405]]
-// CHECK: llx.atomic.exit405:
-// CHECK-NEXT: [[TMP4132:%.*]] = extractvalue { i64, i1 } [[TMP4129]], 1
-// CHECK-NEXT: [[TMP4133:%.*]] = sext i1 [[TMP4132]] to i64
-// CHECK-NEXT: store i64 [[TMP4133]], ptr [[LLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4134:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4135:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4134]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP4135]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4136:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4137:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4136]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP4137]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4138:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4139:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4138]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP4139]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4140:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4141:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4140]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP4141]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4142:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4143:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4144:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4142]], i64 [[TMP4143]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4145:%.*]] = extractvalue { i64, i1 } [[TMP4144]], 0
-// CHECK-NEXT: store i64 [[TMP4145]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4146:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4147:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4148:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4146]], i64 [[TMP4147]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4149:%.*]] = extractvalue { i64, i1 } [[TMP4148]], 0
-// CHECK-NEXT: store i64 [[TMP4149]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4150:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4151:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4150]] seq_cst, align 8
-// CHECK-NEXT: [[TMP4152:%.*]] = icmp sgt i64 [[TMP4151]], [[TMP4150]]
-// CHECK-NEXT: [[TMP4153:%.*]] = select i1 [[TMP4152]], i64 [[TMP4150]], i64 [[TMP4151]]
-// CHECK-NEXT: store i64 [[TMP4153]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4154:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4155:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4154]] seq_cst, align 8
-// CHECK-NEXT: [[TMP4156:%.*]] = icmp slt i64 [[TMP4155]], [[TMP4154]]
-// CHECK-NEXT: [[TMP4157:%.*]] = select i1 [[TMP4156]], i64 [[TMP4154]], i64 [[TMP4155]]
-// CHECK-NEXT: store i64 [[TMP4157]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4158:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4159:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP4158]] seq_cst, align 8
-// CHECK-NEXT: [[TMP4160:%.*]] = icmp slt i64 [[TMP4159]], [[TMP4158]]
-// CHECK-NEXT: [[TMP4161:%.*]] = select i1 [[TMP4160]], i64 [[TMP4158]], i64 [[TMP4159]]
-// CHECK-NEXT: store i64 [[TMP4161]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4162:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4163:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP4162]] seq_cst, align 8
-// CHECK-NEXT: [[TMP4164:%.*]] = icmp sgt i64 [[TMP4163]], [[TMP4162]]
-// CHECK-NEXT: [[TMP4165:%.*]] = select i1 [[TMP4164]], i64 [[TMP4162]], i64 [[TMP4163]]
-// CHECK-NEXT: store i64 [[TMP4165]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4166:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4167:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4168:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4166]], i64 [[TMP4167]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4169:%.*]] = extractvalue { i64, i1 } [[TMP4168]], 0
-// CHECK-NEXT: [[TMP4170:%.*]] = extractvalue { i64, i1 } [[TMP4168]], 1
-// CHECK-NEXT: [[TMP4171:%.*]] = select i1 [[TMP4170]], i64 [[TMP4166]], i64 [[TMP4169]]
-// CHECK-NEXT: store i64 [[TMP4171]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4172:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4173:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4174:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4172]], i64 [[TMP4173]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4175:%.*]] = extractvalue { i64, i1 } [[TMP4174]], 0
-// CHECK-NEXT: [[TMP4176:%.*]] = extractvalue { i64, i1 } [[TMP4174]], 1
-// CHECK-NEXT: [[TMP4177:%.*]] = select i1 [[TMP4176]], i64 [[TMP4172]], i64 [[TMP4175]]
-// CHECK-NEXT: store i64 [[TMP4177]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4178:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4179:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4180:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4178]], i64 [[TMP4179]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4181:%.*]] = extractvalue { i64, i1 } [[TMP4180]], 0
-// CHECK-NEXT: [[TMP4182:%.*]] = extractvalue { i64, i1 } [[TMP4180]], 1
-// CHECK-NEXT: br i1 [[TMP4182]], label [[LLX_ATOMIC_EXIT407:%.*]], label [[LLX_ATOMIC_CONT408:%.*]]
-// CHECK: llx.atomic.cont408:
-// CHECK-NEXT: store i64 [[TMP4181]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT407]]
-// CHECK: llx.atomic.exit407:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4183:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4184:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4185:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4183]], i64 [[TMP4184]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4186:%.*]] = extractvalue { i64, i1 } [[TMP4185]], 0
-// CHECK-NEXT: [[TMP4187:%.*]] = extractvalue { i64, i1 } [[TMP4185]], 1
-// CHECK-NEXT: br i1 [[TMP4187]], label [[LLX_ATOMIC_EXIT409:%.*]], label [[LLX_ATOMIC_CONT410:%.*]]
-// CHECK: llx.atomic.cont410:
-// CHECK-NEXT: store i64 [[TMP4186]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT409]]
-// CHECK: llx.atomic.exit409:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4188:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4189:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4190:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4188]], i64 [[TMP4189]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4191:%.*]] = extractvalue { i64, i1 } [[TMP4190]], 1
-// CHECK-NEXT: [[TMP4192:%.*]] = sext i1 [[TMP4191]] to i64
-// CHECK-NEXT: store i64 [[TMP4192]], ptr [[LLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4193:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4194:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4195:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4193]], i64 [[TMP4194]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4196:%.*]] = extractvalue { i64, i1 } [[TMP4195]], 1
-// CHECK-NEXT: [[TMP4197:%.*]] = sext i1 [[TMP4196]] to i64
-// CHECK-NEXT: store i64 [[TMP4197]], ptr [[LLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4198:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4199:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4200:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4198]], i64 [[TMP4199]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4201:%.*]] = extractvalue { i64, i1 } [[TMP4200]], 0
-// CHECK-NEXT: [[TMP4202:%.*]] = extractvalue { i64, i1 } [[TMP4200]], 1
-// CHECK-NEXT: br i1 [[TMP4202]], label [[LLX_ATOMIC_EXIT411:%.*]], label [[LLX_ATOMIC_CONT412:%.*]]
-// CHECK: llx.atomic.cont412:
-// CHECK-NEXT: store i64 [[TMP4201]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT411]]
-// CHECK: llx.atomic.exit411:
-// CHECK-NEXT: [[TMP4203:%.*]] = extractvalue { i64, i1 } [[TMP4200]], 1
-// CHECK-NEXT: [[TMP4204:%.*]] = sext i1 [[TMP4203]] to i64
-// CHECK-NEXT: store i64 [[TMP4204]], ptr [[LLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4205:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP4206:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP4207:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4205]], i64 [[TMP4206]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4208:%.*]] = extractvalue { i64, i1 } [[TMP4207]], 0
-// CHECK-NEXT: [[TMP4209:%.*]] = extractvalue { i64, i1 } [[TMP4207]], 1
-// CHECK-NEXT: br i1 [[TMP4209]], label [[LLX_ATOMIC_EXIT413:%.*]], label [[LLX_ATOMIC_CONT414:%.*]]
-// CHECK: llx.atomic.cont414:
-// CHECK-NEXT: store i64 [[TMP4208]], ptr [[LLV]], align 8
-// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT413]]
-// CHECK: llx.atomic.exit413:
-// CHECK-NEXT: [[TMP4210:%.*]] = extractvalue { i64, i1 } [[TMP4207]], 1
-// CHECK-NEXT: [[TMP4211:%.*]] = sext i1 [[TMP4210]] to i64
-// CHECK-NEXT: store i64 [[TMP4211]], ptr [[LLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4212:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4213:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4212]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP4213]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4214:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4215:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4214]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP4215]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4216:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4217:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4216]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP4217]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4218:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4219:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4218]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP4219]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4220:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4221:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4222:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4220]], i64 [[TMP4221]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4223:%.*]] = extractvalue { i64, i1 } [[TMP4222]], 0
-// CHECK-NEXT: store i64 [[TMP4223]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4224:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4225:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4226:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4224]], i64 [[TMP4225]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4227:%.*]] = extractvalue { i64, i1 } [[TMP4226]], 0
-// CHECK-NEXT: store i64 [[TMP4227]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4228:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4229:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4228]] monotonic, align 8
-// CHECK-NEXT: [[TMP4230:%.*]] = icmp ugt i64 [[TMP4229]], [[TMP4228]]
-// CHECK-NEXT: [[TMP4231:%.*]] = select i1 [[TMP4230]], i64 [[TMP4228]], i64 [[TMP4229]]
-// CHECK-NEXT: store i64 [[TMP4231]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4232:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4233:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4232]] monotonic, align 8
-// CHECK-NEXT: [[TMP4234:%.*]] = icmp ult i64 [[TMP4233]], [[TMP4232]]
-// CHECK-NEXT: [[TMP4235:%.*]] = select i1 [[TMP4234]], i64 [[TMP4232]], i64 [[TMP4233]]
-// CHECK-NEXT: store i64 [[TMP4235]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4236:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4237:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4236]] monotonic, align 8
-// CHECK-NEXT: [[TMP4238:%.*]] = icmp ult i64 [[TMP4237]], [[TMP4236]]
-// CHECK-NEXT: [[TMP4239:%.*]] = select i1 [[TMP4238]], i64 [[TMP4236]], i64 [[TMP4237]]
-// CHECK-NEXT: store i64 [[TMP4239]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4240:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4241:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4240]] monotonic, align 8
-// CHECK-NEXT: [[TMP4242:%.*]] = icmp ugt i64 [[TMP4241]], [[TMP4240]]
-// CHECK-NEXT: [[TMP4243:%.*]] = select i1 [[TMP4242]], i64 [[TMP4240]], i64 [[TMP4241]]
-// CHECK-NEXT: store i64 [[TMP4243]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4244:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4245:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4246:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4244]], i64 [[TMP4245]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4247:%.*]] = extractvalue { i64, i1 } [[TMP4246]], 0
-// CHECK-NEXT: [[TMP4248:%.*]] = extractvalue { i64, i1 } [[TMP4246]], 1
-// CHECK-NEXT: [[TMP4249:%.*]] = select i1 [[TMP4248]], i64 [[TMP4244]], i64 [[TMP4247]]
-// CHECK-NEXT: store i64 [[TMP4249]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4250:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4251:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4252:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4250]], i64 [[TMP4251]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4253:%.*]] = extractvalue { i64, i1 } [[TMP4252]], 0
-// CHECK-NEXT: [[TMP4254:%.*]] = extractvalue { i64, i1 } [[TMP4252]], 1
-// CHECK-NEXT: [[TMP4255:%.*]] = select i1 [[TMP4254]], i64 [[TMP4250]], i64 [[TMP4253]]
-// CHECK-NEXT: store i64 [[TMP4255]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4256:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4257:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4258:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4256]], i64 [[TMP4257]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4259:%.*]] = extractvalue { i64, i1 } [[TMP4258]], 0
-// CHECK-NEXT: [[TMP4260:%.*]] = extractvalue { i64, i1 } [[TMP4258]], 1
-// CHECK-NEXT: br i1 [[TMP4260]], label [[ULLX_ATOMIC_EXIT:%.*]], label [[ULLX_ATOMIC_CONT:%.*]]
+// CHECK-NEXT: [[TMP2338:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2339:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2338]], ptr [[LLX_ATOMIC_EXPECTED_PTR4655]], align 8
+// CHECK-NEXT: store i64 [[TMP2339]], ptr [[LLX_ATOMIC_DESIRED_PTR4656]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4658:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4655]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4659:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4656]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4660:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4658]], i64 [[LLX_CMPXCHG_DESIRED4659]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4661:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4660]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4661]], ptr [[LLX_ATOMIC_EXPECTED_PTR4657]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4662:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4660]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4663:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4657]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS4662]], label [[LLX_ATOMIC_EXIT4664:%.*]], label [[LLX_ATOMIC_CONT4665:%.*]]
+// CHECK: llx.atomic.cont4665:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4663]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT4664]]
+// CHECK: llx.atomic.exit4664:
+// CHECK-NEXT: [[TMP2340:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2341:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2340]], ptr [[LLX_ATOMIC_EXPECTED_PTR4666]], align 8
+// CHECK-NEXT: store i64 [[TMP2341]], ptr [[LLX_ATOMIC_DESIRED_PTR4667]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4669:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4666]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4670:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4667]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4671:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4669]], i64 [[LLX_CMPXCHG_DESIRED4670]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4672:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4671]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4672]], ptr [[LLX_ATOMIC_EXPECTED_PTR4668]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4673:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4671]], 1
+// CHECK-NEXT: [[TMP2342:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS4673]] to i64
+// CHECK-NEXT: store i64 [[TMP2342]], ptr [[LLR]], align 8
+// CHECK-NEXT: [[TMP2343:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2344:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2343]], ptr [[LLX_ATOMIC_EXPECTED_PTR4674]], align 8
+// CHECK-NEXT: store i64 [[TMP2344]], ptr [[LLX_ATOMIC_DESIRED_PTR4675]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4677:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4674]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4678:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4675]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4679:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4677]], i64 [[LLX_CMPXCHG_DESIRED4678]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4680:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4679]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4680]], ptr [[LLX_ATOMIC_EXPECTED_PTR4676]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4681:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4679]], 1
+// CHECK-NEXT: [[TMP2345:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS4681]] to i64
+// CHECK-NEXT: store i64 [[TMP2345]], ptr [[LLR]], align 8
+// CHECK-NEXT: [[TMP2346:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2347:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2346]], ptr [[LLX_ATOMIC_EXPECTED_PTR4682]], align 8
+// CHECK-NEXT: store i64 [[TMP2347]], ptr [[LLX_ATOMIC_DESIRED_PTR4683]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4685:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4682]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4686:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4683]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4687:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4685]], i64 [[LLX_CMPXCHG_DESIRED4686]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4688:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4687]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4688]], ptr [[LLX_ATOMIC_EXPECTED_PTR4684]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4689:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4687]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4690:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4684]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS4689]], label [[LLX_ATOMIC_EXIT4691:%.*]], label [[LLX_ATOMIC_CONT4692:%.*]]
+// CHECK: llx.atomic.cont4692:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4690]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT4691]]
+// CHECK: llx.atomic.exit4691:
+// CHECK-NEXT: [[TMP2348:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS4689]] to i64
+// CHECK-NEXT: store i64 [[TMP2348]], ptr [[LLR]], align 8
+// CHECK-NEXT: [[TMP2349:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2350:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2349]], ptr [[LLX_ATOMIC_EXPECTED_PTR4693]], align 8
+// CHECK-NEXT: store i64 [[TMP2350]], ptr [[LLX_ATOMIC_DESIRED_PTR4694]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4696:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4693]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4697:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4694]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4698:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4696]], i64 [[LLX_CMPXCHG_DESIRED4697]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4699:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4698]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4699]], ptr [[LLX_ATOMIC_EXPECTED_PTR4695]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4700:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4698]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4701:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4695]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS4700]], label [[LLX_ATOMIC_EXIT4702:%.*]], label [[LLX_ATOMIC_CONT4703:%.*]]
+// CHECK: llx.atomic.cont4703:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4701]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT4702]]
+// CHECK: llx.atomic.exit4702:
+// CHECK-NEXT: [[TMP2351:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS4700]] to i64
+// CHECK-NEXT: store i64 [[TMP2351]], ptr [[LLR]], align 8
+// CHECK-NEXT: [[TMP2352:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2353:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2352]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP2353]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2354:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2355:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2354]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP2355]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2356:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2357:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2356]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP2357]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2358:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2359:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2358]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP2359]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2360:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2361:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2360]], ptr [[LLX_ATOMIC_EXPECTED_PTR4704]], align 8
+// CHECK-NEXT: store i64 [[TMP2361]], ptr [[LLX_ATOMIC_DESIRED_PTR4705]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4707:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4704]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4708:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4705]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4709:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4707]], i64 [[LLX_CMPXCHG_DESIRED4708]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4710:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4709]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4710]], ptr [[LLX_ATOMIC_EXPECTED_PTR4706]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4711:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4709]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4712:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4706]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4712]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2362:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2363:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2362]], ptr [[LLX_ATOMIC_EXPECTED_PTR4713]], align 8
+// CHECK-NEXT: store i64 [[TMP2363]], ptr [[LLX_ATOMIC_DESIRED_PTR4714]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4716:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4713]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4717:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4714]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4718:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4716]], i64 [[LLX_CMPXCHG_DESIRED4717]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4719:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4718]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4719]], ptr [[LLX_ATOMIC_EXPECTED_PTR4715]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4720:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4718]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4721:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4715]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4721]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2364:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2365:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2364]] acq_rel, align 8
+// CHECK-NEXT: [[TMP2366:%.*]] = icmp sgt i64 [[TMP2365]], [[TMP2364]]
+// CHECK-NEXT: [[TMP2367:%.*]] = select i1 [[TMP2366]], i64 [[TMP2364]], i64 [[TMP2365]]
+// CHECK-NEXT: store i64 [[TMP2367]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2368:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2369:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2368]] acq_rel, align 8
+// CHECK-NEXT: [[TMP2370:%.*]] = icmp slt i64 [[TMP2369]], [[TMP2368]]
+// CHECK-NEXT: [[TMP2371:%.*]] = select i1 [[TMP2370]], i64 [[TMP2368]], i64 [[TMP2369]]
+// CHECK-NEXT: store i64 [[TMP2371]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2372:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2373:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2372]] acq_rel, align 8
+// CHECK-NEXT: [[TMP2374:%.*]] = icmp slt i64 [[TMP2373]], [[TMP2372]]
+// CHECK-NEXT: [[TMP2375:%.*]] = select i1 [[TMP2374]], i64 [[TMP2372]], i64 [[TMP2373]]
+// CHECK-NEXT: store i64 [[TMP2375]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2376:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2377:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2376]] acq_rel, align 8
+// CHECK-NEXT: [[TMP2378:%.*]] = icmp sgt i64 [[TMP2377]], [[TMP2376]]
+// CHECK-NEXT: [[TMP2379:%.*]] = select i1 [[TMP2378]], i64 [[TMP2376]], i64 [[TMP2377]]
+// CHECK-NEXT: store i64 [[TMP2379]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2380:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2381:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2380]], ptr [[LLX_ATOMIC_EXPECTED_PTR4722]], align 8
+// CHECK-NEXT: store i64 [[TMP2381]], ptr [[LLX_ATOMIC_DESIRED_PTR4723]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4725:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4722]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4726:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4723]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4727:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4725]], i64 [[LLX_CMPXCHG_DESIRED4726]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4728:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4727]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4728]], ptr [[LLX_ATOMIC_EXPECTED_PTR4724]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4729:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4727]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4730:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4724]], align 8
+// CHECK-NEXT: [[LLX_CAPTURE_CAPTURED4731:%.*]] = select i1 [[LLX_CMPXCHG_SUCCESS4729]], i64 [[TMP2380]], i64 [[LLX_CAPTURE_ACTUAL4730]]
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_CAPTURED4731]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2382:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2383:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2382]], ptr [[LLX_ATOMIC_EXPECTED_PTR4732]], align 8
+// CHECK-NEXT: store i64 [[TMP2383]], ptr [[LLX_ATOMIC_DESIRED_PTR4733]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4735:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4732]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4736:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4733]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4737:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4735]], i64 [[LLX_CMPXCHG_DESIRED4736]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4738:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4737]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4738]], ptr [[LLX_ATOMIC_EXPECTED_PTR4734]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4739:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4737]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4740:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4734]], align 8
+// CHECK-NEXT: [[LLX_CAPTURE_CAPTURED4741:%.*]] = select i1 [[LLX_CMPXCHG_SUCCESS4739]], i64 [[TMP2382]], i64 [[LLX_CAPTURE_ACTUAL4740]]
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_CAPTURED4741]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2384:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2385:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2384]], ptr [[LLX_ATOMIC_EXPECTED_PTR4742]], align 8
+// CHECK-NEXT: store i64 [[TMP2385]], ptr [[LLX_ATOMIC_DESIRED_PTR4743]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4745:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4742]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4746:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4743]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4747:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4745]], i64 [[LLX_CMPXCHG_DESIRED4746]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4748:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4747]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4748]], ptr [[LLX_ATOMIC_EXPECTED_PTR4744]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4749:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4747]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4750:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4744]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS4749]], label [[LLX_ATOMIC_EXIT4751:%.*]], label [[LLX_ATOMIC_CONT4752:%.*]]
+// CHECK: llx.atomic.cont4752:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4750]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT4751]]
+// CHECK: llx.atomic.exit4751:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2386:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2387:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2386]], ptr [[LLX_ATOMIC_EXPECTED_PTR4753]], align 8
+// CHECK-NEXT: store i64 [[TMP2387]], ptr [[LLX_ATOMIC_DESIRED_PTR4754]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4756:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4753]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4757:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4754]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4758:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4756]], i64 [[LLX_CMPXCHG_DESIRED4757]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4759:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4758]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4759]], ptr [[LLX_ATOMIC_EXPECTED_PTR4755]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4760:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4758]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4761:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4755]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS4760]], label [[LLX_ATOMIC_EXIT4762:%.*]], label [[LLX_ATOMIC_CONT4763:%.*]]
+// CHECK: llx.atomic.cont4763:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4761]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT4762]]
+// CHECK: llx.atomic.exit4762:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2388:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2389:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2388]], ptr [[LLX_ATOMIC_EXPECTED_PTR4764]], align 8
+// CHECK-NEXT: store i64 [[TMP2389]], ptr [[LLX_ATOMIC_DESIRED_PTR4765]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4767:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4764]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4768:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4765]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4769:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4767]], i64 [[LLX_CMPXCHG_DESIRED4768]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4770:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4769]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4770]], ptr [[LLX_ATOMIC_EXPECTED_PTR4766]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4771:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4769]], 1
+// CHECK-NEXT: [[TMP2390:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS4771]] to i64
+// CHECK-NEXT: store i64 [[TMP2390]], ptr [[LLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2391:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2392:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2391]], ptr [[LLX_ATOMIC_EXPECTED_PTR4772]], align 8
+// CHECK-NEXT: store i64 [[TMP2392]], ptr [[LLX_ATOMIC_DESIRED_PTR4773]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4775:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4772]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4776:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4773]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4777:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4775]], i64 [[LLX_CMPXCHG_DESIRED4776]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4778:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4777]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4778]], ptr [[LLX_ATOMIC_EXPECTED_PTR4774]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4779:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4777]], 1
+// CHECK-NEXT: [[TMP2393:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS4779]] to i64
+// CHECK-NEXT: store i64 [[TMP2393]], ptr [[LLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2394:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2395:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2394]], ptr [[LLX_ATOMIC_EXPECTED_PTR4780]], align 8
+// CHECK-NEXT: store i64 [[TMP2395]], ptr [[LLX_ATOMIC_DESIRED_PTR4781]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4783:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4780]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4784:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4781]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4785:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4783]], i64 [[LLX_CMPXCHG_DESIRED4784]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4786:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4785]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4786]], ptr [[LLX_ATOMIC_EXPECTED_PTR4782]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4787:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4785]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4788:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4782]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS4787]], label [[LLX_ATOMIC_EXIT4789:%.*]], label [[LLX_ATOMIC_CONT4790:%.*]]
+// CHECK: llx.atomic.cont4790:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4788]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT4789]]
+// CHECK: llx.atomic.exit4789:
+// CHECK-NEXT: [[TMP2396:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS4787]] to i64
+// CHECK-NEXT: store i64 [[TMP2396]], ptr [[LLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2397:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2398:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2397]], ptr [[LLX_ATOMIC_EXPECTED_PTR4791]], align 8
+// CHECK-NEXT: store i64 [[TMP2398]], ptr [[LLX_ATOMIC_DESIRED_PTR4792]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4794:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4791]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4795:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4792]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4796:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4794]], i64 [[LLX_CMPXCHG_DESIRED4795]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4797:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4796]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4797]], ptr [[LLX_ATOMIC_EXPECTED_PTR4793]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4798:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4796]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4799:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4793]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS4798]], label [[LLX_ATOMIC_EXIT4800:%.*]], label [[LLX_ATOMIC_CONT4801:%.*]]
+// CHECK: llx.atomic.cont4801:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4799]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT4800]]
+// CHECK: llx.atomic.exit4800:
+// CHECK-NEXT: [[TMP2399:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS4798]] to i64
+// CHECK-NEXT: store i64 [[TMP2399]], ptr [[LLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2400:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2401:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2400]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP2401]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2402:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2403:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2402]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP2403]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2404:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2405:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2404]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP2405]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2406:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2407:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2406]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP2407]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2408:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2409:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2408]], ptr [[LLX_ATOMIC_EXPECTED_PTR4802]], align 8
+// CHECK-NEXT: store i64 [[TMP2409]], ptr [[LLX_ATOMIC_DESIRED_PTR4803]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4805:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4802]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4806:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4803]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4807:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4805]], i64 [[LLX_CMPXCHG_DESIRED4806]] acquire acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4808:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4807]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4808]], ptr [[LLX_ATOMIC_EXPECTED_PTR4804]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4809:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4807]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4810:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4804]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4810]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2410:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2411:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2410]], ptr [[LLX_ATOMIC_EXPECTED_PTR4811]], align 8
+// CHECK-NEXT: store i64 [[TMP2411]], ptr [[LLX_ATOMIC_DESIRED_PTR4812]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4814:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4811]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4815:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4812]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4816:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4814]], i64 [[LLX_CMPXCHG_DESIRED4815]] acquire acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4817:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4816]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4817]], ptr [[LLX_ATOMIC_EXPECTED_PTR4813]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4818:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4816]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4819:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4813]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4819]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2412:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2413:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2412]] acquire, align 8
+// CHECK-NEXT: [[TMP2414:%.*]] = icmp sgt i64 [[TMP2413]], [[TMP2412]]
+// CHECK-NEXT: [[TMP2415:%.*]] = select i1 [[TMP2414]], i64 [[TMP2412]], i64 [[TMP2413]]
+// CHECK-NEXT: store i64 [[TMP2415]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2416:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2417:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2416]] acquire, align 8
+// CHECK-NEXT: [[TMP2418:%.*]] = icmp slt i64 [[TMP2417]], [[TMP2416]]
+// CHECK-NEXT: [[TMP2419:%.*]] = select i1 [[TMP2418]], i64 [[TMP2416]], i64 [[TMP2417]]
+// CHECK-NEXT: store i64 [[TMP2419]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2420:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2421:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2420]] acquire, align 8
+// CHECK-NEXT: [[TMP2422:%.*]] = icmp slt i64 [[TMP2421]], [[TMP2420]]
+// CHECK-NEXT: [[TMP2423:%.*]] = select i1 [[TMP2422]], i64 [[TMP2420]], i64 [[TMP2421]]
+// CHECK-NEXT: store i64 [[TMP2423]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2424:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2425:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2424]] acquire, align 8
+// CHECK-NEXT: [[TMP2426:%.*]] = icmp sgt i64 [[TMP2425]], [[TMP2424]]
+// CHECK-NEXT: [[TMP2427:%.*]] = select i1 [[TMP2426]], i64 [[TMP2424]], i64 [[TMP2425]]
+// CHECK-NEXT: store i64 [[TMP2427]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2428:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2429:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2428]], ptr [[LLX_ATOMIC_EXPECTED_PTR4820]], align 8
+// CHECK-NEXT: store i64 [[TMP2429]], ptr [[LLX_ATOMIC_DESIRED_PTR4821]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4823:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4820]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4824:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4821]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4825:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4823]], i64 [[LLX_CMPXCHG_DESIRED4824]] acquire acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4826:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4825]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4826]], ptr [[LLX_ATOMIC_EXPECTED_PTR4822]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4827:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4825]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4828:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4822]], align 8
+// CHECK-NEXT: [[LLX_CAPTURE_CAPTURED4829:%.*]] = select i1 [[LLX_CMPXCHG_SUCCESS4827]], i64 [[TMP2428]], i64 [[LLX_CAPTURE_ACTUAL4828]]
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_CAPTURED4829]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2430:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2431:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2430]], ptr [[LLX_ATOMIC_EXPECTED_PTR4830]], align 8
+// CHECK-NEXT: store i64 [[TMP2431]], ptr [[LLX_ATOMIC_DESIRED_PTR4831]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4833:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4830]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4834:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4831]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4835:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4833]], i64 [[LLX_CMPXCHG_DESIRED4834]] acquire acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4836:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4835]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4836]], ptr [[LLX_ATOMIC_EXPECTED_PTR4832]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4837:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4835]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4838:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4832]], align 8
+// CHECK-NEXT: [[LLX_CAPTURE_CAPTURED4839:%.*]] = select i1 [[LLX_CMPXCHG_SUCCESS4837]], i64 [[TMP2430]], i64 [[LLX_CAPTURE_ACTUAL4838]]
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_CAPTURED4839]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2432:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2433:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2432]], ptr [[LLX_ATOMIC_EXPECTED_PTR4840]], align 8
+// CHECK-NEXT: store i64 [[TMP2433]], ptr [[LLX_ATOMIC_DESIRED_PTR4841]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4843:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4840]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4844:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4841]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4845:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4843]], i64 [[LLX_CMPXCHG_DESIRED4844]] acquire acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4846:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4845]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4846]], ptr [[LLX_ATOMIC_EXPECTED_PTR4842]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4847:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4845]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4848:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4842]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS4847]], label [[LLX_ATOMIC_EXIT4849:%.*]], label [[LLX_ATOMIC_CONT4850:%.*]]
+// CHECK: llx.atomic.cont4850:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4848]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT4849]]
+// CHECK: llx.atomic.exit4849:
+// CHECK-NEXT: [[TMP2434:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2435:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2434]], ptr [[LLX_ATOMIC_EXPECTED_PTR4851]], align 8
+// CHECK-NEXT: store i64 [[TMP2435]], ptr [[LLX_ATOMIC_DESIRED_PTR4852]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4854:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4851]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4855:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4852]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4856:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4854]], i64 [[LLX_CMPXCHG_DESIRED4855]] acquire acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4857:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4856]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4857]], ptr [[LLX_ATOMIC_EXPECTED_PTR4853]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4858:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4856]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4859:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4853]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS4858]], label [[LLX_ATOMIC_EXIT4860:%.*]], label [[LLX_ATOMIC_CONT4861:%.*]]
+// CHECK: llx.atomic.cont4861:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4859]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT4860]]
+// CHECK: llx.atomic.exit4860:
+// CHECK-NEXT: [[TMP2436:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2437:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2436]], ptr [[LLX_ATOMIC_EXPECTED_PTR4862]], align 8
+// CHECK-NEXT: store i64 [[TMP2437]], ptr [[LLX_ATOMIC_DESIRED_PTR4863]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4865:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4862]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4866:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4863]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4867:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4865]], i64 [[LLX_CMPXCHG_DESIRED4866]] acquire acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4868:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4867]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4868]], ptr [[LLX_ATOMIC_EXPECTED_PTR4864]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4869:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4867]], 1
+// CHECK-NEXT: [[TMP2438:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS4869]] to i64
+// CHECK-NEXT: store i64 [[TMP2438]], ptr [[LLR]], align 8
+// CHECK-NEXT: [[TMP2439:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2440:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2439]], ptr [[LLX_ATOMIC_EXPECTED_PTR4870]], align 8
+// CHECK-NEXT: store i64 [[TMP2440]], ptr [[LLX_ATOMIC_DESIRED_PTR4871]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4873:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4870]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4874:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4871]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4875:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4873]], i64 [[LLX_CMPXCHG_DESIRED4874]] acquire acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4876:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4875]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4876]], ptr [[LLX_ATOMIC_EXPECTED_PTR4872]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4877:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4875]], 1
+// CHECK-NEXT: [[TMP2441:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS4877]] to i64
+// CHECK-NEXT: store i64 [[TMP2441]], ptr [[LLR]], align 8
+// CHECK-NEXT: [[TMP2442:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2443:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2442]], ptr [[LLX_ATOMIC_EXPECTED_PTR4878]], align 8
+// CHECK-NEXT: store i64 [[TMP2443]], ptr [[LLX_ATOMIC_DESIRED_PTR4879]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4881:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4878]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4882:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4879]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4883:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4881]], i64 [[LLX_CMPXCHG_DESIRED4882]] acquire acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4884:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4883]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4884]], ptr [[LLX_ATOMIC_EXPECTED_PTR4880]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4885:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4883]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4886:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4880]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS4885]], label [[LLX_ATOMIC_EXIT4887:%.*]], label [[LLX_ATOMIC_CONT4888:%.*]]
+// CHECK: llx.atomic.cont4888:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4886]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT4887]]
+// CHECK: llx.atomic.exit4887:
+// CHECK-NEXT: [[TMP2444:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS4885]] to i64
+// CHECK-NEXT: store i64 [[TMP2444]], ptr [[LLR]], align 8
+// CHECK-NEXT: [[TMP2445:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2446:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2445]], ptr [[LLX_ATOMIC_EXPECTED_PTR4889]], align 8
+// CHECK-NEXT: store i64 [[TMP2446]], ptr [[LLX_ATOMIC_DESIRED_PTR4890]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4892:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4889]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4893:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4890]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4894:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4892]], i64 [[LLX_CMPXCHG_DESIRED4893]] acquire acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4895:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4894]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4895]], ptr [[LLX_ATOMIC_EXPECTED_PTR4891]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4896:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4894]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4897:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4891]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS4896]], label [[LLX_ATOMIC_EXIT4898:%.*]], label [[LLX_ATOMIC_CONT4899:%.*]]
+// CHECK: llx.atomic.cont4899:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4897]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT4898]]
+// CHECK: llx.atomic.exit4898:
+// CHECK-NEXT: [[TMP2447:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS4896]] to i64
+// CHECK-NEXT: store i64 [[TMP2447]], ptr [[LLR]], align 8
+// CHECK-NEXT: [[TMP2448:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2449:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2448]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2449]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2450:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2451:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2450]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2451]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2452:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2453:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2452]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2453]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2454:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2455:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2454]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2455]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2456:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2457:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2456]], ptr [[LLX_ATOMIC_EXPECTED_PTR4900]], align 8
+// CHECK-NEXT: store i64 [[TMP2457]], ptr [[LLX_ATOMIC_DESIRED_PTR4901]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4903:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4900]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4904:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4901]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4905:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4903]], i64 [[LLX_CMPXCHG_DESIRED4904]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4906:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4905]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4906]], ptr [[LLX_ATOMIC_EXPECTED_PTR4902]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4907:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4905]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4908:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4902]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4908]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2458:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2459:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2458]], ptr [[LLX_ATOMIC_EXPECTED_PTR4909]], align 8
+// CHECK-NEXT: store i64 [[TMP2459]], ptr [[LLX_ATOMIC_DESIRED_PTR4910]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4912:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4909]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4913:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4910]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4914:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4912]], i64 [[LLX_CMPXCHG_DESIRED4913]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4915:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4914]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4915]], ptr [[LLX_ATOMIC_EXPECTED_PTR4911]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4916:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4914]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4917:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4911]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4917]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2460:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2461:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2460]] monotonic, align 8
+// CHECK-NEXT: [[TMP2462:%.*]] = icmp sgt i64 [[TMP2461]], [[TMP2460]]
+// CHECK-NEXT: [[TMP2463:%.*]] = select i1 [[TMP2462]], i64 [[TMP2460]], i64 [[TMP2461]]
+// CHECK-NEXT: store i64 [[TMP2463]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2464:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2465:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2464]] monotonic, align 8
+// CHECK-NEXT: [[TMP2466:%.*]] = icmp slt i64 [[TMP2465]], [[TMP2464]]
+// CHECK-NEXT: [[TMP2467:%.*]] = select i1 [[TMP2466]], i64 [[TMP2464]], i64 [[TMP2465]]
+// CHECK-NEXT: store i64 [[TMP2467]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2468:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2469:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2468]] monotonic, align 8
+// CHECK-NEXT: [[TMP2470:%.*]] = icmp slt i64 [[TMP2469]], [[TMP2468]]
+// CHECK-NEXT: [[TMP2471:%.*]] = select i1 [[TMP2470]], i64 [[TMP2468]], i64 [[TMP2469]]
+// CHECK-NEXT: store i64 [[TMP2471]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2472:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2473:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2472]] monotonic, align 8
+// CHECK-NEXT: [[TMP2474:%.*]] = icmp sgt i64 [[TMP2473]], [[TMP2472]]
+// CHECK-NEXT: [[TMP2475:%.*]] = select i1 [[TMP2474]], i64 [[TMP2472]], i64 [[TMP2473]]
+// CHECK-NEXT: store i64 [[TMP2475]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2476:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2477:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2476]], ptr [[LLX_ATOMIC_EXPECTED_PTR4918]], align 8
+// CHECK-NEXT: store i64 [[TMP2477]], ptr [[LLX_ATOMIC_DESIRED_PTR4919]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4921:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4918]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4922:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4919]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4923:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4921]], i64 [[LLX_CMPXCHG_DESIRED4922]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4924:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4923]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4924]], ptr [[LLX_ATOMIC_EXPECTED_PTR4920]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4925:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4923]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4926:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4920]], align 8
+// CHECK-NEXT: [[LLX_CAPTURE_CAPTURED4927:%.*]] = select i1 [[LLX_CMPXCHG_SUCCESS4925]], i64 [[TMP2476]], i64 [[LLX_CAPTURE_ACTUAL4926]]
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_CAPTURED4927]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2478:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2479:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2478]], ptr [[LLX_ATOMIC_EXPECTED_PTR4928]], align 8
+// CHECK-NEXT: store i64 [[TMP2479]], ptr [[LLX_ATOMIC_DESIRED_PTR4929]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4931:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4928]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4932:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4929]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4933:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4931]], i64 [[LLX_CMPXCHG_DESIRED4932]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4934:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4933]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4934]], ptr [[LLX_ATOMIC_EXPECTED_PTR4930]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4935:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4933]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4936:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4930]], align 8
+// CHECK-NEXT: [[LLX_CAPTURE_CAPTURED4937:%.*]] = select i1 [[LLX_CMPXCHG_SUCCESS4935]], i64 [[TMP2478]], i64 [[LLX_CAPTURE_ACTUAL4936]]
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_CAPTURED4937]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP2480:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2481:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2480]], ptr [[LLX_ATOMIC_EXPECTED_PTR4938]], align 8
+// CHECK-NEXT: store i64 [[TMP2481]], ptr [[LLX_ATOMIC_DESIRED_PTR4939]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4941:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4938]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4942:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4939]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4943:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4941]], i64 [[LLX_CMPXCHG_DESIRED4942]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4944:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4943]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4944]], ptr [[LLX_ATOMIC_EXPECTED_PTR4940]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4945:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4943]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4946:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4940]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS4945]], label [[LLX_ATOMIC_EXIT4947:%.*]], label [[LLX_ATOMIC_CONT4948:%.*]]
+// CHECK: llx.atomic.cont4948:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4946]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT4947]]
+// CHECK: llx.atomic.exit4947:
+// CHECK-NEXT: [[TMP2482:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2483:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2482]], ptr [[LLX_ATOMIC_EXPECTED_PTR4949]], align 8
+// CHECK-NEXT: store i64 [[TMP2483]], ptr [[LLX_ATOMIC_DESIRED_PTR4950]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4952:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4949]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4953:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4950]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4954:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4952]], i64 [[LLX_CMPXCHG_DESIRED4953]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4955:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4954]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4955]], ptr [[LLX_ATOMIC_EXPECTED_PTR4951]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4956:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4954]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4957:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4951]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS4956]], label [[LLX_ATOMIC_EXIT4958:%.*]], label [[LLX_ATOMIC_CONT4959:%.*]]
+// CHECK: llx.atomic.cont4959:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4957]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT4958]]
+// CHECK: llx.atomic.exit4958:
+// CHECK-NEXT: [[TMP2484:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2485:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2484]], ptr [[LLX_ATOMIC_EXPECTED_PTR4960]], align 8
+// CHECK-NEXT: store i64 [[TMP2485]], ptr [[LLX_ATOMIC_DESIRED_PTR4961]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4963:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4960]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4964:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4961]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4965:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4963]], i64 [[LLX_CMPXCHG_DESIRED4964]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4966:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4965]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4966]], ptr [[LLX_ATOMIC_EXPECTED_PTR4962]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4967:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4965]], 1
+// CHECK-NEXT: [[TMP2486:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS4967]] to i64
+// CHECK-NEXT: store i64 [[TMP2486]], ptr [[LLR]], align 8
+// CHECK-NEXT: [[TMP2487:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2488:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2487]], ptr [[LLX_ATOMIC_EXPECTED_PTR4968]], align 8
+// CHECK-NEXT: store i64 [[TMP2488]], ptr [[LLX_ATOMIC_DESIRED_PTR4969]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4971:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4968]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4972:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4969]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4973:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4971]], i64 [[LLX_CMPXCHG_DESIRED4972]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4974:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4973]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4974]], ptr [[LLX_ATOMIC_EXPECTED_PTR4970]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4975:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4973]], 1
+// CHECK-NEXT: [[TMP2489:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS4975]] to i64
+// CHECK-NEXT: store i64 [[TMP2489]], ptr [[LLR]], align 8
+// CHECK-NEXT: [[TMP2490:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2491:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2490]], ptr [[LLX_ATOMIC_EXPECTED_PTR4976]], align 8
+// CHECK-NEXT: store i64 [[TMP2491]], ptr [[LLX_ATOMIC_DESIRED_PTR4977]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4979:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4976]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4980:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4977]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4981:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4979]], i64 [[LLX_CMPXCHG_DESIRED4980]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4982:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4981]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4982]], ptr [[LLX_ATOMIC_EXPECTED_PTR4978]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4983:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4981]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4984:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4978]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS4983]], label [[LLX_ATOMIC_EXIT4985:%.*]], label [[LLX_ATOMIC_CONT4986:%.*]]
+// CHECK: llx.atomic.cont4986:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4984]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT4985]]
+// CHECK: llx.atomic.exit4985:
+// CHECK-NEXT: [[TMP2492:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS4983]] to i64
+// CHECK-NEXT: store i64 [[TMP2492]], ptr [[LLR]], align 8
+// CHECK-NEXT: [[TMP2493:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2494:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2493]], ptr [[LLX_ATOMIC_EXPECTED_PTR4987]], align 8
+// CHECK-NEXT: store i64 [[TMP2494]], ptr [[LLX_ATOMIC_DESIRED_PTR4988]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED4990:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4987]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED4991:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4988]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR4992:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED4990]], i64 [[LLX_CMPXCHG_DESIRED4991]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV4993:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4992]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV4993]], ptr [[LLX_ATOMIC_EXPECTED_PTR4989]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS4994:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR4992]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL4995:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4989]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS4994]], label [[LLX_ATOMIC_EXIT4996:%.*]], label [[LLX_ATOMIC_CONT4997:%.*]]
+// CHECK: llx.atomic.cont4997:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL4995]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT4996]]
+// CHECK: llx.atomic.exit4996:
+// CHECK-NEXT: [[TMP2495:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS4994]] to i64
+// CHECK-NEXT: store i64 [[TMP2495]], ptr [[LLR]], align 8
+// CHECK-NEXT: [[TMP2496:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2497:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2496]] release, align 8
+// CHECK-NEXT: store i64 [[TMP2497]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2498:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2499:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2498]] release, align 8
+// CHECK-NEXT: store i64 [[TMP2499]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2500:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2501:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2500]] release, align 8
+// CHECK-NEXT: store i64 [[TMP2501]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2502:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2503:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2502]] release, align 8
+// CHECK-NEXT: store i64 [[TMP2503]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2504:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2505:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2504]], ptr [[LLX_ATOMIC_EXPECTED_PTR4998]], align 8
+// CHECK-NEXT: store i64 [[TMP2505]], ptr [[LLX_ATOMIC_DESIRED_PTR4999]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5001:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4998]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5002:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR4999]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5003:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5001]], i64 [[LLX_CMPXCHG_DESIRED5002]] release monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5004:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5003]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5004]], ptr [[LLX_ATOMIC_EXPECTED_PTR5000]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5005:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5003]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL5006:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5000]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL5006]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2506:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2507:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2506]], ptr [[LLX_ATOMIC_EXPECTED_PTR5007]], align 8
+// CHECK-NEXT: store i64 [[TMP2507]], ptr [[LLX_ATOMIC_DESIRED_PTR5008]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5010:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5007]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5011:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5008]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5012:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5010]], i64 [[LLX_CMPXCHG_DESIRED5011]] release monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5013:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5012]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5013]], ptr [[LLX_ATOMIC_EXPECTED_PTR5009]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5014:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5012]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL5015:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5009]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL5015]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2508:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2509:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2508]] release, align 8
+// CHECK-NEXT: [[TMP2510:%.*]] = icmp sgt i64 [[TMP2509]], [[TMP2508]]
+// CHECK-NEXT: [[TMP2511:%.*]] = select i1 [[TMP2510]], i64 [[TMP2508]], i64 [[TMP2509]]
+// CHECK-NEXT: store i64 [[TMP2511]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2512:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2513:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2512]] release, align 8
+// CHECK-NEXT: [[TMP2514:%.*]] = icmp slt i64 [[TMP2513]], [[TMP2512]]
+// CHECK-NEXT: [[TMP2515:%.*]] = select i1 [[TMP2514]], i64 [[TMP2512]], i64 [[TMP2513]]
+// CHECK-NEXT: store i64 [[TMP2515]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2516:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2517:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2516]] release, align 8
+// CHECK-NEXT: [[TMP2518:%.*]] = icmp slt i64 [[TMP2517]], [[TMP2516]]
+// CHECK-NEXT: [[TMP2519:%.*]] = select i1 [[TMP2518]], i64 [[TMP2516]], i64 [[TMP2517]]
+// CHECK-NEXT: store i64 [[TMP2519]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2520:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2521:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2520]] release, align 8
+// CHECK-NEXT: [[TMP2522:%.*]] = icmp sgt i64 [[TMP2521]], [[TMP2520]]
+// CHECK-NEXT: [[TMP2523:%.*]] = select i1 [[TMP2522]], i64 [[TMP2520]], i64 [[TMP2521]]
+// CHECK-NEXT: store i64 [[TMP2523]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2524:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2525:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2524]], ptr [[LLX_ATOMIC_EXPECTED_PTR5016]], align 8
+// CHECK-NEXT: store i64 [[TMP2525]], ptr [[LLX_ATOMIC_DESIRED_PTR5017]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5019:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5016]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5020:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5017]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5021:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5019]], i64 [[LLX_CMPXCHG_DESIRED5020]] release monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5022:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5021]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5022]], ptr [[LLX_ATOMIC_EXPECTED_PTR5018]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5023:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5021]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL5024:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5018]], align 8
+// CHECK-NEXT: [[LLX_CAPTURE_CAPTURED5025:%.*]] = select i1 [[LLX_CMPXCHG_SUCCESS5023]], i64 [[TMP2524]], i64 [[LLX_CAPTURE_ACTUAL5024]]
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_CAPTURED5025]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2526:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2527:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2526]], ptr [[LLX_ATOMIC_EXPECTED_PTR5026]], align 8
+// CHECK-NEXT: store i64 [[TMP2527]], ptr [[LLX_ATOMIC_DESIRED_PTR5027]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5029:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5026]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5030:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5027]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5031:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5029]], i64 [[LLX_CMPXCHG_DESIRED5030]] release monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5032:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5031]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5032]], ptr [[LLX_ATOMIC_EXPECTED_PTR5028]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5033:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5031]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL5034:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5028]], align 8
+// CHECK-NEXT: [[LLX_CAPTURE_CAPTURED5035:%.*]] = select i1 [[LLX_CMPXCHG_SUCCESS5033]], i64 [[TMP2526]], i64 [[LLX_CAPTURE_ACTUAL5034]]
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_CAPTURED5035]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2528:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2529:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2528]], ptr [[LLX_ATOMIC_EXPECTED_PTR5036]], align 8
+// CHECK-NEXT: store i64 [[TMP2529]], ptr [[LLX_ATOMIC_DESIRED_PTR5037]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5039:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5036]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5040:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5037]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5041:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5039]], i64 [[LLX_CMPXCHG_DESIRED5040]] release monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5042:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5041]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5042]], ptr [[LLX_ATOMIC_EXPECTED_PTR5038]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5043:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5041]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL5044:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5038]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS5043]], label [[LLX_ATOMIC_EXIT5045:%.*]], label [[LLX_ATOMIC_CONT5046:%.*]]
+// CHECK: llx.atomic.cont5046:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL5044]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT5045]]
+// CHECK: llx.atomic.exit5045:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2530:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2531:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2530]], ptr [[LLX_ATOMIC_EXPECTED_PTR5047]], align 8
+// CHECK-NEXT: store i64 [[TMP2531]], ptr [[LLX_ATOMIC_DESIRED_PTR5048]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5050:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5047]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5051:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5048]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5052:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5050]], i64 [[LLX_CMPXCHG_DESIRED5051]] release monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5053:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5052]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5053]], ptr [[LLX_ATOMIC_EXPECTED_PTR5049]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5054:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5052]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL5055:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5049]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS5054]], label [[LLX_ATOMIC_EXIT5056:%.*]], label [[LLX_ATOMIC_CONT5057:%.*]]
+// CHECK: llx.atomic.cont5057:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL5055]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT5056]]
+// CHECK: llx.atomic.exit5056:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2532:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2533:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2532]], ptr [[LLX_ATOMIC_EXPECTED_PTR5058]], align 8
+// CHECK-NEXT: store i64 [[TMP2533]], ptr [[LLX_ATOMIC_DESIRED_PTR5059]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5061:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5058]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5062:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5059]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5063:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5061]], i64 [[LLX_CMPXCHG_DESIRED5062]] release monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5064:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5063]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5064]], ptr [[LLX_ATOMIC_EXPECTED_PTR5060]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5065:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5063]], 1
+// CHECK-NEXT: [[TMP2534:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS5065]] to i64
+// CHECK-NEXT: store i64 [[TMP2534]], ptr [[LLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2535:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2536:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2535]], ptr [[LLX_ATOMIC_EXPECTED_PTR5066]], align 8
+// CHECK-NEXT: store i64 [[TMP2536]], ptr [[LLX_ATOMIC_DESIRED_PTR5067]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5069:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5066]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5070:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5067]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5071:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5069]], i64 [[LLX_CMPXCHG_DESIRED5070]] release monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5072:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5071]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5072]], ptr [[LLX_ATOMIC_EXPECTED_PTR5068]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5073:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5071]], 1
+// CHECK-NEXT: [[TMP2537:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS5073]] to i64
+// CHECK-NEXT: store i64 [[TMP2537]], ptr [[LLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2538:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2539:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2538]], ptr [[LLX_ATOMIC_EXPECTED_PTR5074]], align 8
+// CHECK-NEXT: store i64 [[TMP2539]], ptr [[LLX_ATOMIC_DESIRED_PTR5075]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5077:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5074]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5078:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5075]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5079:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5077]], i64 [[LLX_CMPXCHG_DESIRED5078]] release monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5080:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5079]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5080]], ptr [[LLX_ATOMIC_EXPECTED_PTR5076]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5081:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5079]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL5082:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5076]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS5081]], label [[LLX_ATOMIC_EXIT5083:%.*]], label [[LLX_ATOMIC_CONT5084:%.*]]
+// CHECK: llx.atomic.cont5084:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL5082]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT5083]]
+// CHECK: llx.atomic.exit5083:
+// CHECK-NEXT: [[TMP2540:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS5081]] to i64
+// CHECK-NEXT: store i64 [[TMP2540]], ptr [[LLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2541:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2542:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2541]], ptr [[LLX_ATOMIC_EXPECTED_PTR5085]], align 8
+// CHECK-NEXT: store i64 [[TMP2542]], ptr [[LLX_ATOMIC_DESIRED_PTR5086]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5088:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5085]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5089:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5086]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5090:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5088]], i64 [[LLX_CMPXCHG_DESIRED5089]] release monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5091:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5090]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5091]], ptr [[LLX_ATOMIC_EXPECTED_PTR5087]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5092:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5090]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL5093:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5087]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS5092]], label [[LLX_ATOMIC_EXIT5094:%.*]], label [[LLX_ATOMIC_CONT5095:%.*]]
+// CHECK: llx.atomic.cont5095:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL5093]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT5094]]
+// CHECK: llx.atomic.exit5094:
+// CHECK-NEXT: [[TMP2543:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS5092]] to i64
+// CHECK-NEXT: store i64 [[TMP2543]], ptr [[LLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2544:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2545:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2544]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP2545]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2546:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2547:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2546]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP2547]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2548:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2549:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2548]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP2549]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2550:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2551:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2550]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP2551]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2552:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2553:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2552]], ptr [[LLX_ATOMIC_EXPECTED_PTR5096]], align 8
+// CHECK-NEXT: store i64 [[TMP2553]], ptr [[LLX_ATOMIC_DESIRED_PTR5097]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5099:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5096]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5100:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5097]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5101:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5099]], i64 [[LLX_CMPXCHG_DESIRED5100]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5102:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5101]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5102]], ptr [[LLX_ATOMIC_EXPECTED_PTR5098]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5103:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5101]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL5104:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5098]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL5104]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2554:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2555:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2554]], ptr [[LLX_ATOMIC_EXPECTED_PTR5105]], align 8
+// CHECK-NEXT: store i64 [[TMP2555]], ptr [[LLX_ATOMIC_DESIRED_PTR5106]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5108:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5105]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5109:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5106]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5110:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5108]], i64 [[LLX_CMPXCHG_DESIRED5109]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5111:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5110]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5111]], ptr [[LLX_ATOMIC_EXPECTED_PTR5107]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5112:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5110]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL5113:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5107]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL5113]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2556:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2557:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2556]] seq_cst, align 8
+// CHECK-NEXT: [[TMP2558:%.*]] = icmp sgt i64 [[TMP2557]], [[TMP2556]]
+// CHECK-NEXT: [[TMP2559:%.*]] = select i1 [[TMP2558]], i64 [[TMP2556]], i64 [[TMP2557]]
+// CHECK-NEXT: store i64 [[TMP2559]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2560:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2561:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2560]] seq_cst, align 8
+// CHECK-NEXT: [[TMP2562:%.*]] = icmp slt i64 [[TMP2561]], [[TMP2560]]
+// CHECK-NEXT: [[TMP2563:%.*]] = select i1 [[TMP2562]], i64 [[TMP2560]], i64 [[TMP2561]]
+// CHECK-NEXT: store i64 [[TMP2563]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2564:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2565:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP2564]] seq_cst, align 8
+// CHECK-NEXT: [[TMP2566:%.*]] = icmp slt i64 [[TMP2565]], [[TMP2564]]
+// CHECK-NEXT: [[TMP2567:%.*]] = select i1 [[TMP2566]], i64 [[TMP2564]], i64 [[TMP2565]]
+// CHECK-NEXT: store i64 [[TMP2567]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2568:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2569:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP2568]] seq_cst, align 8
+// CHECK-NEXT: [[TMP2570:%.*]] = icmp sgt i64 [[TMP2569]], [[TMP2568]]
+// CHECK-NEXT: [[TMP2571:%.*]] = select i1 [[TMP2570]], i64 [[TMP2568]], i64 [[TMP2569]]
+// CHECK-NEXT: store i64 [[TMP2571]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2572:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2573:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2572]], ptr [[LLX_ATOMIC_EXPECTED_PTR5114]], align 8
+// CHECK-NEXT: store i64 [[TMP2573]], ptr [[LLX_ATOMIC_DESIRED_PTR5115]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5117:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5114]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5118:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5115]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5119:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5117]], i64 [[LLX_CMPXCHG_DESIRED5118]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5120:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5119]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5120]], ptr [[LLX_ATOMIC_EXPECTED_PTR5116]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5121:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5119]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL5122:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5116]], align 8
+// CHECK-NEXT: [[LLX_CAPTURE_CAPTURED5123:%.*]] = select i1 [[LLX_CMPXCHG_SUCCESS5121]], i64 [[TMP2572]], i64 [[LLX_CAPTURE_ACTUAL5122]]
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_CAPTURED5123]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2574:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2575:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2574]], ptr [[LLX_ATOMIC_EXPECTED_PTR5124]], align 8
+// CHECK-NEXT: store i64 [[TMP2575]], ptr [[LLX_ATOMIC_DESIRED_PTR5125]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5127:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5124]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5128:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5125]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5129:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5127]], i64 [[LLX_CMPXCHG_DESIRED5128]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5130:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5129]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5130]], ptr [[LLX_ATOMIC_EXPECTED_PTR5126]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5131:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5129]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL5132:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5126]], align 8
+// CHECK-NEXT: [[LLX_CAPTURE_CAPTURED5133:%.*]] = select i1 [[LLX_CMPXCHG_SUCCESS5131]], i64 [[TMP2574]], i64 [[LLX_CAPTURE_ACTUAL5132]]
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_CAPTURED5133]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2576:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2577:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2576]], ptr [[LLX_ATOMIC_EXPECTED_PTR5134]], align 8
+// CHECK-NEXT: store i64 [[TMP2577]], ptr [[LLX_ATOMIC_DESIRED_PTR5135]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5137:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5134]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5138:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5135]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5139:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5137]], i64 [[LLX_CMPXCHG_DESIRED5138]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5140:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5139]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5140]], ptr [[LLX_ATOMIC_EXPECTED_PTR5136]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5141:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5139]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL5142:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5136]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS5141]], label [[LLX_ATOMIC_EXIT5143:%.*]], label [[LLX_ATOMIC_CONT5144:%.*]]
+// CHECK: llx.atomic.cont5144:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL5142]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT5143]]
+// CHECK: llx.atomic.exit5143:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2578:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2579:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2578]], ptr [[LLX_ATOMIC_EXPECTED_PTR5145]], align 8
+// CHECK-NEXT: store i64 [[TMP2579]], ptr [[LLX_ATOMIC_DESIRED_PTR5146]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5148:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5145]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5149:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5146]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5150:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5148]], i64 [[LLX_CMPXCHG_DESIRED5149]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5151:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5150]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5151]], ptr [[LLX_ATOMIC_EXPECTED_PTR5147]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5152:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5150]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL5153:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5147]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS5152]], label [[LLX_ATOMIC_EXIT5154:%.*]], label [[LLX_ATOMIC_CONT5155:%.*]]
+// CHECK: llx.atomic.cont5155:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL5153]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT5154]]
+// CHECK: llx.atomic.exit5154:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2580:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2581:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2580]], ptr [[LLX_ATOMIC_EXPECTED_PTR5156]], align 8
+// CHECK-NEXT: store i64 [[TMP2581]], ptr [[LLX_ATOMIC_DESIRED_PTR5157]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5159:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5156]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5160:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5157]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5161:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5159]], i64 [[LLX_CMPXCHG_DESIRED5160]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5162:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5161]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5162]], ptr [[LLX_ATOMIC_EXPECTED_PTR5158]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5163:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5161]], 1
+// CHECK-NEXT: [[TMP2582:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS5163]] to i64
+// CHECK-NEXT: store i64 [[TMP2582]], ptr [[LLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2583:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2584:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2583]], ptr [[LLX_ATOMIC_EXPECTED_PTR5164]], align 8
+// CHECK-NEXT: store i64 [[TMP2584]], ptr [[LLX_ATOMIC_DESIRED_PTR5165]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5167:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5164]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5168:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5165]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5169:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5167]], i64 [[LLX_CMPXCHG_DESIRED5168]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5170:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5169]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5170]], ptr [[LLX_ATOMIC_EXPECTED_PTR5166]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5171:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5169]], 1
+// CHECK-NEXT: [[TMP2585:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS5171]] to i64
+// CHECK-NEXT: store i64 [[TMP2585]], ptr [[LLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2586:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2587:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2586]], ptr [[LLX_ATOMIC_EXPECTED_PTR5172]], align 8
+// CHECK-NEXT: store i64 [[TMP2587]], ptr [[LLX_ATOMIC_DESIRED_PTR5173]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5175:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5172]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5176:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5173]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5177:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5175]], i64 [[LLX_CMPXCHG_DESIRED5176]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5178:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5177]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5178]], ptr [[LLX_ATOMIC_EXPECTED_PTR5174]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5179:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5177]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL5180:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5174]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS5179]], label [[LLX_ATOMIC_EXIT5181:%.*]], label [[LLX_ATOMIC_CONT5182:%.*]]
+// CHECK: llx.atomic.cont5182:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL5180]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT5181]]
+// CHECK: llx.atomic.exit5181:
+// CHECK-NEXT: [[TMP2588:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS5179]] to i64
+// CHECK-NEXT: store i64 [[TMP2588]], ptr [[LLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2589:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP2590:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2589]], ptr [[LLX_ATOMIC_EXPECTED_PTR5183]], align 8
+// CHECK-NEXT: store i64 [[TMP2590]], ptr [[LLX_ATOMIC_DESIRED_PTR5184]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5186:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5183]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED5187:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR5184]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR5188:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5186]], i64 [[LLX_CMPXCHG_DESIRED5187]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV5189:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5188]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV5189]], ptr [[LLX_ATOMIC_EXPECTED_PTR5185]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS5190:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR5188]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL5191:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR5185]], align 8
+// CHECK-NEXT: br i1 [[LLX_CMPXCHG_SUCCESS5190]], label [[LLX_ATOMIC_EXIT5192:%.*]], label [[LLX_ATOMIC_CONT5193:%.*]]
+// CHECK: llx.atomic.cont5193:
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL5191]], ptr [[LLV]], align 8
+// CHECK-NEXT: br label [[LLX_ATOMIC_EXIT5192]]
+// CHECK: llx.atomic.exit5192:
+// CHECK-NEXT: [[TMP2591:%.*]] = sext i1 [[LLX_CMPXCHG_SUCCESS5190]] to i64
+// CHECK-NEXT: store i64 [[TMP2591]], ptr [[LLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2592:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2593:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2592]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2593]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2594:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2595:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2594]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2595]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2596:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2597:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2596]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2597]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2598:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2599:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2598]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2599]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2600:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2601:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2600]], ptr [[ULLX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: store i64 [[TMP2601]], ptr [[ULLX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED]], i64 [[ULLX_CMPXCHG_DESIRED]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5194]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5194]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2602:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2603:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2602]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5195]], align 8
+// CHECK-NEXT: store i64 [[TMP2603]], ptr [[ULLX_ATOMIC_DESIRED_PTR5196]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5198:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5195]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5199:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5196]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5200:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5198]], i64 [[ULLX_CMPXCHG_DESIRED5199]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5201:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5200]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5201]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5197]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5202:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5200]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5203:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5197]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5203]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2604:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2605:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2604]] monotonic, align 8
+// CHECK-NEXT: [[TMP2606:%.*]] = icmp ugt i64 [[TMP2605]], [[TMP2604]]
+// CHECK-NEXT: [[TMP2607:%.*]] = select i1 [[TMP2606]], i64 [[TMP2604]], i64 [[TMP2605]]
+// CHECK-NEXT: store i64 [[TMP2607]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2608:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2609:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2608]] monotonic, align 8
+// CHECK-NEXT: [[TMP2610:%.*]] = icmp ult i64 [[TMP2609]], [[TMP2608]]
+// CHECK-NEXT: [[TMP2611:%.*]] = select i1 [[TMP2610]], i64 [[TMP2608]], i64 [[TMP2609]]
+// CHECK-NEXT: store i64 [[TMP2611]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2612:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2613:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2612]] monotonic, align 8
+// CHECK-NEXT: [[TMP2614:%.*]] = icmp ult i64 [[TMP2613]], [[TMP2612]]
+// CHECK-NEXT: [[TMP2615:%.*]] = select i1 [[TMP2614]], i64 [[TMP2612]], i64 [[TMP2613]]
+// CHECK-NEXT: store i64 [[TMP2615]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2616:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2617:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2616]] monotonic, align 8
+// CHECK-NEXT: [[TMP2618:%.*]] = icmp ugt i64 [[TMP2617]], [[TMP2616]]
+// CHECK-NEXT: [[TMP2619:%.*]] = select i1 [[TMP2618]], i64 [[TMP2616]], i64 [[TMP2617]]
+// CHECK-NEXT: store i64 [[TMP2619]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2620:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2621:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2620]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5204]], align 8
+// CHECK-NEXT: store i64 [[TMP2621]], ptr [[ULLX_ATOMIC_DESIRED_PTR5205]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5207:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5204]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5208:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5205]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5209:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5207]], i64 [[ULLX_CMPXCHG_DESIRED5208]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5210:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5209]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5210]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5206]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5211:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5209]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5212:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5206]], align 8
+// CHECK-NEXT: [[ULLX_CAPTURE_CAPTURED:%.*]] = select i1 [[ULLX_CMPXCHG_SUCCESS5211]], i64 [[TMP2620]], i64 [[ULLX_CAPTURE_ACTUAL5212]]
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_CAPTURED]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2622:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2623:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2622]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5213]], align 8
+// CHECK-NEXT: store i64 [[TMP2623]], ptr [[ULLX_ATOMIC_DESIRED_PTR5214]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5216:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5213]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5217:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5214]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5218:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5216]], i64 [[ULLX_CMPXCHG_DESIRED5217]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5219:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5218]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5219]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5215]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5220:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5218]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5221:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5215]], align 8
+// CHECK-NEXT: [[ULLX_CAPTURE_CAPTURED5222:%.*]] = select i1 [[ULLX_CMPXCHG_SUCCESS5220]], i64 [[TMP2622]], i64 [[ULLX_CAPTURE_ACTUAL5221]]
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_CAPTURED5222]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2624:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2625:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2624]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5223]], align 8
+// CHECK-NEXT: store i64 [[TMP2625]], ptr [[ULLX_ATOMIC_DESIRED_PTR5224]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5226:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5223]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5227:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5224]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5228:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5226]], i64 [[ULLX_CMPXCHG_DESIRED5227]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5229:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5228]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5229]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5225]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5230:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5228]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5231:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5225]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5230]], label [[ULLX_ATOMIC_EXIT:%.*]], label [[ULLX_ATOMIC_CONT:%.*]]
// CHECK: ullx.atomic.cont:
-// CHECK-NEXT: store i64 [[TMP4259]], ptr [[ULLV]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5231]], ptr [[ULLV]], align 8
// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT]]
// CHECK: ullx.atomic.exit:
-// CHECK-NEXT: [[TMP4261:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4262:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4263:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4261]], i64 [[TMP4262]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4264:%.*]] = extractvalue { i64, i1 } [[TMP4263]], 0
-// CHECK-NEXT: [[TMP4265:%.*]] = extractvalue { i64, i1 } [[TMP4263]], 1
-// CHECK-NEXT: br i1 [[TMP4265]], label [[ULLX_ATOMIC_EXIT415:%.*]], label [[ULLX_ATOMIC_CONT416:%.*]]
-// CHECK: ullx.atomic.cont416:
-// CHECK-NEXT: store i64 [[TMP4264]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT415]]
-// CHECK: ullx.atomic.exit415:
-// CHECK-NEXT: [[TMP4266:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4267:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4268:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4266]], i64 [[TMP4267]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4269:%.*]] = extractvalue { i64, i1 } [[TMP4268]], 1
-// CHECK-NEXT: [[TMP4270:%.*]] = zext i1 [[TMP4269]] to i64
-// CHECK-NEXT: store i64 [[TMP4270]], ptr [[ULLR]], align 8
-// CHECK-NEXT: [[TMP4271:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4272:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4273:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4271]], i64 [[TMP4272]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4274:%.*]] = extractvalue { i64, i1 } [[TMP4273]], 1
-// CHECK-NEXT: [[TMP4275:%.*]] = zext i1 [[TMP4274]] to i64
-// CHECK-NEXT: store i64 [[TMP4275]], ptr [[ULLR]], align 8
-// CHECK-NEXT: [[TMP4276:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4277:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4278:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4276]], i64 [[TMP4277]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4279:%.*]] = extractvalue { i64, i1 } [[TMP4278]], 0
-// CHECK-NEXT: [[TMP4280:%.*]] = extractvalue { i64, i1 } [[TMP4278]], 1
-// CHECK-NEXT: br i1 [[TMP4280]], label [[ULLX_ATOMIC_EXIT417:%.*]], label [[ULLX_ATOMIC_CONT418:%.*]]
-// CHECK: ullx.atomic.cont418:
-// CHECK-NEXT: store i64 [[TMP4279]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT417]]
-// CHECK: ullx.atomic.exit417:
-// CHECK-NEXT: [[TMP4281:%.*]] = extractvalue { i64, i1 } [[TMP4278]], 1
-// CHECK-NEXT: [[TMP4282:%.*]] = zext i1 [[TMP4281]] to i64
-// CHECK-NEXT: store i64 [[TMP4282]], ptr [[ULLR]], align 8
-// CHECK-NEXT: [[TMP4283:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4284:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4285:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4283]], i64 [[TMP4284]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4286:%.*]] = extractvalue { i64, i1 } [[TMP4285]], 0
-// CHECK-NEXT: [[TMP4287:%.*]] = extractvalue { i64, i1 } [[TMP4285]], 1
-// CHECK-NEXT: br i1 [[TMP4287]], label [[ULLX_ATOMIC_EXIT419:%.*]], label [[ULLX_ATOMIC_CONT420:%.*]]
-// CHECK: ullx.atomic.cont420:
-// CHECK-NEXT: store i64 [[TMP4286]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT419]]
-// CHECK: ullx.atomic.exit419:
-// CHECK-NEXT: [[TMP4288:%.*]] = extractvalue { i64, i1 } [[TMP4285]], 1
-// CHECK-NEXT: [[TMP4289:%.*]] = zext i1 [[TMP4288]] to i64
-// CHECK-NEXT: store i64 [[TMP4289]], ptr [[ULLR]], align 8
-// CHECK-NEXT: [[TMP4290:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4291:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4290]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP4291]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4292:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4293:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4292]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP4293]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4294:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4295:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4294]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP4295]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4296:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4297:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4296]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP4297]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4298:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4299:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4300:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4298]], i64 [[TMP4299]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP4301:%.*]] = extractvalue { i64, i1 } [[TMP4300]], 0
-// CHECK-NEXT: store i64 [[TMP4301]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4302:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4303:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4304:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4302]], i64 [[TMP4303]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP4305:%.*]] = extractvalue { i64, i1 } [[TMP4304]], 0
-// CHECK-NEXT: store i64 [[TMP4305]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4306:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4307:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4306]] acq_rel, align 8
-// CHECK-NEXT: [[TMP4308:%.*]] = icmp ugt i64 [[TMP4307]], [[TMP4306]]
-// CHECK-NEXT: [[TMP4309:%.*]] = select i1 [[TMP4308]], i64 [[TMP4306]], i64 [[TMP4307]]
-// CHECK-NEXT: store i64 [[TMP4309]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4310:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4311:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4310]] acq_rel, align 8
-// CHECK-NEXT: [[TMP4312:%.*]] = icmp ult i64 [[TMP4311]], [[TMP4310]]
-// CHECK-NEXT: [[TMP4313:%.*]] = select i1 [[TMP4312]], i64 [[TMP4310]], i64 [[TMP4311]]
-// CHECK-NEXT: store i64 [[TMP4313]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4314:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4315:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4314]] acq_rel, align 8
-// CHECK-NEXT: [[TMP4316:%.*]] = icmp ult i64 [[TMP4315]], [[TMP4314]]
-// CHECK-NEXT: [[TMP4317:%.*]] = select i1 [[TMP4316]], i64 [[TMP4314]], i64 [[TMP4315]]
-// CHECK-NEXT: store i64 [[TMP4317]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4318:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4319:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4318]] acq_rel, align 8
-// CHECK-NEXT: [[TMP4320:%.*]] = icmp ugt i64 [[TMP4319]], [[TMP4318]]
-// CHECK-NEXT: [[TMP4321:%.*]] = select i1 [[TMP4320]], i64 [[TMP4318]], i64 [[TMP4319]]
-// CHECK-NEXT: store i64 [[TMP4321]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4322:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4323:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4324:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4322]], i64 [[TMP4323]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP4325:%.*]] = extractvalue { i64, i1 } [[TMP4324]], 0
-// CHECK-NEXT: [[TMP4326:%.*]] = extractvalue { i64, i1 } [[TMP4324]], 1
-// CHECK-NEXT: [[TMP4327:%.*]] = select i1 [[TMP4326]], i64 [[TMP4322]], i64 [[TMP4325]]
-// CHECK-NEXT: store i64 [[TMP4327]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4328:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4329:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4330:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4328]], i64 [[TMP4329]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP4331:%.*]] = extractvalue { i64, i1 } [[TMP4330]], 0
-// CHECK-NEXT: [[TMP4332:%.*]] = extractvalue { i64, i1 } [[TMP4330]], 1
-// CHECK-NEXT: [[TMP4333:%.*]] = select i1 [[TMP4332]], i64 [[TMP4328]], i64 [[TMP4331]]
-// CHECK-NEXT: store i64 [[TMP4333]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4334:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4335:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4336:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4334]], i64 [[TMP4335]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP4337:%.*]] = extractvalue { i64, i1 } [[TMP4336]], 0
-// CHECK-NEXT: [[TMP4338:%.*]] = extractvalue { i64, i1 } [[TMP4336]], 1
-// CHECK-NEXT: br i1 [[TMP4338]], label [[ULLX_ATOMIC_EXIT421:%.*]], label [[ULLX_ATOMIC_CONT422:%.*]]
-// CHECK: ullx.atomic.cont422:
-// CHECK-NEXT: store i64 [[TMP4337]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT421]]
-// CHECK: ullx.atomic.exit421:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4339:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4340:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4341:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4339]], i64 [[TMP4340]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP4342:%.*]] = extractvalue { i64, i1 } [[TMP4341]], 0
-// CHECK-NEXT: [[TMP4343:%.*]] = extractvalue { i64, i1 } [[TMP4341]], 1
-// CHECK-NEXT: br i1 [[TMP4343]], label [[ULLX_ATOMIC_EXIT423:%.*]], label [[ULLX_ATOMIC_CONT424:%.*]]
-// CHECK: ullx.atomic.cont424:
-// CHECK-NEXT: store i64 [[TMP4342]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT423]]
-// CHECK: ullx.atomic.exit423:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4344:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4345:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4346:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4344]], i64 [[TMP4345]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP4347:%.*]] = extractvalue { i64, i1 } [[TMP4346]], 1
-// CHECK-NEXT: [[TMP4348:%.*]] = zext i1 [[TMP4347]] to i64
-// CHECK-NEXT: store i64 [[TMP4348]], ptr [[ULLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4349:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4350:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4351:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4349]], i64 [[TMP4350]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP4352:%.*]] = extractvalue { i64, i1 } [[TMP4351]], 1
-// CHECK-NEXT: [[TMP4353:%.*]] = zext i1 [[TMP4352]] to i64
-// CHECK-NEXT: store i64 [[TMP4353]], ptr [[ULLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4354:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4355:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4356:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4354]], i64 [[TMP4355]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP4357:%.*]] = extractvalue { i64, i1 } [[TMP4356]], 0
-// CHECK-NEXT: [[TMP4358:%.*]] = extractvalue { i64, i1 } [[TMP4356]], 1
-// CHECK-NEXT: br i1 [[TMP4358]], label [[ULLX_ATOMIC_EXIT425:%.*]], label [[ULLX_ATOMIC_CONT426:%.*]]
-// CHECK: ullx.atomic.cont426:
-// CHECK-NEXT: store i64 [[TMP4357]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT425]]
-// CHECK: ullx.atomic.exit425:
-// CHECK-NEXT: [[TMP4359:%.*]] = extractvalue { i64, i1 } [[TMP4356]], 1
-// CHECK-NEXT: [[TMP4360:%.*]] = zext i1 [[TMP4359]] to i64
-// CHECK-NEXT: store i64 [[TMP4360]], ptr [[ULLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4361:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4362:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4363:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4361]], i64 [[TMP4362]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP4364:%.*]] = extractvalue { i64, i1 } [[TMP4363]], 0
-// CHECK-NEXT: [[TMP4365:%.*]] = extractvalue { i64, i1 } [[TMP4363]], 1
-// CHECK-NEXT: br i1 [[TMP4365]], label [[ULLX_ATOMIC_EXIT427:%.*]], label [[ULLX_ATOMIC_CONT428:%.*]]
-// CHECK: ullx.atomic.cont428:
-// CHECK-NEXT: store i64 [[TMP4364]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT427]]
-// CHECK: ullx.atomic.exit427:
-// CHECK-NEXT: [[TMP4366:%.*]] = extractvalue { i64, i1 } [[TMP4363]], 1
-// CHECK-NEXT: [[TMP4367:%.*]] = zext i1 [[TMP4366]] to i64
-// CHECK-NEXT: store i64 [[TMP4367]], ptr [[ULLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4368:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4369:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4368]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP4369]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4370:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4371:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4370]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP4371]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4372:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4373:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4372]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP4373]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4374:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4375:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4374]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP4375]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4376:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4377:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4378:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4376]], i64 [[TMP4377]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP4379:%.*]] = extractvalue { i64, i1 } [[TMP4378]], 0
-// CHECK-NEXT: store i64 [[TMP4379]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4380:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4381:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4382:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4380]], i64 [[TMP4381]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP4383:%.*]] = extractvalue { i64, i1 } [[TMP4382]], 0
-// CHECK-NEXT: store i64 [[TMP4383]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4384:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4385:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4384]] acquire, align 8
-// CHECK-NEXT: [[TMP4386:%.*]] = icmp ugt i64 [[TMP4385]], [[TMP4384]]
-// CHECK-NEXT: [[TMP4387:%.*]] = select i1 [[TMP4386]], i64 [[TMP4384]], i64 [[TMP4385]]
-// CHECK-NEXT: store i64 [[TMP4387]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4388:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4389:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4388]] acquire, align 8
-// CHECK-NEXT: [[TMP4390:%.*]] = icmp ult i64 [[TMP4389]], [[TMP4388]]
-// CHECK-NEXT: [[TMP4391:%.*]] = select i1 [[TMP4390]], i64 [[TMP4388]], i64 [[TMP4389]]
-// CHECK-NEXT: store i64 [[TMP4391]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4392:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4393:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4392]] acquire, align 8
-// CHECK-NEXT: [[TMP4394:%.*]] = icmp ult i64 [[TMP4393]], [[TMP4392]]
-// CHECK-NEXT: [[TMP4395:%.*]] = select i1 [[TMP4394]], i64 [[TMP4392]], i64 [[TMP4393]]
-// CHECK-NEXT: store i64 [[TMP4395]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4396:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4397:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4396]] acquire, align 8
-// CHECK-NEXT: [[TMP4398:%.*]] = icmp ugt i64 [[TMP4397]], [[TMP4396]]
-// CHECK-NEXT: [[TMP4399:%.*]] = select i1 [[TMP4398]], i64 [[TMP4396]], i64 [[TMP4397]]
-// CHECK-NEXT: store i64 [[TMP4399]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4400:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4401:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4402:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4400]], i64 [[TMP4401]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP4403:%.*]] = extractvalue { i64, i1 } [[TMP4402]], 0
-// CHECK-NEXT: [[TMP4404:%.*]] = extractvalue { i64, i1 } [[TMP4402]], 1
-// CHECK-NEXT: [[TMP4405:%.*]] = select i1 [[TMP4404]], i64 [[TMP4400]], i64 [[TMP4403]]
-// CHECK-NEXT: store i64 [[TMP4405]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4406:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4407:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4408:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4406]], i64 [[TMP4407]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP4409:%.*]] = extractvalue { i64, i1 } [[TMP4408]], 0
-// CHECK-NEXT: [[TMP4410:%.*]] = extractvalue { i64, i1 } [[TMP4408]], 1
-// CHECK-NEXT: [[TMP4411:%.*]] = select i1 [[TMP4410]], i64 [[TMP4406]], i64 [[TMP4409]]
-// CHECK-NEXT: store i64 [[TMP4411]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4412:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4413:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4414:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4412]], i64 [[TMP4413]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP4415:%.*]] = extractvalue { i64, i1 } [[TMP4414]], 0
-// CHECK-NEXT: [[TMP4416:%.*]] = extractvalue { i64, i1 } [[TMP4414]], 1
-// CHECK-NEXT: br i1 [[TMP4416]], label [[ULLX_ATOMIC_EXIT429:%.*]], label [[ULLX_ATOMIC_CONT430:%.*]]
-// CHECK: ullx.atomic.cont430:
-// CHECK-NEXT: store i64 [[TMP4415]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT429]]
-// CHECK: ullx.atomic.exit429:
-// CHECK-NEXT: [[TMP4417:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4418:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4419:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4417]], i64 [[TMP4418]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP4420:%.*]] = extractvalue { i64, i1 } [[TMP4419]], 0
-// CHECK-NEXT: [[TMP4421:%.*]] = extractvalue { i64, i1 } [[TMP4419]], 1
-// CHECK-NEXT: br i1 [[TMP4421]], label [[ULLX_ATOMIC_EXIT431:%.*]], label [[ULLX_ATOMIC_CONT432:%.*]]
-// CHECK: ullx.atomic.cont432:
-// CHECK-NEXT: store i64 [[TMP4420]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT431]]
-// CHECK: ullx.atomic.exit431:
-// CHECK-NEXT: [[TMP4422:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4423:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4424:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4422]], i64 [[TMP4423]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP4425:%.*]] = extractvalue { i64, i1 } [[TMP4424]], 1
-// CHECK-NEXT: [[TMP4426:%.*]] = zext i1 [[TMP4425]] to i64
-// CHECK-NEXT: store i64 [[TMP4426]], ptr [[ULLR]], align 8
-// CHECK-NEXT: [[TMP4427:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4428:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4429:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4427]], i64 [[TMP4428]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP4430:%.*]] = extractvalue { i64, i1 } [[TMP4429]], 1
-// CHECK-NEXT: [[TMP4431:%.*]] = zext i1 [[TMP4430]] to i64
-// CHECK-NEXT: store i64 [[TMP4431]], ptr [[ULLR]], align 8
-// CHECK-NEXT: [[TMP4432:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4433:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4434:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4432]], i64 [[TMP4433]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP4435:%.*]] = extractvalue { i64, i1 } [[TMP4434]], 0
-// CHECK-NEXT: [[TMP4436:%.*]] = extractvalue { i64, i1 } [[TMP4434]], 1
-// CHECK-NEXT: br i1 [[TMP4436]], label [[ULLX_ATOMIC_EXIT433:%.*]], label [[ULLX_ATOMIC_CONT434:%.*]]
-// CHECK: ullx.atomic.cont434:
-// CHECK-NEXT: store i64 [[TMP4435]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT433]]
-// CHECK: ullx.atomic.exit433:
-// CHECK-NEXT: [[TMP4437:%.*]] = extractvalue { i64, i1 } [[TMP4434]], 1
-// CHECK-NEXT: [[TMP4438:%.*]] = zext i1 [[TMP4437]] to i64
-// CHECK-NEXT: store i64 [[TMP4438]], ptr [[ULLR]], align 8
-// CHECK-NEXT: [[TMP4439:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4440:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4441:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4439]], i64 [[TMP4440]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP4442:%.*]] = extractvalue { i64, i1 } [[TMP4441]], 0
-// CHECK-NEXT: [[TMP4443:%.*]] = extractvalue { i64, i1 } [[TMP4441]], 1
-// CHECK-NEXT: br i1 [[TMP4443]], label [[ULLX_ATOMIC_EXIT435:%.*]], label [[ULLX_ATOMIC_CONT436:%.*]]
-// CHECK: ullx.atomic.cont436:
-// CHECK-NEXT: store i64 [[TMP4442]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT435]]
-// CHECK: ullx.atomic.exit435:
-// CHECK-NEXT: [[TMP4444:%.*]] = extractvalue { i64, i1 } [[TMP4441]], 1
-// CHECK-NEXT: [[TMP4445:%.*]] = zext i1 [[TMP4444]] to i64
-// CHECK-NEXT: store i64 [[TMP4445]], ptr [[ULLR]], align 8
-// CHECK-NEXT: [[TMP4446:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4447:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4446]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP4447]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4448:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4449:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4448]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP4449]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4450:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4451:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4450]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP4451]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4452:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4453:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4452]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP4453]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4454:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4455:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4456:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4454]], i64 [[TMP4455]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4457:%.*]] = extractvalue { i64, i1 } [[TMP4456]], 0
-// CHECK-NEXT: store i64 [[TMP4457]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4458:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4459:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4460:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4458]], i64 [[TMP4459]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4461:%.*]] = extractvalue { i64, i1 } [[TMP4460]], 0
-// CHECK-NEXT: store i64 [[TMP4461]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4462:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4463:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4462]] monotonic, align 8
-// CHECK-NEXT: [[TMP4464:%.*]] = icmp ugt i64 [[TMP4463]], [[TMP4462]]
-// CHECK-NEXT: [[TMP4465:%.*]] = select i1 [[TMP4464]], i64 [[TMP4462]], i64 [[TMP4463]]
-// CHECK-NEXT: store i64 [[TMP4465]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4466:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4467:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4466]] monotonic, align 8
-// CHECK-NEXT: [[TMP4468:%.*]] = icmp ult i64 [[TMP4467]], [[TMP4466]]
-// CHECK-NEXT: [[TMP4469:%.*]] = select i1 [[TMP4468]], i64 [[TMP4466]], i64 [[TMP4467]]
-// CHECK-NEXT: store i64 [[TMP4469]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4470:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4471:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4470]] monotonic, align 8
-// CHECK-NEXT: [[TMP4472:%.*]] = icmp ult i64 [[TMP4471]], [[TMP4470]]
-// CHECK-NEXT: [[TMP4473:%.*]] = select i1 [[TMP4472]], i64 [[TMP4470]], i64 [[TMP4471]]
-// CHECK-NEXT: store i64 [[TMP4473]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4474:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4475:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4474]] monotonic, align 8
-// CHECK-NEXT: [[TMP4476:%.*]] = icmp ugt i64 [[TMP4475]], [[TMP4474]]
-// CHECK-NEXT: [[TMP4477:%.*]] = select i1 [[TMP4476]], i64 [[TMP4474]], i64 [[TMP4475]]
-// CHECK-NEXT: store i64 [[TMP4477]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4478:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4479:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4480:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4478]], i64 [[TMP4479]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4481:%.*]] = extractvalue { i64, i1 } [[TMP4480]], 0
-// CHECK-NEXT: [[TMP4482:%.*]] = extractvalue { i64, i1 } [[TMP4480]], 1
-// CHECK-NEXT: [[TMP4483:%.*]] = select i1 [[TMP4482]], i64 [[TMP4478]], i64 [[TMP4481]]
-// CHECK-NEXT: store i64 [[TMP4483]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4484:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4485:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4486:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4484]], i64 [[TMP4485]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4487:%.*]] = extractvalue { i64, i1 } [[TMP4486]], 0
-// CHECK-NEXT: [[TMP4488:%.*]] = extractvalue { i64, i1 } [[TMP4486]], 1
-// CHECK-NEXT: [[TMP4489:%.*]] = select i1 [[TMP4488]], i64 [[TMP4484]], i64 [[TMP4487]]
-// CHECK-NEXT: store i64 [[TMP4489]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP4490:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4491:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4492:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4490]], i64 [[TMP4491]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4493:%.*]] = extractvalue { i64, i1 } [[TMP4492]], 0
-// CHECK-NEXT: [[TMP4494:%.*]] = extractvalue { i64, i1 } [[TMP4492]], 1
-// CHECK-NEXT: br i1 [[TMP4494]], label [[ULLX_ATOMIC_EXIT437:%.*]], label [[ULLX_ATOMIC_CONT438:%.*]]
-// CHECK: ullx.atomic.cont438:
-// CHECK-NEXT: store i64 [[TMP4493]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT437]]
-// CHECK: ullx.atomic.exit437:
-// CHECK-NEXT: [[TMP4495:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4496:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4497:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4495]], i64 [[TMP4496]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4498:%.*]] = extractvalue { i64, i1 } [[TMP4497]], 0
-// CHECK-NEXT: [[TMP4499:%.*]] = extractvalue { i64, i1 } [[TMP4497]], 1
-// CHECK-NEXT: br i1 [[TMP4499]], label [[ULLX_ATOMIC_EXIT439:%.*]], label [[ULLX_ATOMIC_CONT440:%.*]]
-// CHECK: ullx.atomic.cont440:
-// CHECK-NEXT: store i64 [[TMP4498]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT439]]
-// CHECK: ullx.atomic.exit439:
-// CHECK-NEXT: [[TMP4500:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4501:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4502:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4500]], i64 [[TMP4501]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4503:%.*]] = extractvalue { i64, i1 } [[TMP4502]], 1
-// CHECK-NEXT: [[TMP4504:%.*]] = zext i1 [[TMP4503]] to i64
-// CHECK-NEXT: store i64 [[TMP4504]], ptr [[ULLR]], align 8
-// CHECK-NEXT: [[TMP4505:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4506:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4507:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4505]], i64 [[TMP4506]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4508:%.*]] = extractvalue { i64, i1 } [[TMP4507]], 1
-// CHECK-NEXT: [[TMP4509:%.*]] = zext i1 [[TMP4508]] to i64
-// CHECK-NEXT: store i64 [[TMP4509]], ptr [[ULLR]], align 8
-// CHECK-NEXT: [[TMP4510:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4511:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4512:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4510]], i64 [[TMP4511]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4513:%.*]] = extractvalue { i64, i1 } [[TMP4512]], 0
-// CHECK-NEXT: [[TMP4514:%.*]] = extractvalue { i64, i1 } [[TMP4512]], 1
-// CHECK-NEXT: br i1 [[TMP4514]], label [[ULLX_ATOMIC_EXIT441:%.*]], label [[ULLX_ATOMIC_CONT442:%.*]]
-// CHECK: ullx.atomic.cont442:
-// CHECK-NEXT: store i64 [[TMP4513]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT441]]
-// CHECK: ullx.atomic.exit441:
-// CHECK-NEXT: [[TMP4515:%.*]] = extractvalue { i64, i1 } [[TMP4512]], 1
-// CHECK-NEXT: [[TMP4516:%.*]] = zext i1 [[TMP4515]] to i64
-// CHECK-NEXT: store i64 [[TMP4516]], ptr [[ULLR]], align 8
-// CHECK-NEXT: [[TMP4517:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4518:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4519:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4517]], i64 [[TMP4518]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP4520:%.*]] = extractvalue { i64, i1 } [[TMP4519]], 0
-// CHECK-NEXT: [[TMP4521:%.*]] = extractvalue { i64, i1 } [[TMP4519]], 1
-// CHECK-NEXT: br i1 [[TMP4521]], label [[ULLX_ATOMIC_EXIT443:%.*]], label [[ULLX_ATOMIC_CONT444:%.*]]
-// CHECK: ullx.atomic.cont444:
-// CHECK-NEXT: store i64 [[TMP4520]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT443]]
-// CHECK: ullx.atomic.exit443:
-// CHECK-NEXT: [[TMP4522:%.*]] = extractvalue { i64, i1 } [[TMP4519]], 1
-// CHECK-NEXT: [[TMP4523:%.*]] = zext i1 [[TMP4522]] to i64
-// CHECK-NEXT: store i64 [[TMP4523]], ptr [[ULLR]], align 8
-// CHECK-NEXT: [[TMP4524:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4525:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4524]] release, align 8
-// CHECK-NEXT: store i64 [[TMP4525]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4526:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4527:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4526]] release, align 8
-// CHECK-NEXT: store i64 [[TMP4527]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4528:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4529:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4528]] release, align 8
-// CHECK-NEXT: store i64 [[TMP4529]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4530:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4531:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4530]] release, align 8
-// CHECK-NEXT: store i64 [[TMP4531]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4532:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4533:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4534:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4532]], i64 [[TMP4533]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4535:%.*]] = extractvalue { i64, i1 } [[TMP4534]], 0
-// CHECK-NEXT: store i64 [[TMP4535]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4536:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4537:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4538:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4536]], i64 [[TMP4537]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4539:%.*]] = extractvalue { i64, i1 } [[TMP4538]], 0
-// CHECK-NEXT: store i64 [[TMP4539]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4540:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4541:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4540]] release, align 8
-// CHECK-NEXT: [[TMP4542:%.*]] = icmp ugt i64 [[TMP4541]], [[TMP4540]]
-// CHECK-NEXT: [[TMP4543:%.*]] = select i1 [[TMP4542]], i64 [[TMP4540]], i64 [[TMP4541]]
-// CHECK-NEXT: store i64 [[TMP4543]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4544:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4545:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4544]] release, align 8
-// CHECK-NEXT: [[TMP4546:%.*]] = icmp ult i64 [[TMP4545]], [[TMP4544]]
-// CHECK-NEXT: [[TMP4547:%.*]] = select i1 [[TMP4546]], i64 [[TMP4544]], i64 [[TMP4545]]
-// CHECK-NEXT: store i64 [[TMP4547]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4548:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4549:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4548]] release, align 8
-// CHECK-NEXT: [[TMP4550:%.*]] = icmp ult i64 [[TMP4549]], [[TMP4548]]
-// CHECK-NEXT: [[TMP4551:%.*]] = select i1 [[TMP4550]], i64 [[TMP4548]], i64 [[TMP4549]]
-// CHECK-NEXT: store i64 [[TMP4551]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4552:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4553:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4552]] release, align 8
-// CHECK-NEXT: [[TMP4554:%.*]] = icmp ugt i64 [[TMP4553]], [[TMP4552]]
-// CHECK-NEXT: [[TMP4555:%.*]] = select i1 [[TMP4554]], i64 [[TMP4552]], i64 [[TMP4553]]
-// CHECK-NEXT: store i64 [[TMP4555]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4556:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4557:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4558:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4556]], i64 [[TMP4557]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4559:%.*]] = extractvalue { i64, i1 } [[TMP4558]], 0
-// CHECK-NEXT: [[TMP4560:%.*]] = extractvalue { i64, i1 } [[TMP4558]], 1
-// CHECK-NEXT: [[TMP4561:%.*]] = select i1 [[TMP4560]], i64 [[TMP4556]], i64 [[TMP4559]]
-// CHECK-NEXT: store i64 [[TMP4561]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4562:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4563:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4564:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4562]], i64 [[TMP4563]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4565:%.*]] = extractvalue { i64, i1 } [[TMP4564]], 0
-// CHECK-NEXT: [[TMP4566:%.*]] = extractvalue { i64, i1 } [[TMP4564]], 1
-// CHECK-NEXT: [[TMP4567:%.*]] = select i1 [[TMP4566]], i64 [[TMP4562]], i64 [[TMP4565]]
-// CHECK-NEXT: store i64 [[TMP4567]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4568:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4569:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4570:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4568]], i64 [[TMP4569]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4571:%.*]] = extractvalue { i64, i1 } [[TMP4570]], 0
-// CHECK-NEXT: [[TMP4572:%.*]] = extractvalue { i64, i1 } [[TMP4570]], 1
-// CHECK-NEXT: br i1 [[TMP4572]], label [[ULLX_ATOMIC_EXIT445:%.*]], label [[ULLX_ATOMIC_CONT446:%.*]]
-// CHECK: ullx.atomic.cont446:
-// CHECK-NEXT: store i64 [[TMP4571]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT445]]
-// CHECK: ullx.atomic.exit445:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4573:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4574:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4575:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4573]], i64 [[TMP4574]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4576:%.*]] = extractvalue { i64, i1 } [[TMP4575]], 0
-// CHECK-NEXT: [[TMP4577:%.*]] = extractvalue { i64, i1 } [[TMP4575]], 1
-// CHECK-NEXT: br i1 [[TMP4577]], label [[ULLX_ATOMIC_EXIT447:%.*]], label [[ULLX_ATOMIC_CONT448:%.*]]
-// CHECK: ullx.atomic.cont448:
-// CHECK-NEXT: store i64 [[TMP4576]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT447]]
-// CHECK: ullx.atomic.exit447:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4578:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4579:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4580:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4578]], i64 [[TMP4579]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4581:%.*]] = extractvalue { i64, i1 } [[TMP4580]], 1
-// CHECK-NEXT: [[TMP4582:%.*]] = zext i1 [[TMP4581]] to i64
-// CHECK-NEXT: store i64 [[TMP4582]], ptr [[ULLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4583:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4584:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4585:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4583]], i64 [[TMP4584]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4586:%.*]] = extractvalue { i64, i1 } [[TMP4585]], 1
-// CHECK-NEXT: [[TMP4587:%.*]] = zext i1 [[TMP4586]] to i64
-// CHECK-NEXT: store i64 [[TMP4587]], ptr [[ULLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4588:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4589:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4590:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4588]], i64 [[TMP4589]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4591:%.*]] = extractvalue { i64, i1 } [[TMP4590]], 0
-// CHECK-NEXT: [[TMP4592:%.*]] = extractvalue { i64, i1 } [[TMP4590]], 1
-// CHECK-NEXT: br i1 [[TMP4592]], label [[ULLX_ATOMIC_EXIT449:%.*]], label [[ULLX_ATOMIC_CONT450:%.*]]
-// CHECK: ullx.atomic.cont450:
-// CHECK-NEXT: store i64 [[TMP4591]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT449]]
-// CHECK: ullx.atomic.exit449:
-// CHECK-NEXT: [[TMP4593:%.*]] = extractvalue { i64, i1 } [[TMP4590]], 1
-// CHECK-NEXT: [[TMP4594:%.*]] = zext i1 [[TMP4593]] to i64
-// CHECK-NEXT: store i64 [[TMP4594]], ptr [[ULLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4595:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4596:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4597:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4595]], i64 [[TMP4596]] release monotonic, align 8
-// CHECK-NEXT: [[TMP4598:%.*]] = extractvalue { i64, i1 } [[TMP4597]], 0
-// CHECK-NEXT: [[TMP4599:%.*]] = extractvalue { i64, i1 } [[TMP4597]], 1
-// CHECK-NEXT: br i1 [[TMP4599]], label [[ULLX_ATOMIC_EXIT451:%.*]], label [[ULLX_ATOMIC_CONT452:%.*]]
-// CHECK: ullx.atomic.cont452:
-// CHECK-NEXT: store i64 [[TMP4598]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT451]]
-// CHECK: ullx.atomic.exit451:
-// CHECK-NEXT: [[TMP4600:%.*]] = extractvalue { i64, i1 } [[TMP4597]], 1
-// CHECK-NEXT: [[TMP4601:%.*]] = zext i1 [[TMP4600]] to i64
-// CHECK-NEXT: store i64 [[TMP4601]], ptr [[ULLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4602:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4603:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4602]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP4603]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4604:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4605:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4604]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP4605]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4606:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4607:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4606]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP4607]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4608:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4609:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4608]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP4609]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4610:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4611:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4612:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4610]], i64 [[TMP4611]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4613:%.*]] = extractvalue { i64, i1 } [[TMP4612]], 0
-// CHECK-NEXT: store i64 [[TMP4613]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4614:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4615:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4616:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4614]], i64 [[TMP4615]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4617:%.*]] = extractvalue { i64, i1 } [[TMP4616]], 0
-// CHECK-NEXT: store i64 [[TMP4617]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4618:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4619:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4618]] seq_cst, align 8
-// CHECK-NEXT: [[TMP4620:%.*]] = icmp ugt i64 [[TMP4619]], [[TMP4618]]
-// CHECK-NEXT: [[TMP4621:%.*]] = select i1 [[TMP4620]], i64 [[TMP4618]], i64 [[TMP4619]]
-// CHECK-NEXT: store i64 [[TMP4621]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4622:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4623:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4622]] seq_cst, align 8
-// CHECK-NEXT: [[TMP4624:%.*]] = icmp ult i64 [[TMP4623]], [[TMP4622]]
-// CHECK-NEXT: [[TMP4625:%.*]] = select i1 [[TMP4624]], i64 [[TMP4622]], i64 [[TMP4623]]
-// CHECK-NEXT: store i64 [[TMP4625]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4626:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4627:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP4626]] seq_cst, align 8
-// CHECK-NEXT: [[TMP4628:%.*]] = icmp ult i64 [[TMP4627]], [[TMP4626]]
-// CHECK-NEXT: [[TMP4629:%.*]] = select i1 [[TMP4628]], i64 [[TMP4626]], i64 [[TMP4627]]
-// CHECK-NEXT: store i64 [[TMP4629]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4630:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4631:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP4630]] seq_cst, align 8
-// CHECK-NEXT: [[TMP4632:%.*]] = icmp ugt i64 [[TMP4631]], [[TMP4630]]
-// CHECK-NEXT: [[TMP4633:%.*]] = select i1 [[TMP4632]], i64 [[TMP4630]], i64 [[TMP4631]]
-// CHECK-NEXT: store i64 [[TMP4633]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4634:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4635:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4636:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4634]], i64 [[TMP4635]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4637:%.*]] = extractvalue { i64, i1 } [[TMP4636]], 0
-// CHECK-NEXT: [[TMP4638:%.*]] = extractvalue { i64, i1 } [[TMP4636]], 1
-// CHECK-NEXT: [[TMP4639:%.*]] = select i1 [[TMP4638]], i64 [[TMP4634]], i64 [[TMP4637]]
-// CHECK-NEXT: store i64 [[TMP4639]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4640:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4641:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4642:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4640]], i64 [[TMP4641]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4643:%.*]] = extractvalue { i64, i1 } [[TMP4642]], 0
-// CHECK-NEXT: [[TMP4644:%.*]] = extractvalue { i64, i1 } [[TMP4642]], 1
-// CHECK-NEXT: [[TMP4645:%.*]] = select i1 [[TMP4644]], i64 [[TMP4640]], i64 [[TMP4643]]
-// CHECK-NEXT: store i64 [[TMP4645]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4646:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4647:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4648:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4646]], i64 [[TMP4647]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4649:%.*]] = extractvalue { i64, i1 } [[TMP4648]], 0
-// CHECK-NEXT: [[TMP4650:%.*]] = extractvalue { i64, i1 } [[TMP4648]], 1
-// CHECK-NEXT: br i1 [[TMP4650]], label [[ULLX_ATOMIC_EXIT453:%.*]], label [[ULLX_ATOMIC_CONT454:%.*]]
-// CHECK: ullx.atomic.cont454:
-// CHECK-NEXT: store i64 [[TMP4649]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT453]]
-// CHECK: ullx.atomic.exit453:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4651:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4652:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4653:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4651]], i64 [[TMP4652]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4654:%.*]] = extractvalue { i64, i1 } [[TMP4653]], 0
-// CHECK-NEXT: [[TMP4655:%.*]] = extractvalue { i64, i1 } [[TMP4653]], 1
-// CHECK-NEXT: br i1 [[TMP4655]], label [[ULLX_ATOMIC_EXIT455:%.*]], label [[ULLX_ATOMIC_CONT456:%.*]]
-// CHECK: ullx.atomic.cont456:
-// CHECK-NEXT: store i64 [[TMP4654]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT455]]
-// CHECK: ullx.atomic.exit455:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4656:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4657:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4658:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4656]], i64 [[TMP4657]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4659:%.*]] = extractvalue { i64, i1 } [[TMP4658]], 1
-// CHECK-NEXT: [[TMP4660:%.*]] = zext i1 [[TMP4659]] to i64
-// CHECK-NEXT: store i64 [[TMP4660]], ptr [[ULLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4661:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4662:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4663:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4661]], i64 [[TMP4662]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4664:%.*]] = extractvalue { i64, i1 } [[TMP4663]], 1
-// CHECK-NEXT: [[TMP4665:%.*]] = zext i1 [[TMP4664]] to i64
-// CHECK-NEXT: store i64 [[TMP4665]], ptr [[ULLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4666:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4667:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4668:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4666]], i64 [[TMP4667]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4669:%.*]] = extractvalue { i64, i1 } [[TMP4668]], 0
-// CHECK-NEXT: [[TMP4670:%.*]] = extractvalue { i64, i1 } [[TMP4668]], 1
-// CHECK-NEXT: br i1 [[TMP4670]], label [[ULLX_ATOMIC_EXIT457:%.*]], label [[ULLX_ATOMIC_CONT458:%.*]]
-// CHECK: ullx.atomic.cont458:
-// CHECK-NEXT: store i64 [[TMP4669]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT457]]
-// CHECK: ullx.atomic.exit457:
-// CHECK-NEXT: [[TMP4671:%.*]] = extractvalue { i64, i1 } [[TMP4668]], 1
-// CHECK-NEXT: [[TMP4672:%.*]] = zext i1 [[TMP4671]] to i64
-// CHECK-NEXT: store i64 [[TMP4672]], ptr [[ULLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4673:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP4674:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP4675:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4673]], i64 [[TMP4674]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP4676:%.*]] = extractvalue { i64, i1 } [[TMP4675]], 0
-// CHECK-NEXT: [[TMP4677:%.*]] = extractvalue { i64, i1 } [[TMP4675]], 1
-// CHECK-NEXT: br i1 [[TMP4677]], label [[ULLX_ATOMIC_EXIT459:%.*]], label [[ULLX_ATOMIC_CONT460:%.*]]
-// CHECK: ullx.atomic.cont460:
-// CHECK-NEXT: store i64 [[TMP4676]], ptr [[ULLV]], align 8
-// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT459]]
-// CHECK: ullx.atomic.exit459:
-// CHECK-NEXT: [[TMP4678:%.*]] = extractvalue { i64, i1 } [[TMP4675]], 1
-// CHECK-NEXT: [[TMP4679:%.*]] = zext i1 [[TMP4678]] to i64
-// CHECK-NEXT: store i64 [[TMP4679]], ptr [[ULLR]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4680:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4681:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4680]] monotonic, align 4
-// CHECK-NEXT: store float [[TMP4681]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4682:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4683:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4682]] monotonic, align 4
-// CHECK-NEXT: store float [[TMP4683]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4684:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4685:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4684]] monotonic, align 4
-// CHECK-NEXT: store float [[TMP4685]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4686:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4687:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4686]] monotonic, align 4
-// CHECK-NEXT: store float [[TMP4687]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4688:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4689:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4690:%.*]] = bitcast float [[TMP4688]] to i32
-// CHECK-NEXT: [[TMP4691:%.*]] = bitcast float [[TMP4689]] to i32
-// CHECK-NEXT: [[TMP4692:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4690]], i32 [[TMP4691]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP4693:%.*]] = extractvalue { i32, i1 } [[TMP4692]], 0
-// CHECK-NEXT: [[TMP4694:%.*]] = bitcast i32 [[TMP4693]] to float
-// CHECK-NEXT: store float [[TMP4694]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4695:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4696:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4697:%.*]] = bitcast float [[TMP4695]] to i32
-// CHECK-NEXT: [[TMP4698:%.*]] = bitcast float [[TMP4696]] to i32
-// CHECK-NEXT: [[TMP4699:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4697]], i32 [[TMP4698]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP4700:%.*]] = extractvalue { i32, i1 } [[TMP4699]], 0
-// CHECK-NEXT: [[TMP4701:%.*]] = bitcast i32 [[TMP4700]] to float
-// CHECK-NEXT: store float [[TMP4701]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4702:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4703:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4702]] monotonic, align 4
-// CHECK-NEXT: [[TMP4704:%.*]] = fcmp ogt float [[TMP4703]], [[TMP4702]]
-// CHECK-NEXT: [[TMP4705:%.*]] = select i1 [[TMP4704]], float [[TMP4702]], float [[TMP4703]]
-// CHECK-NEXT: store float [[TMP4705]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4706:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4707:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4706]] monotonic, align 4
-// CHECK-NEXT: [[TMP4708:%.*]] = fcmp olt float [[TMP4707]], [[TMP4706]]
-// CHECK-NEXT: [[TMP4709:%.*]] = select i1 [[TMP4708]], float [[TMP4706]], float [[TMP4707]]
-// CHECK-NEXT: store float [[TMP4709]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4710:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4711:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4710]] monotonic, align 4
-// CHECK-NEXT: [[TMP4712:%.*]] = fcmp olt float [[TMP4711]], [[TMP4710]]
-// CHECK-NEXT: [[TMP4713:%.*]] = select i1 [[TMP4712]], float [[TMP4710]], float [[TMP4711]]
-// CHECK-NEXT: store float [[TMP4713]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4714:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4715:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4714]] monotonic, align 4
-// CHECK-NEXT: [[TMP4716:%.*]] = fcmp ogt float [[TMP4715]], [[TMP4714]]
-// CHECK-NEXT: [[TMP4717:%.*]] = select i1 [[TMP4716]], float [[TMP4714]], float [[TMP4715]]
-// CHECK-NEXT: store float [[TMP4717]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4718:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4719:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4720:%.*]] = bitcast float [[TMP4718]] to i32
-// CHECK-NEXT: [[TMP4721:%.*]] = bitcast float [[TMP4719]] to i32
-// CHECK-NEXT: [[TMP4722:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4720]], i32 [[TMP4721]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP4723:%.*]] = extractvalue { i32, i1 } [[TMP4722]], 0
-// CHECK-NEXT: [[TMP4724:%.*]] = bitcast i32 [[TMP4723]] to float
-// CHECK-NEXT: [[TMP4725:%.*]] = extractvalue { i32, i1 } [[TMP4722]], 1
-// CHECK-NEXT: [[TMP4726:%.*]] = select i1 [[TMP4725]], float [[TMP4718]], float [[TMP4724]]
-// CHECK-NEXT: store float [[TMP4726]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4727:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4728:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4729:%.*]] = bitcast float [[TMP4727]] to i32
-// CHECK-NEXT: [[TMP4730:%.*]] = bitcast float [[TMP4728]] to i32
-// CHECK-NEXT: [[TMP4731:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4729]], i32 [[TMP4730]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP4732:%.*]] = extractvalue { i32, i1 } [[TMP4731]], 0
-// CHECK-NEXT: [[TMP4733:%.*]] = bitcast i32 [[TMP4732]] to float
-// CHECK-NEXT: [[TMP4734:%.*]] = extractvalue { i32, i1 } [[TMP4731]], 1
-// CHECK-NEXT: [[TMP4735:%.*]] = select i1 [[TMP4734]], float [[TMP4727]], float [[TMP4733]]
-// CHECK-NEXT: store float [[TMP4735]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4736:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4737:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4738:%.*]] = bitcast float [[TMP4736]] to i32
-// CHECK-NEXT: [[TMP4739:%.*]] = bitcast float [[TMP4737]] to i32
-// CHECK-NEXT: [[TMP4740:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4738]], i32 [[TMP4739]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP4741:%.*]] = extractvalue { i32, i1 } [[TMP4740]], 0
-// CHECK-NEXT: [[TMP4742:%.*]] = bitcast i32 [[TMP4741]] to float
-// CHECK-NEXT: [[TMP4743:%.*]] = extractvalue { i32, i1 } [[TMP4740]], 1
-// CHECK-NEXT: br i1 [[TMP4743]], label [[FX_ATOMIC_EXIT:%.*]], label [[FX_ATOMIC_CONT:%.*]]
+// CHECK-NEXT: [[TMP2626:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2627:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2626]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5232]], align 8
+// CHECK-NEXT: store i64 [[TMP2627]], ptr [[ULLX_ATOMIC_DESIRED_PTR5233]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5235:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5232]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5236:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5233]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5237:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5235]], i64 [[ULLX_CMPXCHG_DESIRED5236]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5238:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5237]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5238]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5234]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5239:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5237]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5240:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5234]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5239]], label [[ULLX_ATOMIC_EXIT5241:%.*]], label [[ULLX_ATOMIC_CONT5242:%.*]]
+// CHECK: ullx.atomic.cont5242:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5240]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5241]]
+// CHECK: ullx.atomic.exit5241:
+// CHECK-NEXT: [[TMP2628:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2629:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2628]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5243]], align 8
+// CHECK-NEXT: store i64 [[TMP2629]], ptr [[ULLX_ATOMIC_DESIRED_PTR5244]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5246:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5243]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5247:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5244]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5248:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5246]], i64 [[ULLX_CMPXCHG_DESIRED5247]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5249:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5248]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5249]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5245]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5250:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5248]], 1
+// CHECK-NEXT: [[TMP2630:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5250]] to i64
+// CHECK-NEXT: store i64 [[TMP2630]], ptr [[ULLR]], align 8
+// CHECK-NEXT: [[TMP2631:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2632:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2631]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5251]], align 8
+// CHECK-NEXT: store i64 [[TMP2632]], ptr [[ULLX_ATOMIC_DESIRED_PTR5252]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5254:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5251]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5255:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5252]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5256:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5254]], i64 [[ULLX_CMPXCHG_DESIRED5255]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5257:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5256]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5257]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5253]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5258:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5256]], 1
+// CHECK-NEXT: [[TMP2633:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5258]] to i64
+// CHECK-NEXT: store i64 [[TMP2633]], ptr [[ULLR]], align 8
+// CHECK-NEXT: [[TMP2634:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2635:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2634]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5259]], align 8
+// CHECK-NEXT: store i64 [[TMP2635]], ptr [[ULLX_ATOMIC_DESIRED_PTR5260]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5262:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5259]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5263:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5260]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5264:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5262]], i64 [[ULLX_CMPXCHG_DESIRED5263]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5265:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5264]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5265]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5261]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5266:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5264]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5267:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5261]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5266]], label [[ULLX_ATOMIC_EXIT5268:%.*]], label [[ULLX_ATOMIC_CONT5269:%.*]]
+// CHECK: ullx.atomic.cont5269:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5267]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5268]]
+// CHECK: ullx.atomic.exit5268:
+// CHECK-NEXT: [[TMP2636:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5266]] to i64
+// CHECK-NEXT: store i64 [[TMP2636]], ptr [[ULLR]], align 8
+// CHECK-NEXT: [[TMP2637:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2638:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2637]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5270]], align 8
+// CHECK-NEXT: store i64 [[TMP2638]], ptr [[ULLX_ATOMIC_DESIRED_PTR5271]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5273:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5270]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5274:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5271]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5275:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5273]], i64 [[ULLX_CMPXCHG_DESIRED5274]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5276:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5275]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5276]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5272]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5277:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5275]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5278:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5272]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5277]], label [[ULLX_ATOMIC_EXIT5279:%.*]], label [[ULLX_ATOMIC_CONT5280:%.*]]
+// CHECK: ullx.atomic.cont5280:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5278]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5279]]
+// CHECK: ullx.atomic.exit5279:
+// CHECK-NEXT: [[TMP2639:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5277]] to i64
+// CHECK-NEXT: store i64 [[TMP2639]], ptr [[ULLR]], align 8
+// CHECK-NEXT: [[TMP2640:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2641:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2640]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP2641]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2642:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2643:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2642]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP2643]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2644:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2645:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2644]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP2645]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2646:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2647:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2646]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP2647]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2648:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2649:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2648]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5281]], align 8
+// CHECK-NEXT: store i64 [[TMP2649]], ptr [[ULLX_ATOMIC_DESIRED_PTR5282]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5284:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5281]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5285:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5282]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5286:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5284]], i64 [[ULLX_CMPXCHG_DESIRED5285]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5287:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5286]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5287]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5283]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5288:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5286]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5289:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5283]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5289]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2650:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2651:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2650]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5290]], align 8
+// CHECK-NEXT: store i64 [[TMP2651]], ptr [[ULLX_ATOMIC_DESIRED_PTR5291]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5293:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5290]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5294:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5291]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5295:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5293]], i64 [[ULLX_CMPXCHG_DESIRED5294]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5296:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5295]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5296]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5292]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5297:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5295]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5298:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5292]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5298]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2652:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2653:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2652]] acq_rel, align 8
+// CHECK-NEXT: [[TMP2654:%.*]] = icmp ugt i64 [[TMP2653]], [[TMP2652]]
+// CHECK-NEXT: [[TMP2655:%.*]] = select i1 [[TMP2654]], i64 [[TMP2652]], i64 [[TMP2653]]
+// CHECK-NEXT: store i64 [[TMP2655]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2656:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2657:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2656]] acq_rel, align 8
+// CHECK-NEXT: [[TMP2658:%.*]] = icmp ult i64 [[TMP2657]], [[TMP2656]]
+// CHECK-NEXT: [[TMP2659:%.*]] = select i1 [[TMP2658]], i64 [[TMP2656]], i64 [[TMP2657]]
+// CHECK-NEXT: store i64 [[TMP2659]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2660:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2661:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2660]] acq_rel, align 8
+// CHECK-NEXT: [[TMP2662:%.*]] = icmp ult i64 [[TMP2661]], [[TMP2660]]
+// CHECK-NEXT: [[TMP2663:%.*]] = select i1 [[TMP2662]], i64 [[TMP2660]], i64 [[TMP2661]]
+// CHECK-NEXT: store i64 [[TMP2663]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2664:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2665:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2664]] acq_rel, align 8
+// CHECK-NEXT: [[TMP2666:%.*]] = icmp ugt i64 [[TMP2665]], [[TMP2664]]
+// CHECK-NEXT: [[TMP2667:%.*]] = select i1 [[TMP2666]], i64 [[TMP2664]], i64 [[TMP2665]]
+// CHECK-NEXT: store i64 [[TMP2667]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2668:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2669:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2668]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5299]], align 8
+// CHECK-NEXT: store i64 [[TMP2669]], ptr [[ULLX_ATOMIC_DESIRED_PTR5300]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5302:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5299]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5303:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5300]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5304:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5302]], i64 [[ULLX_CMPXCHG_DESIRED5303]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5305:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5304]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5305]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5301]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5306:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5304]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5307:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5301]], align 8
+// CHECK-NEXT: [[ULLX_CAPTURE_CAPTURED5308:%.*]] = select i1 [[ULLX_CMPXCHG_SUCCESS5306]], i64 [[TMP2668]], i64 [[ULLX_CAPTURE_ACTUAL5307]]
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_CAPTURED5308]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2670:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2671:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2670]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5309]], align 8
+// CHECK-NEXT: store i64 [[TMP2671]], ptr [[ULLX_ATOMIC_DESIRED_PTR5310]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5312:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5309]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5313:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5310]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5314:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5312]], i64 [[ULLX_CMPXCHG_DESIRED5313]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5315:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5314]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5315]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5311]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5316:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5314]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5317:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5311]], align 8
+// CHECK-NEXT: [[ULLX_CAPTURE_CAPTURED5318:%.*]] = select i1 [[ULLX_CMPXCHG_SUCCESS5316]], i64 [[TMP2670]], i64 [[ULLX_CAPTURE_ACTUAL5317]]
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_CAPTURED5318]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2672:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2673:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2672]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5319]], align 8
+// CHECK-NEXT: store i64 [[TMP2673]], ptr [[ULLX_ATOMIC_DESIRED_PTR5320]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5322:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5319]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5323:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5320]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5324:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5322]], i64 [[ULLX_CMPXCHG_DESIRED5323]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5325:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5324]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5325]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5321]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5326:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5324]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5327:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5321]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5326]], label [[ULLX_ATOMIC_EXIT5328:%.*]], label [[ULLX_ATOMIC_CONT5329:%.*]]
+// CHECK: ullx.atomic.cont5329:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5327]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5328]]
+// CHECK: ullx.atomic.exit5328:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2674:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2675:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2674]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5330]], align 8
+// CHECK-NEXT: store i64 [[TMP2675]], ptr [[ULLX_ATOMIC_DESIRED_PTR5331]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5333:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5330]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5334:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5331]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5335:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5333]], i64 [[ULLX_CMPXCHG_DESIRED5334]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5336:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5335]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5336]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5332]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5337:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5335]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5338:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5332]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5337]], label [[ULLX_ATOMIC_EXIT5339:%.*]], label [[ULLX_ATOMIC_CONT5340:%.*]]
+// CHECK: ullx.atomic.cont5340:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5338]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5339]]
+// CHECK: ullx.atomic.exit5339:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2676:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2677:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2676]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5341]], align 8
+// CHECK-NEXT: store i64 [[TMP2677]], ptr [[ULLX_ATOMIC_DESIRED_PTR5342]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5344:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5341]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5345:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5342]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5346:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5344]], i64 [[ULLX_CMPXCHG_DESIRED5345]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5347:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5346]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5347]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5343]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5348:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5346]], 1
+// CHECK-NEXT: [[TMP2678:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5348]] to i64
+// CHECK-NEXT: store i64 [[TMP2678]], ptr [[ULLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2679:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2680:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2679]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5349]], align 8
+// CHECK-NEXT: store i64 [[TMP2680]], ptr [[ULLX_ATOMIC_DESIRED_PTR5350]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5352:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5349]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5353:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5350]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5354:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5352]], i64 [[ULLX_CMPXCHG_DESIRED5353]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5355:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5354]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5355]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5351]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5356:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5354]], 1
+// CHECK-NEXT: [[TMP2681:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5356]] to i64
+// CHECK-NEXT: store i64 [[TMP2681]], ptr [[ULLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2682:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2683:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2682]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5357]], align 8
+// CHECK-NEXT: store i64 [[TMP2683]], ptr [[ULLX_ATOMIC_DESIRED_PTR5358]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5360:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5357]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5361:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5358]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5362:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5360]], i64 [[ULLX_CMPXCHG_DESIRED5361]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5363:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5362]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5363]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5359]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5364:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5362]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5365:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5359]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5364]], label [[ULLX_ATOMIC_EXIT5366:%.*]], label [[ULLX_ATOMIC_CONT5367:%.*]]
+// CHECK: ullx.atomic.cont5367:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5365]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5366]]
+// CHECK: ullx.atomic.exit5366:
+// CHECK-NEXT: [[TMP2684:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5364]] to i64
+// CHECK-NEXT: store i64 [[TMP2684]], ptr [[ULLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2685:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2686:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2685]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5368]], align 8
+// CHECK-NEXT: store i64 [[TMP2686]], ptr [[ULLX_ATOMIC_DESIRED_PTR5369]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5371:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5368]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5372:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5369]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5373:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5371]], i64 [[ULLX_CMPXCHG_DESIRED5372]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5374:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5373]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5374]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5370]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5375:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5373]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5376:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5370]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5375]], label [[ULLX_ATOMIC_EXIT5377:%.*]], label [[ULLX_ATOMIC_CONT5378:%.*]]
+// CHECK: ullx.atomic.cont5378:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5376]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5377]]
+// CHECK: ullx.atomic.exit5377:
+// CHECK-NEXT: [[TMP2687:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5375]] to i64
+// CHECK-NEXT: store i64 [[TMP2687]], ptr [[ULLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2688:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2689:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2688]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP2689]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2690:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2691:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2690]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP2691]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2692:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2693:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2692]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP2693]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2694:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2695:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2694]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP2695]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2696:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2697:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2696]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5379]], align 8
+// CHECK-NEXT: store i64 [[TMP2697]], ptr [[ULLX_ATOMIC_DESIRED_PTR5380]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5382:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5379]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5383:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5380]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5384:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5382]], i64 [[ULLX_CMPXCHG_DESIRED5383]] acquire acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5385:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5384]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5385]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5381]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5386:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5384]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5387:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5381]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5387]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2698:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2699:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2698]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5388]], align 8
+// CHECK-NEXT: store i64 [[TMP2699]], ptr [[ULLX_ATOMIC_DESIRED_PTR5389]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5391:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5388]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5392:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5389]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5393:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5391]], i64 [[ULLX_CMPXCHG_DESIRED5392]] acquire acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5394:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5393]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5394]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5390]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5395:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5393]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5396:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5390]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5396]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2700:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2701:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2700]] acquire, align 8
+// CHECK-NEXT: [[TMP2702:%.*]] = icmp ugt i64 [[TMP2701]], [[TMP2700]]
+// CHECK-NEXT: [[TMP2703:%.*]] = select i1 [[TMP2702]], i64 [[TMP2700]], i64 [[TMP2701]]
+// CHECK-NEXT: store i64 [[TMP2703]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2704:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2705:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2704]] acquire, align 8
+// CHECK-NEXT: [[TMP2706:%.*]] = icmp ult i64 [[TMP2705]], [[TMP2704]]
+// CHECK-NEXT: [[TMP2707:%.*]] = select i1 [[TMP2706]], i64 [[TMP2704]], i64 [[TMP2705]]
+// CHECK-NEXT: store i64 [[TMP2707]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2708:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2709:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2708]] acquire, align 8
+// CHECK-NEXT: [[TMP2710:%.*]] = icmp ult i64 [[TMP2709]], [[TMP2708]]
+// CHECK-NEXT: [[TMP2711:%.*]] = select i1 [[TMP2710]], i64 [[TMP2708]], i64 [[TMP2709]]
+// CHECK-NEXT: store i64 [[TMP2711]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2712:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2713:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2712]] acquire, align 8
+// CHECK-NEXT: [[TMP2714:%.*]] = icmp ugt i64 [[TMP2713]], [[TMP2712]]
+// CHECK-NEXT: [[TMP2715:%.*]] = select i1 [[TMP2714]], i64 [[TMP2712]], i64 [[TMP2713]]
+// CHECK-NEXT: store i64 [[TMP2715]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2716:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2717:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2716]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5397]], align 8
+// CHECK-NEXT: store i64 [[TMP2717]], ptr [[ULLX_ATOMIC_DESIRED_PTR5398]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5400:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5397]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5401:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5398]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5402:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5400]], i64 [[ULLX_CMPXCHG_DESIRED5401]] acquire acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5403:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5402]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5403]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5399]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5404:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5402]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5405:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5399]], align 8
+// CHECK-NEXT: [[ULLX_CAPTURE_CAPTURED5406:%.*]] = select i1 [[ULLX_CMPXCHG_SUCCESS5404]], i64 [[TMP2716]], i64 [[ULLX_CAPTURE_ACTUAL5405]]
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_CAPTURED5406]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2718:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2719:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2718]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5407]], align 8
+// CHECK-NEXT: store i64 [[TMP2719]], ptr [[ULLX_ATOMIC_DESIRED_PTR5408]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5410:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5407]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5411:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5408]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5412:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5410]], i64 [[ULLX_CMPXCHG_DESIRED5411]] acquire acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5413:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5412]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5413]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5409]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5414:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5412]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5415:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5409]], align 8
+// CHECK-NEXT: [[ULLX_CAPTURE_CAPTURED5416:%.*]] = select i1 [[ULLX_CMPXCHG_SUCCESS5414]], i64 [[TMP2718]], i64 [[ULLX_CAPTURE_ACTUAL5415]]
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_CAPTURED5416]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2720:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2721:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2720]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5417]], align 8
+// CHECK-NEXT: store i64 [[TMP2721]], ptr [[ULLX_ATOMIC_DESIRED_PTR5418]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5420:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5417]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5421:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5418]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5422:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5420]], i64 [[ULLX_CMPXCHG_DESIRED5421]] acquire acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5423:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5422]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5423]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5419]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5424:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5422]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5425:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5419]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5424]], label [[ULLX_ATOMIC_EXIT5426:%.*]], label [[ULLX_ATOMIC_CONT5427:%.*]]
+// CHECK: ullx.atomic.cont5427:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5425]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5426]]
+// CHECK: ullx.atomic.exit5426:
+// CHECK-NEXT: [[TMP2722:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2723:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2722]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5428]], align 8
+// CHECK-NEXT: store i64 [[TMP2723]], ptr [[ULLX_ATOMIC_DESIRED_PTR5429]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5431:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5428]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5432:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5429]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5433:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5431]], i64 [[ULLX_CMPXCHG_DESIRED5432]] acquire acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5434:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5433]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5434]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5430]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5435:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5433]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5436:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5430]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5435]], label [[ULLX_ATOMIC_EXIT5437:%.*]], label [[ULLX_ATOMIC_CONT5438:%.*]]
+// CHECK: ullx.atomic.cont5438:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5436]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5437]]
+// CHECK: ullx.atomic.exit5437:
+// CHECK-NEXT: [[TMP2724:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2725:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2724]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5439]], align 8
+// CHECK-NEXT: store i64 [[TMP2725]], ptr [[ULLX_ATOMIC_DESIRED_PTR5440]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5442:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5439]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5443:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5440]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5444:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5442]], i64 [[ULLX_CMPXCHG_DESIRED5443]] acquire acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5445:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5444]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5445]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5441]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5446:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5444]], 1
+// CHECK-NEXT: [[TMP2726:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5446]] to i64
+// CHECK-NEXT: store i64 [[TMP2726]], ptr [[ULLR]], align 8
+// CHECK-NEXT: [[TMP2727:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2728:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2727]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5447]], align 8
+// CHECK-NEXT: store i64 [[TMP2728]], ptr [[ULLX_ATOMIC_DESIRED_PTR5448]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5450:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5447]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5451:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5448]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5452:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5450]], i64 [[ULLX_CMPXCHG_DESIRED5451]] acquire acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5453:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5452]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5453]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5449]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5454:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5452]], 1
+// CHECK-NEXT: [[TMP2729:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5454]] to i64
+// CHECK-NEXT: store i64 [[TMP2729]], ptr [[ULLR]], align 8
+// CHECK-NEXT: [[TMP2730:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2731:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2730]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5455]], align 8
+// CHECK-NEXT: store i64 [[TMP2731]], ptr [[ULLX_ATOMIC_DESIRED_PTR5456]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5458:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5455]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5459:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5456]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5460:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5458]], i64 [[ULLX_CMPXCHG_DESIRED5459]] acquire acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5461:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5460]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5461]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5457]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5462:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5460]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5463:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5457]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5462]], label [[ULLX_ATOMIC_EXIT5464:%.*]], label [[ULLX_ATOMIC_CONT5465:%.*]]
+// CHECK: ullx.atomic.cont5465:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5463]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5464]]
+// CHECK: ullx.atomic.exit5464:
+// CHECK-NEXT: [[TMP2732:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5462]] to i64
+// CHECK-NEXT: store i64 [[TMP2732]], ptr [[ULLR]], align 8
+// CHECK-NEXT: [[TMP2733:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2734:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2733]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5466]], align 8
+// CHECK-NEXT: store i64 [[TMP2734]], ptr [[ULLX_ATOMIC_DESIRED_PTR5467]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5469:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5466]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5470:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5467]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5471:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5469]], i64 [[ULLX_CMPXCHG_DESIRED5470]] acquire acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5472:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5471]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5472]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5468]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5473:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5471]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5474:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5468]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5473]], label [[ULLX_ATOMIC_EXIT5475:%.*]], label [[ULLX_ATOMIC_CONT5476:%.*]]
+// CHECK: ullx.atomic.cont5476:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5474]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5475]]
+// CHECK: ullx.atomic.exit5475:
+// CHECK-NEXT: [[TMP2735:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5473]] to i64
+// CHECK-NEXT: store i64 [[TMP2735]], ptr [[ULLR]], align 8
+// CHECK-NEXT: [[TMP2736:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2737:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2736]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2737]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2738:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2739:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2738]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2739]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2740:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2741:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2740]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2741]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2742:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2743:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2742]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP2743]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2744:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2745:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2744]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5477]], align 8
+// CHECK-NEXT: store i64 [[TMP2745]], ptr [[ULLX_ATOMIC_DESIRED_PTR5478]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5480:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5477]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5481:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5478]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5482:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5480]], i64 [[ULLX_CMPXCHG_DESIRED5481]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5483:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5482]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5483]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5479]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5484:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5482]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5485:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5479]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5485]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2746:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2747:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2746]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5486]], align 8
+// CHECK-NEXT: store i64 [[TMP2747]], ptr [[ULLX_ATOMIC_DESIRED_PTR5487]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5489:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5486]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5490:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5487]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5491:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5489]], i64 [[ULLX_CMPXCHG_DESIRED5490]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5492:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5491]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5492]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5488]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5493:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5491]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5494:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5488]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5494]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2748:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2749:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2748]] monotonic, align 8
+// CHECK-NEXT: [[TMP2750:%.*]] = icmp ugt i64 [[TMP2749]], [[TMP2748]]
+// CHECK-NEXT: [[TMP2751:%.*]] = select i1 [[TMP2750]], i64 [[TMP2748]], i64 [[TMP2749]]
+// CHECK-NEXT: store i64 [[TMP2751]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2752:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2753:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2752]] monotonic, align 8
+// CHECK-NEXT: [[TMP2754:%.*]] = icmp ult i64 [[TMP2753]], [[TMP2752]]
+// CHECK-NEXT: [[TMP2755:%.*]] = select i1 [[TMP2754]], i64 [[TMP2752]], i64 [[TMP2753]]
+// CHECK-NEXT: store i64 [[TMP2755]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2756:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2757:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2756]] monotonic, align 8
+// CHECK-NEXT: [[TMP2758:%.*]] = icmp ult i64 [[TMP2757]], [[TMP2756]]
+// CHECK-NEXT: [[TMP2759:%.*]] = select i1 [[TMP2758]], i64 [[TMP2756]], i64 [[TMP2757]]
+// CHECK-NEXT: store i64 [[TMP2759]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2760:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2761:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2760]] monotonic, align 8
+// CHECK-NEXT: [[TMP2762:%.*]] = icmp ugt i64 [[TMP2761]], [[TMP2760]]
+// CHECK-NEXT: [[TMP2763:%.*]] = select i1 [[TMP2762]], i64 [[TMP2760]], i64 [[TMP2761]]
+// CHECK-NEXT: store i64 [[TMP2763]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2764:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2765:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2764]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5495]], align 8
+// CHECK-NEXT: store i64 [[TMP2765]], ptr [[ULLX_ATOMIC_DESIRED_PTR5496]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5498:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5495]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5499:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5496]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5500:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5498]], i64 [[ULLX_CMPXCHG_DESIRED5499]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5501:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5500]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5501]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5497]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5502:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5500]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5503:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5497]], align 8
+// CHECK-NEXT: [[ULLX_CAPTURE_CAPTURED5504:%.*]] = select i1 [[ULLX_CMPXCHG_SUCCESS5502]], i64 [[TMP2764]], i64 [[ULLX_CAPTURE_ACTUAL5503]]
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_CAPTURED5504]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2766:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2767:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2766]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5505]], align 8
+// CHECK-NEXT: store i64 [[TMP2767]], ptr [[ULLX_ATOMIC_DESIRED_PTR5506]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5508:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5505]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5509:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5506]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5510:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5508]], i64 [[ULLX_CMPXCHG_DESIRED5509]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5511:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5510]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5511]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5507]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5512:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5510]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5513:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5507]], align 8
+// CHECK-NEXT: [[ULLX_CAPTURE_CAPTURED5514:%.*]] = select i1 [[ULLX_CMPXCHG_SUCCESS5512]], i64 [[TMP2766]], i64 [[ULLX_CAPTURE_ACTUAL5513]]
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_CAPTURED5514]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP2768:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2769:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2768]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5515]], align 8
+// CHECK-NEXT: store i64 [[TMP2769]], ptr [[ULLX_ATOMIC_DESIRED_PTR5516]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5518:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5515]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5519:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5516]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5520:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5518]], i64 [[ULLX_CMPXCHG_DESIRED5519]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5521:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5520]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5521]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5517]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5522:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5520]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5523:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5517]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5522]], label [[ULLX_ATOMIC_EXIT5524:%.*]], label [[ULLX_ATOMIC_CONT5525:%.*]]
+// CHECK: ullx.atomic.cont5525:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5523]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5524]]
+// CHECK: ullx.atomic.exit5524:
+// CHECK-NEXT: [[TMP2770:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2771:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2770]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5526]], align 8
+// CHECK-NEXT: store i64 [[TMP2771]], ptr [[ULLX_ATOMIC_DESIRED_PTR5527]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5529:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5526]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5530:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5527]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5531:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5529]], i64 [[ULLX_CMPXCHG_DESIRED5530]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5532:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5531]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5532]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5528]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5533:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5531]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5534:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5528]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5533]], label [[ULLX_ATOMIC_EXIT5535:%.*]], label [[ULLX_ATOMIC_CONT5536:%.*]]
+// CHECK: ullx.atomic.cont5536:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5534]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5535]]
+// CHECK: ullx.atomic.exit5535:
+// CHECK-NEXT: [[TMP2772:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2773:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2772]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5537]], align 8
+// CHECK-NEXT: store i64 [[TMP2773]], ptr [[ULLX_ATOMIC_DESIRED_PTR5538]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5540:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5537]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5541:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5538]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5542:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5540]], i64 [[ULLX_CMPXCHG_DESIRED5541]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5543:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5542]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5543]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5539]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5544:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5542]], 1
+// CHECK-NEXT: [[TMP2774:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5544]] to i64
+// CHECK-NEXT: store i64 [[TMP2774]], ptr [[ULLR]], align 8
+// CHECK-NEXT: [[TMP2775:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2776:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2775]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5545]], align 8
+// CHECK-NEXT: store i64 [[TMP2776]], ptr [[ULLX_ATOMIC_DESIRED_PTR5546]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5548:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5545]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5549:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5546]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5550:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5548]], i64 [[ULLX_CMPXCHG_DESIRED5549]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5551:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5550]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5551]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5547]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5552:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5550]], 1
+// CHECK-NEXT: [[TMP2777:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5552]] to i64
+// CHECK-NEXT: store i64 [[TMP2777]], ptr [[ULLR]], align 8
+// CHECK-NEXT: [[TMP2778:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2779:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2778]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5553]], align 8
+// CHECK-NEXT: store i64 [[TMP2779]], ptr [[ULLX_ATOMIC_DESIRED_PTR5554]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5556:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5553]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5557:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5554]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5558:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5556]], i64 [[ULLX_CMPXCHG_DESIRED5557]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5559:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5558]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5559]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5555]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5560:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5558]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5561:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5555]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5560]], label [[ULLX_ATOMIC_EXIT5562:%.*]], label [[ULLX_ATOMIC_CONT5563:%.*]]
+// CHECK: ullx.atomic.cont5563:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5561]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5562]]
+// CHECK: ullx.atomic.exit5562:
+// CHECK-NEXT: [[TMP2780:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5560]] to i64
+// CHECK-NEXT: store i64 [[TMP2780]], ptr [[ULLR]], align 8
+// CHECK-NEXT: [[TMP2781:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2782:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2781]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5564]], align 8
+// CHECK-NEXT: store i64 [[TMP2782]], ptr [[ULLX_ATOMIC_DESIRED_PTR5565]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5567:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5564]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5568:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5565]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5569:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5567]], i64 [[ULLX_CMPXCHG_DESIRED5568]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5570:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5569]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5570]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5566]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5571:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5569]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5572:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5566]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5571]], label [[ULLX_ATOMIC_EXIT5573:%.*]], label [[ULLX_ATOMIC_CONT5574:%.*]]
+// CHECK: ullx.atomic.cont5574:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5572]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5573]]
+// CHECK: ullx.atomic.exit5573:
+// CHECK-NEXT: [[TMP2783:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5571]] to i64
+// CHECK-NEXT: store i64 [[TMP2783]], ptr [[ULLR]], align 8
+// CHECK-NEXT: [[TMP2784:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2785:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2784]] release, align 8
+// CHECK-NEXT: store i64 [[TMP2785]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2786:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2787:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2786]] release, align 8
+// CHECK-NEXT: store i64 [[TMP2787]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2788:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2789:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2788]] release, align 8
+// CHECK-NEXT: store i64 [[TMP2789]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2790:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2791:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2790]] release, align 8
+// CHECK-NEXT: store i64 [[TMP2791]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2792:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2793:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2792]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5575]], align 8
+// CHECK-NEXT: store i64 [[TMP2793]], ptr [[ULLX_ATOMIC_DESIRED_PTR5576]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5578:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5575]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5579:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5576]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5580:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5578]], i64 [[ULLX_CMPXCHG_DESIRED5579]] release monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5581:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5580]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5581]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5577]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5582:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5580]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5583:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5577]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5583]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2794:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2795:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2794]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5584]], align 8
+// CHECK-NEXT: store i64 [[TMP2795]], ptr [[ULLX_ATOMIC_DESIRED_PTR5585]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5587:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5584]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5588:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5585]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5589:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5587]], i64 [[ULLX_CMPXCHG_DESIRED5588]] release monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5590:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5589]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5590]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5586]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5591:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5589]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5592:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5586]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5592]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2796:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2797:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2796]] release, align 8
+// CHECK-NEXT: [[TMP2798:%.*]] = icmp ugt i64 [[TMP2797]], [[TMP2796]]
+// CHECK-NEXT: [[TMP2799:%.*]] = select i1 [[TMP2798]], i64 [[TMP2796]], i64 [[TMP2797]]
+// CHECK-NEXT: store i64 [[TMP2799]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2800:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2801:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2800]] release, align 8
+// CHECK-NEXT: [[TMP2802:%.*]] = icmp ult i64 [[TMP2801]], [[TMP2800]]
+// CHECK-NEXT: [[TMP2803:%.*]] = select i1 [[TMP2802]], i64 [[TMP2800]], i64 [[TMP2801]]
+// CHECK-NEXT: store i64 [[TMP2803]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2804:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2805:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2804]] release, align 8
+// CHECK-NEXT: [[TMP2806:%.*]] = icmp ult i64 [[TMP2805]], [[TMP2804]]
+// CHECK-NEXT: [[TMP2807:%.*]] = select i1 [[TMP2806]], i64 [[TMP2804]], i64 [[TMP2805]]
+// CHECK-NEXT: store i64 [[TMP2807]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2808:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2809:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2808]] release, align 8
+// CHECK-NEXT: [[TMP2810:%.*]] = icmp ugt i64 [[TMP2809]], [[TMP2808]]
+// CHECK-NEXT: [[TMP2811:%.*]] = select i1 [[TMP2810]], i64 [[TMP2808]], i64 [[TMP2809]]
+// CHECK-NEXT: store i64 [[TMP2811]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2812:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2813:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2812]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5593]], align 8
+// CHECK-NEXT: store i64 [[TMP2813]], ptr [[ULLX_ATOMIC_DESIRED_PTR5594]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5596:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5593]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5597:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5594]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5598:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5596]], i64 [[ULLX_CMPXCHG_DESIRED5597]] release monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5599:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5598]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5599]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5595]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5600:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5598]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5601:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5595]], align 8
+// CHECK-NEXT: [[ULLX_CAPTURE_CAPTURED5602:%.*]] = select i1 [[ULLX_CMPXCHG_SUCCESS5600]], i64 [[TMP2812]], i64 [[ULLX_CAPTURE_ACTUAL5601]]
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_CAPTURED5602]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2814:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2815:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2814]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5603]], align 8
+// CHECK-NEXT: store i64 [[TMP2815]], ptr [[ULLX_ATOMIC_DESIRED_PTR5604]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5606:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5603]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5607:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5604]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5608:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5606]], i64 [[ULLX_CMPXCHG_DESIRED5607]] release monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5609:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5608]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5609]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5605]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5610:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5608]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5611:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5605]], align 8
+// CHECK-NEXT: [[ULLX_CAPTURE_CAPTURED5612:%.*]] = select i1 [[ULLX_CMPXCHG_SUCCESS5610]], i64 [[TMP2814]], i64 [[ULLX_CAPTURE_ACTUAL5611]]
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_CAPTURED5612]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2816:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2817:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2816]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5613]], align 8
+// CHECK-NEXT: store i64 [[TMP2817]], ptr [[ULLX_ATOMIC_DESIRED_PTR5614]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5616:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5613]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5617:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5614]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5618:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5616]], i64 [[ULLX_CMPXCHG_DESIRED5617]] release monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5619:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5618]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5619]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5615]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5620:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5618]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5621:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5615]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5620]], label [[ULLX_ATOMIC_EXIT5622:%.*]], label [[ULLX_ATOMIC_CONT5623:%.*]]
+// CHECK: ullx.atomic.cont5623:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5621]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5622]]
+// CHECK: ullx.atomic.exit5622:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2818:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2819:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2818]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5624]], align 8
+// CHECK-NEXT: store i64 [[TMP2819]], ptr [[ULLX_ATOMIC_DESIRED_PTR5625]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5627:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5624]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5628:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5625]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5629:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5627]], i64 [[ULLX_CMPXCHG_DESIRED5628]] release monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5630:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5629]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5630]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5626]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5631:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5629]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5632:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5626]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5631]], label [[ULLX_ATOMIC_EXIT5633:%.*]], label [[ULLX_ATOMIC_CONT5634:%.*]]
+// CHECK: ullx.atomic.cont5634:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5632]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5633]]
+// CHECK: ullx.atomic.exit5633:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2820:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2821:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2820]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5635]], align 8
+// CHECK-NEXT: store i64 [[TMP2821]], ptr [[ULLX_ATOMIC_DESIRED_PTR5636]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5638:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5635]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5639:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5636]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5640:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5638]], i64 [[ULLX_CMPXCHG_DESIRED5639]] release monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5641:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5640]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5641]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5637]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5642:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5640]], 1
+// CHECK-NEXT: [[TMP2822:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5642]] to i64
+// CHECK-NEXT: store i64 [[TMP2822]], ptr [[ULLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2823:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2824:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2823]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5643]], align 8
+// CHECK-NEXT: store i64 [[TMP2824]], ptr [[ULLX_ATOMIC_DESIRED_PTR5644]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5646:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5643]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5647:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5644]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5648:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5646]], i64 [[ULLX_CMPXCHG_DESIRED5647]] release monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5649:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5648]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5649]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5645]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5650:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5648]], 1
+// CHECK-NEXT: [[TMP2825:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5650]] to i64
+// CHECK-NEXT: store i64 [[TMP2825]], ptr [[ULLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2826:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2827:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2826]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5651]], align 8
+// CHECK-NEXT: store i64 [[TMP2827]], ptr [[ULLX_ATOMIC_DESIRED_PTR5652]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5654:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5651]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5655:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5652]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5656:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5654]], i64 [[ULLX_CMPXCHG_DESIRED5655]] release monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5657:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5656]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5657]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5653]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5658:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5656]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5659:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5653]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5658]], label [[ULLX_ATOMIC_EXIT5660:%.*]], label [[ULLX_ATOMIC_CONT5661:%.*]]
+// CHECK: ullx.atomic.cont5661:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5659]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5660]]
+// CHECK: ullx.atomic.exit5660:
+// CHECK-NEXT: [[TMP2828:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5658]] to i64
+// CHECK-NEXT: store i64 [[TMP2828]], ptr [[ULLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2829:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2830:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2829]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5662]], align 8
+// CHECK-NEXT: store i64 [[TMP2830]], ptr [[ULLX_ATOMIC_DESIRED_PTR5663]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5665:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5662]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5666:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5663]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5667:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5665]], i64 [[ULLX_CMPXCHG_DESIRED5666]] release monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5668:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5667]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5668]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5664]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5669:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5667]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5670:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5664]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5669]], label [[ULLX_ATOMIC_EXIT5671:%.*]], label [[ULLX_ATOMIC_CONT5672:%.*]]
+// CHECK: ullx.atomic.cont5672:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5670]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5671]]
+// CHECK: ullx.atomic.exit5671:
+// CHECK-NEXT: [[TMP2831:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5669]] to i64
+// CHECK-NEXT: store i64 [[TMP2831]], ptr [[ULLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2832:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2833:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2832]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP2833]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2834:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2835:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2834]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP2835]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2836:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2837:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2836]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP2837]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2838:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2839:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2838]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP2839]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2840:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2841:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2840]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5673]], align 8
+// CHECK-NEXT: store i64 [[TMP2841]], ptr [[ULLX_ATOMIC_DESIRED_PTR5674]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5676:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5673]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5677:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5674]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5678:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5676]], i64 [[ULLX_CMPXCHG_DESIRED5677]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5679:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5678]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5679]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5675]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5680:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5678]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5681:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5675]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5681]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2842:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2843:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2842]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5682]], align 8
+// CHECK-NEXT: store i64 [[TMP2843]], ptr [[ULLX_ATOMIC_DESIRED_PTR5683]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5685:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5682]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5686:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5683]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5687:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5685]], i64 [[ULLX_CMPXCHG_DESIRED5686]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5688:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5687]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5688]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5684]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5689:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5687]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5690:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5684]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5690]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2844:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2845:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2844]] seq_cst, align 8
+// CHECK-NEXT: [[TMP2846:%.*]] = icmp ugt i64 [[TMP2845]], [[TMP2844]]
+// CHECK-NEXT: [[TMP2847:%.*]] = select i1 [[TMP2846]], i64 [[TMP2844]], i64 [[TMP2845]]
+// CHECK-NEXT: store i64 [[TMP2847]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2848:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2849:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2848]] seq_cst, align 8
+// CHECK-NEXT: [[TMP2850:%.*]] = icmp ult i64 [[TMP2849]], [[TMP2848]]
+// CHECK-NEXT: [[TMP2851:%.*]] = select i1 [[TMP2850]], i64 [[TMP2848]], i64 [[TMP2849]]
+// CHECK-NEXT: store i64 [[TMP2851]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2852:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2853:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP2852]] seq_cst, align 8
+// CHECK-NEXT: [[TMP2854:%.*]] = icmp ult i64 [[TMP2853]], [[TMP2852]]
+// CHECK-NEXT: [[TMP2855:%.*]] = select i1 [[TMP2854]], i64 [[TMP2852]], i64 [[TMP2853]]
+// CHECK-NEXT: store i64 [[TMP2855]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2856:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2857:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP2856]] seq_cst, align 8
+// CHECK-NEXT: [[TMP2858:%.*]] = icmp ugt i64 [[TMP2857]], [[TMP2856]]
+// CHECK-NEXT: [[TMP2859:%.*]] = select i1 [[TMP2858]], i64 [[TMP2856]], i64 [[TMP2857]]
+// CHECK-NEXT: store i64 [[TMP2859]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2860:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2861:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2860]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5691]], align 8
+// CHECK-NEXT: store i64 [[TMP2861]], ptr [[ULLX_ATOMIC_DESIRED_PTR5692]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5694:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5691]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5695:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5692]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5696:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5694]], i64 [[ULLX_CMPXCHG_DESIRED5695]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5697:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5696]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5697]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5693]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5698:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5696]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5699:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5693]], align 8
+// CHECK-NEXT: [[ULLX_CAPTURE_CAPTURED5700:%.*]] = select i1 [[ULLX_CMPXCHG_SUCCESS5698]], i64 [[TMP2860]], i64 [[ULLX_CAPTURE_ACTUAL5699]]
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_CAPTURED5700]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2862:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2863:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2862]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5701]], align 8
+// CHECK-NEXT: store i64 [[TMP2863]], ptr [[ULLX_ATOMIC_DESIRED_PTR5702]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5704:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5701]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5705:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5702]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5706:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5704]], i64 [[ULLX_CMPXCHG_DESIRED5705]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5707:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5706]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5707]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5703]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5708:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5706]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5709:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5703]], align 8
+// CHECK-NEXT: [[ULLX_CAPTURE_CAPTURED5710:%.*]] = select i1 [[ULLX_CMPXCHG_SUCCESS5708]], i64 [[TMP2862]], i64 [[ULLX_CAPTURE_ACTUAL5709]]
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_CAPTURED5710]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2864:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2865:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2864]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5711]], align 8
+// CHECK-NEXT: store i64 [[TMP2865]], ptr [[ULLX_ATOMIC_DESIRED_PTR5712]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5714:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5711]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5715:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5712]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5716:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5714]], i64 [[ULLX_CMPXCHG_DESIRED5715]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5717:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5716]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5717]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5713]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5718:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5716]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5719:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5713]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5718]], label [[ULLX_ATOMIC_EXIT5720:%.*]], label [[ULLX_ATOMIC_CONT5721:%.*]]
+// CHECK: ullx.atomic.cont5721:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5719]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5720]]
+// CHECK: ullx.atomic.exit5720:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2866:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2867:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2866]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5722]], align 8
+// CHECK-NEXT: store i64 [[TMP2867]], ptr [[ULLX_ATOMIC_DESIRED_PTR5723]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5725:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5722]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5726:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5723]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5727:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5725]], i64 [[ULLX_CMPXCHG_DESIRED5726]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5728:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5727]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5728]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5724]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5729:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5727]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5730:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5724]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5729]], label [[ULLX_ATOMIC_EXIT5731:%.*]], label [[ULLX_ATOMIC_CONT5732:%.*]]
+// CHECK: ullx.atomic.cont5732:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5730]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5731]]
+// CHECK: ullx.atomic.exit5731:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2868:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2869:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2868]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5733]], align 8
+// CHECK-NEXT: store i64 [[TMP2869]], ptr [[ULLX_ATOMIC_DESIRED_PTR5734]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5736:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5733]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5737:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5734]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5738:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5736]], i64 [[ULLX_CMPXCHG_DESIRED5737]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5739:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5738]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5739]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5735]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5740:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5738]], 1
+// CHECK-NEXT: [[TMP2870:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5740]] to i64
+// CHECK-NEXT: store i64 [[TMP2870]], ptr [[ULLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2871:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2872:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2871]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5741]], align 8
+// CHECK-NEXT: store i64 [[TMP2872]], ptr [[ULLX_ATOMIC_DESIRED_PTR5742]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5744:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5741]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5745:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5742]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5746:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5744]], i64 [[ULLX_CMPXCHG_DESIRED5745]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5747:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5746]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5747]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5743]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5748:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5746]], 1
+// CHECK-NEXT: [[TMP2873:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5748]] to i64
+// CHECK-NEXT: store i64 [[TMP2873]], ptr [[ULLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2874:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2875:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2874]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5749]], align 8
+// CHECK-NEXT: store i64 [[TMP2875]], ptr [[ULLX_ATOMIC_DESIRED_PTR5750]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5752:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5749]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5753:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5750]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5754:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5752]], i64 [[ULLX_CMPXCHG_DESIRED5753]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5755:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5754]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5755]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5751]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5756:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5754]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5757:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5751]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5756]], label [[ULLX_ATOMIC_EXIT5758:%.*]], label [[ULLX_ATOMIC_CONT5759:%.*]]
+// CHECK: ullx.atomic.cont5759:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5757]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5758]]
+// CHECK: ullx.atomic.exit5758:
+// CHECK-NEXT: [[TMP2876:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5756]] to i64
+// CHECK-NEXT: store i64 [[TMP2876]], ptr [[ULLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2877:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP2878:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP2877]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5760]], align 8
+// CHECK-NEXT: store i64 [[TMP2878]], ptr [[ULLX_ATOMIC_DESIRED_PTR5761]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5763:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5760]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED5764:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR5761]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR5765:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5763]], i64 [[ULLX_CMPXCHG_DESIRED5764]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV5766:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5765]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV5766]], ptr [[ULLX_ATOMIC_EXPECTED_PTR5762]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS5767:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR5765]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL5768:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR5762]], align 8
+// CHECK-NEXT: br i1 [[ULLX_CMPXCHG_SUCCESS5767]], label [[ULLX_ATOMIC_EXIT5769:%.*]], label [[ULLX_ATOMIC_CONT5770:%.*]]
+// CHECK: ullx.atomic.cont5770:
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL5768]], ptr [[ULLV]], align 8
+// CHECK-NEXT: br label [[ULLX_ATOMIC_EXIT5769]]
+// CHECK: ullx.atomic.exit5769:
+// CHECK-NEXT: [[TMP2879:%.*]] = zext i1 [[ULLX_CMPXCHG_SUCCESS5767]] to i64
+// CHECK-NEXT: store i64 [[TMP2879]], ptr [[ULLR]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2880:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2881:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP2880]] monotonic, align 4
+// CHECK-NEXT: store float [[TMP2881]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2882:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2883:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP2882]] monotonic, align 4
+// CHECK-NEXT: store float [[TMP2883]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2884:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2885:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP2884]] monotonic, align 4
+// CHECK-NEXT: store float [[TMP2885]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2886:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2887:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP2886]] monotonic, align 4
+// CHECK-NEXT: store float [[TMP2887]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2888:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2889:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2888]], ptr [[FX_ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: store float [[TMP2889]], ptr [[FX_ATOMIC_DESIRED_PTR]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED]], i32 [[FX_CMPXCHG_DESIRED]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV]], ptr [[FX_ATOMIC_EXPECTED_PTR5771]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5771]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2890:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2891:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2890]], ptr [[FX_ATOMIC_EXPECTED_PTR5772]], align 4
+// CHECK-NEXT: store float [[TMP2891]], ptr [[FX_ATOMIC_DESIRED_PTR5773]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5775:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5772]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5776:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5773]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5777:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5775]], i32 [[FX_CMPXCHG_DESIRED5776]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5778:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5777]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5778]], ptr [[FX_ATOMIC_EXPECTED_PTR5774]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5779:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5777]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5780:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5774]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL5780]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2892:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2893:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP2892]] monotonic, align 4
+// CHECK-NEXT: [[TMP2894:%.*]] = fcmp ogt float [[TMP2893]], [[TMP2892]]
+// CHECK-NEXT: [[TMP2895:%.*]] = select i1 [[TMP2894]], float [[TMP2892]], float [[TMP2893]]
+// CHECK-NEXT: store float [[TMP2895]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2896:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2897:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP2896]] monotonic, align 4
+// CHECK-NEXT: [[TMP2898:%.*]] = fcmp olt float [[TMP2897]], [[TMP2896]]
+// CHECK-NEXT: [[TMP2899:%.*]] = select i1 [[TMP2898]], float [[TMP2896]], float [[TMP2897]]
+// CHECK-NEXT: store float [[TMP2899]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2900:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2901:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP2900]] monotonic, align 4
+// CHECK-NEXT: [[TMP2902:%.*]] = fcmp olt float [[TMP2901]], [[TMP2900]]
+// CHECK-NEXT: [[TMP2903:%.*]] = select i1 [[TMP2902]], float [[TMP2900]], float [[TMP2901]]
+// CHECK-NEXT: store float [[TMP2903]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2904:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2905:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP2904]] monotonic, align 4
+// CHECK-NEXT: [[TMP2906:%.*]] = fcmp ogt float [[TMP2905]], [[TMP2904]]
+// CHECK-NEXT: [[TMP2907:%.*]] = select i1 [[TMP2906]], float [[TMP2904]], float [[TMP2905]]
+// CHECK-NEXT: store float [[TMP2907]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2908:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2909:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2908]], ptr [[FX_ATOMIC_EXPECTED_PTR5781]], align 4
+// CHECK-NEXT: store float [[TMP2909]], ptr [[FX_ATOMIC_DESIRED_PTR5782]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5784:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5781]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5785:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5782]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5786:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5784]], i32 [[FX_CMPXCHG_DESIRED5785]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5787:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5786]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5787]], ptr [[FX_ATOMIC_EXPECTED_PTR5783]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5788:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5786]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5789:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5783]], align 4
+// CHECK-NEXT: [[FX_CAPTURE_CAPTURED:%.*]] = select i1 [[FX_CMPXCHG_SUCCESS5788]], float [[TMP2908]], float [[FX_CAPTURE_ACTUAL5789]]
+// CHECK-NEXT: store float [[FX_CAPTURE_CAPTURED]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2910:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2911:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2910]], ptr [[FX_ATOMIC_EXPECTED_PTR5790]], align 4
+// CHECK-NEXT: store float [[TMP2911]], ptr [[FX_ATOMIC_DESIRED_PTR5791]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5793:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5790]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5794:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5791]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5795:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5793]], i32 [[FX_CMPXCHG_DESIRED5794]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5796:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5795]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5796]], ptr [[FX_ATOMIC_EXPECTED_PTR5792]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5797:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5795]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5798:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5792]], align 4
+// CHECK-NEXT: [[FX_CAPTURE_CAPTURED5799:%.*]] = select i1 [[FX_CMPXCHG_SUCCESS5797]], float [[TMP2910]], float [[FX_CAPTURE_ACTUAL5798]]
+// CHECK-NEXT: store float [[FX_CAPTURE_CAPTURED5799]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2912:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2913:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2912]], ptr [[FX_ATOMIC_EXPECTED_PTR5800]], align 4
+// CHECK-NEXT: store float [[TMP2913]], ptr [[FX_ATOMIC_DESIRED_PTR5801]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5803:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5800]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5804:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5801]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5805:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5803]], i32 [[FX_CMPXCHG_DESIRED5804]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5806:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5805]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5806]], ptr [[FX_ATOMIC_EXPECTED_PTR5802]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5807:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5805]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5808:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5802]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS5807]], label [[FX_ATOMIC_EXIT:%.*]], label [[FX_ATOMIC_CONT:%.*]]
// CHECK: fx.atomic.cont:
-// CHECK-NEXT: store float [[TMP4742]], ptr [[FV]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL5808]], ptr [[FV]], align 4
// CHECK-NEXT: br label [[FX_ATOMIC_EXIT]]
// CHECK: fx.atomic.exit:
-// CHECK-NEXT: [[TMP4744:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4745:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4746:%.*]] = bitcast float [[TMP4744]] to i32
-// CHECK-NEXT: [[TMP4747:%.*]] = bitcast float [[TMP4745]] to i32
-// CHECK-NEXT: [[TMP4748:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4746]], i32 [[TMP4747]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP4749:%.*]] = extractvalue { i32, i1 } [[TMP4748]], 0
-// CHECK-NEXT: [[TMP4750:%.*]] = bitcast i32 [[TMP4749]] to float
-// CHECK-NEXT: [[TMP4751:%.*]] = extractvalue { i32, i1 } [[TMP4748]], 1
-// CHECK-NEXT: br i1 [[TMP4751]], label [[FX_ATOMIC_EXIT461:%.*]], label [[FX_ATOMIC_CONT462:%.*]]
-// CHECK: fx.atomic.cont462:
-// CHECK-NEXT: store float [[TMP4750]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT461]]
-// CHECK: fx.atomic.exit461:
-// CHECK-NEXT: [[TMP4752:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4753:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4754:%.*]] = bitcast float [[TMP4752]] to i32
-// CHECK-NEXT: [[TMP4755:%.*]] = bitcast float [[TMP4753]] to i32
-// CHECK-NEXT: [[TMP4756:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4754]], i32 [[TMP4755]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP4757:%.*]] = extractvalue { i32, i1 } [[TMP4756]], 1
-// CHECK-NEXT: [[TMP4758:%.*]] = sext i1 [[TMP4757]] to i32
-// CHECK-NEXT: store i32 [[TMP4758]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP4759:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4760:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4761:%.*]] = bitcast float [[TMP4759]] to i32
-// CHECK-NEXT: [[TMP4762:%.*]] = bitcast float [[TMP4760]] to i32
-// CHECK-NEXT: [[TMP4763:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4761]], i32 [[TMP4762]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP4764:%.*]] = extractvalue { i32, i1 } [[TMP4763]], 1
-// CHECK-NEXT: [[TMP4765:%.*]] = sext i1 [[TMP4764]] to i32
-// CHECK-NEXT: store i32 [[TMP4765]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP4766:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4767:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4768:%.*]] = bitcast float [[TMP4766]] to i32
-// CHECK-NEXT: [[TMP4769:%.*]] = bitcast float [[TMP4767]] to i32
-// CHECK-NEXT: [[TMP4770:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4768]], i32 [[TMP4769]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP4771:%.*]] = extractvalue { i32, i1 } [[TMP4770]], 0
-// CHECK-NEXT: [[TMP4772:%.*]] = bitcast i32 [[TMP4771]] to float
-// CHECK-NEXT: [[TMP4773:%.*]] = extractvalue { i32, i1 } [[TMP4770]], 1
-// CHECK-NEXT: br i1 [[TMP4773]], label [[FX_ATOMIC_EXIT463:%.*]], label [[FX_ATOMIC_CONT464:%.*]]
-// CHECK: fx.atomic.cont464:
-// CHECK-NEXT: store float [[TMP4772]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT463]]
-// CHECK: fx.atomic.exit463:
-// CHECK-NEXT: [[TMP4774:%.*]] = extractvalue { i32, i1 } [[TMP4770]], 1
-// CHECK-NEXT: [[TMP4775:%.*]] = sext i1 [[TMP4774]] to i32
-// CHECK-NEXT: store i32 [[TMP4775]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP4776:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4777:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4778:%.*]] = bitcast float [[TMP4776]] to i32
-// CHECK-NEXT: [[TMP4779:%.*]] = bitcast float [[TMP4777]] to i32
-// CHECK-NEXT: [[TMP4780:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4778]], i32 [[TMP4779]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP4781:%.*]] = extractvalue { i32, i1 } [[TMP4780]], 0
-// CHECK-NEXT: [[TMP4782:%.*]] = bitcast i32 [[TMP4781]] to float
-// CHECK-NEXT: [[TMP4783:%.*]] = extractvalue { i32, i1 } [[TMP4780]], 1
-// CHECK-NEXT: br i1 [[TMP4783]], label [[FX_ATOMIC_EXIT465:%.*]], label [[FX_ATOMIC_CONT466:%.*]]
-// CHECK: fx.atomic.cont466:
-// CHECK-NEXT: store float [[TMP4782]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT465]]
-// CHECK: fx.atomic.exit465:
-// CHECK-NEXT: [[TMP4784:%.*]] = extractvalue { i32, i1 } [[TMP4780]], 1
-// CHECK-NEXT: [[TMP4785:%.*]] = sext i1 [[TMP4784]] to i32
-// CHECK-NEXT: store i32 [[TMP4785]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP4786:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4787:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4786]] acq_rel, align 4
-// CHECK-NEXT: store float [[TMP4787]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4788:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4789:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4788]] acq_rel, align 4
-// CHECK-NEXT: store float [[TMP4789]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4790:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4791:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4790]] acq_rel, align 4
-// CHECK-NEXT: store float [[TMP4791]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4792:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4793:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4792]] acq_rel, align 4
-// CHECK-NEXT: store float [[TMP4793]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4794:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4795:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4796:%.*]] = bitcast float [[TMP4794]] to i32
-// CHECK-NEXT: [[TMP4797:%.*]] = bitcast float [[TMP4795]] to i32
-// CHECK-NEXT: [[TMP4798:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4796]], i32 [[TMP4797]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP4799:%.*]] = extractvalue { i32, i1 } [[TMP4798]], 0
-// CHECK-NEXT: [[TMP4800:%.*]] = bitcast i32 [[TMP4799]] to float
-// CHECK-NEXT: store float [[TMP4800]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4801:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4802:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4803:%.*]] = bitcast float [[TMP4801]] to i32
-// CHECK-NEXT: [[TMP4804:%.*]] = bitcast float [[TMP4802]] to i32
-// CHECK-NEXT: [[TMP4805:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4803]], i32 [[TMP4804]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP4806:%.*]] = extractvalue { i32, i1 } [[TMP4805]], 0
-// CHECK-NEXT: [[TMP4807:%.*]] = bitcast i32 [[TMP4806]] to float
-// CHECK-NEXT: store float [[TMP4807]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4808:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4809:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4808]] acq_rel, align 4
-// CHECK-NEXT: [[TMP4810:%.*]] = fcmp ogt float [[TMP4809]], [[TMP4808]]
-// CHECK-NEXT: [[TMP4811:%.*]] = select i1 [[TMP4810]], float [[TMP4808]], float [[TMP4809]]
-// CHECK-NEXT: store float [[TMP4811]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4812:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4813:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4812]] acq_rel, align 4
-// CHECK-NEXT: [[TMP4814:%.*]] = fcmp olt float [[TMP4813]], [[TMP4812]]
-// CHECK-NEXT: [[TMP4815:%.*]] = select i1 [[TMP4814]], float [[TMP4812]], float [[TMP4813]]
-// CHECK-NEXT: store float [[TMP4815]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4816:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4817:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4816]] acq_rel, align 4
-// CHECK-NEXT: [[TMP4818:%.*]] = fcmp olt float [[TMP4817]], [[TMP4816]]
-// CHECK-NEXT: [[TMP4819:%.*]] = select i1 [[TMP4818]], float [[TMP4816]], float [[TMP4817]]
-// CHECK-NEXT: store float [[TMP4819]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4820:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4821:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4820]] acq_rel, align 4
-// CHECK-NEXT: [[TMP4822:%.*]] = fcmp ogt float [[TMP4821]], [[TMP4820]]
-// CHECK-NEXT: [[TMP4823:%.*]] = select i1 [[TMP4822]], float [[TMP4820]], float [[TMP4821]]
-// CHECK-NEXT: store float [[TMP4823]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4824:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4825:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4826:%.*]] = bitcast float [[TMP4824]] to i32
-// CHECK-NEXT: [[TMP4827:%.*]] = bitcast float [[TMP4825]] to i32
-// CHECK-NEXT: [[TMP4828:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4826]], i32 [[TMP4827]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP4829:%.*]] = extractvalue { i32, i1 } [[TMP4828]], 0
-// CHECK-NEXT: [[TMP4830:%.*]] = bitcast i32 [[TMP4829]] to float
-// CHECK-NEXT: [[TMP4831:%.*]] = extractvalue { i32, i1 } [[TMP4828]], 1
-// CHECK-NEXT: [[TMP4832:%.*]] = select i1 [[TMP4831]], float [[TMP4824]], float [[TMP4830]]
-// CHECK-NEXT: store float [[TMP4832]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4833:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4834:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4835:%.*]] = bitcast float [[TMP4833]] to i32
-// CHECK-NEXT: [[TMP4836:%.*]] = bitcast float [[TMP4834]] to i32
-// CHECK-NEXT: [[TMP4837:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4835]], i32 [[TMP4836]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP4838:%.*]] = extractvalue { i32, i1 } [[TMP4837]], 0
-// CHECK-NEXT: [[TMP4839:%.*]] = bitcast i32 [[TMP4838]] to float
-// CHECK-NEXT: [[TMP4840:%.*]] = extractvalue { i32, i1 } [[TMP4837]], 1
-// CHECK-NEXT: [[TMP4841:%.*]] = select i1 [[TMP4840]], float [[TMP4833]], float [[TMP4839]]
-// CHECK-NEXT: store float [[TMP4841]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4842:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4843:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4844:%.*]] = bitcast float [[TMP4842]] to i32
-// CHECK-NEXT: [[TMP4845:%.*]] = bitcast float [[TMP4843]] to i32
-// CHECK-NEXT: [[TMP4846:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4844]], i32 [[TMP4845]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP4847:%.*]] = extractvalue { i32, i1 } [[TMP4846]], 0
-// CHECK-NEXT: [[TMP4848:%.*]] = bitcast i32 [[TMP4847]] to float
-// CHECK-NEXT: [[TMP4849:%.*]] = extractvalue { i32, i1 } [[TMP4846]], 1
-// CHECK-NEXT: br i1 [[TMP4849]], label [[FX_ATOMIC_EXIT467:%.*]], label [[FX_ATOMIC_CONT468:%.*]]
-// CHECK: fx.atomic.cont468:
-// CHECK-NEXT: store float [[TMP4848]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT467]]
-// CHECK: fx.atomic.exit467:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4850:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4851:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4852:%.*]] = bitcast float [[TMP4850]] to i32
-// CHECK-NEXT: [[TMP4853:%.*]] = bitcast float [[TMP4851]] to i32
-// CHECK-NEXT: [[TMP4854:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4852]], i32 [[TMP4853]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP4855:%.*]] = extractvalue { i32, i1 } [[TMP4854]], 0
-// CHECK-NEXT: [[TMP4856:%.*]] = bitcast i32 [[TMP4855]] to float
-// CHECK-NEXT: [[TMP4857:%.*]] = extractvalue { i32, i1 } [[TMP4854]], 1
-// CHECK-NEXT: br i1 [[TMP4857]], label [[FX_ATOMIC_EXIT469:%.*]], label [[FX_ATOMIC_CONT470:%.*]]
-// CHECK: fx.atomic.cont470:
-// CHECK-NEXT: store float [[TMP4856]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT469]]
-// CHECK: fx.atomic.exit469:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4858:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4859:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4860:%.*]] = bitcast float [[TMP4858]] to i32
-// CHECK-NEXT: [[TMP4861:%.*]] = bitcast float [[TMP4859]] to i32
-// CHECK-NEXT: [[TMP4862:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4860]], i32 [[TMP4861]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP4863:%.*]] = extractvalue { i32, i1 } [[TMP4862]], 1
-// CHECK-NEXT: [[TMP4864:%.*]] = sext i1 [[TMP4863]] to i32
-// CHECK-NEXT: store i32 [[TMP4864]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4865:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4866:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4867:%.*]] = bitcast float [[TMP4865]] to i32
-// CHECK-NEXT: [[TMP4868:%.*]] = bitcast float [[TMP4866]] to i32
-// CHECK-NEXT: [[TMP4869:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4867]], i32 [[TMP4868]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP4870:%.*]] = extractvalue { i32, i1 } [[TMP4869]], 1
-// CHECK-NEXT: [[TMP4871:%.*]] = sext i1 [[TMP4870]] to i32
-// CHECK-NEXT: store i32 [[TMP4871]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4872:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4873:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4874:%.*]] = bitcast float [[TMP4872]] to i32
-// CHECK-NEXT: [[TMP4875:%.*]] = bitcast float [[TMP4873]] to i32
-// CHECK-NEXT: [[TMP4876:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4874]], i32 [[TMP4875]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP4877:%.*]] = extractvalue { i32, i1 } [[TMP4876]], 0
-// CHECK-NEXT: [[TMP4878:%.*]] = bitcast i32 [[TMP4877]] to float
-// CHECK-NEXT: [[TMP4879:%.*]] = extractvalue { i32, i1 } [[TMP4876]], 1
-// CHECK-NEXT: br i1 [[TMP4879]], label [[FX_ATOMIC_EXIT471:%.*]], label [[FX_ATOMIC_CONT472:%.*]]
-// CHECK: fx.atomic.cont472:
-// CHECK-NEXT: store float [[TMP4878]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT471]]
-// CHECK: fx.atomic.exit471:
-// CHECK-NEXT: [[TMP4880:%.*]] = extractvalue { i32, i1 } [[TMP4876]], 1
-// CHECK-NEXT: [[TMP4881:%.*]] = sext i1 [[TMP4880]] to i32
-// CHECK-NEXT: store i32 [[TMP4881]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4882:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4883:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4884:%.*]] = bitcast float [[TMP4882]] to i32
-// CHECK-NEXT: [[TMP4885:%.*]] = bitcast float [[TMP4883]] to i32
-// CHECK-NEXT: [[TMP4886:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4884]], i32 [[TMP4885]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP4887:%.*]] = extractvalue { i32, i1 } [[TMP4886]], 0
-// CHECK-NEXT: [[TMP4888:%.*]] = bitcast i32 [[TMP4887]] to float
-// CHECK-NEXT: [[TMP4889:%.*]] = extractvalue { i32, i1 } [[TMP4886]], 1
-// CHECK-NEXT: br i1 [[TMP4889]], label [[FX_ATOMIC_EXIT473:%.*]], label [[FX_ATOMIC_CONT474:%.*]]
-// CHECK: fx.atomic.cont474:
-// CHECK-NEXT: store float [[TMP4888]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT473]]
-// CHECK: fx.atomic.exit473:
-// CHECK-NEXT: [[TMP4890:%.*]] = extractvalue { i32, i1 } [[TMP4886]], 1
-// CHECK-NEXT: [[TMP4891:%.*]] = sext i1 [[TMP4890]] to i32
-// CHECK-NEXT: store i32 [[TMP4891]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP4892:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4893:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4892]] acquire, align 4
-// CHECK-NEXT: store float [[TMP4893]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4894:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4895:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4894]] acquire, align 4
-// CHECK-NEXT: store float [[TMP4895]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4896:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4897:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4896]] acquire, align 4
-// CHECK-NEXT: store float [[TMP4897]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4898:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4899:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4898]] acquire, align 4
-// CHECK-NEXT: store float [[TMP4899]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4900:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4901:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4902:%.*]] = bitcast float [[TMP4900]] to i32
-// CHECK-NEXT: [[TMP4903:%.*]] = bitcast float [[TMP4901]] to i32
-// CHECK-NEXT: [[TMP4904:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4902]], i32 [[TMP4903]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP4905:%.*]] = extractvalue { i32, i1 } [[TMP4904]], 0
-// CHECK-NEXT: [[TMP4906:%.*]] = bitcast i32 [[TMP4905]] to float
-// CHECK-NEXT: store float [[TMP4906]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4907:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4908:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4909:%.*]] = bitcast float [[TMP4907]] to i32
-// CHECK-NEXT: [[TMP4910:%.*]] = bitcast float [[TMP4908]] to i32
-// CHECK-NEXT: [[TMP4911:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4909]], i32 [[TMP4910]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP4912:%.*]] = extractvalue { i32, i1 } [[TMP4911]], 0
-// CHECK-NEXT: [[TMP4913:%.*]] = bitcast i32 [[TMP4912]] to float
-// CHECK-NEXT: store float [[TMP4913]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4914:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4915:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4914]] acquire, align 4
-// CHECK-NEXT: [[TMP4916:%.*]] = fcmp ogt float [[TMP4915]], [[TMP4914]]
-// CHECK-NEXT: [[TMP4917:%.*]] = select i1 [[TMP4916]], float [[TMP4914]], float [[TMP4915]]
-// CHECK-NEXT: store float [[TMP4917]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4918:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4919:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4918]] acquire, align 4
-// CHECK-NEXT: [[TMP4920:%.*]] = fcmp olt float [[TMP4919]], [[TMP4918]]
-// CHECK-NEXT: [[TMP4921:%.*]] = select i1 [[TMP4920]], float [[TMP4918]], float [[TMP4919]]
-// CHECK-NEXT: store float [[TMP4921]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4922:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4923:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP4922]] acquire, align 4
-// CHECK-NEXT: [[TMP4924:%.*]] = fcmp olt float [[TMP4923]], [[TMP4922]]
-// CHECK-NEXT: [[TMP4925:%.*]] = select i1 [[TMP4924]], float [[TMP4922]], float [[TMP4923]]
-// CHECK-NEXT: store float [[TMP4925]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4926:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4927:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4926]] acquire, align 4
-// CHECK-NEXT: [[TMP4928:%.*]] = fcmp ogt float [[TMP4927]], [[TMP4926]]
-// CHECK-NEXT: [[TMP4929:%.*]] = select i1 [[TMP4928]], float [[TMP4926]], float [[TMP4927]]
-// CHECK-NEXT: store float [[TMP4929]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4930:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4931:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4932:%.*]] = bitcast float [[TMP4930]] to i32
-// CHECK-NEXT: [[TMP4933:%.*]] = bitcast float [[TMP4931]] to i32
-// CHECK-NEXT: [[TMP4934:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4932]], i32 [[TMP4933]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP4935:%.*]] = extractvalue { i32, i1 } [[TMP4934]], 0
-// CHECK-NEXT: [[TMP4936:%.*]] = bitcast i32 [[TMP4935]] to float
-// CHECK-NEXT: [[TMP4937:%.*]] = extractvalue { i32, i1 } [[TMP4934]], 1
-// CHECK-NEXT: [[TMP4938:%.*]] = select i1 [[TMP4937]], float [[TMP4930]], float [[TMP4936]]
-// CHECK-NEXT: store float [[TMP4938]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4939:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4940:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4941:%.*]] = bitcast float [[TMP4939]] to i32
-// CHECK-NEXT: [[TMP4942:%.*]] = bitcast float [[TMP4940]] to i32
-// CHECK-NEXT: [[TMP4943:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4941]], i32 [[TMP4942]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP4944:%.*]] = extractvalue { i32, i1 } [[TMP4943]], 0
-// CHECK-NEXT: [[TMP4945:%.*]] = bitcast i32 [[TMP4944]] to float
-// CHECK-NEXT: [[TMP4946:%.*]] = extractvalue { i32, i1 } [[TMP4943]], 1
-// CHECK-NEXT: [[TMP4947:%.*]] = select i1 [[TMP4946]], float [[TMP4939]], float [[TMP4945]]
-// CHECK-NEXT: store float [[TMP4947]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP4948:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4949:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4950:%.*]] = bitcast float [[TMP4948]] to i32
-// CHECK-NEXT: [[TMP4951:%.*]] = bitcast float [[TMP4949]] to i32
-// CHECK-NEXT: [[TMP4952:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4950]], i32 [[TMP4951]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP4953:%.*]] = extractvalue { i32, i1 } [[TMP4952]], 0
-// CHECK-NEXT: [[TMP4954:%.*]] = bitcast i32 [[TMP4953]] to float
-// CHECK-NEXT: [[TMP4955:%.*]] = extractvalue { i32, i1 } [[TMP4952]], 1
-// CHECK-NEXT: br i1 [[TMP4955]], label [[FX_ATOMIC_EXIT475:%.*]], label [[FX_ATOMIC_CONT476:%.*]]
-// CHECK: fx.atomic.cont476:
-// CHECK-NEXT: store float [[TMP4954]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT475]]
-// CHECK: fx.atomic.exit475:
-// CHECK-NEXT: [[TMP4956:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4957:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4958:%.*]] = bitcast float [[TMP4956]] to i32
-// CHECK-NEXT: [[TMP4959:%.*]] = bitcast float [[TMP4957]] to i32
-// CHECK-NEXT: [[TMP4960:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4958]], i32 [[TMP4959]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP4961:%.*]] = extractvalue { i32, i1 } [[TMP4960]], 0
-// CHECK-NEXT: [[TMP4962:%.*]] = bitcast i32 [[TMP4961]] to float
-// CHECK-NEXT: [[TMP4963:%.*]] = extractvalue { i32, i1 } [[TMP4960]], 1
-// CHECK-NEXT: br i1 [[TMP4963]], label [[FX_ATOMIC_EXIT477:%.*]], label [[FX_ATOMIC_CONT478:%.*]]
-// CHECK: fx.atomic.cont478:
-// CHECK-NEXT: store float [[TMP4962]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT477]]
-// CHECK: fx.atomic.exit477:
-// CHECK-NEXT: [[TMP4964:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4965:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4966:%.*]] = bitcast float [[TMP4964]] to i32
-// CHECK-NEXT: [[TMP4967:%.*]] = bitcast float [[TMP4965]] to i32
-// CHECK-NEXT: [[TMP4968:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4966]], i32 [[TMP4967]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP4969:%.*]] = extractvalue { i32, i1 } [[TMP4968]], 1
-// CHECK-NEXT: [[TMP4970:%.*]] = sext i1 [[TMP4969]] to i32
-// CHECK-NEXT: store i32 [[TMP4970]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP4971:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4972:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4973:%.*]] = bitcast float [[TMP4971]] to i32
-// CHECK-NEXT: [[TMP4974:%.*]] = bitcast float [[TMP4972]] to i32
-// CHECK-NEXT: [[TMP4975:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4973]], i32 [[TMP4974]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP4976:%.*]] = extractvalue { i32, i1 } [[TMP4975]], 1
-// CHECK-NEXT: [[TMP4977:%.*]] = sext i1 [[TMP4976]] to i32
-// CHECK-NEXT: store i32 [[TMP4977]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP4978:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4979:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4980:%.*]] = bitcast float [[TMP4978]] to i32
-// CHECK-NEXT: [[TMP4981:%.*]] = bitcast float [[TMP4979]] to i32
-// CHECK-NEXT: [[TMP4982:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4980]], i32 [[TMP4981]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP4983:%.*]] = extractvalue { i32, i1 } [[TMP4982]], 0
-// CHECK-NEXT: [[TMP4984:%.*]] = bitcast i32 [[TMP4983]] to float
-// CHECK-NEXT: [[TMP4985:%.*]] = extractvalue { i32, i1 } [[TMP4982]], 1
-// CHECK-NEXT: br i1 [[TMP4985]], label [[FX_ATOMIC_EXIT479:%.*]], label [[FX_ATOMIC_CONT480:%.*]]
-// CHECK: fx.atomic.cont480:
-// CHECK-NEXT: store float [[TMP4984]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT479]]
-// CHECK: fx.atomic.exit479:
-// CHECK-NEXT: [[TMP4986:%.*]] = extractvalue { i32, i1 } [[TMP4982]], 1
-// CHECK-NEXT: [[TMP4987:%.*]] = sext i1 [[TMP4986]] to i32
-// CHECK-NEXT: store i32 [[TMP4987]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP4988:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4989:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP4990:%.*]] = bitcast float [[TMP4988]] to i32
-// CHECK-NEXT: [[TMP4991:%.*]] = bitcast float [[TMP4989]] to i32
-// CHECK-NEXT: [[TMP4992:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP4990]], i32 [[TMP4991]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP4993:%.*]] = extractvalue { i32, i1 } [[TMP4992]], 0
-// CHECK-NEXT: [[TMP4994:%.*]] = bitcast i32 [[TMP4993]] to float
-// CHECK-NEXT: [[TMP4995:%.*]] = extractvalue { i32, i1 } [[TMP4992]], 1
-// CHECK-NEXT: br i1 [[TMP4995]], label [[FX_ATOMIC_EXIT481:%.*]], label [[FX_ATOMIC_CONT482:%.*]]
-// CHECK: fx.atomic.cont482:
-// CHECK-NEXT: store float [[TMP4994]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT481]]
-// CHECK: fx.atomic.exit481:
-// CHECK-NEXT: [[TMP4996:%.*]] = extractvalue { i32, i1 } [[TMP4992]], 1
-// CHECK-NEXT: [[TMP4997:%.*]] = sext i1 [[TMP4996]] to i32
-// CHECK-NEXT: store i32 [[TMP4997]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP4998:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP4999:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP4998]] monotonic, align 4
-// CHECK-NEXT: store float [[TMP4999]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP5000:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5001:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5000]] monotonic, align 4
-// CHECK-NEXT: store float [[TMP5001]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP5002:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5003:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5002]] monotonic, align 4
-// CHECK-NEXT: store float [[TMP5003]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP5004:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5005:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5004]] monotonic, align 4
-// CHECK-NEXT: store float [[TMP5005]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP5006:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5007:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5008:%.*]] = bitcast float [[TMP5006]] to i32
-// CHECK-NEXT: [[TMP5009:%.*]] = bitcast float [[TMP5007]] to i32
-// CHECK-NEXT: [[TMP5010:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5008]], i32 [[TMP5009]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP5011:%.*]] = extractvalue { i32, i1 } [[TMP5010]], 0
-// CHECK-NEXT: [[TMP5012:%.*]] = bitcast i32 [[TMP5011]] to float
-// CHECK-NEXT: store float [[TMP5012]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP5013:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5014:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5015:%.*]] = bitcast float [[TMP5013]] to i32
-// CHECK-NEXT: [[TMP5016:%.*]] = bitcast float [[TMP5014]] to i32
-// CHECK-NEXT: [[TMP5017:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5015]], i32 [[TMP5016]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP5018:%.*]] = extractvalue { i32, i1 } [[TMP5017]], 0
-// CHECK-NEXT: [[TMP5019:%.*]] = bitcast i32 [[TMP5018]] to float
-// CHECK-NEXT: store float [[TMP5019]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP5020:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5021:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5020]] monotonic, align 4
-// CHECK-NEXT: [[TMP5022:%.*]] = fcmp ogt float [[TMP5021]], [[TMP5020]]
-// CHECK-NEXT: [[TMP5023:%.*]] = select i1 [[TMP5022]], float [[TMP5020]], float [[TMP5021]]
-// CHECK-NEXT: store float [[TMP5023]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP5024:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5025:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5024]] monotonic, align 4
-// CHECK-NEXT: [[TMP5026:%.*]] = fcmp olt float [[TMP5025]], [[TMP5024]]
-// CHECK-NEXT: [[TMP5027:%.*]] = select i1 [[TMP5026]], float [[TMP5024]], float [[TMP5025]]
-// CHECK-NEXT: store float [[TMP5027]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP5028:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5029:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5028]] monotonic, align 4
-// CHECK-NEXT: [[TMP5030:%.*]] = fcmp olt float [[TMP5029]], [[TMP5028]]
-// CHECK-NEXT: [[TMP5031:%.*]] = select i1 [[TMP5030]], float [[TMP5028]], float [[TMP5029]]
-// CHECK-NEXT: store float [[TMP5031]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP5032:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5033:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5032]] monotonic, align 4
-// CHECK-NEXT: [[TMP5034:%.*]] = fcmp ogt float [[TMP5033]], [[TMP5032]]
-// CHECK-NEXT: [[TMP5035:%.*]] = select i1 [[TMP5034]], float [[TMP5032]], float [[TMP5033]]
-// CHECK-NEXT: store float [[TMP5035]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP5036:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5037:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5038:%.*]] = bitcast float [[TMP5036]] to i32
-// CHECK-NEXT: [[TMP5039:%.*]] = bitcast float [[TMP5037]] to i32
-// CHECK-NEXT: [[TMP5040:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5038]], i32 [[TMP5039]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP5041:%.*]] = extractvalue { i32, i1 } [[TMP5040]], 0
-// CHECK-NEXT: [[TMP5042:%.*]] = bitcast i32 [[TMP5041]] to float
-// CHECK-NEXT: [[TMP5043:%.*]] = extractvalue { i32, i1 } [[TMP5040]], 1
-// CHECK-NEXT: [[TMP5044:%.*]] = select i1 [[TMP5043]], float [[TMP5036]], float [[TMP5042]]
-// CHECK-NEXT: store float [[TMP5044]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP5045:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5046:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5047:%.*]] = bitcast float [[TMP5045]] to i32
-// CHECK-NEXT: [[TMP5048:%.*]] = bitcast float [[TMP5046]] to i32
-// CHECK-NEXT: [[TMP5049:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5047]], i32 [[TMP5048]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP5050:%.*]] = extractvalue { i32, i1 } [[TMP5049]], 0
-// CHECK-NEXT: [[TMP5051:%.*]] = bitcast i32 [[TMP5050]] to float
-// CHECK-NEXT: [[TMP5052:%.*]] = extractvalue { i32, i1 } [[TMP5049]], 1
-// CHECK-NEXT: [[TMP5053:%.*]] = select i1 [[TMP5052]], float [[TMP5045]], float [[TMP5051]]
-// CHECK-NEXT: store float [[TMP5053]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP5054:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5055:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5056:%.*]] = bitcast float [[TMP5054]] to i32
-// CHECK-NEXT: [[TMP5057:%.*]] = bitcast float [[TMP5055]] to i32
-// CHECK-NEXT: [[TMP5058:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5056]], i32 [[TMP5057]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP5059:%.*]] = extractvalue { i32, i1 } [[TMP5058]], 0
-// CHECK-NEXT: [[TMP5060:%.*]] = bitcast i32 [[TMP5059]] to float
-// CHECK-NEXT: [[TMP5061:%.*]] = extractvalue { i32, i1 } [[TMP5058]], 1
-// CHECK-NEXT: br i1 [[TMP5061]], label [[FX_ATOMIC_EXIT483:%.*]], label [[FX_ATOMIC_CONT484:%.*]]
-// CHECK: fx.atomic.cont484:
-// CHECK-NEXT: store float [[TMP5060]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT483]]
-// CHECK: fx.atomic.exit483:
-// CHECK-NEXT: [[TMP5062:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5063:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5064:%.*]] = bitcast float [[TMP5062]] to i32
-// CHECK-NEXT: [[TMP5065:%.*]] = bitcast float [[TMP5063]] to i32
-// CHECK-NEXT: [[TMP5066:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5064]], i32 [[TMP5065]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP5067:%.*]] = extractvalue { i32, i1 } [[TMP5066]], 0
-// CHECK-NEXT: [[TMP5068:%.*]] = bitcast i32 [[TMP5067]] to float
-// CHECK-NEXT: [[TMP5069:%.*]] = extractvalue { i32, i1 } [[TMP5066]], 1
-// CHECK-NEXT: br i1 [[TMP5069]], label [[FX_ATOMIC_EXIT485:%.*]], label [[FX_ATOMIC_CONT486:%.*]]
-// CHECK: fx.atomic.cont486:
-// CHECK-NEXT: store float [[TMP5068]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT485]]
-// CHECK: fx.atomic.exit485:
-// CHECK-NEXT: [[TMP5070:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5071:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5072:%.*]] = bitcast float [[TMP5070]] to i32
-// CHECK-NEXT: [[TMP5073:%.*]] = bitcast float [[TMP5071]] to i32
-// CHECK-NEXT: [[TMP5074:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5072]], i32 [[TMP5073]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP5075:%.*]] = extractvalue { i32, i1 } [[TMP5074]], 1
-// CHECK-NEXT: [[TMP5076:%.*]] = sext i1 [[TMP5075]] to i32
-// CHECK-NEXT: store i32 [[TMP5076]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP5077:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5078:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5079:%.*]] = bitcast float [[TMP5077]] to i32
-// CHECK-NEXT: [[TMP5080:%.*]] = bitcast float [[TMP5078]] to i32
-// CHECK-NEXT: [[TMP5081:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5079]], i32 [[TMP5080]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP5082:%.*]] = extractvalue { i32, i1 } [[TMP5081]], 1
-// CHECK-NEXT: [[TMP5083:%.*]] = sext i1 [[TMP5082]] to i32
-// CHECK-NEXT: store i32 [[TMP5083]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP5084:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5085:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5086:%.*]] = bitcast float [[TMP5084]] to i32
-// CHECK-NEXT: [[TMP5087:%.*]] = bitcast float [[TMP5085]] to i32
-// CHECK-NEXT: [[TMP5088:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5086]], i32 [[TMP5087]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP5089:%.*]] = extractvalue { i32, i1 } [[TMP5088]], 0
-// CHECK-NEXT: [[TMP5090:%.*]] = bitcast i32 [[TMP5089]] to float
-// CHECK-NEXT: [[TMP5091:%.*]] = extractvalue { i32, i1 } [[TMP5088]], 1
-// CHECK-NEXT: br i1 [[TMP5091]], label [[FX_ATOMIC_EXIT487:%.*]], label [[FX_ATOMIC_CONT488:%.*]]
-// CHECK: fx.atomic.cont488:
-// CHECK-NEXT: store float [[TMP5090]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT487]]
-// CHECK: fx.atomic.exit487:
-// CHECK-NEXT: [[TMP5092:%.*]] = extractvalue { i32, i1 } [[TMP5088]], 1
-// CHECK-NEXT: [[TMP5093:%.*]] = sext i1 [[TMP5092]] to i32
-// CHECK-NEXT: store i32 [[TMP5093]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP5094:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5095:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5096:%.*]] = bitcast float [[TMP5094]] to i32
-// CHECK-NEXT: [[TMP5097:%.*]] = bitcast float [[TMP5095]] to i32
-// CHECK-NEXT: [[TMP5098:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5096]], i32 [[TMP5097]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP5099:%.*]] = extractvalue { i32, i1 } [[TMP5098]], 0
-// CHECK-NEXT: [[TMP5100:%.*]] = bitcast i32 [[TMP5099]] to float
-// CHECK-NEXT: [[TMP5101:%.*]] = extractvalue { i32, i1 } [[TMP5098]], 1
-// CHECK-NEXT: br i1 [[TMP5101]], label [[FX_ATOMIC_EXIT489:%.*]], label [[FX_ATOMIC_CONT490:%.*]]
-// CHECK: fx.atomic.cont490:
-// CHECK-NEXT: store float [[TMP5100]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT489]]
-// CHECK: fx.atomic.exit489:
-// CHECK-NEXT: [[TMP5102:%.*]] = extractvalue { i32, i1 } [[TMP5098]], 1
-// CHECK-NEXT: [[TMP5103:%.*]] = sext i1 [[TMP5102]] to i32
-// CHECK-NEXT: store i32 [[TMP5103]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP5104:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5105:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5104]] release, align 4
-// CHECK-NEXT: store float [[TMP5105]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5106:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5107:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5106]] release, align 4
-// CHECK-NEXT: store float [[TMP5107]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5108:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5109:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5108]] release, align 4
-// CHECK-NEXT: store float [[TMP5109]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5110:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5111:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5110]] release, align 4
-// CHECK-NEXT: store float [[TMP5111]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5112:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5113:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5114:%.*]] = bitcast float [[TMP5112]] to i32
-// CHECK-NEXT: [[TMP5115:%.*]] = bitcast float [[TMP5113]] to i32
-// CHECK-NEXT: [[TMP5116:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5114]], i32 [[TMP5115]] release monotonic, align 4
-// CHECK-NEXT: [[TMP5117:%.*]] = extractvalue { i32, i1 } [[TMP5116]], 0
-// CHECK-NEXT: [[TMP5118:%.*]] = bitcast i32 [[TMP5117]] to float
-// CHECK-NEXT: store float [[TMP5118]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5119:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5120:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5121:%.*]] = bitcast float [[TMP5119]] to i32
-// CHECK-NEXT: [[TMP5122:%.*]] = bitcast float [[TMP5120]] to i32
-// CHECK-NEXT: [[TMP5123:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5121]], i32 [[TMP5122]] release monotonic, align 4
-// CHECK-NEXT: [[TMP5124:%.*]] = extractvalue { i32, i1 } [[TMP5123]], 0
-// CHECK-NEXT: [[TMP5125:%.*]] = bitcast i32 [[TMP5124]] to float
-// CHECK-NEXT: store float [[TMP5125]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5126:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5127:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5126]] release, align 4
-// CHECK-NEXT: [[TMP5128:%.*]] = fcmp ogt float [[TMP5127]], [[TMP5126]]
-// CHECK-NEXT: [[TMP5129:%.*]] = select i1 [[TMP5128]], float [[TMP5126]], float [[TMP5127]]
-// CHECK-NEXT: store float [[TMP5129]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5130:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5131:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5130]] release, align 4
-// CHECK-NEXT: [[TMP5132:%.*]] = fcmp olt float [[TMP5131]], [[TMP5130]]
-// CHECK-NEXT: [[TMP5133:%.*]] = select i1 [[TMP5132]], float [[TMP5130]], float [[TMP5131]]
-// CHECK-NEXT: store float [[TMP5133]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5134:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5135:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5134]] release, align 4
-// CHECK-NEXT: [[TMP5136:%.*]] = fcmp olt float [[TMP5135]], [[TMP5134]]
-// CHECK-NEXT: [[TMP5137:%.*]] = select i1 [[TMP5136]], float [[TMP5134]], float [[TMP5135]]
-// CHECK-NEXT: store float [[TMP5137]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5138:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5139:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5138]] release, align 4
-// CHECK-NEXT: [[TMP5140:%.*]] = fcmp ogt float [[TMP5139]], [[TMP5138]]
-// CHECK-NEXT: [[TMP5141:%.*]] = select i1 [[TMP5140]], float [[TMP5138]], float [[TMP5139]]
-// CHECK-NEXT: store float [[TMP5141]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5142:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5143:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5144:%.*]] = bitcast float [[TMP5142]] to i32
-// CHECK-NEXT: [[TMP5145:%.*]] = bitcast float [[TMP5143]] to i32
-// CHECK-NEXT: [[TMP5146:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5144]], i32 [[TMP5145]] release monotonic, align 4
-// CHECK-NEXT: [[TMP5147:%.*]] = extractvalue { i32, i1 } [[TMP5146]], 0
-// CHECK-NEXT: [[TMP5148:%.*]] = bitcast i32 [[TMP5147]] to float
-// CHECK-NEXT: [[TMP5149:%.*]] = extractvalue { i32, i1 } [[TMP5146]], 1
-// CHECK-NEXT: [[TMP5150:%.*]] = select i1 [[TMP5149]], float [[TMP5142]], float [[TMP5148]]
-// CHECK-NEXT: store float [[TMP5150]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5151:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5152:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5153:%.*]] = bitcast float [[TMP5151]] to i32
-// CHECK-NEXT: [[TMP5154:%.*]] = bitcast float [[TMP5152]] to i32
-// CHECK-NEXT: [[TMP5155:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5153]], i32 [[TMP5154]] release monotonic, align 4
-// CHECK-NEXT: [[TMP5156:%.*]] = extractvalue { i32, i1 } [[TMP5155]], 0
-// CHECK-NEXT: [[TMP5157:%.*]] = bitcast i32 [[TMP5156]] to float
-// CHECK-NEXT: [[TMP5158:%.*]] = extractvalue { i32, i1 } [[TMP5155]], 1
-// CHECK-NEXT: [[TMP5159:%.*]] = select i1 [[TMP5158]], float [[TMP5151]], float [[TMP5157]]
-// CHECK-NEXT: store float [[TMP5159]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5160:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5161:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5162:%.*]] = bitcast float [[TMP5160]] to i32
-// CHECK-NEXT: [[TMP5163:%.*]] = bitcast float [[TMP5161]] to i32
-// CHECK-NEXT: [[TMP5164:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5162]], i32 [[TMP5163]] release monotonic, align 4
-// CHECK-NEXT: [[TMP5165:%.*]] = extractvalue { i32, i1 } [[TMP5164]], 0
-// CHECK-NEXT: [[TMP5166:%.*]] = bitcast i32 [[TMP5165]] to float
-// CHECK-NEXT: [[TMP5167:%.*]] = extractvalue { i32, i1 } [[TMP5164]], 1
-// CHECK-NEXT: br i1 [[TMP5167]], label [[FX_ATOMIC_EXIT491:%.*]], label [[FX_ATOMIC_CONT492:%.*]]
-// CHECK: fx.atomic.cont492:
-// CHECK-NEXT: store float [[TMP5166]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT491]]
-// CHECK: fx.atomic.exit491:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5168:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5169:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5170:%.*]] = bitcast float [[TMP5168]] to i32
-// CHECK-NEXT: [[TMP5171:%.*]] = bitcast float [[TMP5169]] to i32
-// CHECK-NEXT: [[TMP5172:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5170]], i32 [[TMP5171]] release monotonic, align 4
-// CHECK-NEXT: [[TMP5173:%.*]] = extractvalue { i32, i1 } [[TMP5172]], 0
-// CHECK-NEXT: [[TMP5174:%.*]] = bitcast i32 [[TMP5173]] to float
-// CHECK-NEXT: [[TMP5175:%.*]] = extractvalue { i32, i1 } [[TMP5172]], 1
-// CHECK-NEXT: br i1 [[TMP5175]], label [[FX_ATOMIC_EXIT493:%.*]], label [[FX_ATOMIC_CONT494:%.*]]
-// CHECK: fx.atomic.cont494:
-// CHECK-NEXT: store float [[TMP5174]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT493]]
-// CHECK: fx.atomic.exit493:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5176:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5177:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5178:%.*]] = bitcast float [[TMP5176]] to i32
-// CHECK-NEXT: [[TMP5179:%.*]] = bitcast float [[TMP5177]] to i32
-// CHECK-NEXT: [[TMP5180:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5178]], i32 [[TMP5179]] release monotonic, align 4
-// CHECK-NEXT: [[TMP5181:%.*]] = extractvalue { i32, i1 } [[TMP5180]], 1
-// CHECK-NEXT: [[TMP5182:%.*]] = sext i1 [[TMP5181]] to i32
-// CHECK-NEXT: store i32 [[TMP5182]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5183:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5184:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5185:%.*]] = bitcast float [[TMP5183]] to i32
-// CHECK-NEXT: [[TMP5186:%.*]] = bitcast float [[TMP5184]] to i32
-// CHECK-NEXT: [[TMP5187:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5185]], i32 [[TMP5186]] release monotonic, align 4
-// CHECK-NEXT: [[TMP5188:%.*]] = extractvalue { i32, i1 } [[TMP5187]], 1
-// CHECK-NEXT: [[TMP5189:%.*]] = sext i1 [[TMP5188]] to i32
-// CHECK-NEXT: store i32 [[TMP5189]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5190:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5191:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5192:%.*]] = bitcast float [[TMP5190]] to i32
-// CHECK-NEXT: [[TMP5193:%.*]] = bitcast float [[TMP5191]] to i32
-// CHECK-NEXT: [[TMP5194:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5192]], i32 [[TMP5193]] release monotonic, align 4
-// CHECK-NEXT: [[TMP5195:%.*]] = extractvalue { i32, i1 } [[TMP5194]], 0
-// CHECK-NEXT: [[TMP5196:%.*]] = bitcast i32 [[TMP5195]] to float
-// CHECK-NEXT: [[TMP5197:%.*]] = extractvalue { i32, i1 } [[TMP5194]], 1
-// CHECK-NEXT: br i1 [[TMP5197]], label [[FX_ATOMIC_EXIT495:%.*]], label [[FX_ATOMIC_CONT496:%.*]]
-// CHECK: fx.atomic.cont496:
-// CHECK-NEXT: store float [[TMP5196]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT495]]
-// CHECK: fx.atomic.exit495:
-// CHECK-NEXT: [[TMP5198:%.*]] = extractvalue { i32, i1 } [[TMP5194]], 1
-// CHECK-NEXT: [[TMP5199:%.*]] = sext i1 [[TMP5198]] to i32
-// CHECK-NEXT: store i32 [[TMP5199]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5200:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5201:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5202:%.*]] = bitcast float [[TMP5200]] to i32
-// CHECK-NEXT: [[TMP5203:%.*]] = bitcast float [[TMP5201]] to i32
-// CHECK-NEXT: [[TMP5204:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5202]], i32 [[TMP5203]] release monotonic, align 4
-// CHECK-NEXT: [[TMP5205:%.*]] = extractvalue { i32, i1 } [[TMP5204]], 0
-// CHECK-NEXT: [[TMP5206:%.*]] = bitcast i32 [[TMP5205]] to float
-// CHECK-NEXT: [[TMP5207:%.*]] = extractvalue { i32, i1 } [[TMP5204]], 1
-// CHECK-NEXT: br i1 [[TMP5207]], label [[FX_ATOMIC_EXIT497:%.*]], label [[FX_ATOMIC_CONT498:%.*]]
-// CHECK: fx.atomic.cont498:
-// CHECK-NEXT: store float [[TMP5206]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT497]]
-// CHECK: fx.atomic.exit497:
-// CHECK-NEXT: [[TMP5208:%.*]] = extractvalue { i32, i1 } [[TMP5204]], 1
-// CHECK-NEXT: [[TMP5209:%.*]] = sext i1 [[TMP5208]] to i32
-// CHECK-NEXT: store i32 [[TMP5209]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5210:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5211:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5210]] seq_cst, align 4
-// CHECK-NEXT: store float [[TMP5211]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5212:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5213:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5212]] seq_cst, align 4
-// CHECK-NEXT: store float [[TMP5213]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5214:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5215:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5214]] seq_cst, align 4
-// CHECK-NEXT: store float [[TMP5215]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5216:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5217:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5216]] seq_cst, align 4
-// CHECK-NEXT: store float [[TMP5217]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5218:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5219:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5220:%.*]] = bitcast float [[TMP5218]] to i32
-// CHECK-NEXT: [[TMP5221:%.*]] = bitcast float [[TMP5219]] to i32
-// CHECK-NEXT: [[TMP5222:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5220]], i32 [[TMP5221]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP5223:%.*]] = extractvalue { i32, i1 } [[TMP5222]], 0
-// CHECK-NEXT: [[TMP5224:%.*]] = bitcast i32 [[TMP5223]] to float
-// CHECK-NEXT: store float [[TMP5224]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5225:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5226:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5227:%.*]] = bitcast float [[TMP5225]] to i32
-// CHECK-NEXT: [[TMP5228:%.*]] = bitcast float [[TMP5226]] to i32
-// CHECK-NEXT: [[TMP5229:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5227]], i32 [[TMP5228]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP5230:%.*]] = extractvalue { i32, i1 } [[TMP5229]], 0
-// CHECK-NEXT: [[TMP5231:%.*]] = bitcast i32 [[TMP5230]] to float
-// CHECK-NEXT: store float [[TMP5231]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5232:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5233:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5232]] seq_cst, align 4
-// CHECK-NEXT: [[TMP5234:%.*]] = fcmp ogt float [[TMP5233]], [[TMP5232]]
-// CHECK-NEXT: [[TMP5235:%.*]] = select i1 [[TMP5234]], float [[TMP5232]], float [[TMP5233]]
-// CHECK-NEXT: store float [[TMP5235]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5236:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5237:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5236]] seq_cst, align 4
-// CHECK-NEXT: [[TMP5238:%.*]] = fcmp olt float [[TMP5237]], [[TMP5236]]
-// CHECK-NEXT: [[TMP5239:%.*]] = select i1 [[TMP5238]], float [[TMP5236]], float [[TMP5237]]
-// CHECK-NEXT: store float [[TMP5239]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5240:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5241:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP5240]] seq_cst, align 4
-// CHECK-NEXT: [[TMP5242:%.*]] = fcmp olt float [[TMP5241]], [[TMP5240]]
-// CHECK-NEXT: [[TMP5243:%.*]] = select i1 [[TMP5242]], float [[TMP5240]], float [[TMP5241]]
-// CHECK-NEXT: store float [[TMP5243]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5244:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5245:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP5244]] seq_cst, align 4
-// CHECK-NEXT: [[TMP5246:%.*]] = fcmp ogt float [[TMP5245]], [[TMP5244]]
-// CHECK-NEXT: [[TMP5247:%.*]] = select i1 [[TMP5246]], float [[TMP5244]], float [[TMP5245]]
-// CHECK-NEXT: store float [[TMP5247]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5248:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5249:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5250:%.*]] = bitcast float [[TMP5248]] to i32
-// CHECK-NEXT: [[TMP5251:%.*]] = bitcast float [[TMP5249]] to i32
-// CHECK-NEXT: [[TMP5252:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5250]], i32 [[TMP5251]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP5253:%.*]] = extractvalue { i32, i1 } [[TMP5252]], 0
-// CHECK-NEXT: [[TMP5254:%.*]] = bitcast i32 [[TMP5253]] to float
-// CHECK-NEXT: [[TMP5255:%.*]] = extractvalue { i32, i1 } [[TMP5252]], 1
-// CHECK-NEXT: [[TMP5256:%.*]] = select i1 [[TMP5255]], float [[TMP5248]], float [[TMP5254]]
-// CHECK-NEXT: store float [[TMP5256]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5257:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5258:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5259:%.*]] = bitcast float [[TMP5257]] to i32
-// CHECK-NEXT: [[TMP5260:%.*]] = bitcast float [[TMP5258]] to i32
-// CHECK-NEXT: [[TMP5261:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5259]], i32 [[TMP5260]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP5262:%.*]] = extractvalue { i32, i1 } [[TMP5261]], 0
-// CHECK-NEXT: [[TMP5263:%.*]] = bitcast i32 [[TMP5262]] to float
-// CHECK-NEXT: [[TMP5264:%.*]] = extractvalue { i32, i1 } [[TMP5261]], 1
-// CHECK-NEXT: [[TMP5265:%.*]] = select i1 [[TMP5264]], float [[TMP5257]], float [[TMP5263]]
-// CHECK-NEXT: store float [[TMP5265]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5266:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5267:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5268:%.*]] = bitcast float [[TMP5266]] to i32
-// CHECK-NEXT: [[TMP5269:%.*]] = bitcast float [[TMP5267]] to i32
-// CHECK-NEXT: [[TMP5270:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5268]], i32 [[TMP5269]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP5271:%.*]] = extractvalue { i32, i1 } [[TMP5270]], 0
-// CHECK-NEXT: [[TMP5272:%.*]] = bitcast i32 [[TMP5271]] to float
-// CHECK-NEXT: [[TMP5273:%.*]] = extractvalue { i32, i1 } [[TMP5270]], 1
-// CHECK-NEXT: br i1 [[TMP5273]], label [[FX_ATOMIC_EXIT499:%.*]], label [[FX_ATOMIC_CONT500:%.*]]
-// CHECK: fx.atomic.cont500:
-// CHECK-NEXT: store float [[TMP5272]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT499]]
-// CHECK: fx.atomic.exit499:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5274:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5275:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5276:%.*]] = bitcast float [[TMP5274]] to i32
-// CHECK-NEXT: [[TMP5277:%.*]] = bitcast float [[TMP5275]] to i32
-// CHECK-NEXT: [[TMP5278:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5276]], i32 [[TMP5277]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP5279:%.*]] = extractvalue { i32, i1 } [[TMP5278]], 0
-// CHECK-NEXT: [[TMP5280:%.*]] = bitcast i32 [[TMP5279]] to float
-// CHECK-NEXT: [[TMP5281:%.*]] = extractvalue { i32, i1 } [[TMP5278]], 1
-// CHECK-NEXT: br i1 [[TMP5281]], label [[FX_ATOMIC_EXIT501:%.*]], label [[FX_ATOMIC_CONT502:%.*]]
-// CHECK: fx.atomic.cont502:
-// CHECK-NEXT: store float [[TMP5280]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT501]]
-// CHECK: fx.atomic.exit501:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5282:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5283:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5284:%.*]] = bitcast float [[TMP5282]] to i32
-// CHECK-NEXT: [[TMP5285:%.*]] = bitcast float [[TMP5283]] to i32
-// CHECK-NEXT: [[TMP5286:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5284]], i32 [[TMP5285]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP5287:%.*]] = extractvalue { i32, i1 } [[TMP5286]], 1
-// CHECK-NEXT: [[TMP5288:%.*]] = sext i1 [[TMP5287]] to i32
-// CHECK-NEXT: store i32 [[TMP5288]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5289:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5290:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5291:%.*]] = bitcast float [[TMP5289]] to i32
-// CHECK-NEXT: [[TMP5292:%.*]] = bitcast float [[TMP5290]] to i32
-// CHECK-NEXT: [[TMP5293:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5291]], i32 [[TMP5292]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP5294:%.*]] = extractvalue { i32, i1 } [[TMP5293]], 1
-// CHECK-NEXT: [[TMP5295:%.*]] = sext i1 [[TMP5294]] to i32
-// CHECK-NEXT: store i32 [[TMP5295]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5296:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5297:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5298:%.*]] = bitcast float [[TMP5296]] to i32
-// CHECK-NEXT: [[TMP5299:%.*]] = bitcast float [[TMP5297]] to i32
-// CHECK-NEXT: [[TMP5300:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5298]], i32 [[TMP5299]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP5301:%.*]] = extractvalue { i32, i1 } [[TMP5300]], 0
-// CHECK-NEXT: [[TMP5302:%.*]] = bitcast i32 [[TMP5301]] to float
-// CHECK-NEXT: [[TMP5303:%.*]] = extractvalue { i32, i1 } [[TMP5300]], 1
-// CHECK-NEXT: br i1 [[TMP5303]], label [[FX_ATOMIC_EXIT503:%.*]], label [[FX_ATOMIC_CONT504:%.*]]
-// CHECK: fx.atomic.cont504:
-// CHECK-NEXT: store float [[TMP5302]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT503]]
-// CHECK: fx.atomic.exit503:
-// CHECK-NEXT: [[TMP5304:%.*]] = extractvalue { i32, i1 } [[TMP5300]], 1
-// CHECK-NEXT: [[TMP5305:%.*]] = sext i1 [[TMP5304]] to i32
-// CHECK-NEXT: store i32 [[TMP5305]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5306:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP5307:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP5308:%.*]] = bitcast float [[TMP5306]] to i32
-// CHECK-NEXT: [[TMP5309:%.*]] = bitcast float [[TMP5307]] to i32
-// CHECK-NEXT: [[TMP5310:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP5308]], i32 [[TMP5309]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP5311:%.*]] = extractvalue { i32, i1 } [[TMP5310]], 0
-// CHECK-NEXT: [[TMP5312:%.*]] = bitcast i32 [[TMP5311]] to float
-// CHECK-NEXT: [[TMP5313:%.*]] = extractvalue { i32, i1 } [[TMP5310]], 1
-// CHECK-NEXT: br i1 [[TMP5313]], label [[FX_ATOMIC_EXIT505:%.*]], label [[FX_ATOMIC_CONT506:%.*]]
-// CHECK: fx.atomic.cont506:
-// CHECK-NEXT: store float [[TMP5312]], ptr [[FV]], align 4
-// CHECK-NEXT: br label [[FX_ATOMIC_EXIT505]]
-// CHECK: fx.atomic.exit505:
-// CHECK-NEXT: [[TMP5314:%.*]] = extractvalue { i32, i1 } [[TMP5310]], 1
-// CHECK-NEXT: [[TMP5315:%.*]] = sext i1 [[TMP5314]] to i32
-// CHECK-NEXT: store i32 [[TMP5315]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5316:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5317:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5316]] monotonic, align 8
-// CHECK-NEXT: store double [[TMP5317]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5318:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5319:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5318]] monotonic, align 8
-// CHECK-NEXT: store double [[TMP5319]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5320:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5321:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5320]] monotonic, align 8
-// CHECK-NEXT: store double [[TMP5321]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5322:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5323:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5322]] monotonic, align 8
-// CHECK-NEXT: store double [[TMP5323]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5324:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5325:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5326:%.*]] = bitcast double [[TMP5324]] to i64
-// CHECK-NEXT: [[TMP5327:%.*]] = bitcast double [[TMP5325]] to i64
-// CHECK-NEXT: [[TMP5328:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5326]], i64 [[TMP5327]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5329:%.*]] = extractvalue { i64, i1 } [[TMP5328]], 0
-// CHECK-NEXT: [[TMP5330:%.*]] = bitcast i64 [[TMP5329]] to double
-// CHECK-NEXT: store double [[TMP5330]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5331:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5332:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5333:%.*]] = bitcast double [[TMP5331]] to i64
-// CHECK-NEXT: [[TMP5334:%.*]] = bitcast double [[TMP5332]] to i64
-// CHECK-NEXT: [[TMP5335:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5333]], i64 [[TMP5334]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5336:%.*]] = extractvalue { i64, i1 } [[TMP5335]], 0
-// CHECK-NEXT: [[TMP5337:%.*]] = bitcast i64 [[TMP5336]] to double
-// CHECK-NEXT: store double [[TMP5337]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5338:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5339:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5338]] monotonic, align 8
-// CHECK-NEXT: [[TMP5340:%.*]] = fcmp ogt double [[TMP5339]], [[TMP5338]]
-// CHECK-NEXT: [[TMP5341:%.*]] = select i1 [[TMP5340]], double [[TMP5338]], double [[TMP5339]]
-// CHECK-NEXT: store double [[TMP5341]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5342:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5343:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5342]] monotonic, align 8
-// CHECK-NEXT: [[TMP5344:%.*]] = fcmp olt double [[TMP5343]], [[TMP5342]]
-// CHECK-NEXT: [[TMP5345:%.*]] = select i1 [[TMP5344]], double [[TMP5342]], double [[TMP5343]]
-// CHECK-NEXT: store double [[TMP5345]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5346:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5347:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5346]] monotonic, align 8
-// CHECK-NEXT: [[TMP5348:%.*]] = fcmp olt double [[TMP5347]], [[TMP5346]]
-// CHECK-NEXT: [[TMP5349:%.*]] = select i1 [[TMP5348]], double [[TMP5346]], double [[TMP5347]]
-// CHECK-NEXT: store double [[TMP5349]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5350:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5351:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5350]] monotonic, align 8
-// CHECK-NEXT: [[TMP5352:%.*]] = fcmp ogt double [[TMP5351]], [[TMP5350]]
-// CHECK-NEXT: [[TMP5353:%.*]] = select i1 [[TMP5352]], double [[TMP5350]], double [[TMP5351]]
-// CHECK-NEXT: store double [[TMP5353]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5354:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5355:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5356:%.*]] = bitcast double [[TMP5354]] to i64
-// CHECK-NEXT: [[TMP5357:%.*]] = bitcast double [[TMP5355]] to i64
-// CHECK-NEXT: [[TMP5358:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5356]], i64 [[TMP5357]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5359:%.*]] = extractvalue { i64, i1 } [[TMP5358]], 0
-// CHECK-NEXT: [[TMP5360:%.*]] = bitcast i64 [[TMP5359]] to double
-// CHECK-NEXT: [[TMP5361:%.*]] = extractvalue { i64, i1 } [[TMP5358]], 1
-// CHECK-NEXT: [[TMP5362:%.*]] = select i1 [[TMP5361]], double [[TMP5354]], double [[TMP5360]]
-// CHECK-NEXT: store double [[TMP5362]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5363:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5364:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5365:%.*]] = bitcast double [[TMP5363]] to i64
-// CHECK-NEXT: [[TMP5366:%.*]] = bitcast double [[TMP5364]] to i64
-// CHECK-NEXT: [[TMP5367:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5365]], i64 [[TMP5366]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5368:%.*]] = extractvalue { i64, i1 } [[TMP5367]], 0
-// CHECK-NEXT: [[TMP5369:%.*]] = bitcast i64 [[TMP5368]] to double
-// CHECK-NEXT: [[TMP5370:%.*]] = extractvalue { i64, i1 } [[TMP5367]], 1
-// CHECK-NEXT: [[TMP5371:%.*]] = select i1 [[TMP5370]], double [[TMP5363]], double [[TMP5369]]
-// CHECK-NEXT: store double [[TMP5371]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5372:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5373:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5374:%.*]] = bitcast double [[TMP5372]] to i64
-// CHECK-NEXT: [[TMP5375:%.*]] = bitcast double [[TMP5373]] to i64
-// CHECK-NEXT: [[TMP5376:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5374]], i64 [[TMP5375]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5377:%.*]] = extractvalue { i64, i1 } [[TMP5376]], 0
-// CHECK-NEXT: [[TMP5378:%.*]] = bitcast i64 [[TMP5377]] to double
-// CHECK-NEXT: [[TMP5379:%.*]] = extractvalue { i64, i1 } [[TMP5376]], 1
-// CHECK-NEXT: br i1 [[TMP5379]], label [[DX_ATOMIC_EXIT:%.*]], label [[DX_ATOMIC_CONT:%.*]]
+// CHECK-NEXT: [[TMP2914:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2915:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2914]], ptr [[FX_ATOMIC_EXPECTED_PTR5809]], align 4
+// CHECK-NEXT: store float [[TMP2915]], ptr [[FX_ATOMIC_DESIRED_PTR5810]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5812:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5809]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5813:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5810]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5814:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5812]], i32 [[FX_CMPXCHG_DESIRED5813]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5815:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5814]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5815]], ptr [[FX_ATOMIC_EXPECTED_PTR5811]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5816:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5814]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5817:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5811]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS5816]], label [[FX_ATOMIC_EXIT5818:%.*]], label [[FX_ATOMIC_CONT5819:%.*]]
+// CHECK: fx.atomic.cont5819:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL5817]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT5818]]
+// CHECK: fx.atomic.exit5818:
+// CHECK-NEXT: [[TMP2916:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2917:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2916]], ptr [[FX_ATOMIC_EXPECTED_PTR5820]], align 4
+// CHECK-NEXT: store float [[TMP2917]], ptr [[FX_ATOMIC_DESIRED_PTR5821]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5823:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5820]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5824:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5821]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5825:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5823]], i32 [[FX_CMPXCHG_DESIRED5824]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5826:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5825]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5826]], ptr [[FX_ATOMIC_EXPECTED_PTR5822]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5827:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5825]], 1
+// CHECK-NEXT: [[TMP2918:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS5827]] to i32
+// CHECK-NEXT: store i32 [[TMP2918]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP2919:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2920:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2919]], ptr [[FX_ATOMIC_EXPECTED_PTR5828]], align 4
+// CHECK-NEXT: store float [[TMP2920]], ptr [[FX_ATOMIC_DESIRED_PTR5829]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5831:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5828]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5832:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5829]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5833:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5831]], i32 [[FX_CMPXCHG_DESIRED5832]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5834:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5833]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5834]], ptr [[FX_ATOMIC_EXPECTED_PTR5830]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5835:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5833]], 1
+// CHECK-NEXT: [[TMP2921:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS5835]] to i32
+// CHECK-NEXT: store i32 [[TMP2921]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP2922:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2923:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2922]], ptr [[FX_ATOMIC_EXPECTED_PTR5836]], align 4
+// CHECK-NEXT: store float [[TMP2923]], ptr [[FX_ATOMIC_DESIRED_PTR5837]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5839:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5836]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5840:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5837]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5841:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5839]], i32 [[FX_CMPXCHG_DESIRED5840]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5842:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5841]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5842]], ptr [[FX_ATOMIC_EXPECTED_PTR5838]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5843:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5841]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5844:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5838]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS5843]], label [[FX_ATOMIC_EXIT5845:%.*]], label [[FX_ATOMIC_CONT5846:%.*]]
+// CHECK: fx.atomic.cont5846:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL5844]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT5845]]
+// CHECK: fx.atomic.exit5845:
+// CHECK-NEXT: [[TMP2924:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS5843]] to i32
+// CHECK-NEXT: store i32 [[TMP2924]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP2925:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2926:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2925]], ptr [[FX_ATOMIC_EXPECTED_PTR5847]], align 4
+// CHECK-NEXT: store float [[TMP2926]], ptr [[FX_ATOMIC_DESIRED_PTR5848]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5850:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5847]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5851:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5848]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5852:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5850]], i32 [[FX_CMPXCHG_DESIRED5851]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5853:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5852]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5853]], ptr [[FX_ATOMIC_EXPECTED_PTR5849]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5854:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5852]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5855:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5849]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS5854]], label [[FX_ATOMIC_EXIT5856:%.*]], label [[FX_ATOMIC_CONT5857:%.*]]
+// CHECK: fx.atomic.cont5857:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL5855]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT5856]]
+// CHECK: fx.atomic.exit5856:
+// CHECK-NEXT: [[TMP2927:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS5854]] to i32
+// CHECK-NEXT: store i32 [[TMP2927]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP2928:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2929:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP2928]] acq_rel, align 4
+// CHECK-NEXT: store float [[TMP2929]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2930:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2931:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP2930]] acq_rel, align 4
+// CHECK-NEXT: store float [[TMP2931]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2932:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2933:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP2932]] acq_rel, align 4
+// CHECK-NEXT: store float [[TMP2933]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2934:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2935:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP2934]] acq_rel, align 4
+// CHECK-NEXT: store float [[TMP2935]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2936:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2937:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2936]], ptr [[FX_ATOMIC_EXPECTED_PTR5858]], align 4
+// CHECK-NEXT: store float [[TMP2937]], ptr [[FX_ATOMIC_DESIRED_PTR5859]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5861:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5858]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5862:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5859]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5863:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5861]], i32 [[FX_CMPXCHG_DESIRED5862]] acq_rel acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5864:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5863]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5864]], ptr [[FX_ATOMIC_EXPECTED_PTR5860]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5865:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5863]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5866:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5860]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL5866]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2938:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2939:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2938]], ptr [[FX_ATOMIC_EXPECTED_PTR5867]], align 4
+// CHECK-NEXT: store float [[TMP2939]], ptr [[FX_ATOMIC_DESIRED_PTR5868]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5870:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5867]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5871:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5868]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5872:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5870]], i32 [[FX_CMPXCHG_DESIRED5871]] acq_rel acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5873:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5872]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5873]], ptr [[FX_ATOMIC_EXPECTED_PTR5869]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5874:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5872]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5875:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5869]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL5875]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2940:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2941:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP2940]] acq_rel, align 4
+// CHECK-NEXT: [[TMP2942:%.*]] = fcmp ogt float [[TMP2941]], [[TMP2940]]
+// CHECK-NEXT: [[TMP2943:%.*]] = select i1 [[TMP2942]], float [[TMP2940]], float [[TMP2941]]
+// CHECK-NEXT: store float [[TMP2943]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2944:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2945:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP2944]] acq_rel, align 4
+// CHECK-NEXT: [[TMP2946:%.*]] = fcmp olt float [[TMP2945]], [[TMP2944]]
+// CHECK-NEXT: [[TMP2947:%.*]] = select i1 [[TMP2946]], float [[TMP2944]], float [[TMP2945]]
+// CHECK-NEXT: store float [[TMP2947]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2948:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2949:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP2948]] acq_rel, align 4
+// CHECK-NEXT: [[TMP2950:%.*]] = fcmp olt float [[TMP2949]], [[TMP2948]]
+// CHECK-NEXT: [[TMP2951:%.*]] = select i1 [[TMP2950]], float [[TMP2948]], float [[TMP2949]]
+// CHECK-NEXT: store float [[TMP2951]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2952:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2953:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP2952]] acq_rel, align 4
+// CHECK-NEXT: [[TMP2954:%.*]] = fcmp ogt float [[TMP2953]], [[TMP2952]]
+// CHECK-NEXT: [[TMP2955:%.*]] = select i1 [[TMP2954]], float [[TMP2952]], float [[TMP2953]]
+// CHECK-NEXT: store float [[TMP2955]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2956:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2957:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2956]], ptr [[FX_ATOMIC_EXPECTED_PTR5876]], align 4
+// CHECK-NEXT: store float [[TMP2957]], ptr [[FX_ATOMIC_DESIRED_PTR5877]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5879:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5876]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5880:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5877]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5881:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5879]], i32 [[FX_CMPXCHG_DESIRED5880]] acq_rel acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5882:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5881]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5882]], ptr [[FX_ATOMIC_EXPECTED_PTR5878]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5883:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5881]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5884:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5878]], align 4
+// CHECK-NEXT: [[FX_CAPTURE_CAPTURED5885:%.*]] = select i1 [[FX_CMPXCHG_SUCCESS5883]], float [[TMP2956]], float [[FX_CAPTURE_ACTUAL5884]]
+// CHECK-NEXT: store float [[FX_CAPTURE_CAPTURED5885]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2958:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2959:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2958]], ptr [[FX_ATOMIC_EXPECTED_PTR5886]], align 4
+// CHECK-NEXT: store float [[TMP2959]], ptr [[FX_ATOMIC_DESIRED_PTR5887]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5889:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5886]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5890:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5887]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5891:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5889]], i32 [[FX_CMPXCHG_DESIRED5890]] acq_rel acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5892:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5891]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5892]], ptr [[FX_ATOMIC_EXPECTED_PTR5888]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5893:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5891]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5894:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5888]], align 4
+// CHECK-NEXT: [[FX_CAPTURE_CAPTURED5895:%.*]] = select i1 [[FX_CMPXCHG_SUCCESS5893]], float [[TMP2958]], float [[FX_CAPTURE_ACTUAL5894]]
+// CHECK-NEXT: store float [[FX_CAPTURE_CAPTURED5895]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2960:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2961:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2960]], ptr [[FX_ATOMIC_EXPECTED_PTR5896]], align 4
+// CHECK-NEXT: store float [[TMP2961]], ptr [[FX_ATOMIC_DESIRED_PTR5897]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5899:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5896]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5900:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5897]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5901:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5899]], i32 [[FX_CMPXCHG_DESIRED5900]] acq_rel acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5902:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5901]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5902]], ptr [[FX_ATOMIC_EXPECTED_PTR5898]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5903:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5901]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5904:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5898]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS5903]], label [[FX_ATOMIC_EXIT5905:%.*]], label [[FX_ATOMIC_CONT5906:%.*]]
+// CHECK: fx.atomic.cont5906:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL5904]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT5905]]
+// CHECK: fx.atomic.exit5905:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2962:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2963:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2962]], ptr [[FX_ATOMIC_EXPECTED_PTR5907]], align 4
+// CHECK-NEXT: store float [[TMP2963]], ptr [[FX_ATOMIC_DESIRED_PTR5908]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5910:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5907]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5911:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5908]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5912:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5910]], i32 [[FX_CMPXCHG_DESIRED5911]] acq_rel acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5913:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5912]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5913]], ptr [[FX_ATOMIC_EXPECTED_PTR5909]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5914:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5912]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5915:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5909]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS5914]], label [[FX_ATOMIC_EXIT5916:%.*]], label [[FX_ATOMIC_CONT5917:%.*]]
+// CHECK: fx.atomic.cont5917:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL5915]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT5916]]
+// CHECK: fx.atomic.exit5916:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2964:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2965:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2964]], ptr [[FX_ATOMIC_EXPECTED_PTR5918]], align 4
+// CHECK-NEXT: store float [[TMP2965]], ptr [[FX_ATOMIC_DESIRED_PTR5919]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5921:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5918]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5922:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5919]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5923:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5921]], i32 [[FX_CMPXCHG_DESIRED5922]] acq_rel acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5924:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5923]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5924]], ptr [[FX_ATOMIC_EXPECTED_PTR5920]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5925:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5923]], 1
+// CHECK-NEXT: [[TMP2966:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS5925]] to i32
+// CHECK-NEXT: store i32 [[TMP2966]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2967:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2968:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2967]], ptr [[FX_ATOMIC_EXPECTED_PTR5926]], align 4
+// CHECK-NEXT: store float [[TMP2968]], ptr [[FX_ATOMIC_DESIRED_PTR5927]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5929:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5926]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5930:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5927]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5931:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5929]], i32 [[FX_CMPXCHG_DESIRED5930]] acq_rel acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5932:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5931]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5932]], ptr [[FX_ATOMIC_EXPECTED_PTR5928]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5933:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5931]], 1
+// CHECK-NEXT: [[TMP2969:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS5933]] to i32
+// CHECK-NEXT: store i32 [[TMP2969]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2970:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2971:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2970]], ptr [[FX_ATOMIC_EXPECTED_PTR5934]], align 4
+// CHECK-NEXT: store float [[TMP2971]], ptr [[FX_ATOMIC_DESIRED_PTR5935]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5937:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5934]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5938:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5935]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5939:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5937]], i32 [[FX_CMPXCHG_DESIRED5938]] acq_rel acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5940:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5939]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5940]], ptr [[FX_ATOMIC_EXPECTED_PTR5936]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5941:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5939]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5942:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5936]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS5941]], label [[FX_ATOMIC_EXIT5943:%.*]], label [[FX_ATOMIC_CONT5944:%.*]]
+// CHECK: fx.atomic.cont5944:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL5942]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT5943]]
+// CHECK: fx.atomic.exit5943:
+// CHECK-NEXT: [[TMP2972:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS5941]] to i32
+// CHECK-NEXT: store i32 [[TMP2972]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2973:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2974:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2973]], ptr [[FX_ATOMIC_EXPECTED_PTR5945]], align 4
+// CHECK-NEXT: store float [[TMP2974]], ptr [[FX_ATOMIC_DESIRED_PTR5946]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5948:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5945]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5949:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5946]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5950:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5948]], i32 [[FX_CMPXCHG_DESIRED5949]] acq_rel acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5951:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5950]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5951]], ptr [[FX_ATOMIC_EXPECTED_PTR5947]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5952:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5950]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5953:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5947]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS5952]], label [[FX_ATOMIC_EXIT5954:%.*]], label [[FX_ATOMIC_CONT5955:%.*]]
+// CHECK: fx.atomic.cont5955:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL5953]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT5954]]
+// CHECK: fx.atomic.exit5954:
+// CHECK-NEXT: [[TMP2975:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS5952]] to i32
+// CHECK-NEXT: store i32 [[TMP2975]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP2976:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2977:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP2976]] acquire, align 4
+// CHECK-NEXT: store float [[TMP2977]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2978:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2979:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP2978]] acquire, align 4
+// CHECK-NEXT: store float [[TMP2979]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2980:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2981:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP2980]] acquire, align 4
+// CHECK-NEXT: store float [[TMP2981]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2982:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2983:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP2982]] acquire, align 4
+// CHECK-NEXT: store float [[TMP2983]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2984:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2985:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2984]], ptr [[FX_ATOMIC_EXPECTED_PTR5956]], align 4
+// CHECK-NEXT: store float [[TMP2985]], ptr [[FX_ATOMIC_DESIRED_PTR5957]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5959:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5956]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5960:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5957]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5961:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5959]], i32 [[FX_CMPXCHG_DESIRED5960]] acquire acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5962:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5961]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5962]], ptr [[FX_ATOMIC_EXPECTED_PTR5958]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5963:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5961]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5964:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5958]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL5964]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2986:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2987:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP2986]], ptr [[FX_ATOMIC_EXPECTED_PTR5965]], align 4
+// CHECK-NEXT: store float [[TMP2987]], ptr [[FX_ATOMIC_DESIRED_PTR5966]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5968:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5965]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5969:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5966]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5970:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5968]], i32 [[FX_CMPXCHG_DESIRED5969]] acquire acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5971:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5970]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5971]], ptr [[FX_ATOMIC_EXPECTED_PTR5967]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5972:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5970]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5973:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5967]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL5973]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2988:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2989:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP2988]] acquire, align 4
+// CHECK-NEXT: [[TMP2990:%.*]] = fcmp ogt float [[TMP2989]], [[TMP2988]]
+// CHECK-NEXT: [[TMP2991:%.*]] = select i1 [[TMP2990]], float [[TMP2988]], float [[TMP2989]]
+// CHECK-NEXT: store float [[TMP2991]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2992:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2993:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP2992]] acquire, align 4
+// CHECK-NEXT: [[TMP2994:%.*]] = fcmp olt float [[TMP2993]], [[TMP2992]]
+// CHECK-NEXT: [[TMP2995:%.*]] = select i1 [[TMP2994]], float [[TMP2992]], float [[TMP2993]]
+// CHECK-NEXT: store float [[TMP2995]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP2996:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP2997:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP2996]] acquire, align 4
+// CHECK-NEXT: [[TMP2998:%.*]] = fcmp olt float [[TMP2997]], [[TMP2996]]
+// CHECK-NEXT: [[TMP2999:%.*]] = select i1 [[TMP2998]], float [[TMP2996]], float [[TMP2997]]
+// CHECK-NEXT: store float [[TMP2999]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP3000:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3001:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP3000]] acquire, align 4
+// CHECK-NEXT: [[TMP3002:%.*]] = fcmp ogt float [[TMP3001]], [[TMP3000]]
+// CHECK-NEXT: [[TMP3003:%.*]] = select i1 [[TMP3002]], float [[TMP3000]], float [[TMP3001]]
+// CHECK-NEXT: store float [[TMP3003]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP3004:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3005:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3004]], ptr [[FX_ATOMIC_EXPECTED_PTR5974]], align 4
+// CHECK-NEXT: store float [[TMP3005]], ptr [[FX_ATOMIC_DESIRED_PTR5975]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5977:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5974]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5978:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5975]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5979:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5977]], i32 [[FX_CMPXCHG_DESIRED5978]] acquire acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5980:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5979]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5980]], ptr [[FX_ATOMIC_EXPECTED_PTR5976]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5981:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5979]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5982:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5976]], align 4
+// CHECK-NEXT: [[FX_CAPTURE_CAPTURED5983:%.*]] = select i1 [[FX_CMPXCHG_SUCCESS5981]], float [[TMP3004]], float [[FX_CAPTURE_ACTUAL5982]]
+// CHECK-NEXT: store float [[FX_CAPTURE_CAPTURED5983]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP3006:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3007:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3006]], ptr [[FX_ATOMIC_EXPECTED_PTR5984]], align 4
+// CHECK-NEXT: store float [[TMP3007]], ptr [[FX_ATOMIC_DESIRED_PTR5985]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5987:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5984]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5988:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5985]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5989:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5987]], i32 [[FX_CMPXCHG_DESIRED5988]] acquire acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV5990:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5989]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV5990]], ptr [[FX_ATOMIC_EXPECTED_PTR5986]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS5991:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5989]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL5992:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5986]], align 4
+// CHECK-NEXT: [[FX_CAPTURE_CAPTURED5993:%.*]] = select i1 [[FX_CMPXCHG_SUCCESS5991]], float [[TMP3006]], float [[FX_CAPTURE_ACTUAL5992]]
+// CHECK-NEXT: store float [[FX_CAPTURE_CAPTURED5993]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP3008:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3009:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3008]], ptr [[FX_ATOMIC_EXPECTED_PTR5994]], align 4
+// CHECK-NEXT: store float [[TMP3009]], ptr [[FX_ATOMIC_DESIRED_PTR5995]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5997:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR5994]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED5998:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR5995]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR5999:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5997]], i32 [[FX_CMPXCHG_DESIRED5998]] acquire acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6000:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5999]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6000]], ptr [[FX_ATOMIC_EXPECTED_PTR5996]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6001:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR5999]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6002:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR5996]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS6001]], label [[FX_ATOMIC_EXIT6003:%.*]], label [[FX_ATOMIC_CONT6004:%.*]]
+// CHECK: fx.atomic.cont6004:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6002]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT6003]]
+// CHECK: fx.atomic.exit6003:
+// CHECK-NEXT: [[TMP3010:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3011:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3010]], ptr [[FX_ATOMIC_EXPECTED_PTR6005]], align 4
+// CHECK-NEXT: store float [[TMP3011]], ptr [[FX_ATOMIC_DESIRED_PTR6006]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6008:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6005]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6009:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6006]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6010:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6008]], i32 [[FX_CMPXCHG_DESIRED6009]] acquire acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6011:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6010]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6011]], ptr [[FX_ATOMIC_EXPECTED_PTR6007]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6012:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6010]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6013:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6007]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS6012]], label [[FX_ATOMIC_EXIT6014:%.*]], label [[FX_ATOMIC_CONT6015:%.*]]
+// CHECK: fx.atomic.cont6015:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6013]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT6014]]
+// CHECK: fx.atomic.exit6014:
+// CHECK-NEXT: [[TMP3012:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3013:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3012]], ptr [[FX_ATOMIC_EXPECTED_PTR6016]], align 4
+// CHECK-NEXT: store float [[TMP3013]], ptr [[FX_ATOMIC_DESIRED_PTR6017]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6019:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6016]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6020:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6017]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6021:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6019]], i32 [[FX_CMPXCHG_DESIRED6020]] acquire acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6022:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6021]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6022]], ptr [[FX_ATOMIC_EXPECTED_PTR6018]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6023:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6021]], 1
+// CHECK-NEXT: [[TMP3014:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS6023]] to i32
+// CHECK-NEXT: store i32 [[TMP3014]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3015:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3016:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3015]], ptr [[FX_ATOMIC_EXPECTED_PTR6024]], align 4
+// CHECK-NEXT: store float [[TMP3016]], ptr [[FX_ATOMIC_DESIRED_PTR6025]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6027:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6024]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6028:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6025]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6029:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6027]], i32 [[FX_CMPXCHG_DESIRED6028]] acquire acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6030:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6029]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6030]], ptr [[FX_ATOMIC_EXPECTED_PTR6026]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6031:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6029]], 1
+// CHECK-NEXT: [[TMP3017:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS6031]] to i32
+// CHECK-NEXT: store i32 [[TMP3017]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3018:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3019:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3018]], ptr [[FX_ATOMIC_EXPECTED_PTR6032]], align 4
+// CHECK-NEXT: store float [[TMP3019]], ptr [[FX_ATOMIC_DESIRED_PTR6033]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6035:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6032]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6036:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6033]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6037:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6035]], i32 [[FX_CMPXCHG_DESIRED6036]] acquire acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6038:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6037]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6038]], ptr [[FX_ATOMIC_EXPECTED_PTR6034]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6039:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6037]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6040:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6034]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS6039]], label [[FX_ATOMIC_EXIT6041:%.*]], label [[FX_ATOMIC_CONT6042:%.*]]
+// CHECK: fx.atomic.cont6042:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6040]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT6041]]
+// CHECK: fx.atomic.exit6041:
+// CHECK-NEXT: [[TMP3020:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS6039]] to i32
+// CHECK-NEXT: store i32 [[TMP3020]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3021:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3022:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3021]], ptr [[FX_ATOMIC_EXPECTED_PTR6043]], align 4
+// CHECK-NEXT: store float [[TMP3022]], ptr [[FX_ATOMIC_DESIRED_PTR6044]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6046:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6043]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6047:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6044]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6048:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6046]], i32 [[FX_CMPXCHG_DESIRED6047]] acquire acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6049:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6048]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6049]], ptr [[FX_ATOMIC_EXPECTED_PTR6045]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6050:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6048]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6051:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6045]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS6050]], label [[FX_ATOMIC_EXIT6052:%.*]], label [[FX_ATOMIC_CONT6053:%.*]]
+// CHECK: fx.atomic.cont6053:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6051]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT6052]]
+// CHECK: fx.atomic.exit6052:
+// CHECK-NEXT: [[TMP3023:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS6050]] to i32
+// CHECK-NEXT: store i32 [[TMP3023]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3024:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3025:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP3024]] monotonic, align 4
+// CHECK-NEXT: store float [[TMP3025]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP3026:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3027:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP3026]] monotonic, align 4
+// CHECK-NEXT: store float [[TMP3027]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP3028:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3029:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP3028]] monotonic, align 4
+// CHECK-NEXT: store float [[TMP3029]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP3030:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3031:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP3030]] monotonic, align 4
+// CHECK-NEXT: store float [[TMP3031]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP3032:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3033:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3032]], ptr [[FX_ATOMIC_EXPECTED_PTR6054]], align 4
+// CHECK-NEXT: store float [[TMP3033]], ptr [[FX_ATOMIC_DESIRED_PTR6055]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6057:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6054]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6058:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6055]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6059:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6057]], i32 [[FX_CMPXCHG_DESIRED6058]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6060:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6059]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6060]], ptr [[FX_ATOMIC_EXPECTED_PTR6056]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6061:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6059]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6062:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6056]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6062]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP3034:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3035:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3034]], ptr [[FX_ATOMIC_EXPECTED_PTR6063]], align 4
+// CHECK-NEXT: store float [[TMP3035]], ptr [[FX_ATOMIC_DESIRED_PTR6064]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6066:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6063]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6067:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6064]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6068:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6066]], i32 [[FX_CMPXCHG_DESIRED6067]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6069:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6068]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6069]], ptr [[FX_ATOMIC_EXPECTED_PTR6065]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6070:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6068]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6071:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6065]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6071]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP3036:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3037:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP3036]] monotonic, align 4
+// CHECK-NEXT: [[TMP3038:%.*]] = fcmp ogt float [[TMP3037]], [[TMP3036]]
+// CHECK-NEXT: [[TMP3039:%.*]] = select i1 [[TMP3038]], float [[TMP3036]], float [[TMP3037]]
+// CHECK-NEXT: store float [[TMP3039]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP3040:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3041:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP3040]] monotonic, align 4
+// CHECK-NEXT: [[TMP3042:%.*]] = fcmp olt float [[TMP3041]], [[TMP3040]]
+// CHECK-NEXT: [[TMP3043:%.*]] = select i1 [[TMP3042]], float [[TMP3040]], float [[TMP3041]]
+// CHECK-NEXT: store float [[TMP3043]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP3044:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3045:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP3044]] monotonic, align 4
+// CHECK-NEXT: [[TMP3046:%.*]] = fcmp olt float [[TMP3045]], [[TMP3044]]
+// CHECK-NEXT: [[TMP3047:%.*]] = select i1 [[TMP3046]], float [[TMP3044]], float [[TMP3045]]
+// CHECK-NEXT: store float [[TMP3047]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP3048:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3049:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP3048]] monotonic, align 4
+// CHECK-NEXT: [[TMP3050:%.*]] = fcmp ogt float [[TMP3049]], [[TMP3048]]
+// CHECK-NEXT: [[TMP3051:%.*]] = select i1 [[TMP3050]], float [[TMP3048]], float [[TMP3049]]
+// CHECK-NEXT: store float [[TMP3051]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP3052:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3053:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3052]], ptr [[FX_ATOMIC_EXPECTED_PTR6072]], align 4
+// CHECK-NEXT: store float [[TMP3053]], ptr [[FX_ATOMIC_DESIRED_PTR6073]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6075:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6072]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6076:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6073]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6077:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6075]], i32 [[FX_CMPXCHG_DESIRED6076]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6078:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6077]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6078]], ptr [[FX_ATOMIC_EXPECTED_PTR6074]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6079:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6077]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6080:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6074]], align 4
+// CHECK-NEXT: [[FX_CAPTURE_CAPTURED6081:%.*]] = select i1 [[FX_CMPXCHG_SUCCESS6079]], float [[TMP3052]], float [[FX_CAPTURE_ACTUAL6080]]
+// CHECK-NEXT: store float [[FX_CAPTURE_CAPTURED6081]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP3054:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3055:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3054]], ptr [[FX_ATOMIC_EXPECTED_PTR6082]], align 4
+// CHECK-NEXT: store float [[TMP3055]], ptr [[FX_ATOMIC_DESIRED_PTR6083]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6085:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6082]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6086:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6083]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6087:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6085]], i32 [[FX_CMPXCHG_DESIRED6086]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6088:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6087]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6088]], ptr [[FX_ATOMIC_EXPECTED_PTR6084]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6089:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6087]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6090:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6084]], align 4
+// CHECK-NEXT: [[FX_CAPTURE_CAPTURED6091:%.*]] = select i1 [[FX_CMPXCHG_SUCCESS6089]], float [[TMP3054]], float [[FX_CAPTURE_ACTUAL6090]]
+// CHECK-NEXT: store float [[FX_CAPTURE_CAPTURED6091]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP3056:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3057:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3056]], ptr [[FX_ATOMIC_EXPECTED_PTR6092]], align 4
+// CHECK-NEXT: store float [[TMP3057]], ptr [[FX_ATOMIC_DESIRED_PTR6093]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6095:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6092]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6096:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6093]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6097:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6095]], i32 [[FX_CMPXCHG_DESIRED6096]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6098:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6097]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6098]], ptr [[FX_ATOMIC_EXPECTED_PTR6094]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6099:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6097]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6100:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6094]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS6099]], label [[FX_ATOMIC_EXIT6101:%.*]], label [[FX_ATOMIC_CONT6102:%.*]]
+// CHECK: fx.atomic.cont6102:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6100]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT6101]]
+// CHECK: fx.atomic.exit6101:
+// CHECK-NEXT: [[TMP3058:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3059:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3058]], ptr [[FX_ATOMIC_EXPECTED_PTR6103]], align 4
+// CHECK-NEXT: store float [[TMP3059]], ptr [[FX_ATOMIC_DESIRED_PTR6104]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6106:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6103]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6107:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6104]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6108:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6106]], i32 [[FX_CMPXCHG_DESIRED6107]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6109:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6108]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6109]], ptr [[FX_ATOMIC_EXPECTED_PTR6105]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6110:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6108]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6111:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6105]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS6110]], label [[FX_ATOMIC_EXIT6112:%.*]], label [[FX_ATOMIC_CONT6113:%.*]]
+// CHECK: fx.atomic.cont6113:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6111]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT6112]]
+// CHECK: fx.atomic.exit6112:
+// CHECK-NEXT: [[TMP3060:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3061:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3060]], ptr [[FX_ATOMIC_EXPECTED_PTR6114]], align 4
+// CHECK-NEXT: store float [[TMP3061]], ptr [[FX_ATOMIC_DESIRED_PTR6115]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6117:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6114]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6118:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6115]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6119:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6117]], i32 [[FX_CMPXCHG_DESIRED6118]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6120:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6119]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6120]], ptr [[FX_ATOMIC_EXPECTED_PTR6116]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6121:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6119]], 1
+// CHECK-NEXT: [[TMP3062:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS6121]] to i32
+// CHECK-NEXT: store i32 [[TMP3062]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3063:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3064:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3063]], ptr [[FX_ATOMIC_EXPECTED_PTR6122]], align 4
+// CHECK-NEXT: store float [[TMP3064]], ptr [[FX_ATOMIC_DESIRED_PTR6123]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6125:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6122]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6126:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6123]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6127:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6125]], i32 [[FX_CMPXCHG_DESIRED6126]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6128:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6127]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6128]], ptr [[FX_ATOMIC_EXPECTED_PTR6124]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6129:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6127]], 1
+// CHECK-NEXT: [[TMP3065:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS6129]] to i32
+// CHECK-NEXT: store i32 [[TMP3065]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3066:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3067:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3066]], ptr [[FX_ATOMIC_EXPECTED_PTR6130]], align 4
+// CHECK-NEXT: store float [[TMP3067]], ptr [[FX_ATOMIC_DESIRED_PTR6131]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6133:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6130]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6134:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6131]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6135:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6133]], i32 [[FX_CMPXCHG_DESIRED6134]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6136:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6135]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6136]], ptr [[FX_ATOMIC_EXPECTED_PTR6132]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6137:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6135]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6138:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6132]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS6137]], label [[FX_ATOMIC_EXIT6139:%.*]], label [[FX_ATOMIC_CONT6140:%.*]]
+// CHECK: fx.atomic.cont6140:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6138]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT6139]]
+// CHECK: fx.atomic.exit6139:
+// CHECK-NEXT: [[TMP3068:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS6137]] to i32
+// CHECK-NEXT: store i32 [[TMP3068]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3069:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3070:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3069]], ptr [[FX_ATOMIC_EXPECTED_PTR6141]], align 4
+// CHECK-NEXT: store float [[TMP3070]], ptr [[FX_ATOMIC_DESIRED_PTR6142]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6144:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6141]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6145:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6142]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6146:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6144]], i32 [[FX_CMPXCHG_DESIRED6145]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6147:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6146]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6147]], ptr [[FX_ATOMIC_EXPECTED_PTR6143]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6148:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6146]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6149:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6143]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS6148]], label [[FX_ATOMIC_EXIT6150:%.*]], label [[FX_ATOMIC_CONT6151:%.*]]
+// CHECK: fx.atomic.cont6151:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6149]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT6150]]
+// CHECK: fx.atomic.exit6150:
+// CHECK-NEXT: [[TMP3071:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS6148]] to i32
+// CHECK-NEXT: store i32 [[TMP3071]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3072:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3073:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP3072]] release, align 4
+// CHECK-NEXT: store float [[TMP3073]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3074:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3075:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP3074]] release, align 4
+// CHECK-NEXT: store float [[TMP3075]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3076:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3077:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP3076]] release, align 4
+// CHECK-NEXT: store float [[TMP3077]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3078:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3079:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP3078]] release, align 4
+// CHECK-NEXT: store float [[TMP3079]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3080:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3081:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3080]], ptr [[FX_ATOMIC_EXPECTED_PTR6152]], align 4
+// CHECK-NEXT: store float [[TMP3081]], ptr [[FX_ATOMIC_DESIRED_PTR6153]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6155:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6152]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6156:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6153]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6157:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6155]], i32 [[FX_CMPXCHG_DESIRED6156]] release monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6158:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6157]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6158]], ptr [[FX_ATOMIC_EXPECTED_PTR6154]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6159:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6157]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6160:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6154]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6160]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3082:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3083:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3082]], ptr [[FX_ATOMIC_EXPECTED_PTR6161]], align 4
+// CHECK-NEXT: store float [[TMP3083]], ptr [[FX_ATOMIC_DESIRED_PTR6162]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6164:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6161]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6165:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6162]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6166:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6164]], i32 [[FX_CMPXCHG_DESIRED6165]] release monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6167:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6166]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6167]], ptr [[FX_ATOMIC_EXPECTED_PTR6163]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6168:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6166]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6169:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6163]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6169]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3084:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3085:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP3084]] release, align 4
+// CHECK-NEXT: [[TMP3086:%.*]] = fcmp ogt float [[TMP3085]], [[TMP3084]]
+// CHECK-NEXT: [[TMP3087:%.*]] = select i1 [[TMP3086]], float [[TMP3084]], float [[TMP3085]]
+// CHECK-NEXT: store float [[TMP3087]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3088:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3089:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP3088]] release, align 4
+// CHECK-NEXT: [[TMP3090:%.*]] = fcmp olt float [[TMP3089]], [[TMP3088]]
+// CHECK-NEXT: [[TMP3091:%.*]] = select i1 [[TMP3090]], float [[TMP3088]], float [[TMP3089]]
+// CHECK-NEXT: store float [[TMP3091]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3092:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3093:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP3092]] release, align 4
+// CHECK-NEXT: [[TMP3094:%.*]] = fcmp olt float [[TMP3093]], [[TMP3092]]
+// CHECK-NEXT: [[TMP3095:%.*]] = select i1 [[TMP3094]], float [[TMP3092]], float [[TMP3093]]
+// CHECK-NEXT: store float [[TMP3095]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3096:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3097:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP3096]] release, align 4
+// CHECK-NEXT: [[TMP3098:%.*]] = fcmp ogt float [[TMP3097]], [[TMP3096]]
+// CHECK-NEXT: [[TMP3099:%.*]] = select i1 [[TMP3098]], float [[TMP3096]], float [[TMP3097]]
+// CHECK-NEXT: store float [[TMP3099]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3100:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3101:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3100]], ptr [[FX_ATOMIC_EXPECTED_PTR6170]], align 4
+// CHECK-NEXT: store float [[TMP3101]], ptr [[FX_ATOMIC_DESIRED_PTR6171]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6173:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6170]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6174:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6171]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6175:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6173]], i32 [[FX_CMPXCHG_DESIRED6174]] release monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6176:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6175]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6176]], ptr [[FX_ATOMIC_EXPECTED_PTR6172]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6177:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6175]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6178:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6172]], align 4
+// CHECK-NEXT: [[FX_CAPTURE_CAPTURED6179:%.*]] = select i1 [[FX_CMPXCHG_SUCCESS6177]], float [[TMP3100]], float [[FX_CAPTURE_ACTUAL6178]]
+// CHECK-NEXT: store float [[FX_CAPTURE_CAPTURED6179]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3102:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3103:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3102]], ptr [[FX_ATOMIC_EXPECTED_PTR6180]], align 4
+// CHECK-NEXT: store float [[TMP3103]], ptr [[FX_ATOMIC_DESIRED_PTR6181]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6183:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6180]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6184:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6181]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6185:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6183]], i32 [[FX_CMPXCHG_DESIRED6184]] release monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6186:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6185]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6186]], ptr [[FX_ATOMIC_EXPECTED_PTR6182]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6187:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6185]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6188:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6182]], align 4
+// CHECK-NEXT: [[FX_CAPTURE_CAPTURED6189:%.*]] = select i1 [[FX_CMPXCHG_SUCCESS6187]], float [[TMP3102]], float [[FX_CAPTURE_ACTUAL6188]]
+// CHECK-NEXT: store float [[FX_CAPTURE_CAPTURED6189]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3104:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3105:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3104]], ptr [[FX_ATOMIC_EXPECTED_PTR6190]], align 4
+// CHECK-NEXT: store float [[TMP3105]], ptr [[FX_ATOMIC_DESIRED_PTR6191]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6193:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6190]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6194:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6191]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6195:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6193]], i32 [[FX_CMPXCHG_DESIRED6194]] release monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6196:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6195]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6196]], ptr [[FX_ATOMIC_EXPECTED_PTR6192]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6197:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6195]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6198:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6192]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS6197]], label [[FX_ATOMIC_EXIT6199:%.*]], label [[FX_ATOMIC_CONT6200:%.*]]
+// CHECK: fx.atomic.cont6200:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6198]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT6199]]
+// CHECK: fx.atomic.exit6199:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3106:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3107:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3106]], ptr [[FX_ATOMIC_EXPECTED_PTR6201]], align 4
+// CHECK-NEXT: store float [[TMP3107]], ptr [[FX_ATOMIC_DESIRED_PTR6202]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6204:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6201]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6205:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6202]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6206:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6204]], i32 [[FX_CMPXCHG_DESIRED6205]] release monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6207:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6206]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6207]], ptr [[FX_ATOMIC_EXPECTED_PTR6203]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6208:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6206]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6209:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6203]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS6208]], label [[FX_ATOMIC_EXIT6210:%.*]], label [[FX_ATOMIC_CONT6211:%.*]]
+// CHECK: fx.atomic.cont6211:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6209]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT6210]]
+// CHECK: fx.atomic.exit6210:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3108:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3109:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3108]], ptr [[FX_ATOMIC_EXPECTED_PTR6212]], align 4
+// CHECK-NEXT: store float [[TMP3109]], ptr [[FX_ATOMIC_DESIRED_PTR6213]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6215:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6212]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6216:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6213]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6217:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6215]], i32 [[FX_CMPXCHG_DESIRED6216]] release monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6218:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6217]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6218]], ptr [[FX_ATOMIC_EXPECTED_PTR6214]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6219:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6217]], 1
+// CHECK-NEXT: [[TMP3110:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS6219]] to i32
+// CHECK-NEXT: store i32 [[TMP3110]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3111:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3112:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3111]], ptr [[FX_ATOMIC_EXPECTED_PTR6220]], align 4
+// CHECK-NEXT: store float [[TMP3112]], ptr [[FX_ATOMIC_DESIRED_PTR6221]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6223:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6220]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6224:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6221]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6225:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6223]], i32 [[FX_CMPXCHG_DESIRED6224]] release monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6226:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6225]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6226]], ptr [[FX_ATOMIC_EXPECTED_PTR6222]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6227:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6225]], 1
+// CHECK-NEXT: [[TMP3113:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS6227]] to i32
+// CHECK-NEXT: store i32 [[TMP3113]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3114:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3115:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3114]], ptr [[FX_ATOMIC_EXPECTED_PTR6228]], align 4
+// CHECK-NEXT: store float [[TMP3115]], ptr [[FX_ATOMIC_DESIRED_PTR6229]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6231:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6228]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6232:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6229]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6233:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6231]], i32 [[FX_CMPXCHG_DESIRED6232]] release monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6234:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6233]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6234]], ptr [[FX_ATOMIC_EXPECTED_PTR6230]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6235:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6233]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6236:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6230]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS6235]], label [[FX_ATOMIC_EXIT6237:%.*]], label [[FX_ATOMIC_CONT6238:%.*]]
+// CHECK: fx.atomic.cont6238:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6236]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT6237]]
+// CHECK: fx.atomic.exit6237:
+// CHECK-NEXT: [[TMP3116:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS6235]] to i32
+// CHECK-NEXT: store i32 [[TMP3116]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3117:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3118:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3117]], ptr [[FX_ATOMIC_EXPECTED_PTR6239]], align 4
+// CHECK-NEXT: store float [[TMP3118]], ptr [[FX_ATOMIC_DESIRED_PTR6240]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6242:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6239]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6243:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6240]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6244:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6242]], i32 [[FX_CMPXCHG_DESIRED6243]] release monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6245:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6244]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6245]], ptr [[FX_ATOMIC_EXPECTED_PTR6241]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6246:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6244]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6247:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6241]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS6246]], label [[FX_ATOMIC_EXIT6248:%.*]], label [[FX_ATOMIC_CONT6249:%.*]]
+// CHECK: fx.atomic.cont6249:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6247]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT6248]]
+// CHECK: fx.atomic.exit6248:
+// CHECK-NEXT: [[TMP3119:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS6246]] to i32
+// CHECK-NEXT: store i32 [[TMP3119]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3120:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3121:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP3120]] seq_cst, align 4
+// CHECK-NEXT: store float [[TMP3121]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3122:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3123:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP3122]] seq_cst, align 4
+// CHECK-NEXT: store float [[TMP3123]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3124:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3125:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP3124]] seq_cst, align 4
+// CHECK-NEXT: store float [[TMP3125]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3126:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3127:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP3126]] seq_cst, align 4
+// CHECK-NEXT: store float [[TMP3127]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3128:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3129:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3128]], ptr [[FX_ATOMIC_EXPECTED_PTR6250]], align 4
+// CHECK-NEXT: store float [[TMP3129]], ptr [[FX_ATOMIC_DESIRED_PTR6251]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6253:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6250]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6254:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6251]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6255:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6253]], i32 [[FX_CMPXCHG_DESIRED6254]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6256:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6255]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6256]], ptr [[FX_ATOMIC_EXPECTED_PTR6252]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6257:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6255]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6258:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6252]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6258]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3130:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3131:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3130]], ptr [[FX_ATOMIC_EXPECTED_PTR6259]], align 4
+// CHECK-NEXT: store float [[TMP3131]], ptr [[FX_ATOMIC_DESIRED_PTR6260]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6262:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6259]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6263:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6260]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6264:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6262]], i32 [[FX_CMPXCHG_DESIRED6263]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6265:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6264]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6265]], ptr [[FX_ATOMIC_EXPECTED_PTR6261]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6266:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6264]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6267:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6261]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6267]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3132:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3133:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP3132]] seq_cst, align 4
+// CHECK-NEXT: [[TMP3134:%.*]] = fcmp ogt float [[TMP3133]], [[TMP3132]]
+// CHECK-NEXT: [[TMP3135:%.*]] = select i1 [[TMP3134]], float [[TMP3132]], float [[TMP3133]]
+// CHECK-NEXT: store float [[TMP3135]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3136:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3137:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP3136]] seq_cst, align 4
+// CHECK-NEXT: [[TMP3138:%.*]] = fcmp olt float [[TMP3137]], [[TMP3136]]
+// CHECK-NEXT: [[TMP3139:%.*]] = select i1 [[TMP3138]], float [[TMP3136]], float [[TMP3137]]
+// CHECK-NEXT: store float [[TMP3139]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3140:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3141:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP3140]] seq_cst, align 4
+// CHECK-NEXT: [[TMP3142:%.*]] = fcmp olt float [[TMP3141]], [[TMP3140]]
+// CHECK-NEXT: [[TMP3143:%.*]] = select i1 [[TMP3142]], float [[TMP3140]], float [[TMP3141]]
+// CHECK-NEXT: store float [[TMP3143]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3144:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3145:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP3144]] seq_cst, align 4
+// CHECK-NEXT: [[TMP3146:%.*]] = fcmp ogt float [[TMP3145]], [[TMP3144]]
+// CHECK-NEXT: [[TMP3147:%.*]] = select i1 [[TMP3146]], float [[TMP3144]], float [[TMP3145]]
+// CHECK-NEXT: store float [[TMP3147]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3148:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3149:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3148]], ptr [[FX_ATOMIC_EXPECTED_PTR6268]], align 4
+// CHECK-NEXT: store float [[TMP3149]], ptr [[FX_ATOMIC_DESIRED_PTR6269]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6271:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6268]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6272:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6269]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6273:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6271]], i32 [[FX_CMPXCHG_DESIRED6272]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6274:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6273]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6274]], ptr [[FX_ATOMIC_EXPECTED_PTR6270]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6275:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6273]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6276:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6270]], align 4
+// CHECK-NEXT: [[FX_CAPTURE_CAPTURED6277:%.*]] = select i1 [[FX_CMPXCHG_SUCCESS6275]], float [[TMP3148]], float [[FX_CAPTURE_ACTUAL6276]]
+// CHECK-NEXT: store float [[FX_CAPTURE_CAPTURED6277]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3150:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3151:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3150]], ptr [[FX_ATOMIC_EXPECTED_PTR6278]], align 4
+// CHECK-NEXT: store float [[TMP3151]], ptr [[FX_ATOMIC_DESIRED_PTR6279]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6281:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6278]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6282:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6279]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6283:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6281]], i32 [[FX_CMPXCHG_DESIRED6282]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6284:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6283]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6284]], ptr [[FX_ATOMIC_EXPECTED_PTR6280]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6285:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6283]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6286:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6280]], align 4
+// CHECK-NEXT: [[FX_CAPTURE_CAPTURED6287:%.*]] = select i1 [[FX_CMPXCHG_SUCCESS6285]], float [[TMP3150]], float [[FX_CAPTURE_ACTUAL6286]]
+// CHECK-NEXT: store float [[FX_CAPTURE_CAPTURED6287]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3152:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3153:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3152]], ptr [[FX_ATOMIC_EXPECTED_PTR6288]], align 4
+// CHECK-NEXT: store float [[TMP3153]], ptr [[FX_ATOMIC_DESIRED_PTR6289]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6291:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6288]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6292:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6289]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6293:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6291]], i32 [[FX_CMPXCHG_DESIRED6292]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6294:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6293]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6294]], ptr [[FX_ATOMIC_EXPECTED_PTR6290]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6295:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6293]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6296:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6290]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS6295]], label [[FX_ATOMIC_EXIT6297:%.*]], label [[FX_ATOMIC_CONT6298:%.*]]
+// CHECK: fx.atomic.cont6298:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6296]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT6297]]
+// CHECK: fx.atomic.exit6297:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3154:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3155:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3154]], ptr [[FX_ATOMIC_EXPECTED_PTR6299]], align 4
+// CHECK-NEXT: store float [[TMP3155]], ptr [[FX_ATOMIC_DESIRED_PTR6300]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6302:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6299]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6303:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6300]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6304:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6302]], i32 [[FX_CMPXCHG_DESIRED6303]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6305:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6304]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6305]], ptr [[FX_ATOMIC_EXPECTED_PTR6301]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6306:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6304]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6307:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6301]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS6306]], label [[FX_ATOMIC_EXIT6308:%.*]], label [[FX_ATOMIC_CONT6309:%.*]]
+// CHECK: fx.atomic.cont6309:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6307]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT6308]]
+// CHECK: fx.atomic.exit6308:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3156:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3157:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3156]], ptr [[FX_ATOMIC_EXPECTED_PTR6310]], align 4
+// CHECK-NEXT: store float [[TMP3157]], ptr [[FX_ATOMIC_DESIRED_PTR6311]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6313:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6310]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6314:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6311]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6315:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6313]], i32 [[FX_CMPXCHG_DESIRED6314]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6316:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6315]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6316]], ptr [[FX_ATOMIC_EXPECTED_PTR6312]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6317:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6315]], 1
+// CHECK-NEXT: [[TMP3158:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS6317]] to i32
+// CHECK-NEXT: store i32 [[TMP3158]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3159:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3160:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3159]], ptr [[FX_ATOMIC_EXPECTED_PTR6318]], align 4
+// CHECK-NEXT: store float [[TMP3160]], ptr [[FX_ATOMIC_DESIRED_PTR6319]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6321:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6318]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6322:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6319]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6323:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6321]], i32 [[FX_CMPXCHG_DESIRED6322]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6324:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6323]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6324]], ptr [[FX_ATOMIC_EXPECTED_PTR6320]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6325:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6323]], 1
+// CHECK-NEXT: [[TMP3161:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS6325]] to i32
+// CHECK-NEXT: store i32 [[TMP3161]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3162:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3163:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3162]], ptr [[FX_ATOMIC_EXPECTED_PTR6326]], align 4
+// CHECK-NEXT: store float [[TMP3163]], ptr [[FX_ATOMIC_DESIRED_PTR6327]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6329:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6326]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6330:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6327]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6331:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6329]], i32 [[FX_CMPXCHG_DESIRED6330]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6332:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6331]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6332]], ptr [[FX_ATOMIC_EXPECTED_PTR6328]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6333:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6331]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6334:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6328]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS6333]], label [[FX_ATOMIC_EXIT6335:%.*]], label [[FX_ATOMIC_CONT6336:%.*]]
+// CHECK: fx.atomic.cont6336:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6334]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT6335]]
+// CHECK: fx.atomic.exit6335:
+// CHECK-NEXT: [[TMP3164:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS6333]] to i32
+// CHECK-NEXT: store i32 [[TMP3164]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3165:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP3166:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP3165]], ptr [[FX_ATOMIC_EXPECTED_PTR6337]], align 4
+// CHECK-NEXT: store float [[TMP3166]], ptr [[FX_ATOMIC_DESIRED_PTR6338]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED6340:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR6337]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6341:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR6338]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR6342:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED6340]], i32 [[FX_CMPXCHG_DESIRED6341]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV6343:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6342]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV6343]], ptr [[FX_ATOMIC_EXPECTED_PTR6339]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS6344:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR6342]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL6345:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR6339]], align 4
+// CHECK-NEXT: br i1 [[FX_CMPXCHG_SUCCESS6344]], label [[FX_ATOMIC_EXIT6346:%.*]], label [[FX_ATOMIC_CONT6347:%.*]]
+// CHECK: fx.atomic.cont6347:
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL6345]], ptr [[FV]], align 4
+// CHECK-NEXT: br label [[FX_ATOMIC_EXIT6346]]
+// CHECK: fx.atomic.exit6346:
+// CHECK-NEXT: [[TMP3167:%.*]] = sext i1 [[FX_CMPXCHG_SUCCESS6344]] to i32
+// CHECK-NEXT: store i32 [[TMP3167]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3168:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3169:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3168]] monotonic, align 8
+// CHECK-NEXT: store double [[TMP3169]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3170:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3171:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3170]] monotonic, align 8
+// CHECK-NEXT: store double [[TMP3171]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3172:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3173:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3172]] monotonic, align 8
+// CHECK-NEXT: store double [[TMP3173]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3174:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3175:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3174]] monotonic, align 8
+// CHECK-NEXT: store double [[TMP3175]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3176:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3177:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3176]], ptr [[DX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: store double [[TMP3177]], ptr [[DX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED]], i64 [[DX_CMPXCHG_DESIRED]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV]], ptr [[DX_ATOMIC_EXPECTED_PTR6348]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6348]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3178:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3179:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3178]], ptr [[DX_ATOMIC_EXPECTED_PTR6349]], align 8
+// CHECK-NEXT: store double [[TMP3179]], ptr [[DX_ATOMIC_DESIRED_PTR6350]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6352:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6349]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6353:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6350]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6354:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6352]], i64 [[DX_CMPXCHG_DESIRED6353]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6355:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6354]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6355]], ptr [[DX_ATOMIC_EXPECTED_PTR6351]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6356:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6354]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6357:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6351]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6357]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3180:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3181:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3180]] monotonic, align 8
+// CHECK-NEXT: [[TMP3182:%.*]] = fcmp ogt double [[TMP3181]], [[TMP3180]]
+// CHECK-NEXT: [[TMP3183:%.*]] = select i1 [[TMP3182]], double [[TMP3180]], double [[TMP3181]]
+// CHECK-NEXT: store double [[TMP3183]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3184:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3185:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3184]] monotonic, align 8
+// CHECK-NEXT: [[TMP3186:%.*]] = fcmp olt double [[TMP3185]], [[TMP3184]]
+// CHECK-NEXT: [[TMP3187:%.*]] = select i1 [[TMP3186]], double [[TMP3184]], double [[TMP3185]]
+// CHECK-NEXT: store double [[TMP3187]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3188:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3189:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3188]] monotonic, align 8
+// CHECK-NEXT: [[TMP3190:%.*]] = fcmp olt double [[TMP3189]], [[TMP3188]]
+// CHECK-NEXT: [[TMP3191:%.*]] = select i1 [[TMP3190]], double [[TMP3188]], double [[TMP3189]]
+// CHECK-NEXT: store double [[TMP3191]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3192:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3193:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3192]] monotonic, align 8
+// CHECK-NEXT: [[TMP3194:%.*]] = fcmp ogt double [[TMP3193]], [[TMP3192]]
+// CHECK-NEXT: [[TMP3195:%.*]] = select i1 [[TMP3194]], double [[TMP3192]], double [[TMP3193]]
+// CHECK-NEXT: store double [[TMP3195]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3196:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3197:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3196]], ptr [[DX_ATOMIC_EXPECTED_PTR6358]], align 8
+// CHECK-NEXT: store double [[TMP3197]], ptr [[DX_ATOMIC_DESIRED_PTR6359]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6361:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6358]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6362:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6359]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6363:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6361]], i64 [[DX_CMPXCHG_DESIRED6362]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6364:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6363]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6364]], ptr [[DX_ATOMIC_EXPECTED_PTR6360]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6365:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6363]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6366:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6360]], align 8
+// CHECK-NEXT: [[DX_CAPTURE_CAPTURED:%.*]] = select i1 [[DX_CMPXCHG_SUCCESS6365]], double [[TMP3196]], double [[DX_CAPTURE_ACTUAL6366]]
+// CHECK-NEXT: store double [[DX_CAPTURE_CAPTURED]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3198:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3199:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3198]], ptr [[DX_ATOMIC_EXPECTED_PTR6367]], align 8
+// CHECK-NEXT: store double [[TMP3199]], ptr [[DX_ATOMIC_DESIRED_PTR6368]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6370:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6367]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6371:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6368]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6372:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6370]], i64 [[DX_CMPXCHG_DESIRED6371]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6373:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6372]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6373]], ptr [[DX_ATOMIC_EXPECTED_PTR6369]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6374:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6372]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6375:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6369]], align 8
+// CHECK-NEXT: [[DX_CAPTURE_CAPTURED6376:%.*]] = select i1 [[DX_CMPXCHG_SUCCESS6374]], double [[TMP3198]], double [[DX_CAPTURE_ACTUAL6375]]
+// CHECK-NEXT: store double [[DX_CAPTURE_CAPTURED6376]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3200:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3201:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3200]], ptr [[DX_ATOMIC_EXPECTED_PTR6377]], align 8
+// CHECK-NEXT: store double [[TMP3201]], ptr [[DX_ATOMIC_DESIRED_PTR6378]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6380:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6377]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6381:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6378]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6382:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6380]], i64 [[DX_CMPXCHG_DESIRED6381]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6383:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6382]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6383]], ptr [[DX_ATOMIC_EXPECTED_PTR6379]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6384:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6382]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6385:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6379]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6384]], label [[DX_ATOMIC_EXIT:%.*]], label [[DX_ATOMIC_CONT:%.*]]
// CHECK: dx.atomic.cont:
-// CHECK-NEXT: store double [[TMP5378]], ptr [[DV]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6385]], ptr [[DV]], align 8
// CHECK-NEXT: br label [[DX_ATOMIC_EXIT]]
// CHECK: dx.atomic.exit:
-// CHECK-NEXT: [[TMP5380:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5381:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5382:%.*]] = bitcast double [[TMP5380]] to i64
-// CHECK-NEXT: [[TMP5383:%.*]] = bitcast double [[TMP5381]] to i64
-// CHECK-NEXT: [[TMP5384:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5382]], i64 [[TMP5383]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5385:%.*]] = extractvalue { i64, i1 } [[TMP5384]], 0
-// CHECK-NEXT: [[TMP5386:%.*]] = bitcast i64 [[TMP5385]] to double
-// CHECK-NEXT: [[TMP5387:%.*]] = extractvalue { i64, i1 } [[TMP5384]], 1
-// CHECK-NEXT: br i1 [[TMP5387]], label [[DX_ATOMIC_EXIT507:%.*]], label [[DX_ATOMIC_CONT508:%.*]]
-// CHECK: dx.atomic.cont508:
-// CHECK-NEXT: store double [[TMP5386]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT507]]
-// CHECK: dx.atomic.exit507:
-// CHECK-NEXT: [[TMP5388:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5389:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5390:%.*]] = bitcast double [[TMP5388]] to i64
-// CHECK-NEXT: [[TMP5391:%.*]] = bitcast double [[TMP5389]] to i64
-// CHECK-NEXT: [[TMP5392:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5390]], i64 [[TMP5391]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5393:%.*]] = extractvalue { i64, i1 } [[TMP5392]], 1
-// CHECK-NEXT: [[TMP5394:%.*]] = sext i1 [[TMP5393]] to i32
-// CHECK-NEXT: store i32 [[TMP5394]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP5395:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5396:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5397:%.*]] = bitcast double [[TMP5395]] to i64
-// CHECK-NEXT: [[TMP5398:%.*]] = bitcast double [[TMP5396]] to i64
-// CHECK-NEXT: [[TMP5399:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5397]], i64 [[TMP5398]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5400:%.*]] = extractvalue { i64, i1 } [[TMP5399]], 1
-// CHECK-NEXT: [[TMP5401:%.*]] = sext i1 [[TMP5400]] to i32
-// CHECK-NEXT: store i32 [[TMP5401]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP5402:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5403:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5404:%.*]] = bitcast double [[TMP5402]] to i64
-// CHECK-NEXT: [[TMP5405:%.*]] = bitcast double [[TMP5403]] to i64
-// CHECK-NEXT: [[TMP5406:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5404]], i64 [[TMP5405]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5407:%.*]] = extractvalue { i64, i1 } [[TMP5406]], 0
-// CHECK-NEXT: [[TMP5408:%.*]] = bitcast i64 [[TMP5407]] to double
-// CHECK-NEXT: [[TMP5409:%.*]] = extractvalue { i64, i1 } [[TMP5406]], 1
-// CHECK-NEXT: br i1 [[TMP5409]], label [[DX_ATOMIC_EXIT509:%.*]], label [[DX_ATOMIC_CONT510:%.*]]
-// CHECK: dx.atomic.cont510:
-// CHECK-NEXT: store double [[TMP5408]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT509]]
-// CHECK: dx.atomic.exit509:
-// CHECK-NEXT: [[TMP5410:%.*]] = extractvalue { i64, i1 } [[TMP5406]], 1
-// CHECK-NEXT: [[TMP5411:%.*]] = sext i1 [[TMP5410]] to i32
-// CHECK-NEXT: store i32 [[TMP5411]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP5412:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5413:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5414:%.*]] = bitcast double [[TMP5412]] to i64
-// CHECK-NEXT: [[TMP5415:%.*]] = bitcast double [[TMP5413]] to i64
-// CHECK-NEXT: [[TMP5416:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5414]], i64 [[TMP5415]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5417:%.*]] = extractvalue { i64, i1 } [[TMP5416]], 0
-// CHECK-NEXT: [[TMP5418:%.*]] = bitcast i64 [[TMP5417]] to double
-// CHECK-NEXT: [[TMP5419:%.*]] = extractvalue { i64, i1 } [[TMP5416]], 1
-// CHECK-NEXT: br i1 [[TMP5419]], label [[DX_ATOMIC_EXIT511:%.*]], label [[DX_ATOMIC_CONT512:%.*]]
-// CHECK: dx.atomic.cont512:
-// CHECK-NEXT: store double [[TMP5418]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT511]]
-// CHECK: dx.atomic.exit511:
-// CHECK-NEXT: [[TMP5420:%.*]] = extractvalue { i64, i1 } [[TMP5416]], 1
-// CHECK-NEXT: [[TMP5421:%.*]] = sext i1 [[TMP5420]] to i32
-// CHECK-NEXT: store i32 [[TMP5421]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP5422:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5423:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5422]] acq_rel, align 8
-// CHECK-NEXT: store double [[TMP5423]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5424:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5425:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5424]] acq_rel, align 8
-// CHECK-NEXT: store double [[TMP5425]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5426:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5427:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5426]] acq_rel, align 8
-// CHECK-NEXT: store double [[TMP5427]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5428:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5429:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5428]] acq_rel, align 8
-// CHECK-NEXT: store double [[TMP5429]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5430:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5431:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5432:%.*]] = bitcast double [[TMP5430]] to i64
-// CHECK-NEXT: [[TMP5433:%.*]] = bitcast double [[TMP5431]] to i64
-// CHECK-NEXT: [[TMP5434:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5432]], i64 [[TMP5433]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP5435:%.*]] = extractvalue { i64, i1 } [[TMP5434]], 0
-// CHECK-NEXT: [[TMP5436:%.*]] = bitcast i64 [[TMP5435]] to double
-// CHECK-NEXT: store double [[TMP5436]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5437:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5438:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5439:%.*]] = bitcast double [[TMP5437]] to i64
-// CHECK-NEXT: [[TMP5440:%.*]] = bitcast double [[TMP5438]] to i64
-// CHECK-NEXT: [[TMP5441:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5439]], i64 [[TMP5440]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP5442:%.*]] = extractvalue { i64, i1 } [[TMP5441]], 0
-// CHECK-NEXT: [[TMP5443:%.*]] = bitcast i64 [[TMP5442]] to double
-// CHECK-NEXT: store double [[TMP5443]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5444:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5445:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5444]] acq_rel, align 8
-// CHECK-NEXT: [[TMP5446:%.*]] = fcmp ogt double [[TMP5445]], [[TMP5444]]
-// CHECK-NEXT: [[TMP5447:%.*]] = select i1 [[TMP5446]], double [[TMP5444]], double [[TMP5445]]
-// CHECK-NEXT: store double [[TMP5447]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5448:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5449:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5448]] acq_rel, align 8
-// CHECK-NEXT: [[TMP5450:%.*]] = fcmp olt double [[TMP5449]], [[TMP5448]]
-// CHECK-NEXT: [[TMP5451:%.*]] = select i1 [[TMP5450]], double [[TMP5448]], double [[TMP5449]]
-// CHECK-NEXT: store double [[TMP5451]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5452:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5453:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5452]] acq_rel, align 8
-// CHECK-NEXT: [[TMP5454:%.*]] = fcmp olt double [[TMP5453]], [[TMP5452]]
-// CHECK-NEXT: [[TMP5455:%.*]] = select i1 [[TMP5454]], double [[TMP5452]], double [[TMP5453]]
-// CHECK-NEXT: store double [[TMP5455]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5456:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5457:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5456]] acq_rel, align 8
-// CHECK-NEXT: [[TMP5458:%.*]] = fcmp ogt double [[TMP5457]], [[TMP5456]]
-// CHECK-NEXT: [[TMP5459:%.*]] = select i1 [[TMP5458]], double [[TMP5456]], double [[TMP5457]]
-// CHECK-NEXT: store double [[TMP5459]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5460:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5461:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5462:%.*]] = bitcast double [[TMP5460]] to i64
-// CHECK-NEXT: [[TMP5463:%.*]] = bitcast double [[TMP5461]] to i64
-// CHECK-NEXT: [[TMP5464:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5462]], i64 [[TMP5463]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP5465:%.*]] = extractvalue { i64, i1 } [[TMP5464]], 0
-// CHECK-NEXT: [[TMP5466:%.*]] = bitcast i64 [[TMP5465]] to double
-// CHECK-NEXT: [[TMP5467:%.*]] = extractvalue { i64, i1 } [[TMP5464]], 1
-// CHECK-NEXT: [[TMP5468:%.*]] = select i1 [[TMP5467]], double [[TMP5460]], double [[TMP5466]]
-// CHECK-NEXT: store double [[TMP5468]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5469:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5470:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5471:%.*]] = bitcast double [[TMP5469]] to i64
-// CHECK-NEXT: [[TMP5472:%.*]] = bitcast double [[TMP5470]] to i64
-// CHECK-NEXT: [[TMP5473:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5471]], i64 [[TMP5472]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP5474:%.*]] = extractvalue { i64, i1 } [[TMP5473]], 0
-// CHECK-NEXT: [[TMP5475:%.*]] = bitcast i64 [[TMP5474]] to double
-// CHECK-NEXT: [[TMP5476:%.*]] = extractvalue { i64, i1 } [[TMP5473]], 1
-// CHECK-NEXT: [[TMP5477:%.*]] = select i1 [[TMP5476]], double [[TMP5469]], double [[TMP5475]]
-// CHECK-NEXT: store double [[TMP5477]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5478:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5479:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5480:%.*]] = bitcast double [[TMP5478]] to i64
-// CHECK-NEXT: [[TMP5481:%.*]] = bitcast double [[TMP5479]] to i64
-// CHECK-NEXT: [[TMP5482:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5480]], i64 [[TMP5481]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP5483:%.*]] = extractvalue { i64, i1 } [[TMP5482]], 0
-// CHECK-NEXT: [[TMP5484:%.*]] = bitcast i64 [[TMP5483]] to double
-// CHECK-NEXT: [[TMP5485:%.*]] = extractvalue { i64, i1 } [[TMP5482]], 1
-// CHECK-NEXT: br i1 [[TMP5485]], label [[DX_ATOMIC_EXIT513:%.*]], label [[DX_ATOMIC_CONT514:%.*]]
-// CHECK: dx.atomic.cont514:
-// CHECK-NEXT: store double [[TMP5484]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT513]]
-// CHECK: dx.atomic.exit513:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5486:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5487:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5488:%.*]] = bitcast double [[TMP5486]] to i64
-// CHECK-NEXT: [[TMP5489:%.*]] = bitcast double [[TMP5487]] to i64
-// CHECK-NEXT: [[TMP5490:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5488]], i64 [[TMP5489]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP5491:%.*]] = extractvalue { i64, i1 } [[TMP5490]], 0
-// CHECK-NEXT: [[TMP5492:%.*]] = bitcast i64 [[TMP5491]] to double
-// CHECK-NEXT: [[TMP5493:%.*]] = extractvalue { i64, i1 } [[TMP5490]], 1
-// CHECK-NEXT: br i1 [[TMP5493]], label [[DX_ATOMIC_EXIT515:%.*]], label [[DX_ATOMIC_CONT516:%.*]]
-// CHECK: dx.atomic.cont516:
-// CHECK-NEXT: store double [[TMP5492]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT515]]
-// CHECK: dx.atomic.exit515:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5494:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5495:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5496:%.*]] = bitcast double [[TMP5494]] to i64
-// CHECK-NEXT: [[TMP5497:%.*]] = bitcast double [[TMP5495]] to i64
-// CHECK-NEXT: [[TMP5498:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5496]], i64 [[TMP5497]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP5499:%.*]] = extractvalue { i64, i1 } [[TMP5498]], 1
-// CHECK-NEXT: [[TMP5500:%.*]] = sext i1 [[TMP5499]] to i32
-// CHECK-NEXT: store i32 [[TMP5500]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5501:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5502:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5503:%.*]] = bitcast double [[TMP5501]] to i64
-// CHECK-NEXT: [[TMP5504:%.*]] = bitcast double [[TMP5502]] to i64
-// CHECK-NEXT: [[TMP5505:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5503]], i64 [[TMP5504]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP5506:%.*]] = extractvalue { i64, i1 } [[TMP5505]], 1
-// CHECK-NEXT: [[TMP5507:%.*]] = sext i1 [[TMP5506]] to i32
-// CHECK-NEXT: store i32 [[TMP5507]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5508:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5509:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5510:%.*]] = bitcast double [[TMP5508]] to i64
-// CHECK-NEXT: [[TMP5511:%.*]] = bitcast double [[TMP5509]] to i64
-// CHECK-NEXT: [[TMP5512:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5510]], i64 [[TMP5511]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP5513:%.*]] = extractvalue { i64, i1 } [[TMP5512]], 0
-// CHECK-NEXT: [[TMP5514:%.*]] = bitcast i64 [[TMP5513]] to double
-// CHECK-NEXT: [[TMP5515:%.*]] = extractvalue { i64, i1 } [[TMP5512]], 1
-// CHECK-NEXT: br i1 [[TMP5515]], label [[DX_ATOMIC_EXIT517:%.*]], label [[DX_ATOMIC_CONT518:%.*]]
-// CHECK: dx.atomic.cont518:
-// CHECK-NEXT: store double [[TMP5514]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT517]]
-// CHECK: dx.atomic.exit517:
-// CHECK-NEXT: [[TMP5516:%.*]] = extractvalue { i64, i1 } [[TMP5512]], 1
-// CHECK-NEXT: [[TMP5517:%.*]] = sext i1 [[TMP5516]] to i32
-// CHECK-NEXT: store i32 [[TMP5517]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5518:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5519:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5520:%.*]] = bitcast double [[TMP5518]] to i64
-// CHECK-NEXT: [[TMP5521:%.*]] = bitcast double [[TMP5519]] to i64
-// CHECK-NEXT: [[TMP5522:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5520]], i64 [[TMP5521]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP5523:%.*]] = extractvalue { i64, i1 } [[TMP5522]], 0
-// CHECK-NEXT: [[TMP5524:%.*]] = bitcast i64 [[TMP5523]] to double
-// CHECK-NEXT: [[TMP5525:%.*]] = extractvalue { i64, i1 } [[TMP5522]], 1
-// CHECK-NEXT: br i1 [[TMP5525]], label [[DX_ATOMIC_EXIT519:%.*]], label [[DX_ATOMIC_CONT520:%.*]]
-// CHECK: dx.atomic.cont520:
-// CHECK-NEXT: store double [[TMP5524]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT519]]
-// CHECK: dx.atomic.exit519:
-// CHECK-NEXT: [[TMP5526:%.*]] = extractvalue { i64, i1 } [[TMP5522]], 1
-// CHECK-NEXT: [[TMP5527:%.*]] = sext i1 [[TMP5526]] to i32
-// CHECK-NEXT: store i32 [[TMP5527]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5528:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5529:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5528]] acquire, align 8
-// CHECK-NEXT: store double [[TMP5529]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5530:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5531:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5530]] acquire, align 8
-// CHECK-NEXT: store double [[TMP5531]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5532:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5533:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5532]] acquire, align 8
-// CHECK-NEXT: store double [[TMP5533]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5534:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5535:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5534]] acquire, align 8
-// CHECK-NEXT: store double [[TMP5535]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5536:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5537:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5538:%.*]] = bitcast double [[TMP5536]] to i64
-// CHECK-NEXT: [[TMP5539:%.*]] = bitcast double [[TMP5537]] to i64
-// CHECK-NEXT: [[TMP5540:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5538]], i64 [[TMP5539]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP5541:%.*]] = extractvalue { i64, i1 } [[TMP5540]], 0
-// CHECK-NEXT: [[TMP5542:%.*]] = bitcast i64 [[TMP5541]] to double
-// CHECK-NEXT: store double [[TMP5542]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5543:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5544:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5545:%.*]] = bitcast double [[TMP5543]] to i64
-// CHECK-NEXT: [[TMP5546:%.*]] = bitcast double [[TMP5544]] to i64
-// CHECK-NEXT: [[TMP5547:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5545]], i64 [[TMP5546]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP5548:%.*]] = extractvalue { i64, i1 } [[TMP5547]], 0
-// CHECK-NEXT: [[TMP5549:%.*]] = bitcast i64 [[TMP5548]] to double
-// CHECK-NEXT: store double [[TMP5549]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5550:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5551:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5550]] acquire, align 8
-// CHECK-NEXT: [[TMP5552:%.*]] = fcmp ogt double [[TMP5551]], [[TMP5550]]
-// CHECK-NEXT: [[TMP5553:%.*]] = select i1 [[TMP5552]], double [[TMP5550]], double [[TMP5551]]
-// CHECK-NEXT: store double [[TMP5553]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5554:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5555:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5554]] acquire, align 8
-// CHECK-NEXT: [[TMP5556:%.*]] = fcmp olt double [[TMP5555]], [[TMP5554]]
-// CHECK-NEXT: [[TMP5557:%.*]] = select i1 [[TMP5556]], double [[TMP5554]], double [[TMP5555]]
-// CHECK-NEXT: store double [[TMP5557]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5558:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5559:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5558]] acquire, align 8
-// CHECK-NEXT: [[TMP5560:%.*]] = fcmp olt double [[TMP5559]], [[TMP5558]]
-// CHECK-NEXT: [[TMP5561:%.*]] = select i1 [[TMP5560]], double [[TMP5558]], double [[TMP5559]]
-// CHECK-NEXT: store double [[TMP5561]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5562:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5563:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5562]] acquire, align 8
-// CHECK-NEXT: [[TMP5564:%.*]] = fcmp ogt double [[TMP5563]], [[TMP5562]]
-// CHECK-NEXT: [[TMP5565:%.*]] = select i1 [[TMP5564]], double [[TMP5562]], double [[TMP5563]]
-// CHECK-NEXT: store double [[TMP5565]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5566:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5567:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5568:%.*]] = bitcast double [[TMP5566]] to i64
-// CHECK-NEXT: [[TMP5569:%.*]] = bitcast double [[TMP5567]] to i64
-// CHECK-NEXT: [[TMP5570:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5568]], i64 [[TMP5569]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP5571:%.*]] = extractvalue { i64, i1 } [[TMP5570]], 0
-// CHECK-NEXT: [[TMP5572:%.*]] = bitcast i64 [[TMP5571]] to double
-// CHECK-NEXT: [[TMP5573:%.*]] = extractvalue { i64, i1 } [[TMP5570]], 1
-// CHECK-NEXT: [[TMP5574:%.*]] = select i1 [[TMP5573]], double [[TMP5566]], double [[TMP5572]]
-// CHECK-NEXT: store double [[TMP5574]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5575:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5576:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5577:%.*]] = bitcast double [[TMP5575]] to i64
-// CHECK-NEXT: [[TMP5578:%.*]] = bitcast double [[TMP5576]] to i64
-// CHECK-NEXT: [[TMP5579:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5577]], i64 [[TMP5578]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP5580:%.*]] = extractvalue { i64, i1 } [[TMP5579]], 0
-// CHECK-NEXT: [[TMP5581:%.*]] = bitcast i64 [[TMP5580]] to double
-// CHECK-NEXT: [[TMP5582:%.*]] = extractvalue { i64, i1 } [[TMP5579]], 1
-// CHECK-NEXT: [[TMP5583:%.*]] = select i1 [[TMP5582]], double [[TMP5575]], double [[TMP5581]]
-// CHECK-NEXT: store double [[TMP5583]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5584:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5585:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5586:%.*]] = bitcast double [[TMP5584]] to i64
-// CHECK-NEXT: [[TMP5587:%.*]] = bitcast double [[TMP5585]] to i64
-// CHECK-NEXT: [[TMP5588:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5586]], i64 [[TMP5587]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP5589:%.*]] = extractvalue { i64, i1 } [[TMP5588]], 0
-// CHECK-NEXT: [[TMP5590:%.*]] = bitcast i64 [[TMP5589]] to double
-// CHECK-NEXT: [[TMP5591:%.*]] = extractvalue { i64, i1 } [[TMP5588]], 1
-// CHECK-NEXT: br i1 [[TMP5591]], label [[DX_ATOMIC_EXIT521:%.*]], label [[DX_ATOMIC_CONT522:%.*]]
-// CHECK: dx.atomic.cont522:
-// CHECK-NEXT: store double [[TMP5590]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT521]]
-// CHECK: dx.atomic.exit521:
-// CHECK-NEXT: [[TMP5592:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5593:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5594:%.*]] = bitcast double [[TMP5592]] to i64
-// CHECK-NEXT: [[TMP5595:%.*]] = bitcast double [[TMP5593]] to i64
-// CHECK-NEXT: [[TMP5596:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5594]], i64 [[TMP5595]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP5597:%.*]] = extractvalue { i64, i1 } [[TMP5596]], 0
-// CHECK-NEXT: [[TMP5598:%.*]] = bitcast i64 [[TMP5597]] to double
-// CHECK-NEXT: [[TMP5599:%.*]] = extractvalue { i64, i1 } [[TMP5596]], 1
-// CHECK-NEXT: br i1 [[TMP5599]], label [[DX_ATOMIC_EXIT523:%.*]], label [[DX_ATOMIC_CONT524:%.*]]
-// CHECK: dx.atomic.cont524:
-// CHECK-NEXT: store double [[TMP5598]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT523]]
-// CHECK: dx.atomic.exit523:
-// CHECK-NEXT: [[TMP5600:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5601:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5602:%.*]] = bitcast double [[TMP5600]] to i64
-// CHECK-NEXT: [[TMP5603:%.*]] = bitcast double [[TMP5601]] to i64
-// CHECK-NEXT: [[TMP5604:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5602]], i64 [[TMP5603]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP5605:%.*]] = extractvalue { i64, i1 } [[TMP5604]], 1
-// CHECK-NEXT: [[TMP5606:%.*]] = sext i1 [[TMP5605]] to i32
-// CHECK-NEXT: store i32 [[TMP5606]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP5607:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5608:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5609:%.*]] = bitcast double [[TMP5607]] to i64
-// CHECK-NEXT: [[TMP5610:%.*]] = bitcast double [[TMP5608]] to i64
-// CHECK-NEXT: [[TMP5611:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5609]], i64 [[TMP5610]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP5612:%.*]] = extractvalue { i64, i1 } [[TMP5611]], 1
-// CHECK-NEXT: [[TMP5613:%.*]] = sext i1 [[TMP5612]] to i32
-// CHECK-NEXT: store i32 [[TMP5613]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP5614:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5615:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5616:%.*]] = bitcast double [[TMP5614]] to i64
-// CHECK-NEXT: [[TMP5617:%.*]] = bitcast double [[TMP5615]] to i64
-// CHECK-NEXT: [[TMP5618:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5616]], i64 [[TMP5617]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP5619:%.*]] = extractvalue { i64, i1 } [[TMP5618]], 0
-// CHECK-NEXT: [[TMP5620:%.*]] = bitcast i64 [[TMP5619]] to double
-// CHECK-NEXT: [[TMP5621:%.*]] = extractvalue { i64, i1 } [[TMP5618]], 1
-// CHECK-NEXT: br i1 [[TMP5621]], label [[DX_ATOMIC_EXIT525:%.*]], label [[DX_ATOMIC_CONT526:%.*]]
-// CHECK: dx.atomic.cont526:
-// CHECK-NEXT: store double [[TMP5620]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT525]]
-// CHECK: dx.atomic.exit525:
-// CHECK-NEXT: [[TMP5622:%.*]] = extractvalue { i64, i1 } [[TMP5618]], 1
-// CHECK-NEXT: [[TMP5623:%.*]] = sext i1 [[TMP5622]] to i32
-// CHECK-NEXT: store i32 [[TMP5623]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP5624:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5625:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5626:%.*]] = bitcast double [[TMP5624]] to i64
-// CHECK-NEXT: [[TMP5627:%.*]] = bitcast double [[TMP5625]] to i64
-// CHECK-NEXT: [[TMP5628:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5626]], i64 [[TMP5627]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP5629:%.*]] = extractvalue { i64, i1 } [[TMP5628]], 0
-// CHECK-NEXT: [[TMP5630:%.*]] = bitcast i64 [[TMP5629]] to double
-// CHECK-NEXT: [[TMP5631:%.*]] = extractvalue { i64, i1 } [[TMP5628]], 1
-// CHECK-NEXT: br i1 [[TMP5631]], label [[DX_ATOMIC_EXIT527:%.*]], label [[DX_ATOMIC_CONT528:%.*]]
-// CHECK: dx.atomic.cont528:
-// CHECK-NEXT: store double [[TMP5630]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT527]]
-// CHECK: dx.atomic.exit527:
-// CHECK-NEXT: [[TMP5632:%.*]] = extractvalue { i64, i1 } [[TMP5628]], 1
-// CHECK-NEXT: [[TMP5633:%.*]] = sext i1 [[TMP5632]] to i32
-// CHECK-NEXT: store i32 [[TMP5633]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP5634:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5635:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5634]] monotonic, align 8
-// CHECK-NEXT: store double [[TMP5635]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5636:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5637:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5636]] monotonic, align 8
-// CHECK-NEXT: store double [[TMP5637]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5638:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5639:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5638]] monotonic, align 8
-// CHECK-NEXT: store double [[TMP5639]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5640:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5641:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5640]] monotonic, align 8
-// CHECK-NEXT: store double [[TMP5641]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5642:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5643:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5644:%.*]] = bitcast double [[TMP5642]] to i64
-// CHECK-NEXT: [[TMP5645:%.*]] = bitcast double [[TMP5643]] to i64
-// CHECK-NEXT: [[TMP5646:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5644]], i64 [[TMP5645]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5647:%.*]] = extractvalue { i64, i1 } [[TMP5646]], 0
-// CHECK-NEXT: [[TMP5648:%.*]] = bitcast i64 [[TMP5647]] to double
-// CHECK-NEXT: store double [[TMP5648]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5649:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5650:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5651:%.*]] = bitcast double [[TMP5649]] to i64
-// CHECK-NEXT: [[TMP5652:%.*]] = bitcast double [[TMP5650]] to i64
-// CHECK-NEXT: [[TMP5653:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5651]], i64 [[TMP5652]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5654:%.*]] = extractvalue { i64, i1 } [[TMP5653]], 0
-// CHECK-NEXT: [[TMP5655:%.*]] = bitcast i64 [[TMP5654]] to double
-// CHECK-NEXT: store double [[TMP5655]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5656:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5657:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5656]] monotonic, align 8
-// CHECK-NEXT: [[TMP5658:%.*]] = fcmp ogt double [[TMP5657]], [[TMP5656]]
-// CHECK-NEXT: [[TMP5659:%.*]] = select i1 [[TMP5658]], double [[TMP5656]], double [[TMP5657]]
-// CHECK-NEXT: store double [[TMP5659]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5660:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5661:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5660]] monotonic, align 8
-// CHECK-NEXT: [[TMP5662:%.*]] = fcmp olt double [[TMP5661]], [[TMP5660]]
-// CHECK-NEXT: [[TMP5663:%.*]] = select i1 [[TMP5662]], double [[TMP5660]], double [[TMP5661]]
-// CHECK-NEXT: store double [[TMP5663]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5664:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5665:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5664]] monotonic, align 8
-// CHECK-NEXT: [[TMP5666:%.*]] = fcmp olt double [[TMP5665]], [[TMP5664]]
-// CHECK-NEXT: [[TMP5667:%.*]] = select i1 [[TMP5666]], double [[TMP5664]], double [[TMP5665]]
-// CHECK-NEXT: store double [[TMP5667]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5668:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5669:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5668]] monotonic, align 8
-// CHECK-NEXT: [[TMP5670:%.*]] = fcmp ogt double [[TMP5669]], [[TMP5668]]
-// CHECK-NEXT: [[TMP5671:%.*]] = select i1 [[TMP5670]], double [[TMP5668]], double [[TMP5669]]
-// CHECK-NEXT: store double [[TMP5671]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5672:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5673:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5674:%.*]] = bitcast double [[TMP5672]] to i64
-// CHECK-NEXT: [[TMP5675:%.*]] = bitcast double [[TMP5673]] to i64
-// CHECK-NEXT: [[TMP5676:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5674]], i64 [[TMP5675]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5677:%.*]] = extractvalue { i64, i1 } [[TMP5676]], 0
-// CHECK-NEXT: [[TMP5678:%.*]] = bitcast i64 [[TMP5677]] to double
-// CHECK-NEXT: [[TMP5679:%.*]] = extractvalue { i64, i1 } [[TMP5676]], 1
-// CHECK-NEXT: [[TMP5680:%.*]] = select i1 [[TMP5679]], double [[TMP5672]], double [[TMP5678]]
-// CHECK-NEXT: store double [[TMP5680]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5681:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5682:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5683:%.*]] = bitcast double [[TMP5681]] to i64
-// CHECK-NEXT: [[TMP5684:%.*]] = bitcast double [[TMP5682]] to i64
-// CHECK-NEXT: [[TMP5685:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5683]], i64 [[TMP5684]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5686:%.*]] = extractvalue { i64, i1 } [[TMP5685]], 0
-// CHECK-NEXT: [[TMP5687:%.*]] = bitcast i64 [[TMP5686]] to double
-// CHECK-NEXT: [[TMP5688:%.*]] = extractvalue { i64, i1 } [[TMP5685]], 1
-// CHECK-NEXT: [[TMP5689:%.*]] = select i1 [[TMP5688]], double [[TMP5681]], double [[TMP5687]]
-// CHECK-NEXT: store double [[TMP5689]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP5690:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5691:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5692:%.*]] = bitcast double [[TMP5690]] to i64
-// CHECK-NEXT: [[TMP5693:%.*]] = bitcast double [[TMP5691]] to i64
-// CHECK-NEXT: [[TMP5694:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5692]], i64 [[TMP5693]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5695:%.*]] = extractvalue { i64, i1 } [[TMP5694]], 0
-// CHECK-NEXT: [[TMP5696:%.*]] = bitcast i64 [[TMP5695]] to double
-// CHECK-NEXT: [[TMP5697:%.*]] = extractvalue { i64, i1 } [[TMP5694]], 1
-// CHECK-NEXT: br i1 [[TMP5697]], label [[DX_ATOMIC_EXIT529:%.*]], label [[DX_ATOMIC_CONT530:%.*]]
-// CHECK: dx.atomic.cont530:
-// CHECK-NEXT: store double [[TMP5696]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT529]]
-// CHECK: dx.atomic.exit529:
-// CHECK-NEXT: [[TMP5698:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5699:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5700:%.*]] = bitcast double [[TMP5698]] to i64
-// CHECK-NEXT: [[TMP5701:%.*]] = bitcast double [[TMP5699]] to i64
-// CHECK-NEXT: [[TMP5702:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5700]], i64 [[TMP5701]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5703:%.*]] = extractvalue { i64, i1 } [[TMP5702]], 0
-// CHECK-NEXT: [[TMP5704:%.*]] = bitcast i64 [[TMP5703]] to double
-// CHECK-NEXT: [[TMP5705:%.*]] = extractvalue { i64, i1 } [[TMP5702]], 1
-// CHECK-NEXT: br i1 [[TMP5705]], label [[DX_ATOMIC_EXIT531:%.*]], label [[DX_ATOMIC_CONT532:%.*]]
-// CHECK: dx.atomic.cont532:
-// CHECK-NEXT: store double [[TMP5704]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT531]]
-// CHECK: dx.atomic.exit531:
-// CHECK-NEXT: [[TMP5706:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5707:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5708:%.*]] = bitcast double [[TMP5706]] to i64
-// CHECK-NEXT: [[TMP5709:%.*]] = bitcast double [[TMP5707]] to i64
-// CHECK-NEXT: [[TMP5710:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5708]], i64 [[TMP5709]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5711:%.*]] = extractvalue { i64, i1 } [[TMP5710]], 1
-// CHECK-NEXT: [[TMP5712:%.*]] = sext i1 [[TMP5711]] to i32
-// CHECK-NEXT: store i32 [[TMP5712]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP5713:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5714:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5715:%.*]] = bitcast double [[TMP5713]] to i64
-// CHECK-NEXT: [[TMP5716:%.*]] = bitcast double [[TMP5714]] to i64
-// CHECK-NEXT: [[TMP5717:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5715]], i64 [[TMP5716]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5718:%.*]] = extractvalue { i64, i1 } [[TMP5717]], 1
-// CHECK-NEXT: [[TMP5719:%.*]] = sext i1 [[TMP5718]] to i32
-// CHECK-NEXT: store i32 [[TMP5719]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP5720:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5721:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5722:%.*]] = bitcast double [[TMP5720]] to i64
-// CHECK-NEXT: [[TMP5723:%.*]] = bitcast double [[TMP5721]] to i64
-// CHECK-NEXT: [[TMP5724:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5722]], i64 [[TMP5723]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5725:%.*]] = extractvalue { i64, i1 } [[TMP5724]], 0
-// CHECK-NEXT: [[TMP5726:%.*]] = bitcast i64 [[TMP5725]] to double
-// CHECK-NEXT: [[TMP5727:%.*]] = extractvalue { i64, i1 } [[TMP5724]], 1
-// CHECK-NEXT: br i1 [[TMP5727]], label [[DX_ATOMIC_EXIT533:%.*]], label [[DX_ATOMIC_CONT534:%.*]]
-// CHECK: dx.atomic.cont534:
-// CHECK-NEXT: store double [[TMP5726]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT533]]
-// CHECK: dx.atomic.exit533:
-// CHECK-NEXT: [[TMP5728:%.*]] = extractvalue { i64, i1 } [[TMP5724]], 1
-// CHECK-NEXT: [[TMP5729:%.*]] = sext i1 [[TMP5728]] to i32
-// CHECK-NEXT: store i32 [[TMP5729]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP5730:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5731:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5732:%.*]] = bitcast double [[TMP5730]] to i64
-// CHECK-NEXT: [[TMP5733:%.*]] = bitcast double [[TMP5731]] to i64
-// CHECK-NEXT: [[TMP5734:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5732]], i64 [[TMP5733]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP5735:%.*]] = extractvalue { i64, i1 } [[TMP5734]], 0
-// CHECK-NEXT: [[TMP5736:%.*]] = bitcast i64 [[TMP5735]] to double
-// CHECK-NEXT: [[TMP5737:%.*]] = extractvalue { i64, i1 } [[TMP5734]], 1
-// CHECK-NEXT: br i1 [[TMP5737]], label [[DX_ATOMIC_EXIT535:%.*]], label [[DX_ATOMIC_CONT536:%.*]]
-// CHECK: dx.atomic.cont536:
-// CHECK-NEXT: store double [[TMP5736]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT535]]
-// CHECK: dx.atomic.exit535:
-// CHECK-NEXT: [[TMP5738:%.*]] = extractvalue { i64, i1 } [[TMP5734]], 1
-// CHECK-NEXT: [[TMP5739:%.*]] = sext i1 [[TMP5738]] to i32
-// CHECK-NEXT: store i32 [[TMP5739]], ptr [[IR]], align 4
-// CHECK-NEXT: [[TMP5740:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5741:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5740]] release, align 8
-// CHECK-NEXT: store double [[TMP5741]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5742:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5743:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5742]] release, align 8
-// CHECK-NEXT: store double [[TMP5743]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5744:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5745:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5744]] release, align 8
-// CHECK-NEXT: store double [[TMP5745]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5746:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5747:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5746]] release, align 8
-// CHECK-NEXT: store double [[TMP5747]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5748:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5749:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5750:%.*]] = bitcast double [[TMP5748]] to i64
-// CHECK-NEXT: [[TMP5751:%.*]] = bitcast double [[TMP5749]] to i64
-// CHECK-NEXT: [[TMP5752:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5750]], i64 [[TMP5751]] release monotonic, align 8
-// CHECK-NEXT: [[TMP5753:%.*]] = extractvalue { i64, i1 } [[TMP5752]], 0
-// CHECK-NEXT: [[TMP5754:%.*]] = bitcast i64 [[TMP5753]] to double
-// CHECK-NEXT: store double [[TMP5754]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5755:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5756:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5757:%.*]] = bitcast double [[TMP5755]] to i64
-// CHECK-NEXT: [[TMP5758:%.*]] = bitcast double [[TMP5756]] to i64
-// CHECK-NEXT: [[TMP5759:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5757]], i64 [[TMP5758]] release monotonic, align 8
-// CHECK-NEXT: [[TMP5760:%.*]] = extractvalue { i64, i1 } [[TMP5759]], 0
-// CHECK-NEXT: [[TMP5761:%.*]] = bitcast i64 [[TMP5760]] to double
-// CHECK-NEXT: store double [[TMP5761]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5762:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5763:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5762]] release, align 8
-// CHECK-NEXT: [[TMP5764:%.*]] = fcmp ogt double [[TMP5763]], [[TMP5762]]
-// CHECK-NEXT: [[TMP5765:%.*]] = select i1 [[TMP5764]], double [[TMP5762]], double [[TMP5763]]
-// CHECK-NEXT: store double [[TMP5765]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5766:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5767:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5766]] release, align 8
-// CHECK-NEXT: [[TMP5768:%.*]] = fcmp olt double [[TMP5767]], [[TMP5766]]
-// CHECK-NEXT: [[TMP5769:%.*]] = select i1 [[TMP5768]], double [[TMP5766]], double [[TMP5767]]
-// CHECK-NEXT: store double [[TMP5769]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5770:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5771:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5770]] release, align 8
-// CHECK-NEXT: [[TMP5772:%.*]] = fcmp olt double [[TMP5771]], [[TMP5770]]
-// CHECK-NEXT: [[TMP5773:%.*]] = select i1 [[TMP5772]], double [[TMP5770]], double [[TMP5771]]
-// CHECK-NEXT: store double [[TMP5773]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5774:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5775:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5774]] release, align 8
-// CHECK-NEXT: [[TMP5776:%.*]] = fcmp ogt double [[TMP5775]], [[TMP5774]]
-// CHECK-NEXT: [[TMP5777:%.*]] = select i1 [[TMP5776]], double [[TMP5774]], double [[TMP5775]]
-// CHECK-NEXT: store double [[TMP5777]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5778:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5779:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5780:%.*]] = bitcast double [[TMP5778]] to i64
-// CHECK-NEXT: [[TMP5781:%.*]] = bitcast double [[TMP5779]] to i64
-// CHECK-NEXT: [[TMP5782:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5780]], i64 [[TMP5781]] release monotonic, align 8
-// CHECK-NEXT: [[TMP5783:%.*]] = extractvalue { i64, i1 } [[TMP5782]], 0
-// CHECK-NEXT: [[TMP5784:%.*]] = bitcast i64 [[TMP5783]] to double
-// CHECK-NEXT: [[TMP5785:%.*]] = extractvalue { i64, i1 } [[TMP5782]], 1
-// CHECK-NEXT: [[TMP5786:%.*]] = select i1 [[TMP5785]], double [[TMP5778]], double [[TMP5784]]
-// CHECK-NEXT: store double [[TMP5786]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5787:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5788:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5789:%.*]] = bitcast double [[TMP5787]] to i64
-// CHECK-NEXT: [[TMP5790:%.*]] = bitcast double [[TMP5788]] to i64
-// CHECK-NEXT: [[TMP5791:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5789]], i64 [[TMP5790]] release monotonic, align 8
-// CHECK-NEXT: [[TMP5792:%.*]] = extractvalue { i64, i1 } [[TMP5791]], 0
-// CHECK-NEXT: [[TMP5793:%.*]] = bitcast i64 [[TMP5792]] to double
-// CHECK-NEXT: [[TMP5794:%.*]] = extractvalue { i64, i1 } [[TMP5791]], 1
-// CHECK-NEXT: [[TMP5795:%.*]] = select i1 [[TMP5794]], double [[TMP5787]], double [[TMP5793]]
-// CHECK-NEXT: store double [[TMP5795]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5796:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5797:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5798:%.*]] = bitcast double [[TMP5796]] to i64
-// CHECK-NEXT: [[TMP5799:%.*]] = bitcast double [[TMP5797]] to i64
-// CHECK-NEXT: [[TMP5800:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5798]], i64 [[TMP5799]] release monotonic, align 8
-// CHECK-NEXT: [[TMP5801:%.*]] = extractvalue { i64, i1 } [[TMP5800]], 0
-// CHECK-NEXT: [[TMP5802:%.*]] = bitcast i64 [[TMP5801]] to double
-// CHECK-NEXT: [[TMP5803:%.*]] = extractvalue { i64, i1 } [[TMP5800]], 1
-// CHECK-NEXT: br i1 [[TMP5803]], label [[DX_ATOMIC_EXIT537:%.*]], label [[DX_ATOMIC_CONT538:%.*]]
-// CHECK: dx.atomic.cont538:
-// CHECK-NEXT: store double [[TMP5802]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT537]]
-// CHECK: dx.atomic.exit537:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5804:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5805:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5806:%.*]] = bitcast double [[TMP5804]] to i64
-// CHECK-NEXT: [[TMP5807:%.*]] = bitcast double [[TMP5805]] to i64
-// CHECK-NEXT: [[TMP5808:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5806]], i64 [[TMP5807]] release monotonic, align 8
-// CHECK-NEXT: [[TMP5809:%.*]] = extractvalue { i64, i1 } [[TMP5808]], 0
-// CHECK-NEXT: [[TMP5810:%.*]] = bitcast i64 [[TMP5809]] to double
-// CHECK-NEXT: [[TMP5811:%.*]] = extractvalue { i64, i1 } [[TMP5808]], 1
-// CHECK-NEXT: br i1 [[TMP5811]], label [[DX_ATOMIC_EXIT539:%.*]], label [[DX_ATOMIC_CONT540:%.*]]
-// CHECK: dx.atomic.cont540:
-// CHECK-NEXT: store double [[TMP5810]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT539]]
-// CHECK: dx.atomic.exit539:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5812:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5813:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5814:%.*]] = bitcast double [[TMP5812]] to i64
-// CHECK-NEXT: [[TMP5815:%.*]] = bitcast double [[TMP5813]] to i64
-// CHECK-NEXT: [[TMP5816:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5814]], i64 [[TMP5815]] release monotonic, align 8
-// CHECK-NEXT: [[TMP5817:%.*]] = extractvalue { i64, i1 } [[TMP5816]], 1
-// CHECK-NEXT: [[TMP5818:%.*]] = sext i1 [[TMP5817]] to i32
-// CHECK-NEXT: store i32 [[TMP5818]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5819:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5820:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5821:%.*]] = bitcast double [[TMP5819]] to i64
-// CHECK-NEXT: [[TMP5822:%.*]] = bitcast double [[TMP5820]] to i64
-// CHECK-NEXT: [[TMP5823:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5821]], i64 [[TMP5822]] release monotonic, align 8
-// CHECK-NEXT: [[TMP5824:%.*]] = extractvalue { i64, i1 } [[TMP5823]], 1
-// CHECK-NEXT: [[TMP5825:%.*]] = sext i1 [[TMP5824]] to i32
-// CHECK-NEXT: store i32 [[TMP5825]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5826:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5827:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5828:%.*]] = bitcast double [[TMP5826]] to i64
-// CHECK-NEXT: [[TMP5829:%.*]] = bitcast double [[TMP5827]] to i64
-// CHECK-NEXT: [[TMP5830:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5828]], i64 [[TMP5829]] release monotonic, align 8
-// CHECK-NEXT: [[TMP5831:%.*]] = extractvalue { i64, i1 } [[TMP5830]], 0
-// CHECK-NEXT: [[TMP5832:%.*]] = bitcast i64 [[TMP5831]] to double
-// CHECK-NEXT: [[TMP5833:%.*]] = extractvalue { i64, i1 } [[TMP5830]], 1
-// CHECK-NEXT: br i1 [[TMP5833]], label [[DX_ATOMIC_EXIT541:%.*]], label [[DX_ATOMIC_CONT542:%.*]]
-// CHECK: dx.atomic.cont542:
-// CHECK-NEXT: store double [[TMP5832]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT541]]
-// CHECK: dx.atomic.exit541:
-// CHECK-NEXT: [[TMP5834:%.*]] = extractvalue { i64, i1 } [[TMP5830]], 1
-// CHECK-NEXT: [[TMP5835:%.*]] = sext i1 [[TMP5834]] to i32
-// CHECK-NEXT: store i32 [[TMP5835]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5836:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5837:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5838:%.*]] = bitcast double [[TMP5836]] to i64
-// CHECK-NEXT: [[TMP5839:%.*]] = bitcast double [[TMP5837]] to i64
-// CHECK-NEXT: [[TMP5840:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5838]], i64 [[TMP5839]] release monotonic, align 8
-// CHECK-NEXT: [[TMP5841:%.*]] = extractvalue { i64, i1 } [[TMP5840]], 0
-// CHECK-NEXT: [[TMP5842:%.*]] = bitcast i64 [[TMP5841]] to double
-// CHECK-NEXT: [[TMP5843:%.*]] = extractvalue { i64, i1 } [[TMP5840]], 1
-// CHECK-NEXT: br i1 [[TMP5843]], label [[DX_ATOMIC_EXIT543:%.*]], label [[DX_ATOMIC_CONT544:%.*]]
-// CHECK: dx.atomic.cont544:
-// CHECK-NEXT: store double [[TMP5842]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT543]]
-// CHECK: dx.atomic.exit543:
-// CHECK-NEXT: [[TMP5844:%.*]] = extractvalue { i64, i1 } [[TMP5840]], 1
-// CHECK-NEXT: [[TMP5845:%.*]] = sext i1 [[TMP5844]] to i32
-// CHECK-NEXT: store i32 [[TMP5845]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5846:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5847:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5846]] seq_cst, align 8
-// CHECK-NEXT: store double [[TMP5847]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5848:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5849:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5848]] seq_cst, align 8
-// CHECK-NEXT: store double [[TMP5849]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5850:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5851:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5850]] seq_cst, align 8
-// CHECK-NEXT: store double [[TMP5851]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5852:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5853:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5852]] seq_cst, align 8
-// CHECK-NEXT: store double [[TMP5853]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5854:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5855:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5856:%.*]] = bitcast double [[TMP5854]] to i64
-// CHECK-NEXT: [[TMP5857:%.*]] = bitcast double [[TMP5855]] to i64
-// CHECK-NEXT: [[TMP5858:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5856]], i64 [[TMP5857]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP5859:%.*]] = extractvalue { i64, i1 } [[TMP5858]], 0
-// CHECK-NEXT: [[TMP5860:%.*]] = bitcast i64 [[TMP5859]] to double
-// CHECK-NEXT: store double [[TMP5860]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5861:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5862:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5863:%.*]] = bitcast double [[TMP5861]] to i64
-// CHECK-NEXT: [[TMP5864:%.*]] = bitcast double [[TMP5862]] to i64
-// CHECK-NEXT: [[TMP5865:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5863]], i64 [[TMP5864]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP5866:%.*]] = extractvalue { i64, i1 } [[TMP5865]], 0
-// CHECK-NEXT: [[TMP5867:%.*]] = bitcast i64 [[TMP5866]] to double
-// CHECK-NEXT: store double [[TMP5867]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5868:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5869:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5868]] seq_cst, align 8
-// CHECK-NEXT: [[TMP5870:%.*]] = fcmp ogt double [[TMP5869]], [[TMP5868]]
-// CHECK-NEXT: [[TMP5871:%.*]] = select i1 [[TMP5870]], double [[TMP5868]], double [[TMP5869]]
-// CHECK-NEXT: store double [[TMP5871]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5872:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5873:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5872]] seq_cst, align 8
-// CHECK-NEXT: [[TMP5874:%.*]] = fcmp olt double [[TMP5873]], [[TMP5872]]
-// CHECK-NEXT: [[TMP5875:%.*]] = select i1 [[TMP5874]], double [[TMP5872]], double [[TMP5873]]
-// CHECK-NEXT: store double [[TMP5875]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5876:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5877:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP5876]] seq_cst, align 8
-// CHECK-NEXT: [[TMP5878:%.*]] = fcmp olt double [[TMP5877]], [[TMP5876]]
-// CHECK-NEXT: [[TMP5879:%.*]] = select i1 [[TMP5878]], double [[TMP5876]], double [[TMP5877]]
-// CHECK-NEXT: store double [[TMP5879]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5880:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5881:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP5880]] seq_cst, align 8
-// CHECK-NEXT: [[TMP5882:%.*]] = fcmp ogt double [[TMP5881]], [[TMP5880]]
-// CHECK-NEXT: [[TMP5883:%.*]] = select i1 [[TMP5882]], double [[TMP5880]], double [[TMP5881]]
-// CHECK-NEXT: store double [[TMP5883]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5884:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5885:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5886:%.*]] = bitcast double [[TMP5884]] to i64
-// CHECK-NEXT: [[TMP5887:%.*]] = bitcast double [[TMP5885]] to i64
-// CHECK-NEXT: [[TMP5888:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5886]], i64 [[TMP5887]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP5889:%.*]] = extractvalue { i64, i1 } [[TMP5888]], 0
-// CHECK-NEXT: [[TMP5890:%.*]] = bitcast i64 [[TMP5889]] to double
-// CHECK-NEXT: [[TMP5891:%.*]] = extractvalue { i64, i1 } [[TMP5888]], 1
-// CHECK-NEXT: [[TMP5892:%.*]] = select i1 [[TMP5891]], double [[TMP5884]], double [[TMP5890]]
-// CHECK-NEXT: store double [[TMP5892]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5893:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5894:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5895:%.*]] = bitcast double [[TMP5893]] to i64
-// CHECK-NEXT: [[TMP5896:%.*]] = bitcast double [[TMP5894]] to i64
-// CHECK-NEXT: [[TMP5897:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5895]], i64 [[TMP5896]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP5898:%.*]] = extractvalue { i64, i1 } [[TMP5897]], 0
-// CHECK-NEXT: [[TMP5899:%.*]] = bitcast i64 [[TMP5898]] to double
-// CHECK-NEXT: [[TMP5900:%.*]] = extractvalue { i64, i1 } [[TMP5897]], 1
-// CHECK-NEXT: [[TMP5901:%.*]] = select i1 [[TMP5900]], double [[TMP5893]], double [[TMP5899]]
-// CHECK-NEXT: store double [[TMP5901]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5902:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5903:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5904:%.*]] = bitcast double [[TMP5902]] to i64
-// CHECK-NEXT: [[TMP5905:%.*]] = bitcast double [[TMP5903]] to i64
-// CHECK-NEXT: [[TMP5906:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5904]], i64 [[TMP5905]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP5907:%.*]] = extractvalue { i64, i1 } [[TMP5906]], 0
-// CHECK-NEXT: [[TMP5908:%.*]] = bitcast i64 [[TMP5907]] to double
-// CHECK-NEXT: [[TMP5909:%.*]] = extractvalue { i64, i1 } [[TMP5906]], 1
-// CHECK-NEXT: br i1 [[TMP5909]], label [[DX_ATOMIC_EXIT545:%.*]], label [[DX_ATOMIC_CONT546:%.*]]
-// CHECK: dx.atomic.cont546:
-// CHECK-NEXT: store double [[TMP5908]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT545]]
-// CHECK: dx.atomic.exit545:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5910:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5911:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5912:%.*]] = bitcast double [[TMP5910]] to i64
-// CHECK-NEXT: [[TMP5913:%.*]] = bitcast double [[TMP5911]] to i64
-// CHECK-NEXT: [[TMP5914:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5912]], i64 [[TMP5913]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP5915:%.*]] = extractvalue { i64, i1 } [[TMP5914]], 0
-// CHECK-NEXT: [[TMP5916:%.*]] = bitcast i64 [[TMP5915]] to double
-// CHECK-NEXT: [[TMP5917:%.*]] = extractvalue { i64, i1 } [[TMP5914]], 1
-// CHECK-NEXT: br i1 [[TMP5917]], label [[DX_ATOMIC_EXIT547:%.*]], label [[DX_ATOMIC_CONT548:%.*]]
-// CHECK: dx.atomic.cont548:
-// CHECK-NEXT: store double [[TMP5916]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT547]]
-// CHECK: dx.atomic.exit547:
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5918:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5919:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5920:%.*]] = bitcast double [[TMP5918]] to i64
-// CHECK-NEXT: [[TMP5921:%.*]] = bitcast double [[TMP5919]] to i64
-// CHECK-NEXT: [[TMP5922:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5920]], i64 [[TMP5921]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP5923:%.*]] = extractvalue { i64, i1 } [[TMP5922]], 1
-// CHECK-NEXT: [[TMP5924:%.*]] = sext i1 [[TMP5923]] to i32
-// CHECK-NEXT: store i32 [[TMP5924]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5925:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5926:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5927:%.*]] = bitcast double [[TMP5925]] to i64
-// CHECK-NEXT: [[TMP5928:%.*]] = bitcast double [[TMP5926]] to i64
-// CHECK-NEXT: [[TMP5929:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5927]], i64 [[TMP5928]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP5930:%.*]] = extractvalue { i64, i1 } [[TMP5929]], 1
-// CHECK-NEXT: [[TMP5931:%.*]] = sext i1 [[TMP5930]] to i32
-// CHECK-NEXT: store i32 [[TMP5931]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5932:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5933:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5934:%.*]] = bitcast double [[TMP5932]] to i64
-// CHECK-NEXT: [[TMP5935:%.*]] = bitcast double [[TMP5933]] to i64
-// CHECK-NEXT: [[TMP5936:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5934]], i64 [[TMP5935]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP5937:%.*]] = extractvalue { i64, i1 } [[TMP5936]], 0
-// CHECK-NEXT: [[TMP5938:%.*]] = bitcast i64 [[TMP5937]] to double
-// CHECK-NEXT: [[TMP5939:%.*]] = extractvalue { i64, i1 } [[TMP5936]], 1
-// CHECK-NEXT: br i1 [[TMP5939]], label [[DX_ATOMIC_EXIT549:%.*]], label [[DX_ATOMIC_CONT550:%.*]]
-// CHECK: dx.atomic.cont550:
-// CHECK-NEXT: store double [[TMP5938]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT549]]
-// CHECK: dx.atomic.exit549:
-// CHECK-NEXT: [[TMP5940:%.*]] = extractvalue { i64, i1 } [[TMP5936]], 1
-// CHECK-NEXT: [[TMP5941:%.*]] = sext i1 [[TMP5940]] to i32
-// CHECK-NEXT: store i32 [[TMP5941]], ptr [[IR]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP5942:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP5943:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP5944:%.*]] = bitcast double [[TMP5942]] to i64
-// CHECK-NEXT: [[TMP5945:%.*]] = bitcast double [[TMP5943]] to i64
-// CHECK-NEXT: [[TMP5946:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP5944]], i64 [[TMP5945]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP5947:%.*]] = extractvalue { i64, i1 } [[TMP5946]], 0
-// CHECK-NEXT: [[TMP5948:%.*]] = bitcast i64 [[TMP5947]] to double
-// CHECK-NEXT: [[TMP5949:%.*]] = extractvalue { i64, i1 } [[TMP5946]], 1
-// CHECK-NEXT: br i1 [[TMP5949]], label [[DX_ATOMIC_EXIT551:%.*]], label [[DX_ATOMIC_CONT552:%.*]]
-// CHECK: dx.atomic.cont552:
-// CHECK-NEXT: store double [[TMP5948]], ptr [[DV]], align 8
-// CHECK-NEXT: br label [[DX_ATOMIC_EXIT551]]
-// CHECK: dx.atomic.exit551:
-// CHECK-NEXT: [[TMP5950:%.*]] = extractvalue { i64, i1 } [[TMP5946]], 1
-// CHECK-NEXT: [[TMP5951:%.*]] = sext i1 [[TMP5950]] to i32
-// CHECK-NEXT: store i32 [[TMP5951]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3202:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3203:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3202]], ptr [[DX_ATOMIC_EXPECTED_PTR6386]], align 8
+// CHECK-NEXT: store double [[TMP3203]], ptr [[DX_ATOMIC_DESIRED_PTR6387]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6389:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6386]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6390:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6387]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6391:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6389]], i64 [[DX_CMPXCHG_DESIRED6390]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6392:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6391]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6392]], ptr [[DX_ATOMIC_EXPECTED_PTR6388]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6393:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6391]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6394:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6388]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6393]], label [[DX_ATOMIC_EXIT6395:%.*]], label [[DX_ATOMIC_CONT6396:%.*]]
+// CHECK: dx.atomic.cont6396:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6394]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6395]]
+// CHECK: dx.atomic.exit6395:
+// CHECK-NEXT: [[TMP3204:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3205:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3204]], ptr [[DX_ATOMIC_EXPECTED_PTR6397]], align 8
+// CHECK-NEXT: store double [[TMP3205]], ptr [[DX_ATOMIC_DESIRED_PTR6398]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6400:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6397]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6401:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6398]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6402:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6400]], i64 [[DX_CMPXCHG_DESIRED6401]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6403:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6402]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6403]], ptr [[DX_ATOMIC_EXPECTED_PTR6399]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6404:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6402]], 1
+// CHECK-NEXT: [[TMP3206:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6404]] to i32
+// CHECK-NEXT: store i32 [[TMP3206]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3207:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3208:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3207]], ptr [[DX_ATOMIC_EXPECTED_PTR6405]], align 8
+// CHECK-NEXT: store double [[TMP3208]], ptr [[DX_ATOMIC_DESIRED_PTR6406]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6408:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6405]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6409:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6406]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6410:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6408]], i64 [[DX_CMPXCHG_DESIRED6409]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6411:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6410]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6411]], ptr [[DX_ATOMIC_EXPECTED_PTR6407]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6412:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6410]], 1
+// CHECK-NEXT: [[TMP3209:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6412]] to i32
+// CHECK-NEXT: store i32 [[TMP3209]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3210:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3211:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3210]], ptr [[DX_ATOMIC_EXPECTED_PTR6413]], align 8
+// CHECK-NEXT: store double [[TMP3211]], ptr [[DX_ATOMIC_DESIRED_PTR6414]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6416:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6413]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6417:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6414]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6418:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6416]], i64 [[DX_CMPXCHG_DESIRED6417]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6419:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6418]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6419]], ptr [[DX_ATOMIC_EXPECTED_PTR6415]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6420:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6418]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6421:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6415]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6420]], label [[DX_ATOMIC_EXIT6422:%.*]], label [[DX_ATOMIC_CONT6423:%.*]]
+// CHECK: dx.atomic.cont6423:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6421]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6422]]
+// CHECK: dx.atomic.exit6422:
+// CHECK-NEXT: [[TMP3212:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6420]] to i32
+// CHECK-NEXT: store i32 [[TMP3212]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3213:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3214:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3213]], ptr [[DX_ATOMIC_EXPECTED_PTR6424]], align 8
+// CHECK-NEXT: store double [[TMP3214]], ptr [[DX_ATOMIC_DESIRED_PTR6425]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6427:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6424]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6428:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6425]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6429:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6427]], i64 [[DX_CMPXCHG_DESIRED6428]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6430:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6429]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6430]], ptr [[DX_ATOMIC_EXPECTED_PTR6426]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6431:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6429]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6432:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6426]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6431]], label [[DX_ATOMIC_EXIT6433:%.*]], label [[DX_ATOMIC_CONT6434:%.*]]
+// CHECK: dx.atomic.cont6434:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6432]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6433]]
+// CHECK: dx.atomic.exit6433:
+// CHECK-NEXT: [[TMP3215:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6431]] to i32
+// CHECK-NEXT: store i32 [[TMP3215]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3216:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3217:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3216]] acq_rel, align 8
+// CHECK-NEXT: store double [[TMP3217]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3218:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3219:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3218]] acq_rel, align 8
+// CHECK-NEXT: store double [[TMP3219]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3220:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3221:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3220]] acq_rel, align 8
+// CHECK-NEXT: store double [[TMP3221]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3222:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3223:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3222]] acq_rel, align 8
+// CHECK-NEXT: store double [[TMP3223]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3224:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3225:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3224]], ptr [[DX_ATOMIC_EXPECTED_PTR6435]], align 8
+// CHECK-NEXT: store double [[TMP3225]], ptr [[DX_ATOMIC_DESIRED_PTR6436]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6438:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6435]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6439:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6436]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6440:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6438]], i64 [[DX_CMPXCHG_DESIRED6439]] acq_rel acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6441:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6440]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6441]], ptr [[DX_ATOMIC_EXPECTED_PTR6437]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6442:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6440]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6443:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6437]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6443]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3226:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3227:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3226]], ptr [[DX_ATOMIC_EXPECTED_PTR6444]], align 8
+// CHECK-NEXT: store double [[TMP3227]], ptr [[DX_ATOMIC_DESIRED_PTR6445]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6447:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6444]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6448:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6445]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6449:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6447]], i64 [[DX_CMPXCHG_DESIRED6448]] acq_rel acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6450:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6449]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6450]], ptr [[DX_ATOMIC_EXPECTED_PTR6446]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6451:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6449]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6452:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6446]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6452]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3228:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3229:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3228]] acq_rel, align 8
+// CHECK-NEXT: [[TMP3230:%.*]] = fcmp ogt double [[TMP3229]], [[TMP3228]]
+// CHECK-NEXT: [[TMP3231:%.*]] = select i1 [[TMP3230]], double [[TMP3228]], double [[TMP3229]]
+// CHECK-NEXT: store double [[TMP3231]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3232:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3233:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3232]] acq_rel, align 8
+// CHECK-NEXT: [[TMP3234:%.*]] = fcmp olt double [[TMP3233]], [[TMP3232]]
+// CHECK-NEXT: [[TMP3235:%.*]] = select i1 [[TMP3234]], double [[TMP3232]], double [[TMP3233]]
+// CHECK-NEXT: store double [[TMP3235]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3236:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3237:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3236]] acq_rel, align 8
+// CHECK-NEXT: [[TMP3238:%.*]] = fcmp olt double [[TMP3237]], [[TMP3236]]
+// CHECK-NEXT: [[TMP3239:%.*]] = select i1 [[TMP3238]], double [[TMP3236]], double [[TMP3237]]
+// CHECK-NEXT: store double [[TMP3239]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3240:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3241:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3240]] acq_rel, align 8
+// CHECK-NEXT: [[TMP3242:%.*]] = fcmp ogt double [[TMP3241]], [[TMP3240]]
+// CHECK-NEXT: [[TMP3243:%.*]] = select i1 [[TMP3242]], double [[TMP3240]], double [[TMP3241]]
+// CHECK-NEXT: store double [[TMP3243]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3244:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3245:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3244]], ptr [[DX_ATOMIC_EXPECTED_PTR6453]], align 8
+// CHECK-NEXT: store double [[TMP3245]], ptr [[DX_ATOMIC_DESIRED_PTR6454]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6456:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6453]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6457:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6454]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6458:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6456]], i64 [[DX_CMPXCHG_DESIRED6457]] acq_rel acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6459:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6458]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6459]], ptr [[DX_ATOMIC_EXPECTED_PTR6455]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6460:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6458]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6461:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6455]], align 8
+// CHECK-NEXT: [[DX_CAPTURE_CAPTURED6462:%.*]] = select i1 [[DX_CMPXCHG_SUCCESS6460]], double [[TMP3244]], double [[DX_CAPTURE_ACTUAL6461]]
+// CHECK-NEXT: store double [[DX_CAPTURE_CAPTURED6462]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3246:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3247:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3246]], ptr [[DX_ATOMIC_EXPECTED_PTR6463]], align 8
+// CHECK-NEXT: store double [[TMP3247]], ptr [[DX_ATOMIC_DESIRED_PTR6464]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6466:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6463]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6467:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6464]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6468:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6466]], i64 [[DX_CMPXCHG_DESIRED6467]] acq_rel acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6469:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6468]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6469]], ptr [[DX_ATOMIC_EXPECTED_PTR6465]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6470:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6468]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6471:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6465]], align 8
+// CHECK-NEXT: [[DX_CAPTURE_CAPTURED6472:%.*]] = select i1 [[DX_CMPXCHG_SUCCESS6470]], double [[TMP3246]], double [[DX_CAPTURE_ACTUAL6471]]
+// CHECK-NEXT: store double [[DX_CAPTURE_CAPTURED6472]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3248:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3249:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3248]], ptr [[DX_ATOMIC_EXPECTED_PTR6473]], align 8
+// CHECK-NEXT: store double [[TMP3249]], ptr [[DX_ATOMIC_DESIRED_PTR6474]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6476:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6473]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6477:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6474]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6478:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6476]], i64 [[DX_CMPXCHG_DESIRED6477]] acq_rel acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6479:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6478]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6479]], ptr [[DX_ATOMIC_EXPECTED_PTR6475]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6480:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6478]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6481:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6475]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6480]], label [[DX_ATOMIC_EXIT6482:%.*]], label [[DX_ATOMIC_CONT6483:%.*]]
+// CHECK: dx.atomic.cont6483:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6481]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6482]]
+// CHECK: dx.atomic.exit6482:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3250:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3251:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3250]], ptr [[DX_ATOMIC_EXPECTED_PTR6484]], align 8
+// CHECK-NEXT: store double [[TMP3251]], ptr [[DX_ATOMIC_DESIRED_PTR6485]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6487:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6484]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6488:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6485]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6489:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6487]], i64 [[DX_CMPXCHG_DESIRED6488]] acq_rel acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6490:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6489]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6490]], ptr [[DX_ATOMIC_EXPECTED_PTR6486]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6491:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6489]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6492:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6486]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6491]], label [[DX_ATOMIC_EXIT6493:%.*]], label [[DX_ATOMIC_CONT6494:%.*]]
+// CHECK: dx.atomic.cont6494:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6492]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6493]]
+// CHECK: dx.atomic.exit6493:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3252:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3253:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3252]], ptr [[DX_ATOMIC_EXPECTED_PTR6495]], align 8
+// CHECK-NEXT: store double [[TMP3253]], ptr [[DX_ATOMIC_DESIRED_PTR6496]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6498:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6495]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6499:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6496]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6500:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6498]], i64 [[DX_CMPXCHG_DESIRED6499]] acq_rel acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6501:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6500]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6501]], ptr [[DX_ATOMIC_EXPECTED_PTR6497]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6502:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6500]], 1
+// CHECK-NEXT: [[TMP3254:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6502]] to i32
+// CHECK-NEXT: store i32 [[TMP3254]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3255:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3256:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3255]], ptr [[DX_ATOMIC_EXPECTED_PTR6503]], align 8
+// CHECK-NEXT: store double [[TMP3256]], ptr [[DX_ATOMIC_DESIRED_PTR6504]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6506:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6503]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6507:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6504]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6508:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6506]], i64 [[DX_CMPXCHG_DESIRED6507]] acq_rel acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6509:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6508]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6509]], ptr [[DX_ATOMIC_EXPECTED_PTR6505]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6510:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6508]], 1
+// CHECK-NEXT: [[TMP3257:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6510]] to i32
+// CHECK-NEXT: store i32 [[TMP3257]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3258:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3259:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3258]], ptr [[DX_ATOMIC_EXPECTED_PTR6511]], align 8
+// CHECK-NEXT: store double [[TMP3259]], ptr [[DX_ATOMIC_DESIRED_PTR6512]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6514:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6511]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6515:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6512]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6516:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6514]], i64 [[DX_CMPXCHG_DESIRED6515]] acq_rel acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6517:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6516]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6517]], ptr [[DX_ATOMIC_EXPECTED_PTR6513]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6518:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6516]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6519:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6513]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6518]], label [[DX_ATOMIC_EXIT6520:%.*]], label [[DX_ATOMIC_CONT6521:%.*]]
+// CHECK: dx.atomic.cont6521:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6519]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6520]]
+// CHECK: dx.atomic.exit6520:
+// CHECK-NEXT: [[TMP3260:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6518]] to i32
+// CHECK-NEXT: store i32 [[TMP3260]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3261:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3262:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3261]], ptr [[DX_ATOMIC_EXPECTED_PTR6522]], align 8
+// CHECK-NEXT: store double [[TMP3262]], ptr [[DX_ATOMIC_DESIRED_PTR6523]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6525:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6522]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6526:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6523]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6527:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6525]], i64 [[DX_CMPXCHG_DESIRED6526]] acq_rel acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6528:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6527]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6528]], ptr [[DX_ATOMIC_EXPECTED_PTR6524]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6529:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6527]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6530:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6524]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6529]], label [[DX_ATOMIC_EXIT6531:%.*]], label [[DX_ATOMIC_CONT6532:%.*]]
+// CHECK: dx.atomic.cont6532:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6530]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6531]]
+// CHECK: dx.atomic.exit6531:
+// CHECK-NEXT: [[TMP3263:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6529]] to i32
+// CHECK-NEXT: store i32 [[TMP3263]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3264:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3265:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3264]] acquire, align 8
+// CHECK-NEXT: store double [[TMP3265]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3266:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3267:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3266]] acquire, align 8
+// CHECK-NEXT: store double [[TMP3267]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3268:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3269:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3268]] acquire, align 8
+// CHECK-NEXT: store double [[TMP3269]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3270:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3271:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3270]] acquire, align 8
+// CHECK-NEXT: store double [[TMP3271]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3272:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3273:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3272]], ptr [[DX_ATOMIC_EXPECTED_PTR6533]], align 8
+// CHECK-NEXT: store double [[TMP3273]], ptr [[DX_ATOMIC_DESIRED_PTR6534]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6536:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6533]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6537:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6534]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6538:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6536]], i64 [[DX_CMPXCHG_DESIRED6537]] acquire acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6539:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6538]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6539]], ptr [[DX_ATOMIC_EXPECTED_PTR6535]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6540:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6538]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6541:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6535]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6541]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3274:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3275:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3274]], ptr [[DX_ATOMIC_EXPECTED_PTR6542]], align 8
+// CHECK-NEXT: store double [[TMP3275]], ptr [[DX_ATOMIC_DESIRED_PTR6543]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6545:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6542]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6546:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6543]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6547:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6545]], i64 [[DX_CMPXCHG_DESIRED6546]] acquire acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6548:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6547]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6548]], ptr [[DX_ATOMIC_EXPECTED_PTR6544]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6549:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6547]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6550:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6544]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6550]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3276:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3277:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3276]] acquire, align 8
+// CHECK-NEXT: [[TMP3278:%.*]] = fcmp ogt double [[TMP3277]], [[TMP3276]]
+// CHECK-NEXT: [[TMP3279:%.*]] = select i1 [[TMP3278]], double [[TMP3276]], double [[TMP3277]]
+// CHECK-NEXT: store double [[TMP3279]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3280:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3281:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3280]] acquire, align 8
+// CHECK-NEXT: [[TMP3282:%.*]] = fcmp olt double [[TMP3281]], [[TMP3280]]
+// CHECK-NEXT: [[TMP3283:%.*]] = select i1 [[TMP3282]], double [[TMP3280]], double [[TMP3281]]
+// CHECK-NEXT: store double [[TMP3283]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3284:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3285:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3284]] acquire, align 8
+// CHECK-NEXT: [[TMP3286:%.*]] = fcmp olt double [[TMP3285]], [[TMP3284]]
+// CHECK-NEXT: [[TMP3287:%.*]] = select i1 [[TMP3286]], double [[TMP3284]], double [[TMP3285]]
+// CHECK-NEXT: store double [[TMP3287]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3288:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3289:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3288]] acquire, align 8
+// CHECK-NEXT: [[TMP3290:%.*]] = fcmp ogt double [[TMP3289]], [[TMP3288]]
+// CHECK-NEXT: [[TMP3291:%.*]] = select i1 [[TMP3290]], double [[TMP3288]], double [[TMP3289]]
+// CHECK-NEXT: store double [[TMP3291]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3292:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3293:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3292]], ptr [[DX_ATOMIC_EXPECTED_PTR6551]], align 8
+// CHECK-NEXT: store double [[TMP3293]], ptr [[DX_ATOMIC_DESIRED_PTR6552]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6554:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6551]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6555:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6552]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6556:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6554]], i64 [[DX_CMPXCHG_DESIRED6555]] acquire acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6557:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6556]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6557]], ptr [[DX_ATOMIC_EXPECTED_PTR6553]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6558:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6556]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6559:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6553]], align 8
+// CHECK-NEXT: [[DX_CAPTURE_CAPTURED6560:%.*]] = select i1 [[DX_CMPXCHG_SUCCESS6558]], double [[TMP3292]], double [[DX_CAPTURE_ACTUAL6559]]
+// CHECK-NEXT: store double [[DX_CAPTURE_CAPTURED6560]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3294:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3295:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3294]], ptr [[DX_ATOMIC_EXPECTED_PTR6561]], align 8
+// CHECK-NEXT: store double [[TMP3295]], ptr [[DX_ATOMIC_DESIRED_PTR6562]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6564:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6561]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6565:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6562]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6566:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6564]], i64 [[DX_CMPXCHG_DESIRED6565]] acquire acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6567:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6566]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6567]], ptr [[DX_ATOMIC_EXPECTED_PTR6563]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6568:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6566]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6569:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6563]], align 8
+// CHECK-NEXT: [[DX_CAPTURE_CAPTURED6570:%.*]] = select i1 [[DX_CMPXCHG_SUCCESS6568]], double [[TMP3294]], double [[DX_CAPTURE_ACTUAL6569]]
+// CHECK-NEXT: store double [[DX_CAPTURE_CAPTURED6570]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3296:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3297:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3296]], ptr [[DX_ATOMIC_EXPECTED_PTR6571]], align 8
+// CHECK-NEXT: store double [[TMP3297]], ptr [[DX_ATOMIC_DESIRED_PTR6572]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6574:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6571]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6575:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6572]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6576:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6574]], i64 [[DX_CMPXCHG_DESIRED6575]] acquire acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6577:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6576]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6577]], ptr [[DX_ATOMIC_EXPECTED_PTR6573]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6578:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6576]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6579:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6573]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6578]], label [[DX_ATOMIC_EXIT6580:%.*]], label [[DX_ATOMIC_CONT6581:%.*]]
+// CHECK: dx.atomic.cont6581:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6579]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6580]]
+// CHECK: dx.atomic.exit6580:
+// CHECK-NEXT: [[TMP3298:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3299:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3298]], ptr [[DX_ATOMIC_EXPECTED_PTR6582]], align 8
+// CHECK-NEXT: store double [[TMP3299]], ptr [[DX_ATOMIC_DESIRED_PTR6583]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6585:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6582]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6586:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6583]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6587:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6585]], i64 [[DX_CMPXCHG_DESIRED6586]] acquire acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6588:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6587]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6588]], ptr [[DX_ATOMIC_EXPECTED_PTR6584]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6589:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6587]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6590:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6584]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6589]], label [[DX_ATOMIC_EXIT6591:%.*]], label [[DX_ATOMIC_CONT6592:%.*]]
+// CHECK: dx.atomic.cont6592:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6590]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6591]]
+// CHECK: dx.atomic.exit6591:
+// CHECK-NEXT: [[TMP3300:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3301:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3300]], ptr [[DX_ATOMIC_EXPECTED_PTR6593]], align 8
+// CHECK-NEXT: store double [[TMP3301]], ptr [[DX_ATOMIC_DESIRED_PTR6594]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6596:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6593]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6597:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6594]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6598:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6596]], i64 [[DX_CMPXCHG_DESIRED6597]] acquire acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6599:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6598]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6599]], ptr [[DX_ATOMIC_EXPECTED_PTR6595]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6600:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6598]], 1
+// CHECK-NEXT: [[TMP3302:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6600]] to i32
+// CHECK-NEXT: store i32 [[TMP3302]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3303:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3304:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3303]], ptr [[DX_ATOMIC_EXPECTED_PTR6601]], align 8
+// CHECK-NEXT: store double [[TMP3304]], ptr [[DX_ATOMIC_DESIRED_PTR6602]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6604:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6601]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6605:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6602]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6606:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6604]], i64 [[DX_CMPXCHG_DESIRED6605]] acquire acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6607:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6606]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6607]], ptr [[DX_ATOMIC_EXPECTED_PTR6603]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6608:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6606]], 1
+// CHECK-NEXT: [[TMP3305:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6608]] to i32
+// CHECK-NEXT: store i32 [[TMP3305]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3306:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3307:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3306]], ptr [[DX_ATOMIC_EXPECTED_PTR6609]], align 8
+// CHECK-NEXT: store double [[TMP3307]], ptr [[DX_ATOMIC_DESIRED_PTR6610]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6612:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6609]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6613:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6610]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6614:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6612]], i64 [[DX_CMPXCHG_DESIRED6613]] acquire acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6615:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6614]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6615]], ptr [[DX_ATOMIC_EXPECTED_PTR6611]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6616:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6614]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6617:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6611]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6616]], label [[DX_ATOMIC_EXIT6618:%.*]], label [[DX_ATOMIC_CONT6619:%.*]]
+// CHECK: dx.atomic.cont6619:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6617]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6618]]
+// CHECK: dx.atomic.exit6618:
+// CHECK-NEXT: [[TMP3308:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6616]] to i32
+// CHECK-NEXT: store i32 [[TMP3308]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3309:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3310:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3309]], ptr [[DX_ATOMIC_EXPECTED_PTR6620]], align 8
+// CHECK-NEXT: store double [[TMP3310]], ptr [[DX_ATOMIC_DESIRED_PTR6621]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6623:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6620]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6624:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6621]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6625:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6623]], i64 [[DX_CMPXCHG_DESIRED6624]] acquire acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6626:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6625]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6626]], ptr [[DX_ATOMIC_EXPECTED_PTR6622]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6627:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6625]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6628:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6622]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6627]], label [[DX_ATOMIC_EXIT6629:%.*]], label [[DX_ATOMIC_CONT6630:%.*]]
+// CHECK: dx.atomic.cont6630:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6628]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6629]]
+// CHECK: dx.atomic.exit6629:
+// CHECK-NEXT: [[TMP3311:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6627]] to i32
+// CHECK-NEXT: store i32 [[TMP3311]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3312:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3313:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3312]] monotonic, align 8
+// CHECK-NEXT: store double [[TMP3313]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3314:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3315:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3314]] monotonic, align 8
+// CHECK-NEXT: store double [[TMP3315]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3316:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3317:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3316]] monotonic, align 8
+// CHECK-NEXT: store double [[TMP3317]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3318:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3319:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3318]] monotonic, align 8
+// CHECK-NEXT: store double [[TMP3319]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3320:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3321:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3320]], ptr [[DX_ATOMIC_EXPECTED_PTR6631]], align 8
+// CHECK-NEXT: store double [[TMP3321]], ptr [[DX_ATOMIC_DESIRED_PTR6632]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6634:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6631]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6635:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6632]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6636:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6634]], i64 [[DX_CMPXCHG_DESIRED6635]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6637:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6636]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6637]], ptr [[DX_ATOMIC_EXPECTED_PTR6633]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6638:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6636]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6639:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6633]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6639]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3322:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3323:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3322]], ptr [[DX_ATOMIC_EXPECTED_PTR6640]], align 8
+// CHECK-NEXT: store double [[TMP3323]], ptr [[DX_ATOMIC_DESIRED_PTR6641]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6643:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6640]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6644:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6641]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6645:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6643]], i64 [[DX_CMPXCHG_DESIRED6644]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6646:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6645]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6646]], ptr [[DX_ATOMIC_EXPECTED_PTR6642]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6647:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6645]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6648:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6642]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6648]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3324:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3325:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3324]] monotonic, align 8
+// CHECK-NEXT: [[TMP3326:%.*]] = fcmp ogt double [[TMP3325]], [[TMP3324]]
+// CHECK-NEXT: [[TMP3327:%.*]] = select i1 [[TMP3326]], double [[TMP3324]], double [[TMP3325]]
+// CHECK-NEXT: store double [[TMP3327]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3328:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3329:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3328]] monotonic, align 8
+// CHECK-NEXT: [[TMP3330:%.*]] = fcmp olt double [[TMP3329]], [[TMP3328]]
+// CHECK-NEXT: [[TMP3331:%.*]] = select i1 [[TMP3330]], double [[TMP3328]], double [[TMP3329]]
+// CHECK-NEXT: store double [[TMP3331]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3332:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3333:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3332]] monotonic, align 8
+// CHECK-NEXT: [[TMP3334:%.*]] = fcmp olt double [[TMP3333]], [[TMP3332]]
+// CHECK-NEXT: [[TMP3335:%.*]] = select i1 [[TMP3334]], double [[TMP3332]], double [[TMP3333]]
+// CHECK-NEXT: store double [[TMP3335]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3336:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3337:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3336]] monotonic, align 8
+// CHECK-NEXT: [[TMP3338:%.*]] = fcmp ogt double [[TMP3337]], [[TMP3336]]
+// CHECK-NEXT: [[TMP3339:%.*]] = select i1 [[TMP3338]], double [[TMP3336]], double [[TMP3337]]
+// CHECK-NEXT: store double [[TMP3339]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3340:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3341:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3340]], ptr [[DX_ATOMIC_EXPECTED_PTR6649]], align 8
+// CHECK-NEXT: store double [[TMP3341]], ptr [[DX_ATOMIC_DESIRED_PTR6650]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6652:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6649]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6653:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6650]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6654:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6652]], i64 [[DX_CMPXCHG_DESIRED6653]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6655:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6654]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6655]], ptr [[DX_ATOMIC_EXPECTED_PTR6651]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6656:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6654]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6657:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6651]], align 8
+// CHECK-NEXT: [[DX_CAPTURE_CAPTURED6658:%.*]] = select i1 [[DX_CMPXCHG_SUCCESS6656]], double [[TMP3340]], double [[DX_CAPTURE_ACTUAL6657]]
+// CHECK-NEXT: store double [[DX_CAPTURE_CAPTURED6658]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3342:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3343:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3342]], ptr [[DX_ATOMIC_EXPECTED_PTR6659]], align 8
+// CHECK-NEXT: store double [[TMP3343]], ptr [[DX_ATOMIC_DESIRED_PTR6660]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6662:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6659]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6663:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6660]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6664:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6662]], i64 [[DX_CMPXCHG_DESIRED6663]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6665:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6664]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6665]], ptr [[DX_ATOMIC_EXPECTED_PTR6661]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6666:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6664]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6667:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6661]], align 8
+// CHECK-NEXT: [[DX_CAPTURE_CAPTURED6668:%.*]] = select i1 [[DX_CMPXCHG_SUCCESS6666]], double [[TMP3342]], double [[DX_CAPTURE_ACTUAL6667]]
+// CHECK-NEXT: store double [[DX_CAPTURE_CAPTURED6668]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP3344:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3345:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3344]], ptr [[DX_ATOMIC_EXPECTED_PTR6669]], align 8
+// CHECK-NEXT: store double [[TMP3345]], ptr [[DX_ATOMIC_DESIRED_PTR6670]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6672:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6669]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6673:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6670]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6674:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6672]], i64 [[DX_CMPXCHG_DESIRED6673]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6675:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6674]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6675]], ptr [[DX_ATOMIC_EXPECTED_PTR6671]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6676:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6674]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6677:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6671]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6676]], label [[DX_ATOMIC_EXIT6678:%.*]], label [[DX_ATOMIC_CONT6679:%.*]]
+// CHECK: dx.atomic.cont6679:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6677]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6678]]
+// CHECK: dx.atomic.exit6678:
+// CHECK-NEXT: [[TMP3346:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3347:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3346]], ptr [[DX_ATOMIC_EXPECTED_PTR6680]], align 8
+// CHECK-NEXT: store double [[TMP3347]], ptr [[DX_ATOMIC_DESIRED_PTR6681]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6683:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6680]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6684:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6681]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6685:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6683]], i64 [[DX_CMPXCHG_DESIRED6684]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6686:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6685]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6686]], ptr [[DX_ATOMIC_EXPECTED_PTR6682]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6687:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6685]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6688:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6682]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6687]], label [[DX_ATOMIC_EXIT6689:%.*]], label [[DX_ATOMIC_CONT6690:%.*]]
+// CHECK: dx.atomic.cont6690:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6688]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6689]]
+// CHECK: dx.atomic.exit6689:
+// CHECK-NEXT: [[TMP3348:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3349:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3348]], ptr [[DX_ATOMIC_EXPECTED_PTR6691]], align 8
+// CHECK-NEXT: store double [[TMP3349]], ptr [[DX_ATOMIC_DESIRED_PTR6692]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6694:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6691]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6695:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6692]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6696:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6694]], i64 [[DX_CMPXCHG_DESIRED6695]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6697:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6696]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6697]], ptr [[DX_ATOMIC_EXPECTED_PTR6693]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6698:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6696]], 1
+// CHECK-NEXT: [[TMP3350:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6698]] to i32
+// CHECK-NEXT: store i32 [[TMP3350]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3351:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3352:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3351]], ptr [[DX_ATOMIC_EXPECTED_PTR6699]], align 8
+// CHECK-NEXT: store double [[TMP3352]], ptr [[DX_ATOMIC_DESIRED_PTR6700]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6702:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6699]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6703:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6700]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6704:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6702]], i64 [[DX_CMPXCHG_DESIRED6703]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6705:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6704]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6705]], ptr [[DX_ATOMIC_EXPECTED_PTR6701]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6706:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6704]], 1
+// CHECK-NEXT: [[TMP3353:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6706]] to i32
+// CHECK-NEXT: store i32 [[TMP3353]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3354:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3355:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3354]], ptr [[DX_ATOMIC_EXPECTED_PTR6707]], align 8
+// CHECK-NEXT: store double [[TMP3355]], ptr [[DX_ATOMIC_DESIRED_PTR6708]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6710:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6707]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6711:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6708]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6712:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6710]], i64 [[DX_CMPXCHG_DESIRED6711]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6713:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6712]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6713]], ptr [[DX_ATOMIC_EXPECTED_PTR6709]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6714:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6712]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6715:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6709]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6714]], label [[DX_ATOMIC_EXIT6716:%.*]], label [[DX_ATOMIC_CONT6717:%.*]]
+// CHECK: dx.atomic.cont6717:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6715]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6716]]
+// CHECK: dx.atomic.exit6716:
+// CHECK-NEXT: [[TMP3356:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6714]] to i32
+// CHECK-NEXT: store i32 [[TMP3356]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3357:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3358:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3357]], ptr [[DX_ATOMIC_EXPECTED_PTR6718]], align 8
+// CHECK-NEXT: store double [[TMP3358]], ptr [[DX_ATOMIC_DESIRED_PTR6719]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6721:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6718]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6722:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6719]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6723:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6721]], i64 [[DX_CMPXCHG_DESIRED6722]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6724:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6723]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6724]], ptr [[DX_ATOMIC_EXPECTED_PTR6720]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6725:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6723]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6726:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6720]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6725]], label [[DX_ATOMIC_EXIT6727:%.*]], label [[DX_ATOMIC_CONT6728:%.*]]
+// CHECK: dx.atomic.cont6728:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6726]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6727]]
+// CHECK: dx.atomic.exit6727:
+// CHECK-NEXT: [[TMP3359:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6725]] to i32
+// CHECK-NEXT: store i32 [[TMP3359]], ptr [[IR]], align 4
+// CHECK-NEXT: [[TMP3360:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3361:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3360]] release, align 8
+// CHECK-NEXT: store double [[TMP3361]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3362:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3363:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3362]] release, align 8
+// CHECK-NEXT: store double [[TMP3363]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3364:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3365:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3364]] release, align 8
+// CHECK-NEXT: store double [[TMP3365]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3366:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3367:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3366]] release, align 8
+// CHECK-NEXT: store double [[TMP3367]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3368:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3369:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3368]], ptr [[DX_ATOMIC_EXPECTED_PTR6729]], align 8
+// CHECK-NEXT: store double [[TMP3369]], ptr [[DX_ATOMIC_DESIRED_PTR6730]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6732:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6729]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6733:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6730]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6734:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6732]], i64 [[DX_CMPXCHG_DESIRED6733]] release monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6735:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6734]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6735]], ptr [[DX_ATOMIC_EXPECTED_PTR6731]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6736:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6734]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6737:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6731]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6737]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3370:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3371:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3370]], ptr [[DX_ATOMIC_EXPECTED_PTR6738]], align 8
+// CHECK-NEXT: store double [[TMP3371]], ptr [[DX_ATOMIC_DESIRED_PTR6739]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6741:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6738]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6742:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6739]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6743:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6741]], i64 [[DX_CMPXCHG_DESIRED6742]] release monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6744:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6743]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6744]], ptr [[DX_ATOMIC_EXPECTED_PTR6740]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6745:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6743]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6746:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6740]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6746]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3372:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3373:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3372]] release, align 8
+// CHECK-NEXT: [[TMP3374:%.*]] = fcmp ogt double [[TMP3373]], [[TMP3372]]
+// CHECK-NEXT: [[TMP3375:%.*]] = select i1 [[TMP3374]], double [[TMP3372]], double [[TMP3373]]
+// CHECK-NEXT: store double [[TMP3375]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3376:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3377:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3376]] release, align 8
+// CHECK-NEXT: [[TMP3378:%.*]] = fcmp olt double [[TMP3377]], [[TMP3376]]
+// CHECK-NEXT: [[TMP3379:%.*]] = select i1 [[TMP3378]], double [[TMP3376]], double [[TMP3377]]
+// CHECK-NEXT: store double [[TMP3379]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3380:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3381:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3380]] release, align 8
+// CHECK-NEXT: [[TMP3382:%.*]] = fcmp olt double [[TMP3381]], [[TMP3380]]
+// CHECK-NEXT: [[TMP3383:%.*]] = select i1 [[TMP3382]], double [[TMP3380]], double [[TMP3381]]
+// CHECK-NEXT: store double [[TMP3383]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3384:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3385:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3384]] release, align 8
+// CHECK-NEXT: [[TMP3386:%.*]] = fcmp ogt double [[TMP3385]], [[TMP3384]]
+// CHECK-NEXT: [[TMP3387:%.*]] = select i1 [[TMP3386]], double [[TMP3384]], double [[TMP3385]]
+// CHECK-NEXT: store double [[TMP3387]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3388:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3389:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3388]], ptr [[DX_ATOMIC_EXPECTED_PTR6747]], align 8
+// CHECK-NEXT: store double [[TMP3389]], ptr [[DX_ATOMIC_DESIRED_PTR6748]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6750:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6747]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6751:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6748]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6752:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6750]], i64 [[DX_CMPXCHG_DESIRED6751]] release monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6753:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6752]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6753]], ptr [[DX_ATOMIC_EXPECTED_PTR6749]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6754:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6752]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6755:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6749]], align 8
+// CHECK-NEXT: [[DX_CAPTURE_CAPTURED6756:%.*]] = select i1 [[DX_CMPXCHG_SUCCESS6754]], double [[TMP3388]], double [[DX_CAPTURE_ACTUAL6755]]
+// CHECK-NEXT: store double [[DX_CAPTURE_CAPTURED6756]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3390:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3391:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3390]], ptr [[DX_ATOMIC_EXPECTED_PTR6757]], align 8
+// CHECK-NEXT: store double [[TMP3391]], ptr [[DX_ATOMIC_DESIRED_PTR6758]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6760:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6757]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6761:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6758]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6762:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6760]], i64 [[DX_CMPXCHG_DESIRED6761]] release monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6763:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6762]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6763]], ptr [[DX_ATOMIC_EXPECTED_PTR6759]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6764:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6762]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6765:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6759]], align 8
+// CHECK-NEXT: [[DX_CAPTURE_CAPTURED6766:%.*]] = select i1 [[DX_CMPXCHG_SUCCESS6764]], double [[TMP3390]], double [[DX_CAPTURE_ACTUAL6765]]
+// CHECK-NEXT: store double [[DX_CAPTURE_CAPTURED6766]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3392:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3393:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3392]], ptr [[DX_ATOMIC_EXPECTED_PTR6767]], align 8
+// CHECK-NEXT: store double [[TMP3393]], ptr [[DX_ATOMIC_DESIRED_PTR6768]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6770:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6767]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6771:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6768]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6772:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6770]], i64 [[DX_CMPXCHG_DESIRED6771]] release monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6773:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6772]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6773]], ptr [[DX_ATOMIC_EXPECTED_PTR6769]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6774:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6772]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6775:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6769]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6774]], label [[DX_ATOMIC_EXIT6776:%.*]], label [[DX_ATOMIC_CONT6777:%.*]]
+// CHECK: dx.atomic.cont6777:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6775]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6776]]
+// CHECK: dx.atomic.exit6776:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3394:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3395:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3394]], ptr [[DX_ATOMIC_EXPECTED_PTR6778]], align 8
+// CHECK-NEXT: store double [[TMP3395]], ptr [[DX_ATOMIC_DESIRED_PTR6779]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6781:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6778]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6782:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6779]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6783:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6781]], i64 [[DX_CMPXCHG_DESIRED6782]] release monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6784:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6783]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6784]], ptr [[DX_ATOMIC_EXPECTED_PTR6780]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6785:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6783]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6786:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6780]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6785]], label [[DX_ATOMIC_EXIT6787:%.*]], label [[DX_ATOMIC_CONT6788:%.*]]
+// CHECK: dx.atomic.cont6788:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6786]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6787]]
+// CHECK: dx.atomic.exit6787:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3396:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3397:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3396]], ptr [[DX_ATOMIC_EXPECTED_PTR6789]], align 8
+// CHECK-NEXT: store double [[TMP3397]], ptr [[DX_ATOMIC_DESIRED_PTR6790]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6792:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6789]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6793:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6790]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6794:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6792]], i64 [[DX_CMPXCHG_DESIRED6793]] release monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6795:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6794]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6795]], ptr [[DX_ATOMIC_EXPECTED_PTR6791]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6796:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6794]], 1
+// CHECK-NEXT: [[TMP3398:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6796]] to i32
+// CHECK-NEXT: store i32 [[TMP3398]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3399:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3400:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3399]], ptr [[DX_ATOMIC_EXPECTED_PTR6797]], align 8
+// CHECK-NEXT: store double [[TMP3400]], ptr [[DX_ATOMIC_DESIRED_PTR6798]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6800:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6797]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6801:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6798]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6802:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6800]], i64 [[DX_CMPXCHG_DESIRED6801]] release monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6803:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6802]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6803]], ptr [[DX_ATOMIC_EXPECTED_PTR6799]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6804:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6802]], 1
+// CHECK-NEXT: [[TMP3401:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6804]] to i32
+// CHECK-NEXT: store i32 [[TMP3401]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3402:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3403:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3402]], ptr [[DX_ATOMIC_EXPECTED_PTR6805]], align 8
+// CHECK-NEXT: store double [[TMP3403]], ptr [[DX_ATOMIC_DESIRED_PTR6806]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6808:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6805]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6809:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6806]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6810:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6808]], i64 [[DX_CMPXCHG_DESIRED6809]] release monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6811:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6810]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6811]], ptr [[DX_ATOMIC_EXPECTED_PTR6807]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6812:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6810]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6813:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6807]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6812]], label [[DX_ATOMIC_EXIT6814:%.*]], label [[DX_ATOMIC_CONT6815:%.*]]
+// CHECK: dx.atomic.cont6815:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6813]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6814]]
+// CHECK: dx.atomic.exit6814:
+// CHECK-NEXT: [[TMP3404:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6812]] to i32
+// CHECK-NEXT: store i32 [[TMP3404]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3405:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3406:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3405]], ptr [[DX_ATOMIC_EXPECTED_PTR6816]], align 8
+// CHECK-NEXT: store double [[TMP3406]], ptr [[DX_ATOMIC_DESIRED_PTR6817]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6819:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6816]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6820:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6817]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6821:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6819]], i64 [[DX_CMPXCHG_DESIRED6820]] release monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6822:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6821]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6822]], ptr [[DX_ATOMIC_EXPECTED_PTR6818]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6823:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6821]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6824:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6818]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6823]], label [[DX_ATOMIC_EXIT6825:%.*]], label [[DX_ATOMIC_CONT6826:%.*]]
+// CHECK: dx.atomic.cont6826:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6824]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6825]]
+// CHECK: dx.atomic.exit6825:
+// CHECK-NEXT: [[TMP3407:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6823]] to i32
+// CHECK-NEXT: store i32 [[TMP3407]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3408:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3409:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3408]] seq_cst, align 8
+// CHECK-NEXT: store double [[TMP3409]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3410:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3411:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3410]] seq_cst, align 8
+// CHECK-NEXT: store double [[TMP3411]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3412:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3413:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3412]] seq_cst, align 8
+// CHECK-NEXT: store double [[TMP3413]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3414:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3415:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3414]] seq_cst, align 8
+// CHECK-NEXT: store double [[TMP3415]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3416:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3417:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3416]], ptr [[DX_ATOMIC_EXPECTED_PTR6827]], align 8
+// CHECK-NEXT: store double [[TMP3417]], ptr [[DX_ATOMIC_DESIRED_PTR6828]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6830:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6827]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6831:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6828]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6832:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6830]], i64 [[DX_CMPXCHG_DESIRED6831]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6833:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6832]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6833]], ptr [[DX_ATOMIC_EXPECTED_PTR6829]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6834:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6832]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6835:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6829]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6835]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3418:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3419:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3418]], ptr [[DX_ATOMIC_EXPECTED_PTR6836]], align 8
+// CHECK-NEXT: store double [[TMP3419]], ptr [[DX_ATOMIC_DESIRED_PTR6837]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6839:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6836]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6840:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6837]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6841:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6839]], i64 [[DX_CMPXCHG_DESIRED6840]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6842:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6841]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6842]], ptr [[DX_ATOMIC_EXPECTED_PTR6838]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6843:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6841]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6844:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6838]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6844]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3420:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3421:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3420]] seq_cst, align 8
+// CHECK-NEXT: [[TMP3422:%.*]] = fcmp ogt double [[TMP3421]], [[TMP3420]]
+// CHECK-NEXT: [[TMP3423:%.*]] = select i1 [[TMP3422]], double [[TMP3420]], double [[TMP3421]]
+// CHECK-NEXT: store double [[TMP3423]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3424:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3425:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3424]] seq_cst, align 8
+// CHECK-NEXT: [[TMP3426:%.*]] = fcmp olt double [[TMP3425]], [[TMP3424]]
+// CHECK-NEXT: [[TMP3427:%.*]] = select i1 [[TMP3426]], double [[TMP3424]], double [[TMP3425]]
+// CHECK-NEXT: store double [[TMP3427]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3428:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3429:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP3428]] seq_cst, align 8
+// CHECK-NEXT: [[TMP3430:%.*]] = fcmp olt double [[TMP3429]], [[TMP3428]]
+// CHECK-NEXT: [[TMP3431:%.*]] = select i1 [[TMP3430]], double [[TMP3428]], double [[TMP3429]]
+// CHECK-NEXT: store double [[TMP3431]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3432:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3433:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP3432]] seq_cst, align 8
+// CHECK-NEXT: [[TMP3434:%.*]] = fcmp ogt double [[TMP3433]], [[TMP3432]]
+// CHECK-NEXT: [[TMP3435:%.*]] = select i1 [[TMP3434]], double [[TMP3432]], double [[TMP3433]]
+// CHECK-NEXT: store double [[TMP3435]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3436:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3437:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3436]], ptr [[DX_ATOMIC_EXPECTED_PTR6845]], align 8
+// CHECK-NEXT: store double [[TMP3437]], ptr [[DX_ATOMIC_DESIRED_PTR6846]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6848:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6845]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6849:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6846]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6850:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6848]], i64 [[DX_CMPXCHG_DESIRED6849]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6851:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6850]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6851]], ptr [[DX_ATOMIC_EXPECTED_PTR6847]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6852:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6850]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6853:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6847]], align 8
+// CHECK-NEXT: [[DX_CAPTURE_CAPTURED6854:%.*]] = select i1 [[DX_CMPXCHG_SUCCESS6852]], double [[TMP3436]], double [[DX_CAPTURE_ACTUAL6853]]
+// CHECK-NEXT: store double [[DX_CAPTURE_CAPTURED6854]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3438:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3439:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3438]], ptr [[DX_ATOMIC_EXPECTED_PTR6855]], align 8
+// CHECK-NEXT: store double [[TMP3439]], ptr [[DX_ATOMIC_DESIRED_PTR6856]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6858:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6855]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6859:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6856]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6860:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6858]], i64 [[DX_CMPXCHG_DESIRED6859]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6861:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6860]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6861]], ptr [[DX_ATOMIC_EXPECTED_PTR6857]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6862:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6860]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6863:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6857]], align 8
+// CHECK-NEXT: [[DX_CAPTURE_CAPTURED6864:%.*]] = select i1 [[DX_CMPXCHG_SUCCESS6862]], double [[TMP3438]], double [[DX_CAPTURE_ACTUAL6863]]
+// CHECK-NEXT: store double [[DX_CAPTURE_CAPTURED6864]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3440:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3441:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3440]], ptr [[DX_ATOMIC_EXPECTED_PTR6865]], align 8
+// CHECK-NEXT: store double [[TMP3441]], ptr [[DX_ATOMIC_DESIRED_PTR6866]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6868:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6865]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6869:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6866]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6870:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6868]], i64 [[DX_CMPXCHG_DESIRED6869]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6871:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6870]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6871]], ptr [[DX_ATOMIC_EXPECTED_PTR6867]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6872:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6870]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6873:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6867]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6872]], label [[DX_ATOMIC_EXIT6874:%.*]], label [[DX_ATOMIC_CONT6875:%.*]]
+// CHECK: dx.atomic.cont6875:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6873]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6874]]
+// CHECK: dx.atomic.exit6874:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3442:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3443:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3442]], ptr [[DX_ATOMIC_EXPECTED_PTR6876]], align 8
+// CHECK-NEXT: store double [[TMP3443]], ptr [[DX_ATOMIC_DESIRED_PTR6877]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6879:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6876]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6880:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6877]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6881:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6879]], i64 [[DX_CMPXCHG_DESIRED6880]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6882:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6881]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6882]], ptr [[DX_ATOMIC_EXPECTED_PTR6878]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6883:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6881]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6884:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6878]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6883]], label [[DX_ATOMIC_EXIT6885:%.*]], label [[DX_ATOMIC_CONT6886:%.*]]
+// CHECK: dx.atomic.cont6886:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6884]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6885]]
+// CHECK: dx.atomic.exit6885:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3444:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3445:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3444]], ptr [[DX_ATOMIC_EXPECTED_PTR6887]], align 8
+// CHECK-NEXT: store double [[TMP3445]], ptr [[DX_ATOMIC_DESIRED_PTR6888]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6890:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6887]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6891:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6888]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6892:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6890]], i64 [[DX_CMPXCHG_DESIRED6891]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6893:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6892]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6893]], ptr [[DX_ATOMIC_EXPECTED_PTR6889]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6894:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6892]], 1
+// CHECK-NEXT: [[TMP3446:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6894]] to i32
+// CHECK-NEXT: store i32 [[TMP3446]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3447:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3448:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3447]], ptr [[DX_ATOMIC_EXPECTED_PTR6895]], align 8
+// CHECK-NEXT: store double [[TMP3448]], ptr [[DX_ATOMIC_DESIRED_PTR6896]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6898:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6895]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6899:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6896]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6900:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6898]], i64 [[DX_CMPXCHG_DESIRED6899]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6901:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6900]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6901]], ptr [[DX_ATOMIC_EXPECTED_PTR6897]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6902:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6900]], 1
+// CHECK-NEXT: [[TMP3449:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6902]] to i32
+// CHECK-NEXT: store i32 [[TMP3449]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3450:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3451:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3450]], ptr [[DX_ATOMIC_EXPECTED_PTR6903]], align 8
+// CHECK-NEXT: store double [[TMP3451]], ptr [[DX_ATOMIC_DESIRED_PTR6904]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6906:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6903]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6907:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6904]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6908:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6906]], i64 [[DX_CMPXCHG_DESIRED6907]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6909:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6908]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6909]], ptr [[DX_ATOMIC_EXPECTED_PTR6905]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6910:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6908]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6911:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6905]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6910]], label [[DX_ATOMIC_EXIT6912:%.*]], label [[DX_ATOMIC_CONT6913:%.*]]
+// CHECK: dx.atomic.cont6913:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6911]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6912]]
+// CHECK: dx.atomic.exit6912:
+// CHECK-NEXT: [[TMP3452:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6910]] to i32
+// CHECK-NEXT: store i32 [[TMP3452]], ptr [[IR]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP3453:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3454:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP3453]], ptr [[DX_ATOMIC_EXPECTED_PTR6914]], align 8
+// CHECK-NEXT: store double [[TMP3454]], ptr [[DX_ATOMIC_DESIRED_PTR6915]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED6917:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR6914]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6918:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR6915]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR6919:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED6917]], i64 [[DX_CMPXCHG_DESIRED6918]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV6920:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6919]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV6920]], ptr [[DX_ATOMIC_EXPECTED_PTR6916]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS6921:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR6919]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL6922:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR6916]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS6921]], label [[DX_ATOMIC_EXIT6923:%.*]], label [[DX_ATOMIC_CONT6924:%.*]]
+// CHECK: dx.atomic.cont6924:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL6922]], ptr [[DV]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT6923]]
+// CHECK: dx.atomic.exit6923:
+// CHECK-NEXT: [[TMP3455:%.*]] = sext i1 [[DX_CMPXCHG_SUCCESS6921]] to i32
+// CHECK-NEXT: store i32 [[TMP3455]], ptr [[IR]], align 4
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: ret void
//
@@ -25447,6 +33991,42 @@ double fail_dxevd() {
// CHECK-NEXT: [[CV:%.*]] = alloca i8, align 1
// CHECK-NEXT: [[CE:%.*]] = alloca i8, align 1
// CHECK-NEXT: [[CD:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR1:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR2:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR3:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR4:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR11:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR12:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR13:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR20:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR21:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR22:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR30:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR31:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR32:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR39:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR40:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR41:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR49:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR50:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR51:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR58:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR59:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR60:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR68:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR69:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR70:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR77:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR78:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR79:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR87:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR88:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR89:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR96:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_DESIRED_PTR97:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[CX_ATOMIC_EXPECTED_PTR98:%.*]] = alloca i8, align 1
// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[CE]], align 1
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP0]] monotonic, align 1
// CHECK-NEXT: store i8 [[TMP1]], ptr [[CV]], align 1
@@ -25455,186 +34035,264 @@ double fail_dxevd() {
// CHECK-NEXT: store i8 [[TMP3]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[CE]], align 1
// CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP4]], i8 [[TMP5]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i8, i1 } [[TMP6]], 0
-// CHECK-NEXT: store i8 [[TMP7]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP8]] monotonic, align 1
-// CHECK-NEXT: [[TMP10:%.*]] = icmp slt i8 [[TMP9]], [[TMP8]]
-// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i8 [[TMP8]], i8 [[TMP9]]
-// CHECK-NEXT: store i8 [[TMP11]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP12]] monotonic, align 1
-// CHECK-NEXT: [[TMP14:%.*]] = icmp sgt i8 [[TMP13]], [[TMP12]]
-// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i8 [[TMP12]], i8 [[TMP13]]
-// CHECK-NEXT: store i8 [[TMP15]], ptr [[CV]], align 1
+// CHECK-NEXT: store i8 [[TMP4]], ptr [[CX_ATOMIC_EXPECTED_PTR]], align 1
+// CHECK-NEXT: store i8 [[TMP5]], ptr [[CX_ATOMIC_DESIRED_PTR]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED]], i8 [[CX_CMPXCHG_DESIRED]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV]], ptr [[CX_ATOMIC_EXPECTED_PTR1]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR1]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP7:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP6]] monotonic, align 1
+// CHECK-NEXT: [[TMP8:%.*]] = icmp slt i8 [[TMP7]], [[TMP6]]
+// CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i8 [[TMP6]], i8 [[TMP7]]
+// CHECK-NEXT: store i8 [[TMP9]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP11:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP10]] monotonic, align 1
+// CHECK-NEXT: [[TMP12:%.*]] = icmp sgt i8 [[TMP11]], [[TMP10]]
+// CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i8 [[TMP10]], i8 [[TMP11]]
+// CHECK-NEXT: store i8 [[TMP13]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP15:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP14]], ptr [[CX_ATOMIC_EXPECTED_PTR2]], align 1
+// CHECK-NEXT: store i8 [[TMP15]], ptr [[CX_ATOMIC_DESIRED_PTR3]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED5:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR2]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED6:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR3]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR7:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED5]], i8 [[CX_CMPXCHG_DESIRED6]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV8:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR7]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV8]], ptr [[CX_ATOMIC_EXPECTED_PTR4]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS9:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR7]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL10:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR4]], align 1
+// CHECK-NEXT: [[CX_CAPTURE_CAPTURED:%.*]] = select i1 [[CX_CMPXCHG_SUCCESS9]], i8 [[TMP14]], i8 [[CX_CAPTURE_ACTUAL10]]
+// CHECK-NEXT: store i8 [[CX_CAPTURE_CAPTURED]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP16:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP17:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP16]], i8 [[TMP17]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i8, i1 } [[TMP18]], 0
-// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i8, i1 } [[TMP18]], 1
-// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i8 [[TMP16]], i8 [[TMP19]]
-// CHECK-NEXT: store i8 [[TMP21]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP17:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP16]] acq_rel, align 1
+// CHECK-NEXT: store i8 [[TMP17]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP18:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP19:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP18]] acq_rel, align 1
+// CHECK-NEXT: store i8 [[TMP19]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP21:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP20]], ptr [[CX_ATOMIC_EXPECTED_PTR11]], align 1
+// CHECK-NEXT: store i8 [[TMP21]], ptr [[CX_ATOMIC_DESIRED_PTR12]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED14:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR11]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED15:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR12]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR16:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED14]], i8 [[CX_CMPXCHG_DESIRED15]] acq_rel acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV17:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR16]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV17]], ptr [[CX_ATOMIC_EXPECTED_PTR13]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS18:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR16]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL19:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR13]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL19]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP22:%.*]] = load i8, ptr [[CE]], align 1
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP22]] acq_rel, align 1
-// CHECK-NEXT: store i8 [[TMP23]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP24]] acq_rel, align 1
+// CHECK-NEXT: [[TMP24:%.*]] = icmp slt i8 [[TMP23]], [[TMP22]]
+// CHECK-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], i8 [[TMP22]], i8 [[TMP23]]
// CHECK-NEXT: store i8 [[TMP25]], ptr [[CV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP26:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP27:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP26]], i8 [[TMP27]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i8, i1 } [[TMP28]], 0
+// CHECK-NEXT: [[TMP27:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP26]] acq_rel, align 1
+// CHECK-NEXT: [[TMP28:%.*]] = icmp sgt i8 [[TMP27]], [[TMP26]]
+// CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i8 [[TMP26]], i8 [[TMP27]]
// CHECK-NEXT: store i8 [[TMP29]], ptr [[CV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP30:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP30]] acq_rel, align 1
-// CHECK-NEXT: [[TMP32:%.*]] = icmp slt i8 [[TMP31]], [[TMP30]]
-// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i8 [[TMP30]], i8 [[TMP31]]
-// CHECK-NEXT: store i8 [[TMP33]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP31:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP30]], ptr [[CX_ATOMIC_EXPECTED_PTR20]], align 1
+// CHECK-NEXT: store i8 [[TMP31]], ptr [[CX_ATOMIC_DESIRED_PTR21]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED23:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR20]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED24:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR21]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR25:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED23]], i8 [[CX_CMPXCHG_DESIRED24]] acq_rel acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV26:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR25]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV26]], ptr [[CX_ATOMIC_EXPECTED_PTR22]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS27:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR25]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL28:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR22]], align 1
+// CHECK-NEXT: [[CX_CAPTURE_CAPTURED29:%.*]] = select i1 [[CX_CMPXCHG_SUCCESS27]], i8 [[TMP30]], i8 [[CX_CAPTURE_ACTUAL28]]
+// CHECK-NEXT: store i8 [[CX_CAPTURE_CAPTURED29]], ptr [[CV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP32:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP33:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP32]] acquire, align 1
+// CHECK-NEXT: store i8 [[TMP33]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP34:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP34]] acq_rel, align 1
-// CHECK-NEXT: [[TMP36:%.*]] = icmp sgt i8 [[TMP35]], [[TMP34]]
-// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i8 [[TMP34]], i8 [[TMP35]]
-// CHECK-NEXT: store i8 [[TMP37]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP34]] acquire, align 1
+// CHECK-NEXT: store i8 [[TMP35]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP36:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP37:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP36]], ptr [[CX_ATOMIC_EXPECTED_PTR30]], align 1
+// CHECK-NEXT: store i8 [[TMP37]], ptr [[CX_ATOMIC_DESIRED_PTR31]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED33:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR30]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED34:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR31]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR35:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED33]], i8 [[CX_CMPXCHG_DESIRED34]] acquire acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV36:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR35]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV36]], ptr [[CX_ATOMIC_EXPECTED_PTR32]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS37:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR35]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL38:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR32]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL38]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP38:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP39:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP38]], i8 [[TMP39]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i8, i1 } [[TMP40]], 0
-// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i8, i1 } [[TMP40]], 1
-// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i8 [[TMP38]], i8 [[TMP41]]
-// CHECK-NEXT: store i8 [[TMP43]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP44:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP44]] acquire, align 1
+// CHECK-NEXT: [[TMP39:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP38]] acquire, align 1
+// CHECK-NEXT: [[TMP40:%.*]] = icmp slt i8 [[TMP39]], [[TMP38]]
+// CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i8 [[TMP38]], i8 [[TMP39]]
+// CHECK-NEXT: store i8 [[TMP41]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP42:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP43:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP42]] acquire, align 1
+// CHECK-NEXT: [[TMP44:%.*]] = icmp sgt i8 [[TMP43]], [[TMP42]]
+// CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP44]], i8 [[TMP42]], i8 [[TMP43]]
// CHECK-NEXT: store i8 [[TMP45]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP46:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP46]] acquire, align 1
-// CHECK-NEXT: store i8 [[TMP47]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP47:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP46]], ptr [[CX_ATOMIC_EXPECTED_PTR39]], align 1
+// CHECK-NEXT: store i8 [[TMP47]], ptr [[CX_ATOMIC_DESIRED_PTR40]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED42:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR39]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED43:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR40]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR44:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED42]], i8 [[CX_CMPXCHG_DESIRED43]] acquire acquire, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV45:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR44]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV45]], ptr [[CX_ATOMIC_EXPECTED_PTR41]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS46:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR44]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL47:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR41]], align 1
+// CHECK-NEXT: [[CX_CAPTURE_CAPTURED48:%.*]] = select i1 [[CX_CMPXCHG_SUCCESS46]], i8 [[TMP46]], i8 [[CX_CAPTURE_ACTUAL47]]
+// CHECK-NEXT: store i8 [[CX_CAPTURE_CAPTURED48]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP48:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP49:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP48]], i8 [[TMP49]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i8, i1 } [[TMP50]], 0
+// CHECK-NEXT: [[TMP49:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP48]] monotonic, align 1
+// CHECK-NEXT: store i8 [[TMP49]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP50:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP51:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP50]] monotonic, align 1
// CHECK-NEXT: store i8 [[TMP51]], ptr [[CV]], align 1
// CHECK-NEXT: [[TMP52:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP52]] acquire, align 1
-// CHECK-NEXT: [[TMP54:%.*]] = icmp slt i8 [[TMP53]], [[TMP52]]
-// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i8 [[TMP52]], i8 [[TMP53]]
-// CHECK-NEXT: store i8 [[TMP55]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP56:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP56]] acquire, align 1
-// CHECK-NEXT: [[TMP58:%.*]] = icmp sgt i8 [[TMP57]], [[TMP56]]
-// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i8 [[TMP56]], i8 [[TMP57]]
-// CHECK-NEXT: store i8 [[TMP59]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP60:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP61:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP60]], i8 [[TMP61]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i8, i1 } [[TMP62]], 0
-// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i8, i1 } [[TMP62]], 1
-// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i8 [[TMP60]], i8 [[TMP63]]
+// CHECK-NEXT: [[TMP53:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP52]], ptr [[CX_ATOMIC_EXPECTED_PTR49]], align 1
+// CHECK-NEXT: store i8 [[TMP53]], ptr [[CX_ATOMIC_DESIRED_PTR50]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED52:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR49]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED53:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR50]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR54:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED52]], i8 [[CX_CMPXCHG_DESIRED53]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV55:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR54]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV55]], ptr [[CX_ATOMIC_EXPECTED_PTR51]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS56:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR54]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL57:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR51]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL57]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP54:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP55:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP54]] monotonic, align 1
+// CHECK-NEXT: [[TMP56:%.*]] = icmp slt i8 [[TMP55]], [[TMP54]]
+// CHECK-NEXT: [[TMP57:%.*]] = select i1 [[TMP56]], i8 [[TMP54]], i8 [[TMP55]]
+// CHECK-NEXT: store i8 [[TMP57]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP58:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP59:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP58]] monotonic, align 1
+// CHECK-NEXT: [[TMP60:%.*]] = icmp sgt i8 [[TMP59]], [[TMP58]]
+// CHECK-NEXT: [[TMP61:%.*]] = select i1 [[TMP60]], i8 [[TMP58]], i8 [[TMP59]]
+// CHECK-NEXT: store i8 [[TMP61]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP62:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP63:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP62]], ptr [[CX_ATOMIC_EXPECTED_PTR58]], align 1
+// CHECK-NEXT: store i8 [[TMP63]], ptr [[CX_ATOMIC_DESIRED_PTR59]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED61:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR58]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED62:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR59]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR63:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED61]], i8 [[CX_CMPXCHG_DESIRED62]] monotonic monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV64:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR63]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV64]], ptr [[CX_ATOMIC_EXPECTED_PTR60]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS65:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR63]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL66:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR60]], align 1
+// CHECK-NEXT: [[CX_CAPTURE_CAPTURED67:%.*]] = select i1 [[CX_CMPXCHG_SUCCESS65]], i8 [[TMP62]], i8 [[CX_CAPTURE_ACTUAL66]]
+// CHECK-NEXT: store i8 [[CX_CAPTURE_CAPTURED67]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP64:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP65:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP64]] release, align 1
// CHECK-NEXT: store i8 [[TMP65]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP66:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP66]] monotonic, align 1
+// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP66]] release, align 1
// CHECK-NEXT: store i8 [[TMP67]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP68:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP68]] monotonic, align 1
-// CHECK-NEXT: store i8 [[TMP69]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP69:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP68]], ptr [[CX_ATOMIC_EXPECTED_PTR68]], align 1
+// CHECK-NEXT: store i8 [[TMP69]], ptr [[CX_ATOMIC_DESIRED_PTR69]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED71:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR68]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED72:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR69]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR73:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED71]], i8 [[CX_CMPXCHG_DESIRED72]] release monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV74:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR73]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV74]], ptr [[CX_ATOMIC_EXPECTED_PTR70]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS75:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR73]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL76:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR70]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL76]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP70:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP71:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP70]], i8 [[TMP71]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i8, i1 } [[TMP72]], 0
+// CHECK-NEXT: [[TMP71:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP70]] release, align 1
+// CHECK-NEXT: [[TMP72:%.*]] = icmp slt i8 [[TMP71]], [[TMP70]]
+// CHECK-NEXT: [[TMP73:%.*]] = select i1 [[TMP72]], i8 [[TMP70]], i8 [[TMP71]]
// CHECK-NEXT: store i8 [[TMP73]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP74:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP74]] monotonic, align 1
-// CHECK-NEXT: [[TMP76:%.*]] = icmp slt i8 [[TMP75]], [[TMP74]]
+// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP74]] release, align 1
+// CHECK-NEXT: [[TMP76:%.*]] = icmp sgt i8 [[TMP75]], [[TMP74]]
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i8 [[TMP74]], i8 [[TMP75]]
// CHECK-NEXT: store i8 [[TMP77]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP78:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP78]] monotonic, align 1
-// CHECK-NEXT: [[TMP80:%.*]] = icmp sgt i8 [[TMP79]], [[TMP78]]
-// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i8 [[TMP78]], i8 [[TMP79]]
-// CHECK-NEXT: store i8 [[TMP81]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP82:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP83:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP82]], i8 [[TMP83]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i8, i1 } [[TMP84]], 0
-// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i8, i1 } [[TMP84]], 1
-// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i8 [[TMP82]], i8 [[TMP85]]
-// CHECK-NEXT: store i8 [[TMP87]], ptr [[CV]], align 1
-// CHECK-NEXT: [[TMP88:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP88]] release, align 1
-// CHECK-NEXT: store i8 [[TMP89]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP90:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP90]] release, align 1
-// CHECK-NEXT: store i8 [[TMP91]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP92:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP93:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP92]], i8 [[TMP93]] release monotonic, align 1
-// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i8, i1 } [[TMP94]], 0
-// CHECK-NEXT: store i8 [[TMP95]], ptr [[CV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP96:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP96]] release, align 1
-// CHECK-NEXT: [[TMP98:%.*]] = icmp slt i8 [[TMP97]], [[TMP96]]
-// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i8 [[TMP96]], i8 [[TMP97]]
-// CHECK-NEXT: store i8 [[TMP99]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP100:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP100]] release, align 1
-// CHECK-NEXT: [[TMP102:%.*]] = icmp sgt i8 [[TMP101]], [[TMP100]]
-// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i8 [[TMP100]], i8 [[TMP101]]
-// CHECK-NEXT: store i8 [[TMP103]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP104:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP105:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP104]], i8 [[TMP105]] release monotonic, align 1
-// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i8, i1 } [[TMP106]], 0
-// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i8, i1 } [[TMP106]], 1
-// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i8 [[TMP104]], i8 [[TMP107]]
-// CHECK-NEXT: store i8 [[TMP109]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP78:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP79:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP78]], ptr [[CX_ATOMIC_EXPECTED_PTR77]], align 1
+// CHECK-NEXT: store i8 [[TMP79]], ptr [[CX_ATOMIC_DESIRED_PTR78]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED80:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR77]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED81:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR78]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR82:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED80]], i8 [[CX_CMPXCHG_DESIRED81]] release monotonic, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV83:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR82]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV83]], ptr [[CX_ATOMIC_EXPECTED_PTR79]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS84:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR82]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL85:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR79]], align 1
+// CHECK-NEXT: [[CX_CAPTURE_CAPTURED86:%.*]] = select i1 [[CX_CMPXCHG_SUCCESS84]], i8 [[TMP78]], i8 [[CX_CAPTURE_ACTUAL85]]
+// CHECK-NEXT: store i8 [[CX_CAPTURE_CAPTURED86]], ptr [[CV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP110:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP110]] seq_cst, align 1
-// CHECK-NEXT: store i8 [[TMP111]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP80:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP81:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP80]] seq_cst, align 1
+// CHECK-NEXT: store i8 [[TMP81]], ptr [[CV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP112:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP112]] seq_cst, align 1
-// CHECK-NEXT: store i8 [[TMP113]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP82:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP83:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP82]] seq_cst, align 1
+// CHECK-NEXT: store i8 [[TMP83]], ptr [[CV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP114:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP115:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP114]], i8 [[TMP115]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i8, i1 } [[TMP116]], 0
-// CHECK-NEXT: store i8 [[TMP117]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP84:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP85:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP84]], ptr [[CX_ATOMIC_EXPECTED_PTR87]], align 1
+// CHECK-NEXT: store i8 [[TMP85]], ptr [[CX_ATOMIC_DESIRED_PTR88]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED90:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR87]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED91:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR88]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR92:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED90]], i8 [[CX_CMPXCHG_DESIRED91]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV93:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR92]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV93]], ptr [[CX_ATOMIC_EXPECTED_PTR89]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS94:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR92]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL95:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR89]], align 1
+// CHECK-NEXT: store i8 [[CX_CAPTURE_ACTUAL95]], ptr [[CV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP118:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP118]] seq_cst, align 1
-// CHECK-NEXT: [[TMP120:%.*]] = icmp slt i8 [[TMP119]], [[TMP118]]
-// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i8 [[TMP118]], i8 [[TMP119]]
-// CHECK-NEXT: store i8 [[TMP121]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP86:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw min ptr [[CX]], i8 [[TMP86]] seq_cst, align 1
+// CHECK-NEXT: [[TMP88:%.*]] = icmp slt i8 [[TMP87]], [[TMP86]]
+// CHECK-NEXT: [[TMP89:%.*]] = select i1 [[TMP88]], i8 [[TMP86]], i8 [[TMP87]]
+// CHECK-NEXT: store i8 [[TMP89]], ptr [[CV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP122:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP122]] seq_cst, align 1
-// CHECK-NEXT: [[TMP124:%.*]] = icmp sgt i8 [[TMP123]], [[TMP122]]
-// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i8 [[TMP122]], i8 [[TMP123]]
-// CHECK-NEXT: store i8 [[TMP125]], ptr [[CV]], align 1
+// CHECK-NEXT: [[TMP90:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw max ptr [[CX]], i8 [[TMP90]] seq_cst, align 1
+// CHECK-NEXT: [[TMP92:%.*]] = icmp sgt i8 [[TMP91]], [[TMP90]]
+// CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP92]], i8 [[TMP90]], i8 [[TMP91]]
+// CHECK-NEXT: store i8 [[TMP93]], ptr [[CV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP126:%.*]] = load i8, ptr [[CE]], align 1
-// CHECK-NEXT: [[TMP127:%.*]] = load i8, ptr [[CD]], align 1
-// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[CX]], i8 [[TMP126]], i8 [[TMP127]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i8, i1 } [[TMP128]], 0
-// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i8, i1 } [[TMP128]], 1
-// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i8 [[TMP126]], i8 [[TMP129]]
-// CHECK-NEXT: store i8 [[TMP131]], ptr [[CV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP132:%.*]] = load i8, ptr [[CV]], align 1
-// CHECK-NEXT: ret i8 [[TMP132]]
+// CHECK-NEXT: [[TMP94:%.*]] = load i8, ptr [[CE]], align 1
+// CHECK-NEXT: [[TMP95:%.*]] = load i8, ptr [[CD]], align 1
+// CHECK-NEXT: store i8 [[TMP94]], ptr [[CX_ATOMIC_EXPECTED_PTR96]], align 1
+// CHECK-NEXT: store i8 [[TMP95]], ptr [[CX_ATOMIC_DESIRED_PTR97]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_EXPECTED99:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR96]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_DESIRED100:%.*]] = load i8, ptr [[CX_ATOMIC_DESIRED_PTR97]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PAIR101:%.*]] = cmpxchg ptr [[CX]], i8 [[CX_CMPXCHG_EXPECTED99]], i8 [[CX_CMPXCHG_DESIRED100]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[CX_CMPXCHG_PREV102:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR101]], 0
+// CHECK-NEXT: store i8 [[CX_CMPXCHG_PREV102]], ptr [[CX_ATOMIC_EXPECTED_PTR98]], align 1
+// CHECK-NEXT: [[CX_CMPXCHG_SUCCESS103:%.*]] = extractvalue { i8, i1 } [[CX_CMPXCHG_PAIR101]], 1
+// CHECK-NEXT: [[CX_CAPTURE_ACTUAL104:%.*]] = load i8, ptr [[CX_ATOMIC_EXPECTED_PTR98]], align 1
+// CHECK-NEXT: [[CX_CAPTURE_CAPTURED105:%.*]] = select i1 [[CX_CMPXCHG_SUCCESS103]], i8 [[TMP94]], i8 [[CX_CAPTURE_ACTUAL104]]
+// CHECK-NEXT: store i8 [[CX_CAPTURE_CAPTURED105]], ptr [[CV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP96:%.*]] = load i8, ptr [[CV]], align 1
+// CHECK-NEXT: ret i8 [[TMP96]]
//
//
// CHECK-LABEL: @ucxevd(
@@ -25643,6 +34301,42 @@ double fail_dxevd() {
// CHECK-NEXT: [[UCV:%.*]] = alloca i8, align 1
// CHECK-NEXT: [[UCE:%.*]] = alloca i8, align 1
// CHECK-NEXT: [[UCD:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR1:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR2:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR3:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR4:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR11:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR12:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR13:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR20:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR21:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR22:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR30:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR31:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR32:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR39:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR40:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR41:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR49:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR50:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR51:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR58:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR59:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR60:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR68:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR69:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR70:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR77:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR78:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR79:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR87:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR88:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR89:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR96:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_DESIRED_PTR97:%.*]] = alloca i8, align 1
+// CHECK-NEXT: [[UCX_ATOMIC_EXPECTED_PTR98:%.*]] = alloca i8, align 1
// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[UCE]], align 1
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP0]] monotonic, align 1
// CHECK-NEXT: store i8 [[TMP1]], ptr [[UCV]], align 1
@@ -25651,186 +34345,264 @@ double fail_dxevd() {
// CHECK-NEXT: store i8 [[TMP3]], ptr [[UCV]], align 1
// CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[UCE]], align 1
// CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP4]], i8 [[TMP5]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i8, i1 } [[TMP6]], 0
-// CHECK-NEXT: store i8 [[TMP7]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP8]] monotonic, align 1
-// CHECK-NEXT: [[TMP10:%.*]] = icmp ult i8 [[TMP9]], [[TMP8]]
-// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i8 [[TMP8]], i8 [[TMP9]]
-// CHECK-NEXT: store i8 [[TMP11]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP12]] monotonic, align 1
-// CHECK-NEXT: [[TMP14:%.*]] = icmp ugt i8 [[TMP13]], [[TMP12]]
-// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i8 [[TMP12]], i8 [[TMP13]]
-// CHECK-NEXT: store i8 [[TMP15]], ptr [[UCV]], align 1
+// CHECK-NEXT: store i8 [[TMP4]], ptr [[UCX_ATOMIC_EXPECTED_PTR]], align 1
+// CHECK-NEXT: store i8 [[TMP5]], ptr [[UCX_ATOMIC_DESIRED_PTR]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED]], i8 [[UCX_CMPXCHG_DESIRED]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV]], ptr [[UCX_ATOMIC_EXPECTED_PTR1]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR1]], align 1
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP7:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP6]] monotonic, align 1
+// CHECK-NEXT: [[TMP8:%.*]] = icmp ult i8 [[TMP7]], [[TMP6]]
+// CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i8 [[TMP6]], i8 [[TMP7]]
+// CHECK-NEXT: store i8 [[TMP9]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP11:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP10]] monotonic, align 1
+// CHECK-NEXT: [[TMP12:%.*]] = icmp ugt i8 [[TMP11]], [[TMP10]]
+// CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i8 [[TMP10]], i8 [[TMP11]]
+// CHECK-NEXT: store i8 [[TMP13]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP14:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP15:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP14]], ptr [[UCX_ATOMIC_EXPECTED_PTR2]], align 1
+// CHECK-NEXT: store i8 [[TMP15]], ptr [[UCX_ATOMIC_DESIRED_PTR3]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED5:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR2]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED6:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR3]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR7:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED5]], i8 [[UCX_CMPXCHG_DESIRED6]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV8:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR7]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV8]], ptr [[UCX_ATOMIC_EXPECTED_PTR4]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS9:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR7]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL10:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR4]], align 1
+// CHECK-NEXT: [[UCX_CAPTURE_CAPTURED:%.*]] = select i1 [[UCX_CMPXCHG_SUCCESS9]], i8 [[TMP14]], i8 [[UCX_CAPTURE_ACTUAL10]]
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_CAPTURED]], ptr [[UCV]], align 1
// CHECK-NEXT: [[TMP16:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP17:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP16]], i8 [[TMP17]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i8, i1 } [[TMP18]], 0
-// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i8, i1 } [[TMP18]], 1
-// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i8 [[TMP16]], i8 [[TMP19]]
-// CHECK-NEXT: store i8 [[TMP21]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP17:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP16]] acq_rel, align 1
+// CHECK-NEXT: store i8 [[TMP17]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP18:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP19:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP18]] acq_rel, align 1
+// CHECK-NEXT: store i8 [[TMP19]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP21:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP20]], ptr [[UCX_ATOMIC_EXPECTED_PTR11]], align 1
+// CHECK-NEXT: store i8 [[TMP21]], ptr [[UCX_ATOMIC_DESIRED_PTR12]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED14:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR11]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED15:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR12]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR16:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED14]], i8 [[UCX_CMPXCHG_DESIRED15]] acq_rel acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV17:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR16]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV17]], ptr [[UCX_ATOMIC_EXPECTED_PTR13]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS18:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR16]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL19:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR13]], align 1
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL19]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP22:%.*]] = load i8, ptr [[UCE]], align 1
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP22]] acq_rel, align 1
-// CHECK-NEXT: store i8 [[TMP23]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP24]] acq_rel, align 1
+// CHECK-NEXT: [[TMP24:%.*]] = icmp ult i8 [[TMP23]], [[TMP22]]
+// CHECK-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], i8 [[TMP22]], i8 [[TMP23]]
// CHECK-NEXT: store i8 [[TMP25]], ptr [[UCV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP26:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP27:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP26]], i8 [[TMP27]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i8, i1 } [[TMP28]], 0
+// CHECK-NEXT: [[TMP27:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP26]] acq_rel, align 1
+// CHECK-NEXT: [[TMP28:%.*]] = icmp ugt i8 [[TMP27]], [[TMP26]]
+// CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i8 [[TMP26]], i8 [[TMP27]]
// CHECK-NEXT: store i8 [[TMP29]], ptr [[UCV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP30:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP30]] acq_rel, align 1
-// CHECK-NEXT: [[TMP32:%.*]] = icmp ult i8 [[TMP31]], [[TMP30]]
-// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i8 [[TMP30]], i8 [[TMP31]]
-// CHECK-NEXT: store i8 [[TMP33]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP31:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP30]], ptr [[UCX_ATOMIC_EXPECTED_PTR20]], align 1
+// CHECK-NEXT: store i8 [[TMP31]], ptr [[UCX_ATOMIC_DESIRED_PTR21]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED23:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR20]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED24:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR21]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR25:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED23]], i8 [[UCX_CMPXCHG_DESIRED24]] acq_rel acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV26:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR25]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV26]], ptr [[UCX_ATOMIC_EXPECTED_PTR22]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS27:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR25]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL28:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR22]], align 1
+// CHECK-NEXT: [[UCX_CAPTURE_CAPTURED29:%.*]] = select i1 [[UCX_CMPXCHG_SUCCESS27]], i8 [[TMP30]], i8 [[UCX_CAPTURE_ACTUAL28]]
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_CAPTURED29]], ptr [[UCV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP32:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP33:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP32]] acquire, align 1
+// CHECK-NEXT: store i8 [[TMP33]], ptr [[UCV]], align 1
// CHECK-NEXT: [[TMP34:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP34]] acq_rel, align 1
-// CHECK-NEXT: [[TMP36:%.*]] = icmp ugt i8 [[TMP35]], [[TMP34]]
-// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i8 [[TMP34]], i8 [[TMP35]]
-// CHECK-NEXT: store i8 [[TMP37]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP34]] acquire, align 1
+// CHECK-NEXT: store i8 [[TMP35]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP36:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP37:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP36]], ptr [[UCX_ATOMIC_EXPECTED_PTR30]], align 1
+// CHECK-NEXT: store i8 [[TMP37]], ptr [[UCX_ATOMIC_DESIRED_PTR31]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED33:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR30]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED34:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR31]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR35:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED33]], i8 [[UCX_CMPXCHG_DESIRED34]] acquire acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV36:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR35]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV36]], ptr [[UCX_ATOMIC_EXPECTED_PTR32]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS37:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR35]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL38:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR32]], align 1
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL38]], ptr [[UCV]], align 1
// CHECK-NEXT: [[TMP38:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP39:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP38]], i8 [[TMP39]] acq_rel acquire, align 1
-// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i8, i1 } [[TMP40]], 0
-// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i8, i1 } [[TMP40]], 1
-// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i8 [[TMP38]], i8 [[TMP41]]
-// CHECK-NEXT: store i8 [[TMP43]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP44:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP44]] acquire, align 1
+// CHECK-NEXT: [[TMP39:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP38]] acquire, align 1
+// CHECK-NEXT: [[TMP40:%.*]] = icmp ult i8 [[TMP39]], [[TMP38]]
+// CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i8 [[TMP38]], i8 [[TMP39]]
+// CHECK-NEXT: store i8 [[TMP41]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP42:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP43:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP42]] acquire, align 1
+// CHECK-NEXT: [[TMP44:%.*]] = icmp ugt i8 [[TMP43]], [[TMP42]]
+// CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP44]], i8 [[TMP42]], i8 [[TMP43]]
// CHECK-NEXT: store i8 [[TMP45]], ptr [[UCV]], align 1
// CHECK-NEXT: [[TMP46:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP46]] acquire, align 1
-// CHECK-NEXT: store i8 [[TMP47]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP47:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP46]], ptr [[UCX_ATOMIC_EXPECTED_PTR39]], align 1
+// CHECK-NEXT: store i8 [[TMP47]], ptr [[UCX_ATOMIC_DESIRED_PTR40]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED42:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR39]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED43:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR40]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR44:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED42]], i8 [[UCX_CMPXCHG_DESIRED43]] acquire acquire, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV45:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR44]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV45]], ptr [[UCX_ATOMIC_EXPECTED_PTR41]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS46:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR44]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL47:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR41]], align 1
+// CHECK-NEXT: [[UCX_CAPTURE_CAPTURED48:%.*]] = select i1 [[UCX_CMPXCHG_SUCCESS46]], i8 [[TMP46]], i8 [[UCX_CAPTURE_ACTUAL47]]
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_CAPTURED48]], ptr [[UCV]], align 1
// CHECK-NEXT: [[TMP48:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP49:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP48]], i8 [[TMP49]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i8, i1 } [[TMP50]], 0
+// CHECK-NEXT: [[TMP49:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP48]] monotonic, align 1
+// CHECK-NEXT: store i8 [[TMP49]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP50:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP51:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP50]] monotonic, align 1
// CHECK-NEXT: store i8 [[TMP51]], ptr [[UCV]], align 1
// CHECK-NEXT: [[TMP52:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP52]] acquire, align 1
-// CHECK-NEXT: [[TMP54:%.*]] = icmp ult i8 [[TMP53]], [[TMP52]]
-// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i8 [[TMP52]], i8 [[TMP53]]
-// CHECK-NEXT: store i8 [[TMP55]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP56:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP56]] acquire, align 1
-// CHECK-NEXT: [[TMP58:%.*]] = icmp ugt i8 [[TMP57]], [[TMP56]]
-// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i8 [[TMP56]], i8 [[TMP57]]
-// CHECK-NEXT: store i8 [[TMP59]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP60:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP61:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP60]], i8 [[TMP61]] acquire acquire, align 1
-// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i8, i1 } [[TMP62]], 0
-// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i8, i1 } [[TMP62]], 1
-// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i8 [[TMP60]], i8 [[TMP63]]
+// CHECK-NEXT: [[TMP53:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP52]], ptr [[UCX_ATOMIC_EXPECTED_PTR49]], align 1
+// CHECK-NEXT: store i8 [[TMP53]], ptr [[UCX_ATOMIC_DESIRED_PTR50]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED52:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR49]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED53:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR50]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR54:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED52]], i8 [[UCX_CMPXCHG_DESIRED53]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV55:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR54]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV55]], ptr [[UCX_ATOMIC_EXPECTED_PTR51]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS56:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR54]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL57:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR51]], align 1
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL57]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP54:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP55:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP54]] monotonic, align 1
+// CHECK-NEXT: [[TMP56:%.*]] = icmp ult i8 [[TMP55]], [[TMP54]]
+// CHECK-NEXT: [[TMP57:%.*]] = select i1 [[TMP56]], i8 [[TMP54]], i8 [[TMP55]]
+// CHECK-NEXT: store i8 [[TMP57]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP58:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP59:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP58]] monotonic, align 1
+// CHECK-NEXT: [[TMP60:%.*]] = icmp ugt i8 [[TMP59]], [[TMP58]]
+// CHECK-NEXT: [[TMP61:%.*]] = select i1 [[TMP60]], i8 [[TMP58]], i8 [[TMP59]]
+// CHECK-NEXT: store i8 [[TMP61]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP62:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP63:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP62]], ptr [[UCX_ATOMIC_EXPECTED_PTR58]], align 1
+// CHECK-NEXT: store i8 [[TMP63]], ptr [[UCX_ATOMIC_DESIRED_PTR59]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED61:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR58]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED62:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR59]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR63:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED61]], i8 [[UCX_CMPXCHG_DESIRED62]] monotonic monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV64:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR63]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV64]], ptr [[UCX_ATOMIC_EXPECTED_PTR60]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS65:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR63]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL66:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR60]], align 1
+// CHECK-NEXT: [[UCX_CAPTURE_CAPTURED67:%.*]] = select i1 [[UCX_CMPXCHG_SUCCESS65]], i8 [[TMP62]], i8 [[UCX_CAPTURE_ACTUAL66]]
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_CAPTURED67]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP64:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP65:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP64]] release, align 1
// CHECK-NEXT: store i8 [[TMP65]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP66:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP66]] monotonic, align 1
+// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP66]] release, align 1
// CHECK-NEXT: store i8 [[TMP67]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP68:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP68]] monotonic, align 1
-// CHECK-NEXT: store i8 [[TMP69]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP69:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP68]], ptr [[UCX_ATOMIC_EXPECTED_PTR68]], align 1
+// CHECK-NEXT: store i8 [[TMP69]], ptr [[UCX_ATOMIC_DESIRED_PTR69]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED71:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR68]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED72:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR69]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR73:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED71]], i8 [[UCX_CMPXCHG_DESIRED72]] release monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV74:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR73]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV74]], ptr [[UCX_ATOMIC_EXPECTED_PTR70]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS75:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR73]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL76:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR70]], align 1
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL76]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP70:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP71:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP70]], i8 [[TMP71]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i8, i1 } [[TMP72]], 0
+// CHECK-NEXT: [[TMP71:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP70]] release, align 1
+// CHECK-NEXT: [[TMP72:%.*]] = icmp ult i8 [[TMP71]], [[TMP70]]
+// CHECK-NEXT: [[TMP73:%.*]] = select i1 [[TMP72]], i8 [[TMP70]], i8 [[TMP71]]
// CHECK-NEXT: store i8 [[TMP73]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP74:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP74]] monotonic, align 1
-// CHECK-NEXT: [[TMP76:%.*]] = icmp ult i8 [[TMP75]], [[TMP74]]
+// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP74]] release, align 1
+// CHECK-NEXT: [[TMP76:%.*]] = icmp ugt i8 [[TMP75]], [[TMP74]]
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i8 [[TMP74]], i8 [[TMP75]]
// CHECK-NEXT: store i8 [[TMP77]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP78:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP78]] monotonic, align 1
-// CHECK-NEXT: [[TMP80:%.*]] = icmp ugt i8 [[TMP79]], [[TMP78]]
-// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i8 [[TMP78]], i8 [[TMP79]]
+// CHECK-NEXT: [[TMP79:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP78]], ptr [[UCX_ATOMIC_EXPECTED_PTR77]], align 1
+// CHECK-NEXT: store i8 [[TMP79]], ptr [[UCX_ATOMIC_DESIRED_PTR78]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED80:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR77]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED81:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR78]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR82:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED80]], i8 [[UCX_CMPXCHG_DESIRED81]] release monotonic, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV83:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR82]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV83]], ptr [[UCX_ATOMIC_EXPECTED_PTR79]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS84:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR82]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL85:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR79]], align 1
+// CHECK-NEXT: [[UCX_CAPTURE_CAPTURED86:%.*]] = select i1 [[UCX_CMPXCHG_SUCCESS84]], i8 [[TMP78]], i8 [[UCX_CAPTURE_ACTUAL85]]
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_CAPTURED86]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP80:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP81:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP80]] seq_cst, align 1
// CHECK-NEXT: store i8 [[TMP81]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP82:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP83:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP82]], i8 [[TMP83]] monotonic monotonic, align 1
-// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i8, i1 } [[TMP84]], 0
-// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i8, i1 } [[TMP84]], 1
-// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i8 [[TMP82]], i8 [[TMP85]]
-// CHECK-NEXT: store i8 [[TMP87]], ptr [[UCV]], align 1
-// CHECK-NEXT: [[TMP88:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP88]] release, align 1
-// CHECK-NEXT: store i8 [[TMP89]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP83:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP82]] seq_cst, align 1
+// CHECK-NEXT: store i8 [[TMP83]], ptr [[UCV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP90:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP90]] release, align 1
-// CHECK-NEXT: store i8 [[TMP91]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP84:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP85:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP84]], ptr [[UCX_ATOMIC_EXPECTED_PTR87]], align 1
+// CHECK-NEXT: store i8 [[TMP85]], ptr [[UCX_ATOMIC_DESIRED_PTR88]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED90:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR87]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED91:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR88]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR92:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED90]], i8 [[UCX_CMPXCHG_DESIRED91]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV93:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR92]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV93]], ptr [[UCX_ATOMIC_EXPECTED_PTR89]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS94:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR92]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL95:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR89]], align 1
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_ACTUAL95]], ptr [[UCV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP92:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP93:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP92]], i8 [[TMP93]] release monotonic, align 1
-// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i8, i1 } [[TMP94]], 0
-// CHECK-NEXT: store i8 [[TMP95]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP96:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP96]] release, align 1
-// CHECK-NEXT: [[TMP98:%.*]] = icmp ult i8 [[TMP97]], [[TMP96]]
-// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i8 [[TMP96]], i8 [[TMP97]]
-// CHECK-NEXT: store i8 [[TMP99]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP100:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP100]] release, align 1
-// CHECK-NEXT: [[TMP102:%.*]] = icmp ugt i8 [[TMP101]], [[TMP100]]
-// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i8 [[TMP100]], i8 [[TMP101]]
-// CHECK-NEXT: store i8 [[TMP103]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP104:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP105:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP104]], i8 [[TMP105]] release monotonic, align 1
-// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i8, i1 } [[TMP106]], 0
-// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i8, i1 } [[TMP106]], 1
-// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i8 [[TMP104]], i8 [[TMP107]]
-// CHECK-NEXT: store i8 [[TMP109]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP110:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP110]] seq_cst, align 1
-// CHECK-NEXT: store i8 [[TMP111]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP112:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP112]] seq_cst, align 1
-// CHECK-NEXT: store i8 [[TMP113]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP114:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP115:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP114]], i8 [[TMP115]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i8, i1 } [[TMP116]], 0
-// CHECK-NEXT: store i8 [[TMP117]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP118:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP118]] seq_cst, align 1
-// CHECK-NEXT: [[TMP120:%.*]] = icmp ult i8 [[TMP119]], [[TMP118]]
-// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i8 [[TMP118]], i8 [[TMP119]]
-// CHECK-NEXT: store i8 [[TMP121]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP86:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw umin ptr [[UCX]], i8 [[TMP86]] seq_cst, align 1
+// CHECK-NEXT: [[TMP88:%.*]] = icmp ult i8 [[TMP87]], [[TMP86]]
+// CHECK-NEXT: [[TMP89:%.*]] = select i1 [[TMP88]], i8 [[TMP86]], i8 [[TMP87]]
+// CHECK-NEXT: store i8 [[TMP89]], ptr [[UCV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP122:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP122]] seq_cst, align 1
-// CHECK-NEXT: [[TMP124:%.*]] = icmp ugt i8 [[TMP123]], [[TMP122]]
-// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i8 [[TMP122]], i8 [[TMP123]]
-// CHECK-NEXT: store i8 [[TMP125]], ptr [[UCV]], align 1
+// CHECK-NEXT: [[TMP90:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw umax ptr [[UCX]], i8 [[TMP90]] seq_cst, align 1
+// CHECK-NEXT: [[TMP92:%.*]] = icmp ugt i8 [[TMP91]], [[TMP90]]
+// CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP92]], i8 [[TMP90]], i8 [[TMP91]]
+// CHECK-NEXT: store i8 [[TMP93]], ptr [[UCV]], align 1
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP126:%.*]] = load i8, ptr [[UCE]], align 1
-// CHECK-NEXT: [[TMP127:%.*]] = load i8, ptr [[UCD]], align 1
-// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[UCX]], i8 [[TMP126]], i8 [[TMP127]] seq_cst seq_cst, align 1
-// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i8, i1 } [[TMP128]], 0
-// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i8, i1 } [[TMP128]], 1
-// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i8 [[TMP126]], i8 [[TMP129]]
-// CHECK-NEXT: store i8 [[TMP131]], ptr [[UCV]], align 1
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP132:%.*]] = load i8, ptr [[UCV]], align 1
-// CHECK-NEXT: ret i8 [[TMP132]]
+// CHECK-NEXT: [[TMP94:%.*]] = load i8, ptr [[UCE]], align 1
+// CHECK-NEXT: [[TMP95:%.*]] = load i8, ptr [[UCD]], align 1
+// CHECK-NEXT: store i8 [[TMP94]], ptr [[UCX_ATOMIC_EXPECTED_PTR96]], align 1
+// CHECK-NEXT: store i8 [[TMP95]], ptr [[UCX_ATOMIC_DESIRED_PTR97]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_EXPECTED99:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR96]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_DESIRED100:%.*]] = load i8, ptr [[UCX_ATOMIC_DESIRED_PTR97]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PAIR101:%.*]] = cmpxchg ptr [[UCX]], i8 [[UCX_CMPXCHG_EXPECTED99]], i8 [[UCX_CMPXCHG_DESIRED100]] seq_cst seq_cst, align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_PREV102:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR101]], 0
+// CHECK-NEXT: store i8 [[UCX_CMPXCHG_PREV102]], ptr [[UCX_ATOMIC_EXPECTED_PTR98]], align 1
+// CHECK-NEXT: [[UCX_CMPXCHG_SUCCESS103:%.*]] = extractvalue { i8, i1 } [[UCX_CMPXCHG_PAIR101]], 1
+// CHECK-NEXT: [[UCX_CAPTURE_ACTUAL104:%.*]] = load i8, ptr [[UCX_ATOMIC_EXPECTED_PTR98]], align 1
+// CHECK-NEXT: [[UCX_CAPTURE_CAPTURED105:%.*]] = select i1 [[UCX_CMPXCHG_SUCCESS103]], i8 [[TMP94]], i8 [[UCX_CAPTURE_ACTUAL104]]
+// CHECK-NEXT: store i8 [[UCX_CAPTURE_CAPTURED105]], ptr [[UCV]], align 1
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP96:%.*]] = load i8, ptr [[UCV]], align 1
+// CHECK-NEXT: ret i8 [[TMP96]]
//
//
// CHECK-LABEL: @sxevd(
@@ -25839,6 +34611,42 @@ double fail_dxevd() {
// CHECK-NEXT: [[SV:%.*]] = alloca i16, align 2
// CHECK-NEXT: [[SE:%.*]] = alloca i16, align 2
// CHECK-NEXT: [[SD:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR1:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR2:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR3:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR4:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR11:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR12:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR13:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR20:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR21:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR22:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR30:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR31:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR32:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR39:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR40:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR41:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR49:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR50:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR51:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR58:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR59:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR60:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR68:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR69:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR70:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR77:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR78:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR79:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR87:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR88:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR89:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR96:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_DESIRED_PTR97:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[SX_ATOMIC_EXPECTED_PTR98:%.*]] = alloca i16, align 2
// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[SE]], align 2
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP0]] monotonic, align 2
// CHECK-NEXT: store i16 [[TMP1]], ptr [[SV]], align 2
@@ -25847,186 +34655,264 @@ double fail_dxevd() {
// CHECK-NEXT: store i16 [[TMP3]], ptr [[SV]], align 2
// CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr [[SE]], align 2
// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP4]], i16 [[TMP5]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i16, i1 } [[TMP6]], 0
-// CHECK-NEXT: store i16 [[TMP7]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP8:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP8]] monotonic, align 2
-// CHECK-NEXT: [[TMP10:%.*]] = icmp slt i16 [[TMP9]], [[TMP8]]
-// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i16 [[TMP8]], i16 [[TMP9]]
-// CHECK-NEXT: store i16 [[TMP11]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP12:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP12]] monotonic, align 2
-// CHECK-NEXT: [[TMP14:%.*]] = icmp sgt i16 [[TMP13]], [[TMP12]]
-// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i16 [[TMP12]], i16 [[TMP13]]
-// CHECK-NEXT: store i16 [[TMP15]], ptr [[SV]], align 2
+// CHECK-NEXT: store i16 [[TMP4]], ptr [[SX_ATOMIC_EXPECTED_PTR]], align 2
+// CHECK-NEXT: store i16 [[TMP5]], ptr [[SX_ATOMIC_DESIRED_PTR]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED]], i16 [[SX_CMPXCHG_DESIRED]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV]], ptr [[SX_ATOMIC_EXPECTED_PTR1]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR1]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP7:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP6]] monotonic, align 2
+// CHECK-NEXT: [[TMP8:%.*]] = icmp slt i16 [[TMP7]], [[TMP6]]
+// CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i16 [[TMP6]], i16 [[TMP7]]
+// CHECK-NEXT: store i16 [[TMP9]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP10:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP11:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP10]] monotonic, align 2
+// CHECK-NEXT: [[TMP12:%.*]] = icmp sgt i16 [[TMP11]], [[TMP10]]
+// CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i16 [[TMP10]], i16 [[TMP11]]
+// CHECK-NEXT: store i16 [[TMP13]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP14:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP15:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP14]], ptr [[SX_ATOMIC_EXPECTED_PTR2]], align 2
+// CHECK-NEXT: store i16 [[TMP15]], ptr [[SX_ATOMIC_DESIRED_PTR3]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED5:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR2]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED6:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR3]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR7:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED5]], i16 [[SX_CMPXCHG_DESIRED6]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV8:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR7]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV8]], ptr [[SX_ATOMIC_EXPECTED_PTR4]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS9:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR7]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL10:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR4]], align 2
+// CHECK-NEXT: [[SX_CAPTURE_CAPTURED:%.*]] = select i1 [[SX_CMPXCHG_SUCCESS9]], i16 [[TMP14]], i16 [[SX_CAPTURE_ACTUAL10]]
+// CHECK-NEXT: store i16 [[SX_CAPTURE_CAPTURED]], ptr [[SV]], align 2
// CHECK-NEXT: [[TMP16:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP17:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP16]], i16 [[TMP17]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i16, i1 } [[TMP18]], 0
-// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i16, i1 } [[TMP18]], 1
-// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i16 [[TMP16]], i16 [[TMP19]]
-// CHECK-NEXT: store i16 [[TMP21]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP17:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP16]] acq_rel, align 2
+// CHECK-NEXT: store i16 [[TMP17]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP18:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP19:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP18]] acq_rel, align 2
+// CHECK-NEXT: store i16 [[TMP19]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP20:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP21:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP20]], ptr [[SX_ATOMIC_EXPECTED_PTR11]], align 2
+// CHECK-NEXT: store i16 [[TMP21]], ptr [[SX_ATOMIC_DESIRED_PTR12]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED14:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR11]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED15:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR12]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR16:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED14]], i16 [[SX_CMPXCHG_DESIRED15]] acq_rel acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV17:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR16]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV17]], ptr [[SX_ATOMIC_EXPECTED_PTR13]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS18:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR16]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL19:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR13]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL19]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP22:%.*]] = load i16, ptr [[SE]], align 2
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP22]] acq_rel, align 2
-// CHECK-NEXT: store i16 [[TMP23]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP24:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP24]] acq_rel, align 2
+// CHECK-NEXT: [[TMP24:%.*]] = icmp slt i16 [[TMP23]], [[TMP22]]
+// CHECK-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], i16 [[TMP22]], i16 [[TMP23]]
// CHECK-NEXT: store i16 [[TMP25]], ptr [[SV]], align 2
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP26:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP27:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP26]], i16 [[TMP27]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i16, i1 } [[TMP28]], 0
+// CHECK-NEXT: [[TMP27:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP26]] acq_rel, align 2
+// CHECK-NEXT: [[TMP28:%.*]] = icmp sgt i16 [[TMP27]], [[TMP26]]
+// CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i16 [[TMP26]], i16 [[TMP27]]
// CHECK-NEXT: store i16 [[TMP29]], ptr [[SV]], align 2
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP30:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP30]] acq_rel, align 2
-// CHECK-NEXT: [[TMP32:%.*]] = icmp slt i16 [[TMP31]], [[TMP30]]
-// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i16 [[TMP30]], i16 [[TMP31]]
+// CHECK-NEXT: [[TMP31:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP30]], ptr [[SX_ATOMIC_EXPECTED_PTR20]], align 2
+// CHECK-NEXT: store i16 [[TMP31]], ptr [[SX_ATOMIC_DESIRED_PTR21]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED23:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR20]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED24:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR21]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR25:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED23]], i16 [[SX_CMPXCHG_DESIRED24]] acq_rel acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV26:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR25]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV26]], ptr [[SX_ATOMIC_EXPECTED_PTR22]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS27:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR25]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL28:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR22]], align 2
+// CHECK-NEXT: [[SX_CAPTURE_CAPTURED29:%.*]] = select i1 [[SX_CMPXCHG_SUCCESS27]], i16 [[TMP30]], i16 [[SX_CAPTURE_ACTUAL28]]
+// CHECK-NEXT: store i16 [[SX_CAPTURE_CAPTURED29]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP32:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP33:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP32]] acquire, align 2
// CHECK-NEXT: store i16 [[TMP33]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP34:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP34]] acq_rel, align 2
-// CHECK-NEXT: [[TMP36:%.*]] = icmp sgt i16 [[TMP35]], [[TMP34]]
-// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i16 [[TMP34]], i16 [[TMP35]]
-// CHECK-NEXT: store i16 [[TMP37]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP34]] acquire, align 2
+// CHECK-NEXT: store i16 [[TMP35]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP36:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP37:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP36]], ptr [[SX_ATOMIC_EXPECTED_PTR30]], align 2
+// CHECK-NEXT: store i16 [[TMP37]], ptr [[SX_ATOMIC_DESIRED_PTR31]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED33:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR30]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED34:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR31]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR35:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED33]], i16 [[SX_CMPXCHG_DESIRED34]] acquire acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV36:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR35]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV36]], ptr [[SX_ATOMIC_EXPECTED_PTR32]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS37:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR35]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL38:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR32]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL38]], ptr [[SV]], align 2
// CHECK-NEXT: [[TMP38:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP39:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP38]], i16 [[TMP39]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i16, i1 } [[TMP40]], 0
-// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i16, i1 } [[TMP40]], 1
-// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i16 [[TMP38]], i16 [[TMP41]]
-// CHECK-NEXT: store i16 [[TMP43]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP44:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP44]] acquire, align 2
+// CHECK-NEXT: [[TMP39:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP38]] acquire, align 2
+// CHECK-NEXT: [[TMP40:%.*]] = icmp slt i16 [[TMP39]], [[TMP38]]
+// CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i16 [[TMP38]], i16 [[TMP39]]
+// CHECK-NEXT: store i16 [[TMP41]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP42:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP43:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP42]] acquire, align 2
+// CHECK-NEXT: [[TMP44:%.*]] = icmp sgt i16 [[TMP43]], [[TMP42]]
+// CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP44]], i16 [[TMP42]], i16 [[TMP43]]
// CHECK-NEXT: store i16 [[TMP45]], ptr [[SV]], align 2
// CHECK-NEXT: [[TMP46:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP46]] acquire, align 2
-// CHECK-NEXT: store i16 [[TMP47]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP47:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP46]], ptr [[SX_ATOMIC_EXPECTED_PTR39]], align 2
+// CHECK-NEXT: store i16 [[TMP47]], ptr [[SX_ATOMIC_DESIRED_PTR40]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED42:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR39]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED43:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR40]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR44:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED42]], i16 [[SX_CMPXCHG_DESIRED43]] acquire acquire, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV45:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR44]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV45]], ptr [[SX_ATOMIC_EXPECTED_PTR41]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS46:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR44]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL47:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR41]], align 2
+// CHECK-NEXT: [[SX_CAPTURE_CAPTURED48:%.*]] = select i1 [[SX_CMPXCHG_SUCCESS46]], i16 [[TMP46]], i16 [[SX_CAPTURE_ACTUAL47]]
+// CHECK-NEXT: store i16 [[SX_CAPTURE_CAPTURED48]], ptr [[SV]], align 2
// CHECK-NEXT: [[TMP48:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP49:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP48]], i16 [[TMP49]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i16, i1 } [[TMP50]], 0
+// CHECK-NEXT: [[TMP49:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP48]] monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP49]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP50:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP51:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP50]] monotonic, align 2
// CHECK-NEXT: store i16 [[TMP51]], ptr [[SV]], align 2
// CHECK-NEXT: [[TMP52:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP52]] acquire, align 2
-// CHECK-NEXT: [[TMP54:%.*]] = icmp slt i16 [[TMP53]], [[TMP52]]
-// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i16 [[TMP52]], i16 [[TMP53]]
-// CHECK-NEXT: store i16 [[TMP55]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP56:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP56]] acquire, align 2
-// CHECK-NEXT: [[TMP58:%.*]] = icmp sgt i16 [[TMP57]], [[TMP56]]
-// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i16 [[TMP56]], i16 [[TMP57]]
-// CHECK-NEXT: store i16 [[TMP59]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP60:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP61:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP60]], i16 [[TMP61]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i16, i1 } [[TMP62]], 0
-// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i16, i1 } [[TMP62]], 1
-// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i16 [[TMP60]], i16 [[TMP63]]
+// CHECK-NEXT: [[TMP53:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP52]], ptr [[SX_ATOMIC_EXPECTED_PTR49]], align 2
+// CHECK-NEXT: store i16 [[TMP53]], ptr [[SX_ATOMIC_DESIRED_PTR50]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED52:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR49]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED53:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR50]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR54:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED52]], i16 [[SX_CMPXCHG_DESIRED53]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV55:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR54]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV55]], ptr [[SX_ATOMIC_EXPECTED_PTR51]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS56:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR54]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL57:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR51]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL57]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP54:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP55:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP54]] monotonic, align 2
+// CHECK-NEXT: [[TMP56:%.*]] = icmp slt i16 [[TMP55]], [[TMP54]]
+// CHECK-NEXT: [[TMP57:%.*]] = select i1 [[TMP56]], i16 [[TMP54]], i16 [[TMP55]]
+// CHECK-NEXT: store i16 [[TMP57]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP58:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP59:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP58]] monotonic, align 2
+// CHECK-NEXT: [[TMP60:%.*]] = icmp sgt i16 [[TMP59]], [[TMP58]]
+// CHECK-NEXT: [[TMP61:%.*]] = select i1 [[TMP60]], i16 [[TMP58]], i16 [[TMP59]]
+// CHECK-NEXT: store i16 [[TMP61]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP62:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP63:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP62]], ptr [[SX_ATOMIC_EXPECTED_PTR58]], align 2
+// CHECK-NEXT: store i16 [[TMP63]], ptr [[SX_ATOMIC_DESIRED_PTR59]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED61:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR58]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED62:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR59]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR63:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED61]], i16 [[SX_CMPXCHG_DESIRED62]] monotonic monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV64:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR63]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV64]], ptr [[SX_ATOMIC_EXPECTED_PTR60]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS65:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR63]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL66:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR60]], align 2
+// CHECK-NEXT: [[SX_CAPTURE_CAPTURED67:%.*]] = select i1 [[SX_CMPXCHG_SUCCESS65]], i16 [[TMP62]], i16 [[SX_CAPTURE_ACTUAL66]]
+// CHECK-NEXT: store i16 [[SX_CAPTURE_CAPTURED67]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP64:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP65:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP64]] release, align 2
// CHECK-NEXT: store i16 [[TMP65]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP66:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP66]] monotonic, align 2
+// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP66]] release, align 2
// CHECK-NEXT: store i16 [[TMP67]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP68:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP68]] monotonic, align 2
-// CHECK-NEXT: store i16 [[TMP69]], ptr [[SV]], align 2
+// CHECK-NEXT: [[TMP69:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP68]], ptr [[SX_ATOMIC_EXPECTED_PTR68]], align 2
+// CHECK-NEXT: store i16 [[TMP69]], ptr [[SX_ATOMIC_DESIRED_PTR69]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED71:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR68]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED72:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR69]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR73:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED71]], i16 [[SX_CMPXCHG_DESIRED72]] release monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV74:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR73]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV74]], ptr [[SX_ATOMIC_EXPECTED_PTR70]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS75:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR73]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL76:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR70]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL76]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP70:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP71:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP70]], i16 [[TMP71]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i16, i1 } [[TMP72]], 0
+// CHECK-NEXT: [[TMP71:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP70]] release, align 2
+// CHECK-NEXT: [[TMP72:%.*]] = icmp slt i16 [[TMP71]], [[TMP70]]
+// CHECK-NEXT: [[TMP73:%.*]] = select i1 [[TMP72]], i16 [[TMP70]], i16 [[TMP71]]
// CHECK-NEXT: store i16 [[TMP73]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP74:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP74]] monotonic, align 2
-// CHECK-NEXT: [[TMP76:%.*]] = icmp slt i16 [[TMP75]], [[TMP74]]
+// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP74]] release, align 2
+// CHECK-NEXT: [[TMP76:%.*]] = icmp sgt i16 [[TMP75]], [[TMP74]]
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i16 [[TMP74]], i16 [[TMP75]]
// CHECK-NEXT: store i16 [[TMP77]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP78:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP78]] monotonic, align 2
-// CHECK-NEXT: [[TMP80:%.*]] = icmp sgt i16 [[TMP79]], [[TMP78]]
-// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i16 [[TMP78]], i16 [[TMP79]]
+// CHECK-NEXT: [[TMP79:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP78]], ptr [[SX_ATOMIC_EXPECTED_PTR77]], align 2
+// CHECK-NEXT: store i16 [[TMP79]], ptr [[SX_ATOMIC_DESIRED_PTR78]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED80:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR77]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED81:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR78]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR82:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED80]], i16 [[SX_CMPXCHG_DESIRED81]] release monotonic, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV83:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR82]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV83]], ptr [[SX_ATOMIC_EXPECTED_PTR79]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS84:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR82]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL85:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR79]], align 2
+// CHECK-NEXT: [[SX_CAPTURE_CAPTURED86:%.*]] = select i1 [[SX_CMPXCHG_SUCCESS84]], i16 [[TMP78]], i16 [[SX_CAPTURE_ACTUAL85]]
+// CHECK-NEXT: store i16 [[SX_CAPTURE_CAPTURED86]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP80:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP81:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP80]] seq_cst, align 2
// CHECK-NEXT: store i16 [[TMP81]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP82:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP83:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP82]], i16 [[TMP83]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i16, i1 } [[TMP84]], 0
-// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i16, i1 } [[TMP84]], 1
-// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i16 [[TMP82]], i16 [[TMP85]]
-// CHECK-NEXT: store i16 [[TMP87]], ptr [[SV]], align 2
-// CHECK-NEXT: [[TMP88:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP88]] release, align 2
+// CHECK-NEXT: [[TMP83:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP82]] seq_cst, align 2
+// CHECK-NEXT: store i16 [[TMP83]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP84:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP85:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP84]], ptr [[SX_ATOMIC_EXPECTED_PTR87]], align 2
+// CHECK-NEXT: store i16 [[TMP85]], ptr [[SX_ATOMIC_DESIRED_PTR88]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED90:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR87]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED91:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR88]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR92:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED90]], i16 [[SX_CMPXCHG_DESIRED91]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV93:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR92]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV93]], ptr [[SX_ATOMIC_EXPECTED_PTR89]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS94:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR92]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL95:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR89]], align 2
+// CHECK-NEXT: store i16 [[SX_CAPTURE_ACTUAL95]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP86:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP86]] seq_cst, align 2
+// CHECK-NEXT: [[TMP88:%.*]] = icmp slt i16 [[TMP87]], [[TMP86]]
+// CHECK-NEXT: [[TMP89:%.*]] = select i1 [[TMP88]], i16 [[TMP86]], i16 [[TMP87]]
// CHECK-NEXT: store i16 [[TMP89]], ptr [[SV]], align 2
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP90:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP90]] release, align 2
-// CHECK-NEXT: store i16 [[TMP91]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP92:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP93:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP92]], i16 [[TMP93]] release monotonic, align 2
-// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i16, i1 } [[TMP94]], 0
-// CHECK-NEXT: store i16 [[TMP95]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP96:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP96]] release, align 2
-// CHECK-NEXT: [[TMP98:%.*]] = icmp slt i16 [[TMP97]], [[TMP96]]
-// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i16 [[TMP96]], i16 [[TMP97]]
-// CHECK-NEXT: store i16 [[TMP99]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP100:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP100]] release, align 2
-// CHECK-NEXT: [[TMP102:%.*]] = icmp sgt i16 [[TMP101]], [[TMP100]]
-// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i16 [[TMP100]], i16 [[TMP101]]
-// CHECK-NEXT: store i16 [[TMP103]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP104:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP105:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP104]], i16 [[TMP105]] release monotonic, align 2
-// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i16, i1 } [[TMP106]], 0
-// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i16, i1 } [[TMP106]], 1
-// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i16 [[TMP104]], i16 [[TMP107]]
-// CHECK-NEXT: store i16 [[TMP109]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP110:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP110]] seq_cst, align 2
-// CHECK-NEXT: store i16 [[TMP111]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP112:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP112]] seq_cst, align 2
-// CHECK-NEXT: store i16 [[TMP113]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP114:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP115:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP114]], i16 [[TMP115]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i16, i1 } [[TMP116]], 0
-// CHECK-NEXT: store i16 [[TMP117]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP118:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw min ptr [[SX]], i16 [[TMP118]] seq_cst, align 2
-// CHECK-NEXT: [[TMP120:%.*]] = icmp slt i16 [[TMP119]], [[TMP118]]
-// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i16 [[TMP118]], i16 [[TMP119]]
-// CHECK-NEXT: store i16 [[TMP121]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP122:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP122]] seq_cst, align 2
-// CHECK-NEXT: [[TMP124:%.*]] = icmp sgt i16 [[TMP123]], [[TMP122]]
-// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i16 [[TMP122]], i16 [[TMP123]]
-// CHECK-NEXT: store i16 [[TMP125]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP126:%.*]] = load i16, ptr [[SE]], align 2
-// CHECK-NEXT: [[TMP127:%.*]] = load i16, ptr [[SD]], align 2
-// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[SX]], i16 [[TMP126]], i16 [[TMP127]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i16, i1 } [[TMP128]], 0
-// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i16, i1 } [[TMP128]], 1
-// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i16 [[TMP126]], i16 [[TMP129]]
-// CHECK-NEXT: store i16 [[TMP131]], ptr [[SV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP132:%.*]] = load i16, ptr [[SV]], align 2
-// CHECK-NEXT: ret i16 [[TMP132]]
+// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw max ptr [[SX]], i16 [[TMP90]] seq_cst, align 2
+// CHECK-NEXT: [[TMP92:%.*]] = icmp sgt i16 [[TMP91]], [[TMP90]]
+// CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP92]], i16 [[TMP90]], i16 [[TMP91]]
+// CHECK-NEXT: store i16 [[TMP93]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP94:%.*]] = load i16, ptr [[SE]], align 2
+// CHECK-NEXT: [[TMP95:%.*]] = load i16, ptr [[SD]], align 2
+// CHECK-NEXT: store i16 [[TMP94]], ptr [[SX_ATOMIC_EXPECTED_PTR96]], align 2
+// CHECK-NEXT: store i16 [[TMP95]], ptr [[SX_ATOMIC_DESIRED_PTR97]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_EXPECTED99:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR96]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_DESIRED100:%.*]] = load i16, ptr [[SX_ATOMIC_DESIRED_PTR97]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PAIR101:%.*]] = cmpxchg ptr [[SX]], i16 [[SX_CMPXCHG_EXPECTED99]], i16 [[SX_CMPXCHG_DESIRED100]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[SX_CMPXCHG_PREV102:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR101]], 0
+// CHECK-NEXT: store i16 [[SX_CMPXCHG_PREV102]], ptr [[SX_ATOMIC_EXPECTED_PTR98]], align 2
+// CHECK-NEXT: [[SX_CMPXCHG_SUCCESS103:%.*]] = extractvalue { i16, i1 } [[SX_CMPXCHG_PAIR101]], 1
+// CHECK-NEXT: [[SX_CAPTURE_ACTUAL104:%.*]] = load i16, ptr [[SX_ATOMIC_EXPECTED_PTR98]], align 2
+// CHECK-NEXT: [[SX_CAPTURE_CAPTURED105:%.*]] = select i1 [[SX_CMPXCHG_SUCCESS103]], i16 [[TMP94]], i16 [[SX_CAPTURE_ACTUAL104]]
+// CHECK-NEXT: store i16 [[SX_CAPTURE_CAPTURED105]], ptr [[SV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP96:%.*]] = load i16, ptr [[SV]], align 2
+// CHECK-NEXT: ret i16 [[TMP96]]
//
//
// CHECK-LABEL: @usxevd(
@@ -26035,6 +34921,42 @@ double fail_dxevd() {
// CHECK-NEXT: [[USV:%.*]] = alloca i16, align 2
// CHECK-NEXT: [[USE:%.*]] = alloca i16, align 2
// CHECK-NEXT: [[USD:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR1:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR2:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR3:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR4:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR11:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR12:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR13:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR20:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR21:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR22:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR30:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR31:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR32:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR39:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR40:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR41:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR49:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR50:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR51:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR58:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR59:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR60:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR68:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR69:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR70:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR77:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR78:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR79:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR87:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR88:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR89:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR96:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_DESIRED_PTR97:%.*]] = alloca i16, align 2
+// CHECK-NEXT: [[USX_ATOMIC_EXPECTED_PTR98:%.*]] = alloca i16, align 2
// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[USE]], align 2
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP0]] monotonic, align 2
// CHECK-NEXT: store i16 [[TMP1]], ptr [[USV]], align 2
@@ -26043,186 +34965,264 @@ double fail_dxevd() {
// CHECK-NEXT: store i16 [[TMP3]], ptr [[USV]], align 2
// CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr [[USE]], align 2
// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP4]], i16 [[TMP5]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i16, i1 } [[TMP6]], 0
-// CHECK-NEXT: store i16 [[TMP7]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP8:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP8]] monotonic, align 2
-// CHECK-NEXT: [[TMP10:%.*]] = icmp ult i16 [[TMP9]], [[TMP8]]
-// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i16 [[TMP8]], i16 [[TMP9]]
-// CHECK-NEXT: store i16 [[TMP11]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP12:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP12]] monotonic, align 2
-// CHECK-NEXT: [[TMP14:%.*]] = icmp ugt i16 [[TMP13]], [[TMP12]]
-// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i16 [[TMP12]], i16 [[TMP13]]
-// CHECK-NEXT: store i16 [[TMP15]], ptr [[USV]], align 2
+// CHECK-NEXT: store i16 [[TMP4]], ptr [[USX_ATOMIC_EXPECTED_PTR]], align 2
+// CHECK-NEXT: store i16 [[TMP5]], ptr [[USX_ATOMIC_DESIRED_PTR]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED]], i16 [[USX_CMPXCHG_DESIRED]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV]], ptr [[USX_ATOMIC_EXPECTED_PTR1]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR1]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP7:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP6]] monotonic, align 2
+// CHECK-NEXT: [[TMP8:%.*]] = icmp ult i16 [[TMP7]], [[TMP6]]
+// CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i16 [[TMP6]], i16 [[TMP7]]
+// CHECK-NEXT: store i16 [[TMP9]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP10:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP11:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP10]] monotonic, align 2
+// CHECK-NEXT: [[TMP12:%.*]] = icmp ugt i16 [[TMP11]], [[TMP10]]
+// CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i16 [[TMP10]], i16 [[TMP11]]
+// CHECK-NEXT: store i16 [[TMP13]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP14:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP15:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP14]], ptr [[USX_ATOMIC_EXPECTED_PTR2]], align 2
+// CHECK-NEXT: store i16 [[TMP15]], ptr [[USX_ATOMIC_DESIRED_PTR3]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED5:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR2]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED6:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR3]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR7:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED5]], i16 [[USX_CMPXCHG_DESIRED6]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV8:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR7]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV8]], ptr [[USX_ATOMIC_EXPECTED_PTR4]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS9:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR7]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL10:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR4]], align 2
+// CHECK-NEXT: [[USX_CAPTURE_CAPTURED:%.*]] = select i1 [[USX_CMPXCHG_SUCCESS9]], i16 [[TMP14]], i16 [[USX_CAPTURE_ACTUAL10]]
+// CHECK-NEXT: store i16 [[USX_CAPTURE_CAPTURED]], ptr [[USV]], align 2
// CHECK-NEXT: [[TMP16:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP17:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP16]], i16 [[TMP17]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i16, i1 } [[TMP18]], 0
-// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i16, i1 } [[TMP18]], 1
-// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i16 [[TMP16]], i16 [[TMP19]]
-// CHECK-NEXT: store i16 [[TMP21]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP17:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP16]] acq_rel, align 2
+// CHECK-NEXT: store i16 [[TMP17]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP18:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP19:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP18]] acq_rel, align 2
+// CHECK-NEXT: store i16 [[TMP19]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP20:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP21:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP20]], ptr [[USX_ATOMIC_EXPECTED_PTR11]], align 2
+// CHECK-NEXT: store i16 [[TMP21]], ptr [[USX_ATOMIC_DESIRED_PTR12]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED14:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR11]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED15:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR12]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR16:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED14]], i16 [[USX_CMPXCHG_DESIRED15]] acq_rel acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV17:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR16]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV17]], ptr [[USX_ATOMIC_EXPECTED_PTR13]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS18:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR16]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL19:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR13]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL19]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP22:%.*]] = load i16, ptr [[USE]], align 2
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP22]] acq_rel, align 2
-// CHECK-NEXT: store i16 [[TMP23]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP24:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP24]] acq_rel, align 2
+// CHECK-NEXT: [[TMP24:%.*]] = icmp ult i16 [[TMP23]], [[TMP22]]
+// CHECK-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], i16 [[TMP22]], i16 [[TMP23]]
// CHECK-NEXT: store i16 [[TMP25]], ptr [[USV]], align 2
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP26:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP27:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP26]], i16 [[TMP27]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i16, i1 } [[TMP28]], 0
+// CHECK-NEXT: [[TMP27:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP26]] acq_rel, align 2
+// CHECK-NEXT: [[TMP28:%.*]] = icmp ugt i16 [[TMP27]], [[TMP26]]
+// CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i16 [[TMP26]], i16 [[TMP27]]
// CHECK-NEXT: store i16 [[TMP29]], ptr [[USV]], align 2
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP30:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP30]] acq_rel, align 2
-// CHECK-NEXT: [[TMP32:%.*]] = icmp ult i16 [[TMP31]], [[TMP30]]
-// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i16 [[TMP30]], i16 [[TMP31]]
+// CHECK-NEXT: [[TMP31:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP30]], ptr [[USX_ATOMIC_EXPECTED_PTR20]], align 2
+// CHECK-NEXT: store i16 [[TMP31]], ptr [[USX_ATOMIC_DESIRED_PTR21]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED23:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR20]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED24:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR21]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR25:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED23]], i16 [[USX_CMPXCHG_DESIRED24]] acq_rel acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV26:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR25]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV26]], ptr [[USX_ATOMIC_EXPECTED_PTR22]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS27:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR25]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL28:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR22]], align 2
+// CHECK-NEXT: [[USX_CAPTURE_CAPTURED29:%.*]] = select i1 [[USX_CMPXCHG_SUCCESS27]], i16 [[TMP30]], i16 [[USX_CAPTURE_ACTUAL28]]
+// CHECK-NEXT: store i16 [[USX_CAPTURE_CAPTURED29]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP32:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP33:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP32]] acquire, align 2
// CHECK-NEXT: store i16 [[TMP33]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP34:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP34]] acq_rel, align 2
-// CHECK-NEXT: [[TMP36:%.*]] = icmp ugt i16 [[TMP35]], [[TMP34]]
-// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i16 [[TMP34]], i16 [[TMP35]]
-// CHECK-NEXT: store i16 [[TMP37]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP34]] acquire, align 2
+// CHECK-NEXT: store i16 [[TMP35]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP36:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP37:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP36]], ptr [[USX_ATOMIC_EXPECTED_PTR30]], align 2
+// CHECK-NEXT: store i16 [[TMP37]], ptr [[USX_ATOMIC_DESIRED_PTR31]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED33:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR30]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED34:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR31]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR35:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED33]], i16 [[USX_CMPXCHG_DESIRED34]] acquire acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV36:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR35]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV36]], ptr [[USX_ATOMIC_EXPECTED_PTR32]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS37:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR35]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL38:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR32]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL38]], ptr [[USV]], align 2
// CHECK-NEXT: [[TMP38:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP39:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP38]], i16 [[TMP39]] acq_rel acquire, align 2
-// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i16, i1 } [[TMP40]], 0
-// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i16, i1 } [[TMP40]], 1
-// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i16 [[TMP38]], i16 [[TMP41]]
-// CHECK-NEXT: store i16 [[TMP43]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP44:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP44]] acquire, align 2
+// CHECK-NEXT: [[TMP39:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP38]] acquire, align 2
+// CHECK-NEXT: [[TMP40:%.*]] = icmp ult i16 [[TMP39]], [[TMP38]]
+// CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i16 [[TMP38]], i16 [[TMP39]]
+// CHECK-NEXT: store i16 [[TMP41]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP42:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP43:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP42]] acquire, align 2
+// CHECK-NEXT: [[TMP44:%.*]] = icmp ugt i16 [[TMP43]], [[TMP42]]
+// CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP44]], i16 [[TMP42]], i16 [[TMP43]]
// CHECK-NEXT: store i16 [[TMP45]], ptr [[USV]], align 2
// CHECK-NEXT: [[TMP46:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP46]] acquire, align 2
-// CHECK-NEXT: store i16 [[TMP47]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP47:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP46]], ptr [[USX_ATOMIC_EXPECTED_PTR39]], align 2
+// CHECK-NEXT: store i16 [[TMP47]], ptr [[USX_ATOMIC_DESIRED_PTR40]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED42:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR39]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED43:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR40]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR44:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED42]], i16 [[USX_CMPXCHG_DESIRED43]] acquire acquire, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV45:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR44]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV45]], ptr [[USX_ATOMIC_EXPECTED_PTR41]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS46:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR44]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL47:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR41]], align 2
+// CHECK-NEXT: [[USX_CAPTURE_CAPTURED48:%.*]] = select i1 [[USX_CMPXCHG_SUCCESS46]], i16 [[TMP46]], i16 [[USX_CAPTURE_ACTUAL47]]
+// CHECK-NEXT: store i16 [[USX_CAPTURE_CAPTURED48]], ptr [[USV]], align 2
// CHECK-NEXT: [[TMP48:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP49:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP48]], i16 [[TMP49]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i16, i1 } [[TMP50]], 0
+// CHECK-NEXT: [[TMP49:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP48]] monotonic, align 2
+// CHECK-NEXT: store i16 [[TMP49]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP50:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP51:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP50]] monotonic, align 2
// CHECK-NEXT: store i16 [[TMP51]], ptr [[USV]], align 2
// CHECK-NEXT: [[TMP52:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP52]] acquire, align 2
-// CHECK-NEXT: [[TMP54:%.*]] = icmp ult i16 [[TMP53]], [[TMP52]]
-// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i16 [[TMP52]], i16 [[TMP53]]
-// CHECK-NEXT: store i16 [[TMP55]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP56:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP56]] acquire, align 2
-// CHECK-NEXT: [[TMP58:%.*]] = icmp ugt i16 [[TMP57]], [[TMP56]]
-// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i16 [[TMP56]], i16 [[TMP57]]
-// CHECK-NEXT: store i16 [[TMP59]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP60:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP61:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP60]], i16 [[TMP61]] acquire acquire, align 2
-// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i16, i1 } [[TMP62]], 0
-// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i16, i1 } [[TMP62]], 1
-// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i16 [[TMP60]], i16 [[TMP63]]
+// CHECK-NEXT: [[TMP53:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP52]], ptr [[USX_ATOMIC_EXPECTED_PTR49]], align 2
+// CHECK-NEXT: store i16 [[TMP53]], ptr [[USX_ATOMIC_DESIRED_PTR50]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED52:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR49]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED53:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR50]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR54:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED52]], i16 [[USX_CMPXCHG_DESIRED53]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV55:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR54]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV55]], ptr [[USX_ATOMIC_EXPECTED_PTR51]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS56:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR54]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL57:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR51]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL57]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP54:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP55:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP54]] monotonic, align 2
+// CHECK-NEXT: [[TMP56:%.*]] = icmp ult i16 [[TMP55]], [[TMP54]]
+// CHECK-NEXT: [[TMP57:%.*]] = select i1 [[TMP56]], i16 [[TMP54]], i16 [[TMP55]]
+// CHECK-NEXT: store i16 [[TMP57]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP58:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP59:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP58]] monotonic, align 2
+// CHECK-NEXT: [[TMP60:%.*]] = icmp ugt i16 [[TMP59]], [[TMP58]]
+// CHECK-NEXT: [[TMP61:%.*]] = select i1 [[TMP60]], i16 [[TMP58]], i16 [[TMP59]]
+// CHECK-NEXT: store i16 [[TMP61]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP62:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP63:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP62]], ptr [[USX_ATOMIC_EXPECTED_PTR58]], align 2
+// CHECK-NEXT: store i16 [[TMP63]], ptr [[USX_ATOMIC_DESIRED_PTR59]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED61:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR58]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED62:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR59]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR63:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED61]], i16 [[USX_CMPXCHG_DESIRED62]] monotonic monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV64:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR63]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV64]], ptr [[USX_ATOMIC_EXPECTED_PTR60]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS65:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR63]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL66:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR60]], align 2
+// CHECK-NEXT: [[USX_CAPTURE_CAPTURED67:%.*]] = select i1 [[USX_CMPXCHG_SUCCESS65]], i16 [[TMP62]], i16 [[USX_CAPTURE_ACTUAL66]]
+// CHECK-NEXT: store i16 [[USX_CAPTURE_CAPTURED67]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP64:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP65:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP64]] release, align 2
// CHECK-NEXT: store i16 [[TMP65]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP66:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP66]] monotonic, align 2
+// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP66]] release, align 2
// CHECK-NEXT: store i16 [[TMP67]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP68:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP68]] monotonic, align 2
-// CHECK-NEXT: store i16 [[TMP69]], ptr [[USV]], align 2
+// CHECK-NEXT: [[TMP69:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP68]], ptr [[USX_ATOMIC_EXPECTED_PTR68]], align 2
+// CHECK-NEXT: store i16 [[TMP69]], ptr [[USX_ATOMIC_DESIRED_PTR69]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED71:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR68]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED72:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR69]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR73:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED71]], i16 [[USX_CMPXCHG_DESIRED72]] release monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV74:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR73]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV74]], ptr [[USX_ATOMIC_EXPECTED_PTR70]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS75:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR73]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL76:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR70]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL76]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP70:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP71:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP70]], i16 [[TMP71]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i16, i1 } [[TMP72]], 0
+// CHECK-NEXT: [[TMP71:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP70]] release, align 2
+// CHECK-NEXT: [[TMP72:%.*]] = icmp ult i16 [[TMP71]], [[TMP70]]
+// CHECK-NEXT: [[TMP73:%.*]] = select i1 [[TMP72]], i16 [[TMP70]], i16 [[TMP71]]
// CHECK-NEXT: store i16 [[TMP73]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP74:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP74]] monotonic, align 2
-// CHECK-NEXT: [[TMP76:%.*]] = icmp ult i16 [[TMP75]], [[TMP74]]
+// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP74]] release, align 2
+// CHECK-NEXT: [[TMP76:%.*]] = icmp ugt i16 [[TMP75]], [[TMP74]]
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i16 [[TMP74]], i16 [[TMP75]]
// CHECK-NEXT: store i16 [[TMP77]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP78:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP78]] monotonic, align 2
-// CHECK-NEXT: [[TMP80:%.*]] = icmp ugt i16 [[TMP79]], [[TMP78]]
-// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i16 [[TMP78]], i16 [[TMP79]]
+// CHECK-NEXT: [[TMP79:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP78]], ptr [[USX_ATOMIC_EXPECTED_PTR77]], align 2
+// CHECK-NEXT: store i16 [[TMP79]], ptr [[USX_ATOMIC_DESIRED_PTR78]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED80:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR77]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED81:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR78]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR82:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED80]], i16 [[USX_CMPXCHG_DESIRED81]] release monotonic, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV83:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR82]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV83]], ptr [[USX_ATOMIC_EXPECTED_PTR79]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS84:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR82]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL85:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR79]], align 2
+// CHECK-NEXT: [[USX_CAPTURE_CAPTURED86:%.*]] = select i1 [[USX_CMPXCHG_SUCCESS84]], i16 [[TMP78]], i16 [[USX_CAPTURE_ACTUAL85]]
+// CHECK-NEXT: store i16 [[USX_CAPTURE_CAPTURED86]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP80:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP81:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP80]] seq_cst, align 2
// CHECK-NEXT: store i16 [[TMP81]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP82:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP83:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP82]], i16 [[TMP83]] monotonic monotonic, align 2
-// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i16, i1 } [[TMP84]], 0
-// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i16, i1 } [[TMP84]], 1
-// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i16 [[TMP82]], i16 [[TMP85]]
-// CHECK-NEXT: store i16 [[TMP87]], ptr [[USV]], align 2
-// CHECK-NEXT: [[TMP88:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP88]] release, align 2
+// CHECK-NEXT: [[TMP83:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP82]] seq_cst, align 2
+// CHECK-NEXT: store i16 [[TMP83]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP84:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP85:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP84]], ptr [[USX_ATOMIC_EXPECTED_PTR87]], align 2
+// CHECK-NEXT: store i16 [[TMP85]], ptr [[USX_ATOMIC_DESIRED_PTR88]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED90:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR87]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED91:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR88]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR92:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED90]], i16 [[USX_CMPXCHG_DESIRED91]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV93:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR92]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV93]], ptr [[USX_ATOMIC_EXPECTED_PTR89]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS94:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR92]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL95:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR89]], align 2
+// CHECK-NEXT: store i16 [[USX_CAPTURE_ACTUAL95]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP86:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP86]] seq_cst, align 2
+// CHECK-NEXT: [[TMP88:%.*]] = icmp ult i16 [[TMP87]], [[TMP86]]
+// CHECK-NEXT: [[TMP89:%.*]] = select i1 [[TMP88]], i16 [[TMP86]], i16 [[TMP87]]
// CHECK-NEXT: store i16 [[TMP89]], ptr [[USV]], align 2
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP90:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP90]] release, align 2
-// CHECK-NEXT: store i16 [[TMP91]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP92:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP93:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP92]], i16 [[TMP93]] release monotonic, align 2
-// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i16, i1 } [[TMP94]], 0
-// CHECK-NEXT: store i16 [[TMP95]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP96:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP96]] release, align 2
-// CHECK-NEXT: [[TMP98:%.*]] = icmp ult i16 [[TMP97]], [[TMP96]]
-// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i16 [[TMP96]], i16 [[TMP97]]
-// CHECK-NEXT: store i16 [[TMP99]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP100:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP100]] release, align 2
-// CHECK-NEXT: [[TMP102:%.*]] = icmp ugt i16 [[TMP101]], [[TMP100]]
-// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i16 [[TMP100]], i16 [[TMP101]]
-// CHECK-NEXT: store i16 [[TMP103]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP104:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP105:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP104]], i16 [[TMP105]] release monotonic, align 2
-// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i16, i1 } [[TMP106]], 0
-// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i16, i1 } [[TMP106]], 1
-// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i16 [[TMP104]], i16 [[TMP107]]
-// CHECK-NEXT: store i16 [[TMP109]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP110:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP110]] seq_cst, align 2
-// CHECK-NEXT: store i16 [[TMP111]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP112:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP112]] seq_cst, align 2
-// CHECK-NEXT: store i16 [[TMP113]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP114:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP115:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP114]], i16 [[TMP115]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i16, i1 } [[TMP116]], 0
-// CHECK-NEXT: store i16 [[TMP117]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP118:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw umin ptr [[USX]], i16 [[TMP118]] seq_cst, align 2
-// CHECK-NEXT: [[TMP120:%.*]] = icmp ult i16 [[TMP119]], [[TMP118]]
-// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i16 [[TMP118]], i16 [[TMP119]]
-// CHECK-NEXT: store i16 [[TMP121]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP122:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP122]] seq_cst, align 2
-// CHECK-NEXT: [[TMP124:%.*]] = icmp ugt i16 [[TMP123]], [[TMP122]]
-// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i16 [[TMP122]], i16 [[TMP123]]
-// CHECK-NEXT: store i16 [[TMP125]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP126:%.*]] = load i16, ptr [[USE]], align 2
-// CHECK-NEXT: [[TMP127:%.*]] = load i16, ptr [[USD]], align 2
-// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[USX]], i16 [[TMP126]], i16 [[TMP127]] seq_cst seq_cst, align 2
-// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i16, i1 } [[TMP128]], 0
-// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i16, i1 } [[TMP128]], 1
-// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i16 [[TMP126]], i16 [[TMP129]]
-// CHECK-NEXT: store i16 [[TMP131]], ptr [[USV]], align 2
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP132:%.*]] = load i16, ptr [[USV]], align 2
-// CHECK-NEXT: ret i16 [[TMP132]]
+// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw umax ptr [[USX]], i16 [[TMP90]] seq_cst, align 2
+// CHECK-NEXT: [[TMP92:%.*]] = icmp ugt i16 [[TMP91]], [[TMP90]]
+// CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP92]], i16 [[TMP90]], i16 [[TMP91]]
+// CHECK-NEXT: store i16 [[TMP93]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP94:%.*]] = load i16, ptr [[USE]], align 2
+// CHECK-NEXT: [[TMP95:%.*]] = load i16, ptr [[USD]], align 2
+// CHECK-NEXT: store i16 [[TMP94]], ptr [[USX_ATOMIC_EXPECTED_PTR96]], align 2
+// CHECK-NEXT: store i16 [[TMP95]], ptr [[USX_ATOMIC_DESIRED_PTR97]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_EXPECTED99:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR96]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_DESIRED100:%.*]] = load i16, ptr [[USX_ATOMIC_DESIRED_PTR97]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PAIR101:%.*]] = cmpxchg ptr [[USX]], i16 [[USX_CMPXCHG_EXPECTED99]], i16 [[USX_CMPXCHG_DESIRED100]] seq_cst seq_cst, align 2
+// CHECK-NEXT: [[USX_CMPXCHG_PREV102:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR101]], 0
+// CHECK-NEXT: store i16 [[USX_CMPXCHG_PREV102]], ptr [[USX_ATOMIC_EXPECTED_PTR98]], align 2
+// CHECK-NEXT: [[USX_CMPXCHG_SUCCESS103:%.*]] = extractvalue { i16, i1 } [[USX_CMPXCHG_PAIR101]], 1
+// CHECK-NEXT: [[USX_CAPTURE_ACTUAL104:%.*]] = load i16, ptr [[USX_ATOMIC_EXPECTED_PTR98]], align 2
+// CHECK-NEXT: [[USX_CAPTURE_CAPTURED105:%.*]] = select i1 [[USX_CMPXCHG_SUCCESS103]], i16 [[TMP94]], i16 [[USX_CAPTURE_ACTUAL104]]
+// CHECK-NEXT: store i16 [[USX_CAPTURE_CAPTURED105]], ptr [[USV]], align 2
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP96:%.*]] = load i16, ptr [[USV]], align 2
+// CHECK-NEXT: ret i16 [[TMP96]]
//
//
// CHECK-LABEL: @ixevd(
@@ -26231,6 +35231,42 @@ double fail_dxevd() {
// CHECK-NEXT: [[IV:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[IE:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[ID:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR1:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR2:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR3:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR4:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR11:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR12:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR13:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR20:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR21:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR22:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR30:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR31:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR32:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR39:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR40:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR41:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR49:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR50:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR51:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR58:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR59:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR60:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR68:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR69:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR70:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR77:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR78:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR79:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR87:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR88:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR89:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR96:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_DESIRED_PTR97:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[IX_ATOMIC_EXPECTED_PTR98:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[IE]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP0]] monotonic, align 4
// CHECK-NEXT: store i32 [[TMP1]], ptr [[IV]], align 4
@@ -26239,186 +35275,264 @@ double fail_dxevd() {
// CHECK-NEXT: store i32 [[TMP3]], ptr [[IV]], align 4
// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[IE]], align 4
// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP4]], i32 [[TMP5]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0
-// CHECK-NEXT: store i32 [[TMP7]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP8]] monotonic, align 4
-// CHECK-NEXT: [[TMP10:%.*]] = icmp slt i32 [[TMP9]], [[TMP8]]
-// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i32 [[TMP8]], i32 [[TMP9]]
-// CHECK-NEXT: store i32 [[TMP11]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP12]] monotonic, align 4
-// CHECK-NEXT: [[TMP14:%.*]] = icmp sgt i32 [[TMP13]], [[TMP12]]
-// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i32 [[TMP12]], i32 [[TMP13]]
-// CHECK-NEXT: store i32 [[TMP15]], ptr [[IV]], align 4
+// CHECK-NEXT: store i32 [[TMP4]], ptr [[IX_ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: store i32 [[TMP5]], ptr [[IX_ATOMIC_DESIRED_PTR]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED]], i32 [[IX_CMPXCHG_DESIRED]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV]], ptr [[IX_ATOMIC_EXPECTED_PTR1]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR1]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP7:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP6]] monotonic, align 4
+// CHECK-NEXT: [[TMP8:%.*]] = icmp slt i32 [[TMP7]], [[TMP6]]
+// CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i32 [[TMP6]], i32 [[TMP7]]
+// CHECK-NEXT: store i32 [[TMP9]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP11:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP10]] monotonic, align 4
+// CHECK-NEXT: [[TMP12:%.*]] = icmp sgt i32 [[TMP11]], [[TMP10]]
+// CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i32 [[TMP10]], i32 [[TMP11]]
+// CHECK-NEXT: store i32 [[TMP13]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP14]], ptr [[IX_ATOMIC_EXPECTED_PTR2]], align 4
+// CHECK-NEXT: store i32 [[TMP15]], ptr [[IX_ATOMIC_DESIRED_PTR3]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED5:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR2]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED6:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR3]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR7:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED5]], i32 [[IX_CMPXCHG_DESIRED6]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV8:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR7]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV8]], ptr [[IX_ATOMIC_EXPECTED_PTR4]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS9:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR7]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL10:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR4]], align 4
+// CHECK-NEXT: [[IX_CAPTURE_CAPTURED:%.*]] = select i1 [[IX_CMPXCHG_SUCCESS9]], i32 [[TMP14]], i32 [[IX_CAPTURE_ACTUAL10]]
+// CHECK-NEXT: store i32 [[IX_CAPTURE_CAPTURED]], ptr [[IV]], align 4
// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP16]], i32 [[TMP17]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i32, i1 } [[TMP18]], 0
-// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i32, i1 } [[TMP18]], 1
-// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i32 [[TMP16]], i32 [[TMP19]]
-// CHECK-NEXT: store i32 [[TMP21]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP17:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP16]] acq_rel, align 4
+// CHECK-NEXT: store i32 [[TMP17]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP19:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP18]] acq_rel, align 4
+// CHECK-NEXT: store i32 [[TMP19]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP20]], ptr [[IX_ATOMIC_EXPECTED_PTR11]], align 4
+// CHECK-NEXT: store i32 [[TMP21]], ptr [[IX_ATOMIC_DESIRED_PTR12]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED14:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR11]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED15:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR12]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR16:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED14]], i32 [[IX_CMPXCHG_DESIRED15]] acq_rel acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV17:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR16]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV17]], ptr [[IX_ATOMIC_EXPECTED_PTR13]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS18:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR16]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL19:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR13]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL19]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[IE]], align 4
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP22]] acq_rel, align 4
-// CHECK-NEXT: store i32 [[TMP23]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP24]] acq_rel, align 4
+// CHECK-NEXT: [[TMP24:%.*]] = icmp slt i32 [[TMP23]], [[TMP22]]
+// CHECK-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], i32 [[TMP22]], i32 [[TMP23]]
// CHECK-NEXT: store i32 [[TMP25]], ptr [[IV]], align 4
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP26]], i32 [[TMP27]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i32, i1 } [[TMP28]], 0
+// CHECK-NEXT: [[TMP27:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP26]] acq_rel, align 4
+// CHECK-NEXT: [[TMP28:%.*]] = icmp sgt i32 [[TMP27]], [[TMP26]]
+// CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i32 [[TMP26]], i32 [[TMP27]]
// CHECK-NEXT: store i32 [[TMP29]], ptr [[IV]], align 4
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP30]] acq_rel, align 4
-// CHECK-NEXT: [[TMP32:%.*]] = icmp slt i32 [[TMP31]], [[TMP30]]
-// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i32 [[TMP30]], i32 [[TMP31]]
+// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP30]], ptr [[IX_ATOMIC_EXPECTED_PTR20]], align 4
+// CHECK-NEXT: store i32 [[TMP31]], ptr [[IX_ATOMIC_DESIRED_PTR21]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED23:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR20]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED24:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR21]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR25:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED23]], i32 [[IX_CMPXCHG_DESIRED24]] acq_rel acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV26:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR25]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV26]], ptr [[IX_ATOMIC_EXPECTED_PTR22]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS27:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR25]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL28:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR22]], align 4
+// CHECK-NEXT: [[IX_CAPTURE_CAPTURED29:%.*]] = select i1 [[IX_CMPXCHG_SUCCESS27]], i32 [[TMP30]], i32 [[IX_CAPTURE_ACTUAL28]]
+// CHECK-NEXT: store i32 [[IX_CAPTURE_CAPTURED29]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP33:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP32]] acquire, align 4
// CHECK-NEXT: store i32 [[TMP33]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP34]] acq_rel, align 4
-// CHECK-NEXT: [[TMP36:%.*]] = icmp sgt i32 [[TMP35]], [[TMP34]]
-// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i32 [[TMP34]], i32 [[TMP35]]
-// CHECK-NEXT: store i32 [[TMP37]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP34]] acquire, align 4
+// CHECK-NEXT: store i32 [[TMP35]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP36]], ptr [[IX_ATOMIC_EXPECTED_PTR30]], align 4
+// CHECK-NEXT: store i32 [[TMP37]], ptr [[IX_ATOMIC_DESIRED_PTR31]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED33:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR30]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED34:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR31]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR35:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED33]], i32 [[IX_CMPXCHG_DESIRED34]] acquire acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV36:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR35]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV36]], ptr [[IX_ATOMIC_EXPECTED_PTR32]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS37:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR35]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL38:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR32]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL38]], ptr [[IV]], align 4
// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP38]], i32 [[TMP39]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i32, i1 } [[TMP40]], 0
-// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i32, i1 } [[TMP40]], 1
-// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP38]], i32 [[TMP41]]
-// CHECK-NEXT: store i32 [[TMP43]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP44:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP44]] acquire, align 4
+// CHECK-NEXT: [[TMP39:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP38]] acquire, align 4
+// CHECK-NEXT: [[TMP40:%.*]] = icmp slt i32 [[TMP39]], [[TMP38]]
+// CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i32 [[TMP38]], i32 [[TMP39]]
+// CHECK-NEXT: store i32 [[TMP41]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP42:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP43:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP42]] acquire, align 4
+// CHECK-NEXT: [[TMP44:%.*]] = icmp sgt i32 [[TMP43]], [[TMP42]]
+// CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP44]], i32 [[TMP42]], i32 [[TMP43]]
// CHECK-NEXT: store i32 [[TMP45]], ptr [[IV]], align 4
// CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP46]] acquire, align 4
-// CHECK-NEXT: store i32 [[TMP47]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP46]], ptr [[IX_ATOMIC_EXPECTED_PTR39]], align 4
+// CHECK-NEXT: store i32 [[TMP47]], ptr [[IX_ATOMIC_DESIRED_PTR40]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED42:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR39]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED43:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR40]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR44:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED42]], i32 [[IX_CMPXCHG_DESIRED43]] acquire acquire, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV45:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR44]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV45]], ptr [[IX_ATOMIC_EXPECTED_PTR41]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS46:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR44]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL47:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR41]], align 4
+// CHECK-NEXT: [[IX_CAPTURE_CAPTURED48:%.*]] = select i1 [[IX_CMPXCHG_SUCCESS46]], i32 [[TMP46]], i32 [[IX_CAPTURE_ACTUAL47]]
+// CHECK-NEXT: store i32 [[IX_CAPTURE_CAPTURED48]], ptr [[IV]], align 4
// CHECK-NEXT: [[TMP48:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP48]], i32 [[TMP49]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i32, i1 } [[TMP50]], 0
+// CHECK-NEXT: [[TMP49:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP48]] monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP49]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP51:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP50]] monotonic, align 4
// CHECK-NEXT: store i32 [[TMP51]], ptr [[IV]], align 4
// CHECK-NEXT: [[TMP52:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP52]] acquire, align 4
-// CHECK-NEXT: [[TMP54:%.*]] = icmp slt i32 [[TMP53]], [[TMP52]]
-// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i32 [[TMP52]], i32 [[TMP53]]
-// CHECK-NEXT: store i32 [[TMP55]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP56:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP56]] acquire, align 4
-// CHECK-NEXT: [[TMP58:%.*]] = icmp sgt i32 [[TMP57]], [[TMP56]]
-// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i32 [[TMP56]], i32 [[TMP57]]
-// CHECK-NEXT: store i32 [[TMP59]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP60:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP61:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP60]], i32 [[TMP61]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i32, i1 } [[TMP62]], 0
-// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i32, i1 } [[TMP62]], 1
-// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i32 [[TMP60]], i32 [[TMP63]]
+// CHECK-NEXT: [[TMP53:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP52]], ptr [[IX_ATOMIC_EXPECTED_PTR49]], align 4
+// CHECK-NEXT: store i32 [[TMP53]], ptr [[IX_ATOMIC_DESIRED_PTR50]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED52:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR49]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED53:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR50]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR54:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED52]], i32 [[IX_CMPXCHG_DESIRED53]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV55:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR54]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV55]], ptr [[IX_ATOMIC_EXPECTED_PTR51]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS56:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR54]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL57:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR51]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL57]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP54:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP55:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP54]] monotonic, align 4
+// CHECK-NEXT: [[TMP56:%.*]] = icmp slt i32 [[TMP55]], [[TMP54]]
+// CHECK-NEXT: [[TMP57:%.*]] = select i1 [[TMP56]], i32 [[TMP54]], i32 [[TMP55]]
+// CHECK-NEXT: store i32 [[TMP57]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP58:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP59:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP58]] monotonic, align 4
+// CHECK-NEXT: [[TMP60:%.*]] = icmp sgt i32 [[TMP59]], [[TMP58]]
+// CHECK-NEXT: [[TMP61:%.*]] = select i1 [[TMP60]], i32 [[TMP58]], i32 [[TMP59]]
+// CHECK-NEXT: store i32 [[TMP61]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP62:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP63:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP62]], ptr [[IX_ATOMIC_EXPECTED_PTR58]], align 4
+// CHECK-NEXT: store i32 [[TMP63]], ptr [[IX_ATOMIC_DESIRED_PTR59]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED61:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR58]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED62:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR59]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR63:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED61]], i32 [[IX_CMPXCHG_DESIRED62]] monotonic monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV64:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR63]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV64]], ptr [[IX_ATOMIC_EXPECTED_PTR60]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS65:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR63]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL66:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR60]], align 4
+// CHECK-NEXT: [[IX_CAPTURE_CAPTURED67:%.*]] = select i1 [[IX_CMPXCHG_SUCCESS65]], i32 [[TMP62]], i32 [[IX_CAPTURE_ACTUAL66]]
+// CHECK-NEXT: store i32 [[IX_CAPTURE_CAPTURED67]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP64:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP65:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP64]] release, align 4
// CHECK-NEXT: store i32 [[TMP65]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP66:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP66]] monotonic, align 4
+// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP66]] release, align 4
// CHECK-NEXT: store i32 [[TMP67]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP68:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP68]] monotonic, align 4
-// CHECK-NEXT: store i32 [[TMP69]], ptr [[IV]], align 4
+// CHECK-NEXT: [[TMP69:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP68]], ptr [[IX_ATOMIC_EXPECTED_PTR68]], align 4
+// CHECK-NEXT: store i32 [[TMP69]], ptr [[IX_ATOMIC_DESIRED_PTR69]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED71:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR68]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED72:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR69]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR73:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED71]], i32 [[IX_CMPXCHG_DESIRED72]] release monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV74:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR73]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV74]], ptr [[IX_ATOMIC_EXPECTED_PTR70]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS75:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR73]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL76:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR70]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL76]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP70:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP71:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP70]], i32 [[TMP71]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i32, i1 } [[TMP72]], 0
+// CHECK-NEXT: [[TMP71:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP70]] release, align 4
+// CHECK-NEXT: [[TMP72:%.*]] = icmp slt i32 [[TMP71]], [[TMP70]]
+// CHECK-NEXT: [[TMP73:%.*]] = select i1 [[TMP72]], i32 [[TMP70]], i32 [[TMP71]]
// CHECK-NEXT: store i32 [[TMP73]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP74:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP74]] monotonic, align 4
-// CHECK-NEXT: [[TMP76:%.*]] = icmp slt i32 [[TMP75]], [[TMP74]]
+// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP74]] release, align 4
+// CHECK-NEXT: [[TMP76:%.*]] = icmp sgt i32 [[TMP75]], [[TMP74]]
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i32 [[TMP74]], i32 [[TMP75]]
// CHECK-NEXT: store i32 [[TMP77]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP78:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP78]] monotonic, align 4
-// CHECK-NEXT: [[TMP80:%.*]] = icmp sgt i32 [[TMP79]], [[TMP78]]
-// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i32 [[TMP78]], i32 [[TMP79]]
+// CHECK-NEXT: [[TMP79:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP78]], ptr [[IX_ATOMIC_EXPECTED_PTR77]], align 4
+// CHECK-NEXT: store i32 [[TMP79]], ptr [[IX_ATOMIC_DESIRED_PTR78]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED80:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR77]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED81:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR78]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR82:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED80]], i32 [[IX_CMPXCHG_DESIRED81]] release monotonic, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV83:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR82]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV83]], ptr [[IX_ATOMIC_EXPECTED_PTR79]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS84:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR82]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL85:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR79]], align 4
+// CHECK-NEXT: [[IX_CAPTURE_CAPTURED86:%.*]] = select i1 [[IX_CMPXCHG_SUCCESS84]], i32 [[TMP78]], i32 [[IX_CAPTURE_ACTUAL85]]
+// CHECK-NEXT: store i32 [[IX_CAPTURE_CAPTURED86]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP80:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP81:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP80]] seq_cst, align 4
// CHECK-NEXT: store i32 [[TMP81]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP82:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP83:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP82]], i32 [[TMP83]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i32, i1 } [[TMP84]], 0
-// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i32, i1 } [[TMP84]], 1
-// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i32 [[TMP82]], i32 [[TMP85]]
-// CHECK-NEXT: store i32 [[TMP87]], ptr [[IV]], align 4
-// CHECK-NEXT: [[TMP88:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP88]] release, align 4
+// CHECK-NEXT: [[TMP83:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP82]] seq_cst, align 4
+// CHECK-NEXT: store i32 [[TMP83]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP84:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP85:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP84]], ptr [[IX_ATOMIC_EXPECTED_PTR87]], align 4
+// CHECK-NEXT: store i32 [[TMP85]], ptr [[IX_ATOMIC_DESIRED_PTR88]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED90:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR87]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED91:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR88]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR92:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED90]], i32 [[IX_CMPXCHG_DESIRED91]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV93:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR92]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV93]], ptr [[IX_ATOMIC_EXPECTED_PTR89]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS94:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR92]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL95:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR89]], align 4
+// CHECK-NEXT: store i32 [[IX_CAPTURE_ACTUAL95]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP86:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP86]] seq_cst, align 4
+// CHECK-NEXT: [[TMP88:%.*]] = icmp slt i32 [[TMP87]], [[TMP86]]
+// CHECK-NEXT: [[TMP89:%.*]] = select i1 [[TMP88]], i32 [[TMP86]], i32 [[TMP87]]
// CHECK-NEXT: store i32 [[TMP89]], ptr [[IV]], align 4
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP90:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP90]] release, align 4
-// CHECK-NEXT: store i32 [[TMP91]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP92:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP93:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP92]], i32 [[TMP93]] release monotonic, align 4
-// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i32, i1 } [[TMP94]], 0
-// CHECK-NEXT: store i32 [[TMP95]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP96:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP96]] release, align 4
-// CHECK-NEXT: [[TMP98:%.*]] = icmp slt i32 [[TMP97]], [[TMP96]]
-// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i32 [[TMP96]], i32 [[TMP97]]
-// CHECK-NEXT: store i32 [[TMP99]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP100:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP100]] release, align 4
-// CHECK-NEXT: [[TMP102:%.*]] = icmp sgt i32 [[TMP101]], [[TMP100]]
-// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i32 [[TMP100]], i32 [[TMP101]]
-// CHECK-NEXT: store i32 [[TMP103]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP104:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP105:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP104]], i32 [[TMP105]] release monotonic, align 4
-// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i32, i1 } [[TMP106]], 0
-// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i32, i1 } [[TMP106]], 1
-// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i32 [[TMP104]], i32 [[TMP107]]
-// CHECK-NEXT: store i32 [[TMP109]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP110:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP110]] seq_cst, align 4
-// CHECK-NEXT: store i32 [[TMP111]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP112:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP112]] seq_cst, align 4
-// CHECK-NEXT: store i32 [[TMP113]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP114:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP115:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP114]], i32 [[TMP115]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i32, i1 } [[TMP116]], 0
-// CHECK-NEXT: store i32 [[TMP117]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP118:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw min ptr [[IX]], i32 [[TMP118]] seq_cst, align 4
-// CHECK-NEXT: [[TMP120:%.*]] = icmp slt i32 [[TMP119]], [[TMP118]]
-// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i32 [[TMP118]], i32 [[TMP119]]
-// CHECK-NEXT: store i32 [[TMP121]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP122:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP122]] seq_cst, align 4
-// CHECK-NEXT: [[TMP124:%.*]] = icmp sgt i32 [[TMP123]], [[TMP122]]
-// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i32 [[TMP122]], i32 [[TMP123]]
-// CHECK-NEXT: store i32 [[TMP125]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP126:%.*]] = load i32, ptr [[IE]], align 4
-// CHECK-NEXT: [[TMP127:%.*]] = load i32, ptr [[ID]], align 4
-// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[IX]], i32 [[TMP126]], i32 [[TMP127]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i32, i1 } [[TMP128]], 0
-// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i32, i1 } [[TMP128]], 1
-// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i32 [[TMP126]], i32 [[TMP129]]
-// CHECK-NEXT: store i32 [[TMP131]], ptr [[IV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP132:%.*]] = load i32, ptr [[IV]], align 4
-// CHECK-NEXT: ret i32 [[TMP132]]
+// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw max ptr [[IX]], i32 [[TMP90]] seq_cst, align 4
+// CHECK-NEXT: [[TMP92:%.*]] = icmp sgt i32 [[TMP91]], [[TMP90]]
+// CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP92]], i32 [[TMP90]], i32 [[TMP91]]
+// CHECK-NEXT: store i32 [[TMP93]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP94:%.*]] = load i32, ptr [[IE]], align 4
+// CHECK-NEXT: [[TMP95:%.*]] = load i32, ptr [[ID]], align 4
+// CHECK-NEXT: store i32 [[TMP94]], ptr [[IX_ATOMIC_EXPECTED_PTR96]], align 4
+// CHECK-NEXT: store i32 [[TMP95]], ptr [[IX_ATOMIC_DESIRED_PTR97]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_EXPECTED99:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR96]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_DESIRED100:%.*]] = load i32, ptr [[IX_ATOMIC_DESIRED_PTR97]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PAIR101:%.*]] = cmpxchg ptr [[IX]], i32 [[IX_CMPXCHG_EXPECTED99]], i32 [[IX_CMPXCHG_DESIRED100]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[IX_CMPXCHG_PREV102:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR101]], 0
+// CHECK-NEXT: store i32 [[IX_CMPXCHG_PREV102]], ptr [[IX_ATOMIC_EXPECTED_PTR98]], align 4
+// CHECK-NEXT: [[IX_CMPXCHG_SUCCESS103:%.*]] = extractvalue { i32, i1 } [[IX_CMPXCHG_PAIR101]], 1
+// CHECK-NEXT: [[IX_CAPTURE_ACTUAL104:%.*]] = load i32, ptr [[IX_ATOMIC_EXPECTED_PTR98]], align 4
+// CHECK-NEXT: [[IX_CAPTURE_CAPTURED105:%.*]] = select i1 [[IX_CMPXCHG_SUCCESS103]], i32 [[TMP94]], i32 [[IX_CAPTURE_ACTUAL104]]
+// CHECK-NEXT: store i32 [[IX_CAPTURE_CAPTURED105]], ptr [[IV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP96:%.*]] = load i32, ptr [[IV]], align 4
+// CHECK-NEXT: ret i32 [[TMP96]]
//
//
// CHECK-LABEL: @uixevd(
@@ -26427,6 +35541,42 @@ double fail_dxevd() {
// CHECK-NEXT: [[UIV:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[UIE:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[UID:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR1:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR2:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR3:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR4:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR11:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR12:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR13:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR20:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR21:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR22:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR30:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR31:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR32:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR39:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR40:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR41:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR49:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR50:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR51:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR58:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR59:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR60:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR68:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR69:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR70:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR77:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR78:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR79:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR87:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR88:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR89:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR96:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_DESIRED_PTR97:%.*]] = alloca i32, align 4
+// CHECK-NEXT: [[UIX_ATOMIC_EXPECTED_PTR98:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[UIE]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP0]] monotonic, align 4
// CHECK-NEXT: store i32 [[TMP1]], ptr [[UIV]], align 4
@@ -26435,186 +35585,264 @@ double fail_dxevd() {
// CHECK-NEXT: store i32 [[TMP3]], ptr [[UIV]], align 4
// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[UIE]], align 4
// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP4]], i32 [[TMP5]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0
-// CHECK-NEXT: store i32 [[TMP7]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP8]] monotonic, align 4
-// CHECK-NEXT: [[TMP10:%.*]] = icmp ult i32 [[TMP9]], [[TMP8]]
-// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i32 [[TMP8]], i32 [[TMP9]]
-// CHECK-NEXT: store i32 [[TMP11]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP12]] monotonic, align 4
-// CHECK-NEXT: [[TMP14:%.*]] = icmp ugt i32 [[TMP13]], [[TMP12]]
-// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i32 [[TMP12]], i32 [[TMP13]]
-// CHECK-NEXT: store i32 [[TMP15]], ptr [[UIV]], align 4
+// CHECK-NEXT: store i32 [[TMP4]], ptr [[UIX_ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: store i32 [[TMP5]], ptr [[UIX_ATOMIC_DESIRED_PTR]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED]], i32 [[UIX_CMPXCHG_DESIRED]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV]], ptr [[UIX_ATOMIC_EXPECTED_PTR1]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR1]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP7:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP6]] monotonic, align 4
+// CHECK-NEXT: [[TMP8:%.*]] = icmp ult i32 [[TMP7]], [[TMP6]]
+// CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i32 [[TMP6]], i32 [[TMP7]]
+// CHECK-NEXT: store i32 [[TMP9]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP11:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP10]] monotonic, align 4
+// CHECK-NEXT: [[TMP12:%.*]] = icmp ugt i32 [[TMP11]], [[TMP10]]
+// CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i32 [[TMP10]], i32 [[TMP11]]
+// CHECK-NEXT: store i32 [[TMP13]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP14]], ptr [[UIX_ATOMIC_EXPECTED_PTR2]], align 4
+// CHECK-NEXT: store i32 [[TMP15]], ptr [[UIX_ATOMIC_DESIRED_PTR3]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED5:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR2]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED6:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR3]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR7:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED5]], i32 [[UIX_CMPXCHG_DESIRED6]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV8:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR7]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV8]], ptr [[UIX_ATOMIC_EXPECTED_PTR4]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS9:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR7]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL10:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR4]], align 4
+// CHECK-NEXT: [[UIX_CAPTURE_CAPTURED:%.*]] = select i1 [[UIX_CMPXCHG_SUCCESS9]], i32 [[TMP14]], i32 [[UIX_CAPTURE_ACTUAL10]]
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_CAPTURED]], ptr [[UIV]], align 4
// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP16]], i32 [[TMP17]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i32, i1 } [[TMP18]], 0
-// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i32, i1 } [[TMP18]], 1
-// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i32 [[TMP16]], i32 [[TMP19]]
-// CHECK-NEXT: store i32 [[TMP21]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP17:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP16]] acq_rel, align 4
+// CHECK-NEXT: store i32 [[TMP17]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP19:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP18]] acq_rel, align 4
+// CHECK-NEXT: store i32 [[TMP19]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP20]], ptr [[UIX_ATOMIC_EXPECTED_PTR11]], align 4
+// CHECK-NEXT: store i32 [[TMP21]], ptr [[UIX_ATOMIC_DESIRED_PTR12]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED14:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR11]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED15:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR12]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR16:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED14]], i32 [[UIX_CMPXCHG_DESIRED15]] acq_rel acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV17:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR16]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV17]], ptr [[UIX_ATOMIC_EXPECTED_PTR13]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS18:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR16]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL19:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR13]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL19]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[UIE]], align 4
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP22]] acq_rel, align 4
-// CHECK-NEXT: store i32 [[TMP23]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP24]] acq_rel, align 4
+// CHECK-NEXT: [[TMP24:%.*]] = icmp ult i32 [[TMP23]], [[TMP22]]
+// CHECK-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], i32 [[TMP22]], i32 [[TMP23]]
// CHECK-NEXT: store i32 [[TMP25]], ptr [[UIV]], align 4
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP26]], i32 [[TMP27]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i32, i1 } [[TMP28]], 0
+// CHECK-NEXT: [[TMP27:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP26]] acq_rel, align 4
+// CHECK-NEXT: [[TMP28:%.*]] = icmp ugt i32 [[TMP27]], [[TMP26]]
+// CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i32 [[TMP26]], i32 [[TMP27]]
// CHECK-NEXT: store i32 [[TMP29]], ptr [[UIV]], align 4
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP30]] acq_rel, align 4
-// CHECK-NEXT: [[TMP32:%.*]] = icmp ult i32 [[TMP31]], [[TMP30]]
-// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i32 [[TMP30]], i32 [[TMP31]]
+// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP30]], ptr [[UIX_ATOMIC_EXPECTED_PTR20]], align 4
+// CHECK-NEXT: store i32 [[TMP31]], ptr [[UIX_ATOMIC_DESIRED_PTR21]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED23:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR20]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED24:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR21]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR25:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED23]], i32 [[UIX_CMPXCHG_DESIRED24]] acq_rel acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV26:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR25]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV26]], ptr [[UIX_ATOMIC_EXPECTED_PTR22]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS27:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR25]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL28:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR22]], align 4
+// CHECK-NEXT: [[UIX_CAPTURE_CAPTURED29:%.*]] = select i1 [[UIX_CMPXCHG_SUCCESS27]], i32 [[TMP30]], i32 [[UIX_CAPTURE_ACTUAL28]]
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_CAPTURED29]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP33:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP32]] acquire, align 4
// CHECK-NEXT: store i32 [[TMP33]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP34]] acq_rel, align 4
-// CHECK-NEXT: [[TMP36:%.*]] = icmp ugt i32 [[TMP35]], [[TMP34]]
-// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i32 [[TMP34]], i32 [[TMP35]]
-// CHECK-NEXT: store i32 [[TMP37]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP34]] acquire, align 4
+// CHECK-NEXT: store i32 [[TMP35]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP36]], ptr [[UIX_ATOMIC_EXPECTED_PTR30]], align 4
+// CHECK-NEXT: store i32 [[TMP37]], ptr [[UIX_ATOMIC_DESIRED_PTR31]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED33:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR30]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED34:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR31]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR35:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED33]], i32 [[UIX_CMPXCHG_DESIRED34]] acquire acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV36:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR35]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV36]], ptr [[UIX_ATOMIC_EXPECTED_PTR32]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS37:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR35]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL38:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR32]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL38]], ptr [[UIV]], align 4
// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP38]], i32 [[TMP39]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i32, i1 } [[TMP40]], 0
-// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i32, i1 } [[TMP40]], 1
-// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i32 [[TMP38]], i32 [[TMP41]]
-// CHECK-NEXT: store i32 [[TMP43]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP44:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP44]] acquire, align 4
+// CHECK-NEXT: [[TMP39:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP38]] acquire, align 4
+// CHECK-NEXT: [[TMP40:%.*]] = icmp ult i32 [[TMP39]], [[TMP38]]
+// CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i32 [[TMP38]], i32 [[TMP39]]
+// CHECK-NEXT: store i32 [[TMP41]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP42:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP43:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP42]] acquire, align 4
+// CHECK-NEXT: [[TMP44:%.*]] = icmp ugt i32 [[TMP43]], [[TMP42]]
+// CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP44]], i32 [[TMP42]], i32 [[TMP43]]
// CHECK-NEXT: store i32 [[TMP45]], ptr [[UIV]], align 4
// CHECK-NEXT: [[TMP46:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP46]] acquire, align 4
-// CHECK-NEXT: store i32 [[TMP47]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP47:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP46]], ptr [[UIX_ATOMIC_EXPECTED_PTR39]], align 4
+// CHECK-NEXT: store i32 [[TMP47]], ptr [[UIX_ATOMIC_DESIRED_PTR40]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED42:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR39]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED43:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR40]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR44:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED42]], i32 [[UIX_CMPXCHG_DESIRED43]] acquire acquire, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV45:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR44]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV45]], ptr [[UIX_ATOMIC_EXPECTED_PTR41]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS46:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR44]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL47:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR41]], align 4
+// CHECK-NEXT: [[UIX_CAPTURE_CAPTURED48:%.*]] = select i1 [[UIX_CMPXCHG_SUCCESS46]], i32 [[TMP46]], i32 [[UIX_CAPTURE_ACTUAL47]]
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_CAPTURED48]], ptr [[UIV]], align 4
// CHECK-NEXT: [[TMP48:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP49:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP48]], i32 [[TMP49]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i32, i1 } [[TMP50]], 0
+// CHECK-NEXT: [[TMP49:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP48]] monotonic, align 4
+// CHECK-NEXT: store i32 [[TMP49]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP50:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP51:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP50]] monotonic, align 4
// CHECK-NEXT: store i32 [[TMP51]], ptr [[UIV]], align 4
// CHECK-NEXT: [[TMP52:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP52]] acquire, align 4
-// CHECK-NEXT: [[TMP54:%.*]] = icmp ult i32 [[TMP53]], [[TMP52]]
-// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i32 [[TMP52]], i32 [[TMP53]]
-// CHECK-NEXT: store i32 [[TMP55]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP56:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP56]] acquire, align 4
-// CHECK-NEXT: [[TMP58:%.*]] = icmp ugt i32 [[TMP57]], [[TMP56]]
-// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i32 [[TMP56]], i32 [[TMP57]]
-// CHECK-NEXT: store i32 [[TMP59]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP60:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP61:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP60]], i32 [[TMP61]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i32, i1 } [[TMP62]], 0
-// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i32, i1 } [[TMP62]], 1
-// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i32 [[TMP60]], i32 [[TMP63]]
+// CHECK-NEXT: [[TMP53:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP52]], ptr [[UIX_ATOMIC_EXPECTED_PTR49]], align 4
+// CHECK-NEXT: store i32 [[TMP53]], ptr [[UIX_ATOMIC_DESIRED_PTR50]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED52:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR49]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED53:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR50]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR54:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED52]], i32 [[UIX_CMPXCHG_DESIRED53]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV55:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR54]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV55]], ptr [[UIX_ATOMIC_EXPECTED_PTR51]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS56:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR54]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL57:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR51]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL57]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP54:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP55:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP54]] monotonic, align 4
+// CHECK-NEXT: [[TMP56:%.*]] = icmp ult i32 [[TMP55]], [[TMP54]]
+// CHECK-NEXT: [[TMP57:%.*]] = select i1 [[TMP56]], i32 [[TMP54]], i32 [[TMP55]]
+// CHECK-NEXT: store i32 [[TMP57]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP58:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP59:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP58]] monotonic, align 4
+// CHECK-NEXT: [[TMP60:%.*]] = icmp ugt i32 [[TMP59]], [[TMP58]]
+// CHECK-NEXT: [[TMP61:%.*]] = select i1 [[TMP60]], i32 [[TMP58]], i32 [[TMP59]]
+// CHECK-NEXT: store i32 [[TMP61]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP62:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP63:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP62]], ptr [[UIX_ATOMIC_EXPECTED_PTR58]], align 4
+// CHECK-NEXT: store i32 [[TMP63]], ptr [[UIX_ATOMIC_DESIRED_PTR59]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED61:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR58]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED62:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR59]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR63:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED61]], i32 [[UIX_CMPXCHG_DESIRED62]] monotonic monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV64:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR63]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV64]], ptr [[UIX_ATOMIC_EXPECTED_PTR60]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS65:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR63]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL66:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR60]], align 4
+// CHECK-NEXT: [[UIX_CAPTURE_CAPTURED67:%.*]] = select i1 [[UIX_CMPXCHG_SUCCESS65]], i32 [[TMP62]], i32 [[UIX_CAPTURE_ACTUAL66]]
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_CAPTURED67]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP64:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP65:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP64]] release, align 4
// CHECK-NEXT: store i32 [[TMP65]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP66:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP66]] monotonic, align 4
+// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP66]] release, align 4
// CHECK-NEXT: store i32 [[TMP67]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP68:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP68]] monotonic, align 4
-// CHECK-NEXT: store i32 [[TMP69]], ptr [[UIV]], align 4
+// CHECK-NEXT: [[TMP69:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP68]], ptr [[UIX_ATOMIC_EXPECTED_PTR68]], align 4
+// CHECK-NEXT: store i32 [[TMP69]], ptr [[UIX_ATOMIC_DESIRED_PTR69]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED71:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR68]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED72:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR69]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR73:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED71]], i32 [[UIX_CMPXCHG_DESIRED72]] release monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV74:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR73]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV74]], ptr [[UIX_ATOMIC_EXPECTED_PTR70]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS75:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR73]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL76:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR70]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL76]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP70:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP71:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP70]], i32 [[TMP71]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i32, i1 } [[TMP72]], 0
+// CHECK-NEXT: [[TMP71:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP70]] release, align 4
+// CHECK-NEXT: [[TMP72:%.*]] = icmp ult i32 [[TMP71]], [[TMP70]]
+// CHECK-NEXT: [[TMP73:%.*]] = select i1 [[TMP72]], i32 [[TMP70]], i32 [[TMP71]]
// CHECK-NEXT: store i32 [[TMP73]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP74:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP74]] monotonic, align 4
-// CHECK-NEXT: [[TMP76:%.*]] = icmp ult i32 [[TMP75]], [[TMP74]]
+// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP74]] release, align 4
+// CHECK-NEXT: [[TMP76:%.*]] = icmp ugt i32 [[TMP75]], [[TMP74]]
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i32 [[TMP74]], i32 [[TMP75]]
// CHECK-NEXT: store i32 [[TMP77]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP78:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP78]] monotonic, align 4
-// CHECK-NEXT: [[TMP80:%.*]] = icmp ugt i32 [[TMP79]], [[TMP78]]
-// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i32 [[TMP78]], i32 [[TMP79]]
+// CHECK-NEXT: [[TMP79:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP78]], ptr [[UIX_ATOMIC_EXPECTED_PTR77]], align 4
+// CHECK-NEXT: store i32 [[TMP79]], ptr [[UIX_ATOMIC_DESIRED_PTR78]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED80:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR77]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED81:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR78]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR82:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED80]], i32 [[UIX_CMPXCHG_DESIRED81]] release monotonic, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV83:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR82]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV83]], ptr [[UIX_ATOMIC_EXPECTED_PTR79]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS84:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR82]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL85:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR79]], align 4
+// CHECK-NEXT: [[UIX_CAPTURE_CAPTURED86:%.*]] = select i1 [[UIX_CMPXCHG_SUCCESS84]], i32 [[TMP78]], i32 [[UIX_CAPTURE_ACTUAL85]]
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_CAPTURED86]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP80:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP81:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP80]] seq_cst, align 4
// CHECK-NEXT: store i32 [[TMP81]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP82:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP83:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP82]], i32 [[TMP83]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i32, i1 } [[TMP84]], 0
-// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i32, i1 } [[TMP84]], 1
-// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i32 [[TMP82]], i32 [[TMP85]]
-// CHECK-NEXT: store i32 [[TMP87]], ptr [[UIV]], align 4
-// CHECK-NEXT: [[TMP88:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP88]] release, align 4
+// CHECK-NEXT: [[TMP83:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP82]] seq_cst, align 4
+// CHECK-NEXT: store i32 [[TMP83]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP84:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP85:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP84]], ptr [[UIX_ATOMIC_EXPECTED_PTR87]], align 4
+// CHECK-NEXT: store i32 [[TMP85]], ptr [[UIX_ATOMIC_DESIRED_PTR88]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED90:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR87]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED91:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR88]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR92:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED90]], i32 [[UIX_CMPXCHG_DESIRED91]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV93:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR92]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV93]], ptr [[UIX_ATOMIC_EXPECTED_PTR89]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS94:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR92]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL95:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR89]], align 4
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_ACTUAL95]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP86:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP86]] seq_cst, align 4
+// CHECK-NEXT: [[TMP88:%.*]] = icmp ult i32 [[TMP87]], [[TMP86]]
+// CHECK-NEXT: [[TMP89:%.*]] = select i1 [[TMP88]], i32 [[TMP86]], i32 [[TMP87]]
// CHECK-NEXT: store i32 [[TMP89]], ptr [[UIV]], align 4
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP90:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP90]] release, align 4
-// CHECK-NEXT: store i32 [[TMP91]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP92:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP93:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP92]], i32 [[TMP93]] release monotonic, align 4
-// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i32, i1 } [[TMP94]], 0
-// CHECK-NEXT: store i32 [[TMP95]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP96:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP96]] release, align 4
-// CHECK-NEXT: [[TMP98:%.*]] = icmp ult i32 [[TMP97]], [[TMP96]]
-// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i32 [[TMP96]], i32 [[TMP97]]
-// CHECK-NEXT: store i32 [[TMP99]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP100:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP100]] release, align 4
-// CHECK-NEXT: [[TMP102:%.*]] = icmp ugt i32 [[TMP101]], [[TMP100]]
-// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i32 [[TMP100]], i32 [[TMP101]]
-// CHECK-NEXT: store i32 [[TMP103]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP104:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP105:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP104]], i32 [[TMP105]] release monotonic, align 4
-// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i32, i1 } [[TMP106]], 0
-// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i32, i1 } [[TMP106]], 1
-// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i32 [[TMP104]], i32 [[TMP107]]
-// CHECK-NEXT: store i32 [[TMP109]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP110:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP110]] seq_cst, align 4
-// CHECK-NEXT: store i32 [[TMP111]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP112:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP112]] seq_cst, align 4
-// CHECK-NEXT: store i32 [[TMP113]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP114:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP115:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP114]], i32 [[TMP115]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i32, i1 } [[TMP116]], 0
-// CHECK-NEXT: store i32 [[TMP117]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP118:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw umin ptr [[UIX]], i32 [[TMP118]] seq_cst, align 4
-// CHECK-NEXT: [[TMP120:%.*]] = icmp ult i32 [[TMP119]], [[TMP118]]
-// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i32 [[TMP118]], i32 [[TMP119]]
-// CHECK-NEXT: store i32 [[TMP121]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP122:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP122]] seq_cst, align 4
-// CHECK-NEXT: [[TMP124:%.*]] = icmp ugt i32 [[TMP123]], [[TMP122]]
-// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i32 [[TMP122]], i32 [[TMP123]]
-// CHECK-NEXT: store i32 [[TMP125]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP126:%.*]] = load i32, ptr [[UIE]], align 4
-// CHECK-NEXT: [[TMP127:%.*]] = load i32, ptr [[UID]], align 4
-// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[UIX]], i32 [[TMP126]], i32 [[TMP127]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i32, i1 } [[TMP128]], 0
-// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i32, i1 } [[TMP128]], 1
-// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i32 [[TMP126]], i32 [[TMP129]]
-// CHECK-NEXT: store i32 [[TMP131]], ptr [[UIV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP132:%.*]] = load i32, ptr [[UIV]], align 4
-// CHECK-NEXT: ret i32 [[TMP132]]
+// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw umax ptr [[UIX]], i32 [[TMP90]] seq_cst, align 4
+// CHECK-NEXT: [[TMP92:%.*]] = icmp ugt i32 [[TMP91]], [[TMP90]]
+// CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP92]], i32 [[TMP90]], i32 [[TMP91]]
+// CHECK-NEXT: store i32 [[TMP93]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP94:%.*]] = load i32, ptr [[UIE]], align 4
+// CHECK-NEXT: [[TMP95:%.*]] = load i32, ptr [[UID]], align 4
+// CHECK-NEXT: store i32 [[TMP94]], ptr [[UIX_ATOMIC_EXPECTED_PTR96]], align 4
+// CHECK-NEXT: store i32 [[TMP95]], ptr [[UIX_ATOMIC_DESIRED_PTR97]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_EXPECTED99:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR96]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_DESIRED100:%.*]] = load i32, ptr [[UIX_ATOMIC_DESIRED_PTR97]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PAIR101:%.*]] = cmpxchg ptr [[UIX]], i32 [[UIX_CMPXCHG_EXPECTED99]], i32 [[UIX_CMPXCHG_DESIRED100]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_PREV102:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR101]], 0
+// CHECK-NEXT: store i32 [[UIX_CMPXCHG_PREV102]], ptr [[UIX_ATOMIC_EXPECTED_PTR98]], align 4
+// CHECK-NEXT: [[UIX_CMPXCHG_SUCCESS103:%.*]] = extractvalue { i32, i1 } [[UIX_CMPXCHG_PAIR101]], 1
+// CHECK-NEXT: [[UIX_CAPTURE_ACTUAL104:%.*]] = load i32, ptr [[UIX_ATOMIC_EXPECTED_PTR98]], align 4
+// CHECK-NEXT: [[UIX_CAPTURE_CAPTURED105:%.*]] = select i1 [[UIX_CMPXCHG_SUCCESS103]], i32 [[TMP94]], i32 [[UIX_CAPTURE_ACTUAL104]]
+// CHECK-NEXT: store i32 [[UIX_CAPTURE_CAPTURED105]], ptr [[UIV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP96:%.*]] = load i32, ptr [[UIV]], align 4
+// CHECK-NEXT: ret i32 [[TMP96]]
//
//
// CHECK-LABEL: @lxevd(
@@ -26623,6 +35851,42 @@ double fail_dxevd() {
// CHECK-NEXT: [[LV:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[LE:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[LD:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR1:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR2:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR3:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR4:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR11:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR12:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR13:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR20:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR21:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR22:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR30:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR31:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR32:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR39:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR40:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR41:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR49:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR50:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR51:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR58:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR59:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR60:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR68:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR69:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR70:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR77:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR78:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR79:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR87:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR88:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR89:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR96:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_DESIRED_PTR97:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LX_ATOMIC_EXPECTED_PTR98:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[LE]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP0]] monotonic, align 8
// CHECK-NEXT: store i64 [[TMP1]], ptr [[LV]], align 8
@@ -26631,186 +35895,264 @@ double fail_dxevd() {
// CHECK-NEXT: store i64 [[TMP3]], ptr [[LV]], align 8
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[LE]], align 8
// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP4]], i64 [[TMP5]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
-// CHECK-NEXT: store i64 [[TMP7]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP8]] monotonic, align 8
-// CHECK-NEXT: [[TMP10:%.*]] = icmp slt i64 [[TMP9]], [[TMP8]]
-// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP8]], i64 [[TMP9]]
-// CHECK-NEXT: store i64 [[TMP11]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP12]] monotonic, align 8
-// CHECK-NEXT: [[TMP14:%.*]] = icmp sgt i64 [[TMP13]], [[TMP12]]
-// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP12]], i64 [[TMP13]]
-// CHECK-NEXT: store i64 [[TMP15]], ptr [[LV]], align 8
+// CHECK-NEXT: store i64 [[TMP4]], ptr [[LX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: store i64 [[TMP5]], ptr [[LX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED]], i64 [[LX_CMPXCHG_DESIRED]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV]], ptr [[LX_ATOMIC_EXPECTED_PTR1]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR1]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP7:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP6]] monotonic, align 8
+// CHECK-NEXT: [[TMP8:%.*]] = icmp slt i64 [[TMP7]], [[TMP6]]
+// CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i64 [[TMP6]], i64 [[TMP7]]
+// CHECK-NEXT: store i64 [[TMP9]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP11:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP10]] monotonic, align 8
+// CHECK-NEXT: [[TMP12:%.*]] = icmp sgt i64 [[TMP11]], [[TMP10]]
+// CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i64 [[TMP10]], i64 [[TMP11]]
+// CHECK-NEXT: store i64 [[TMP13]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP15:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP14]], ptr [[LX_ATOMIC_EXPECTED_PTR2]], align 8
+// CHECK-NEXT: store i64 [[TMP15]], ptr [[LX_ATOMIC_DESIRED_PTR3]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED5:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR2]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED6:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR3]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR7:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED5]], i64 [[LX_CMPXCHG_DESIRED6]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV8:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR7]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV8]], ptr [[LX_ATOMIC_EXPECTED_PTR4]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS9:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR7]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL10:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR4]], align 8
+// CHECK-NEXT: [[LX_CAPTURE_CAPTURED:%.*]] = select i1 [[LX_CMPXCHG_SUCCESS9]], i64 [[TMP14]], i64 [[LX_CAPTURE_ACTUAL10]]
+// CHECK-NEXT: store i64 [[LX_CAPTURE_CAPTURED]], ptr [[LV]], align 8
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP17:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP16]], i64 [[TMP17]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i64, i1 } [[TMP18]], 0
-// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i64, i1 } [[TMP18]], 1
-// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i64 [[TMP16]], i64 [[TMP19]]
-// CHECK-NEXT: store i64 [[TMP21]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP17:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP16]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP17]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP18:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP19:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP18]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP19]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP21:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP20]], ptr [[LX_ATOMIC_EXPECTED_PTR11]], align 8
+// CHECK-NEXT: store i64 [[TMP21]], ptr [[LX_ATOMIC_DESIRED_PTR12]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED14:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR11]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED15:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR12]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR16:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED14]], i64 [[LX_CMPXCHG_DESIRED15]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV17:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR16]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV17]], ptr [[LX_ATOMIC_EXPECTED_PTR13]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS18:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR16]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL19:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR13]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL19]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP22:%.*]] = load i64, ptr [[LE]], align 8
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP22]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP23]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP24]] acq_rel, align 8
+// CHECK-NEXT: [[TMP24:%.*]] = icmp slt i64 [[TMP23]], [[TMP22]]
+// CHECK-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], i64 [[TMP22]], i64 [[TMP23]]
// CHECK-NEXT: store i64 [[TMP25]], ptr [[LV]], align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP26:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP26]], i64 [[TMP27]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i64, i1 } [[TMP28]], 0
+// CHECK-NEXT: [[TMP27:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP26]] acq_rel, align 8
+// CHECK-NEXT: [[TMP28:%.*]] = icmp sgt i64 [[TMP27]], [[TMP26]]
+// CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i64 [[TMP26]], i64 [[TMP27]]
// CHECK-NEXT: store i64 [[TMP29]], ptr [[LV]], align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP30:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP30]] acq_rel, align 8
-// CHECK-NEXT: [[TMP32:%.*]] = icmp slt i64 [[TMP31]], [[TMP30]]
-// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i64 [[TMP30]], i64 [[TMP31]]
+// CHECK-NEXT: [[TMP31:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP30]], ptr [[LX_ATOMIC_EXPECTED_PTR20]], align 8
+// CHECK-NEXT: store i64 [[TMP31]], ptr [[LX_ATOMIC_DESIRED_PTR21]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED23:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR20]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED24:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR21]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR25:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED23]], i64 [[LX_CMPXCHG_DESIRED24]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV26:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR25]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV26]], ptr [[LX_ATOMIC_EXPECTED_PTR22]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS27:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR25]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL28:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR22]], align 8
+// CHECK-NEXT: [[LX_CAPTURE_CAPTURED29:%.*]] = select i1 [[LX_CMPXCHG_SUCCESS27]], i64 [[TMP30]], i64 [[LX_CAPTURE_ACTUAL28]]
+// CHECK-NEXT: store i64 [[LX_CAPTURE_CAPTURED29]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP33:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP32]] acquire, align 8
// CHECK-NEXT: store i64 [[TMP33]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP34:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP34]] acq_rel, align 8
-// CHECK-NEXT: [[TMP36:%.*]] = icmp sgt i64 [[TMP35]], [[TMP34]]
-// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i64 [[TMP34]], i64 [[TMP35]]
-// CHECK-NEXT: store i64 [[TMP37]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP34]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP35]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP37:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP36]], ptr [[LX_ATOMIC_EXPECTED_PTR30]], align 8
+// CHECK-NEXT: store i64 [[TMP37]], ptr [[LX_ATOMIC_DESIRED_PTR31]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED33:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR30]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED34:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR31]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR35:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED33]], i64 [[LX_CMPXCHG_DESIRED34]] acquire acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV36:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR35]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV36]], ptr [[LX_ATOMIC_EXPECTED_PTR32]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS37:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR35]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL38:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR32]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL38]], ptr [[LV]], align 8
// CHECK-NEXT: [[TMP38:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP39:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP38]], i64 [[TMP39]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i64, i1 } [[TMP40]], 0
-// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i64, i1 } [[TMP40]], 1
-// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i64 [[TMP38]], i64 [[TMP41]]
-// CHECK-NEXT: store i64 [[TMP43]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP44]] acquire, align 8
+// CHECK-NEXT: [[TMP39:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP38]] acquire, align 8
+// CHECK-NEXT: [[TMP40:%.*]] = icmp slt i64 [[TMP39]], [[TMP38]]
+// CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i64 [[TMP38]], i64 [[TMP39]]
+// CHECK-NEXT: store i64 [[TMP41]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP42:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP43:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP42]] acquire, align 8
+// CHECK-NEXT: [[TMP44:%.*]] = icmp sgt i64 [[TMP43]], [[TMP42]]
+// CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP44]], i64 [[TMP42]], i64 [[TMP43]]
// CHECK-NEXT: store i64 [[TMP45]], ptr [[LV]], align 8
// CHECK-NEXT: [[TMP46:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP46]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP47]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP47:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP46]], ptr [[LX_ATOMIC_EXPECTED_PTR39]], align 8
+// CHECK-NEXT: store i64 [[TMP47]], ptr [[LX_ATOMIC_DESIRED_PTR40]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED42:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR39]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED43:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR40]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR44:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED42]], i64 [[LX_CMPXCHG_DESIRED43]] acquire acquire, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV45:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR44]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV45]], ptr [[LX_ATOMIC_EXPECTED_PTR41]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS46:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR44]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL47:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR41]], align 8
+// CHECK-NEXT: [[LX_CAPTURE_CAPTURED48:%.*]] = select i1 [[LX_CMPXCHG_SUCCESS46]], i64 [[TMP46]], i64 [[LX_CAPTURE_ACTUAL47]]
+// CHECK-NEXT: store i64 [[LX_CAPTURE_CAPTURED48]], ptr [[LV]], align 8
// CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP49:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP48]], i64 [[TMP49]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i64, i1 } [[TMP50]], 0
+// CHECK-NEXT: [[TMP49:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP48]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP49]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP50:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP51:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP50]] monotonic, align 8
// CHECK-NEXT: store i64 [[TMP51]], ptr [[LV]], align 8
// CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP52]] acquire, align 8
-// CHECK-NEXT: [[TMP54:%.*]] = icmp slt i64 [[TMP53]], [[TMP52]]
-// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i64 [[TMP52]], i64 [[TMP53]]
-// CHECK-NEXT: store i64 [[TMP55]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP56]] acquire, align 8
-// CHECK-NEXT: [[TMP58:%.*]] = icmp sgt i64 [[TMP57]], [[TMP56]]
-// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i64 [[TMP56]], i64 [[TMP57]]
-// CHECK-NEXT: store i64 [[TMP59]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP61:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP60]], i64 [[TMP61]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i64, i1 } [[TMP62]], 0
-// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i64, i1 } [[TMP62]], 1
-// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i64 [[TMP60]], i64 [[TMP63]]
+// CHECK-NEXT: [[TMP53:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP52]], ptr [[LX_ATOMIC_EXPECTED_PTR49]], align 8
+// CHECK-NEXT: store i64 [[TMP53]], ptr [[LX_ATOMIC_DESIRED_PTR50]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED52:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR49]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED53:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR50]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR54:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED52]], i64 [[LX_CMPXCHG_DESIRED53]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV55:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR54]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV55]], ptr [[LX_ATOMIC_EXPECTED_PTR51]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS56:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR54]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL57:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR51]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL57]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP54:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP55:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP54]] monotonic, align 8
+// CHECK-NEXT: [[TMP56:%.*]] = icmp slt i64 [[TMP55]], [[TMP54]]
+// CHECK-NEXT: [[TMP57:%.*]] = select i1 [[TMP56]], i64 [[TMP54]], i64 [[TMP55]]
+// CHECK-NEXT: store i64 [[TMP57]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP58:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP59:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP58]] monotonic, align 8
+// CHECK-NEXT: [[TMP60:%.*]] = icmp sgt i64 [[TMP59]], [[TMP58]]
+// CHECK-NEXT: [[TMP61:%.*]] = select i1 [[TMP60]], i64 [[TMP58]], i64 [[TMP59]]
+// CHECK-NEXT: store i64 [[TMP61]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP62:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP63:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP62]], ptr [[LX_ATOMIC_EXPECTED_PTR58]], align 8
+// CHECK-NEXT: store i64 [[TMP63]], ptr [[LX_ATOMIC_DESIRED_PTR59]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED61:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR58]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED62:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR59]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR63:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED61]], i64 [[LX_CMPXCHG_DESIRED62]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV64:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR63]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV64]], ptr [[LX_ATOMIC_EXPECTED_PTR60]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS65:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR63]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL66:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR60]], align 8
+// CHECK-NEXT: [[LX_CAPTURE_CAPTURED67:%.*]] = select i1 [[LX_CMPXCHG_SUCCESS65]], i64 [[TMP62]], i64 [[LX_CAPTURE_ACTUAL66]]
+// CHECK-NEXT: store i64 [[LX_CAPTURE_CAPTURED67]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP64:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP65:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP64]] release, align 8
// CHECK-NEXT: store i64 [[TMP65]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP66:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP66]] monotonic, align 8
+// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP66]] release, align 8
// CHECK-NEXT: store i64 [[TMP67]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP68:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP68]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP69]], ptr [[LV]], align 8
+// CHECK-NEXT: [[TMP69:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP68]], ptr [[LX_ATOMIC_EXPECTED_PTR68]], align 8
+// CHECK-NEXT: store i64 [[TMP69]], ptr [[LX_ATOMIC_DESIRED_PTR69]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED71:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR68]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED72:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR69]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR73:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED71]], i64 [[LX_CMPXCHG_DESIRED72]] release monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV74:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR73]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV74]], ptr [[LX_ATOMIC_EXPECTED_PTR70]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS75:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR73]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL76:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR70]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL76]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP70:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP71:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP70]], i64 [[TMP71]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i64, i1 } [[TMP72]], 0
+// CHECK-NEXT: [[TMP71:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP70]] release, align 8
+// CHECK-NEXT: [[TMP72:%.*]] = icmp slt i64 [[TMP71]], [[TMP70]]
+// CHECK-NEXT: [[TMP73:%.*]] = select i1 [[TMP72]], i64 [[TMP70]], i64 [[TMP71]]
// CHECK-NEXT: store i64 [[TMP73]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP74:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP74]] monotonic, align 8
-// CHECK-NEXT: [[TMP76:%.*]] = icmp slt i64 [[TMP75]], [[TMP74]]
+// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP74]] release, align 8
+// CHECK-NEXT: [[TMP76:%.*]] = icmp sgt i64 [[TMP75]], [[TMP74]]
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i64 [[TMP74]], i64 [[TMP75]]
// CHECK-NEXT: store i64 [[TMP77]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP78:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP78]] monotonic, align 8
-// CHECK-NEXT: [[TMP80:%.*]] = icmp sgt i64 [[TMP79]], [[TMP78]]
-// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i64 [[TMP78]], i64 [[TMP79]]
+// CHECK-NEXT: [[TMP79:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP78]], ptr [[LX_ATOMIC_EXPECTED_PTR77]], align 8
+// CHECK-NEXT: store i64 [[TMP79]], ptr [[LX_ATOMIC_DESIRED_PTR78]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED80:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR77]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED81:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR78]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR82:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED80]], i64 [[LX_CMPXCHG_DESIRED81]] release monotonic, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV83:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR82]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV83]], ptr [[LX_ATOMIC_EXPECTED_PTR79]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS84:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR82]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL85:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR79]], align 8
+// CHECK-NEXT: [[LX_CAPTURE_CAPTURED86:%.*]] = select i1 [[LX_CMPXCHG_SUCCESS84]], i64 [[TMP78]], i64 [[LX_CAPTURE_ACTUAL85]]
+// CHECK-NEXT: store i64 [[LX_CAPTURE_CAPTURED86]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP80:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP81:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP80]] seq_cst, align 8
// CHECK-NEXT: store i64 [[TMP81]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP82:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP83:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP82]], i64 [[TMP83]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i64, i1 } [[TMP84]], 0
-// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i64, i1 } [[TMP84]], 1
-// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i64 [[TMP82]], i64 [[TMP85]]
-// CHECK-NEXT: store i64 [[TMP87]], ptr [[LV]], align 8
-// CHECK-NEXT: [[TMP88:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP88]] release, align 8
+// CHECK-NEXT: [[TMP83:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP82]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP83]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP84:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP85:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP84]], ptr [[LX_ATOMIC_EXPECTED_PTR87]], align 8
+// CHECK-NEXT: store i64 [[TMP85]], ptr [[LX_ATOMIC_DESIRED_PTR88]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED90:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR87]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED91:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR88]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR92:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED90]], i64 [[LX_CMPXCHG_DESIRED91]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV93:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR92]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV93]], ptr [[LX_ATOMIC_EXPECTED_PTR89]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS94:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR92]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL95:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR89]], align 8
+// CHECK-NEXT: store i64 [[LX_CAPTURE_ACTUAL95]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP86:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP86]] seq_cst, align 8
+// CHECK-NEXT: [[TMP88:%.*]] = icmp slt i64 [[TMP87]], [[TMP86]]
+// CHECK-NEXT: [[TMP89:%.*]] = select i1 [[TMP88]], i64 [[TMP86]], i64 [[TMP87]]
// CHECK-NEXT: store i64 [[TMP89]], ptr [[LV]], align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP90:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP90]] release, align 8
-// CHECK-NEXT: store i64 [[TMP91]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP92:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP93:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP92]], i64 [[TMP93]] release monotonic, align 8
-// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i64, i1 } [[TMP94]], 0
-// CHECK-NEXT: store i64 [[TMP95]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP96:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP96]] release, align 8
-// CHECK-NEXT: [[TMP98:%.*]] = icmp slt i64 [[TMP97]], [[TMP96]]
-// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i64 [[TMP96]], i64 [[TMP97]]
-// CHECK-NEXT: store i64 [[TMP99]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP100:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP100]] release, align 8
-// CHECK-NEXT: [[TMP102:%.*]] = icmp sgt i64 [[TMP101]], [[TMP100]]
-// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i64 [[TMP100]], i64 [[TMP101]]
-// CHECK-NEXT: store i64 [[TMP103]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP104:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP105:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP104]], i64 [[TMP105]] release monotonic, align 8
-// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i64, i1 } [[TMP106]], 0
-// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP106]], 1
-// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i64 [[TMP104]], i64 [[TMP107]]
-// CHECK-NEXT: store i64 [[TMP109]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP110:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP110]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP111]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP112:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP112]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP113]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP114:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP115:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP114]], i64 [[TMP115]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i64, i1 } [[TMP116]], 0
-// CHECK-NEXT: store i64 [[TMP117]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP118:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw min ptr [[LX]], i64 [[TMP118]] seq_cst, align 8
-// CHECK-NEXT: [[TMP120:%.*]] = icmp slt i64 [[TMP119]], [[TMP118]]
-// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i64 [[TMP118]], i64 [[TMP119]]
-// CHECK-NEXT: store i64 [[TMP121]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP122:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP122]] seq_cst, align 8
-// CHECK-NEXT: [[TMP124:%.*]] = icmp sgt i64 [[TMP123]], [[TMP122]]
-// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i64 [[TMP122]], i64 [[TMP123]]
-// CHECK-NEXT: store i64 [[TMP125]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP126:%.*]] = load i64, ptr [[LE]], align 8
-// CHECK-NEXT: [[TMP127:%.*]] = load i64, ptr [[LD]], align 8
-// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[LX]], i64 [[TMP126]], i64 [[TMP127]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i64, i1 } [[TMP128]], 0
-// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i64, i1 } [[TMP128]], 1
-// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i64 [[TMP126]], i64 [[TMP129]]
-// CHECK-NEXT: store i64 [[TMP131]], ptr [[LV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP132:%.*]] = load i64, ptr [[LV]], align 8
-// CHECK-NEXT: ret i64 [[TMP132]]
+// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw max ptr [[LX]], i64 [[TMP90]] seq_cst, align 8
+// CHECK-NEXT: [[TMP92:%.*]] = icmp sgt i64 [[TMP91]], [[TMP90]]
+// CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP92]], i64 [[TMP90]], i64 [[TMP91]]
+// CHECK-NEXT: store i64 [[TMP93]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP94:%.*]] = load i64, ptr [[LE]], align 8
+// CHECK-NEXT: [[TMP95:%.*]] = load i64, ptr [[LD]], align 8
+// CHECK-NEXT: store i64 [[TMP94]], ptr [[LX_ATOMIC_EXPECTED_PTR96]], align 8
+// CHECK-NEXT: store i64 [[TMP95]], ptr [[LX_ATOMIC_DESIRED_PTR97]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_EXPECTED99:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR96]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_DESIRED100:%.*]] = load i64, ptr [[LX_ATOMIC_DESIRED_PTR97]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PAIR101:%.*]] = cmpxchg ptr [[LX]], i64 [[LX_CMPXCHG_EXPECTED99]], i64 [[LX_CMPXCHG_DESIRED100]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LX_CMPXCHG_PREV102:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR101]], 0
+// CHECK-NEXT: store i64 [[LX_CMPXCHG_PREV102]], ptr [[LX_ATOMIC_EXPECTED_PTR98]], align 8
+// CHECK-NEXT: [[LX_CMPXCHG_SUCCESS103:%.*]] = extractvalue { i64, i1 } [[LX_CMPXCHG_PAIR101]], 1
+// CHECK-NEXT: [[LX_CAPTURE_ACTUAL104:%.*]] = load i64, ptr [[LX_ATOMIC_EXPECTED_PTR98]], align 8
+// CHECK-NEXT: [[LX_CAPTURE_CAPTURED105:%.*]] = select i1 [[LX_CMPXCHG_SUCCESS103]], i64 [[TMP94]], i64 [[LX_CAPTURE_ACTUAL104]]
+// CHECK-NEXT: store i64 [[LX_CAPTURE_CAPTURED105]], ptr [[LV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP96:%.*]] = load i64, ptr [[LV]], align 8
+// CHECK-NEXT: ret i64 [[TMP96]]
//
//
// CHECK-LABEL: @ulxevd(
@@ -26819,6 +36161,42 @@ double fail_dxevd() {
// CHECK-NEXT: [[ULV:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[ULE:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[ULD:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR1:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR2:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR3:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR4:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR11:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR12:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR13:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR20:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR21:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR22:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR30:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR31:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR32:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR39:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR40:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR41:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR49:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR50:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR51:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR58:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR59:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR60:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR68:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR69:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR70:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR77:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR78:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR79:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR87:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR88:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR89:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR96:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_DESIRED_PTR97:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULX_ATOMIC_EXPECTED_PTR98:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[ULE]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP0]] monotonic, align 8
// CHECK-NEXT: store i64 [[TMP1]], ptr [[ULV]], align 8
@@ -26827,186 +36205,264 @@ double fail_dxevd() {
// CHECK-NEXT: store i64 [[TMP3]], ptr [[ULV]], align 8
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[ULE]], align 8
// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP4]], i64 [[TMP5]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
-// CHECK-NEXT: store i64 [[TMP7]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP8]] monotonic, align 8
-// CHECK-NEXT: [[TMP10:%.*]] = icmp ult i64 [[TMP9]], [[TMP8]]
-// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP8]], i64 [[TMP9]]
-// CHECK-NEXT: store i64 [[TMP11]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP12]] monotonic, align 8
-// CHECK-NEXT: [[TMP14:%.*]] = icmp ugt i64 [[TMP13]], [[TMP12]]
-// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP12]], i64 [[TMP13]]
-// CHECK-NEXT: store i64 [[TMP15]], ptr [[ULV]], align 8
+// CHECK-NEXT: store i64 [[TMP4]], ptr [[ULX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: store i64 [[TMP5]], ptr [[ULX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED]], i64 [[ULX_CMPXCHG_DESIRED]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV]], ptr [[ULX_ATOMIC_EXPECTED_PTR1]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR1]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP7:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP6]] monotonic, align 8
+// CHECK-NEXT: [[TMP8:%.*]] = icmp ult i64 [[TMP7]], [[TMP6]]
+// CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i64 [[TMP6]], i64 [[TMP7]]
+// CHECK-NEXT: store i64 [[TMP9]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP11:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP10]] monotonic, align 8
+// CHECK-NEXT: [[TMP12:%.*]] = icmp ugt i64 [[TMP11]], [[TMP10]]
+// CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i64 [[TMP10]], i64 [[TMP11]]
+// CHECK-NEXT: store i64 [[TMP13]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP15:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP14]], ptr [[ULX_ATOMIC_EXPECTED_PTR2]], align 8
+// CHECK-NEXT: store i64 [[TMP15]], ptr [[ULX_ATOMIC_DESIRED_PTR3]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED5:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR2]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED6:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR3]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR7:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED5]], i64 [[ULX_CMPXCHG_DESIRED6]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV8:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR7]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV8]], ptr [[ULX_ATOMIC_EXPECTED_PTR4]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS9:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR7]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL10:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR4]], align 8
+// CHECK-NEXT: [[ULX_CAPTURE_CAPTURED:%.*]] = select i1 [[ULX_CMPXCHG_SUCCESS9]], i64 [[TMP14]], i64 [[ULX_CAPTURE_ACTUAL10]]
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_CAPTURED]], ptr [[ULV]], align 8
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP17:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP16]], i64 [[TMP17]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i64, i1 } [[TMP18]], 0
-// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i64, i1 } [[TMP18]], 1
-// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i64 [[TMP16]], i64 [[TMP19]]
-// CHECK-NEXT: store i64 [[TMP21]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP17:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP16]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP17]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP18:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP19:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP18]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP19]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP21:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP20]], ptr [[ULX_ATOMIC_EXPECTED_PTR11]], align 8
+// CHECK-NEXT: store i64 [[TMP21]], ptr [[ULX_ATOMIC_DESIRED_PTR12]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED14:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR11]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED15:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR12]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR16:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED14]], i64 [[ULX_CMPXCHG_DESIRED15]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV17:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR16]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV17]], ptr [[ULX_ATOMIC_EXPECTED_PTR13]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS18:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR16]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL19:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR13]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL19]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP22:%.*]] = load i64, ptr [[ULE]], align 8
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP22]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP23]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP24]] acq_rel, align 8
+// CHECK-NEXT: [[TMP24:%.*]] = icmp ult i64 [[TMP23]], [[TMP22]]
+// CHECK-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], i64 [[TMP22]], i64 [[TMP23]]
// CHECK-NEXT: store i64 [[TMP25]], ptr [[ULV]], align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP26:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP26]], i64 [[TMP27]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i64, i1 } [[TMP28]], 0
+// CHECK-NEXT: [[TMP27:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP26]] acq_rel, align 8
+// CHECK-NEXT: [[TMP28:%.*]] = icmp ugt i64 [[TMP27]], [[TMP26]]
+// CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i64 [[TMP26]], i64 [[TMP27]]
// CHECK-NEXT: store i64 [[TMP29]], ptr [[ULV]], align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP30:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP30]] acq_rel, align 8
-// CHECK-NEXT: [[TMP32:%.*]] = icmp ult i64 [[TMP31]], [[TMP30]]
-// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i64 [[TMP30]], i64 [[TMP31]]
+// CHECK-NEXT: [[TMP31:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP30]], ptr [[ULX_ATOMIC_EXPECTED_PTR20]], align 8
+// CHECK-NEXT: store i64 [[TMP31]], ptr [[ULX_ATOMIC_DESIRED_PTR21]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED23:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR20]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED24:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR21]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR25:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED23]], i64 [[ULX_CMPXCHG_DESIRED24]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV26:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR25]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV26]], ptr [[ULX_ATOMIC_EXPECTED_PTR22]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS27:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR25]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL28:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR22]], align 8
+// CHECK-NEXT: [[ULX_CAPTURE_CAPTURED29:%.*]] = select i1 [[ULX_CMPXCHG_SUCCESS27]], i64 [[TMP30]], i64 [[ULX_CAPTURE_ACTUAL28]]
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_CAPTURED29]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP33:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP32]] acquire, align 8
// CHECK-NEXT: store i64 [[TMP33]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP34:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP34]] acq_rel, align 8
-// CHECK-NEXT: [[TMP36:%.*]] = icmp ugt i64 [[TMP35]], [[TMP34]]
-// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i64 [[TMP34]], i64 [[TMP35]]
-// CHECK-NEXT: store i64 [[TMP37]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP34]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP35]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP37:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP36]], ptr [[ULX_ATOMIC_EXPECTED_PTR30]], align 8
+// CHECK-NEXT: store i64 [[TMP37]], ptr [[ULX_ATOMIC_DESIRED_PTR31]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED33:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR30]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED34:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR31]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR35:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED33]], i64 [[ULX_CMPXCHG_DESIRED34]] acquire acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV36:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR35]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV36]], ptr [[ULX_ATOMIC_EXPECTED_PTR32]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS37:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR35]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL38:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR32]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL38]], ptr [[ULV]], align 8
// CHECK-NEXT: [[TMP38:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP39:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP38]], i64 [[TMP39]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i64, i1 } [[TMP40]], 0
-// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i64, i1 } [[TMP40]], 1
-// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i64 [[TMP38]], i64 [[TMP41]]
-// CHECK-NEXT: store i64 [[TMP43]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP44]] acquire, align 8
+// CHECK-NEXT: [[TMP39:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP38]] acquire, align 8
+// CHECK-NEXT: [[TMP40:%.*]] = icmp ult i64 [[TMP39]], [[TMP38]]
+// CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i64 [[TMP38]], i64 [[TMP39]]
+// CHECK-NEXT: store i64 [[TMP41]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP42:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP43:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP42]] acquire, align 8
+// CHECK-NEXT: [[TMP44:%.*]] = icmp ugt i64 [[TMP43]], [[TMP42]]
+// CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP44]], i64 [[TMP42]], i64 [[TMP43]]
// CHECK-NEXT: store i64 [[TMP45]], ptr [[ULV]], align 8
// CHECK-NEXT: [[TMP46:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP46]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP47]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP47:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP46]], ptr [[ULX_ATOMIC_EXPECTED_PTR39]], align 8
+// CHECK-NEXT: store i64 [[TMP47]], ptr [[ULX_ATOMIC_DESIRED_PTR40]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED42:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR39]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED43:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR40]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR44:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED42]], i64 [[ULX_CMPXCHG_DESIRED43]] acquire acquire, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV45:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR44]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV45]], ptr [[ULX_ATOMIC_EXPECTED_PTR41]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS46:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR44]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL47:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR41]], align 8
+// CHECK-NEXT: [[ULX_CAPTURE_CAPTURED48:%.*]] = select i1 [[ULX_CMPXCHG_SUCCESS46]], i64 [[TMP46]], i64 [[ULX_CAPTURE_ACTUAL47]]
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_CAPTURED48]], ptr [[ULV]], align 8
// CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP49:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP48]], i64 [[TMP49]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i64, i1 } [[TMP50]], 0
+// CHECK-NEXT: [[TMP49:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP48]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP49]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP50:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP51:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP50]] monotonic, align 8
// CHECK-NEXT: store i64 [[TMP51]], ptr [[ULV]], align 8
// CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP52]] acquire, align 8
-// CHECK-NEXT: [[TMP54:%.*]] = icmp ult i64 [[TMP53]], [[TMP52]]
-// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i64 [[TMP52]], i64 [[TMP53]]
-// CHECK-NEXT: store i64 [[TMP55]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP56]] acquire, align 8
-// CHECK-NEXT: [[TMP58:%.*]] = icmp ugt i64 [[TMP57]], [[TMP56]]
-// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i64 [[TMP56]], i64 [[TMP57]]
-// CHECK-NEXT: store i64 [[TMP59]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP61:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP60]], i64 [[TMP61]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i64, i1 } [[TMP62]], 0
-// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i64, i1 } [[TMP62]], 1
-// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i64 [[TMP60]], i64 [[TMP63]]
+// CHECK-NEXT: [[TMP53:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP52]], ptr [[ULX_ATOMIC_EXPECTED_PTR49]], align 8
+// CHECK-NEXT: store i64 [[TMP53]], ptr [[ULX_ATOMIC_DESIRED_PTR50]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED52:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR49]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED53:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR50]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR54:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED52]], i64 [[ULX_CMPXCHG_DESIRED53]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV55:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR54]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV55]], ptr [[ULX_ATOMIC_EXPECTED_PTR51]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS56:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR54]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL57:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR51]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL57]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP54:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP55:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP54]] monotonic, align 8
+// CHECK-NEXT: [[TMP56:%.*]] = icmp ult i64 [[TMP55]], [[TMP54]]
+// CHECK-NEXT: [[TMP57:%.*]] = select i1 [[TMP56]], i64 [[TMP54]], i64 [[TMP55]]
+// CHECK-NEXT: store i64 [[TMP57]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP58:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP59:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP58]] monotonic, align 8
+// CHECK-NEXT: [[TMP60:%.*]] = icmp ugt i64 [[TMP59]], [[TMP58]]
+// CHECK-NEXT: [[TMP61:%.*]] = select i1 [[TMP60]], i64 [[TMP58]], i64 [[TMP59]]
+// CHECK-NEXT: store i64 [[TMP61]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP62:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP63:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP62]], ptr [[ULX_ATOMIC_EXPECTED_PTR58]], align 8
+// CHECK-NEXT: store i64 [[TMP63]], ptr [[ULX_ATOMIC_DESIRED_PTR59]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED61:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR58]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED62:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR59]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR63:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED61]], i64 [[ULX_CMPXCHG_DESIRED62]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV64:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR63]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV64]], ptr [[ULX_ATOMIC_EXPECTED_PTR60]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS65:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR63]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL66:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR60]], align 8
+// CHECK-NEXT: [[ULX_CAPTURE_CAPTURED67:%.*]] = select i1 [[ULX_CMPXCHG_SUCCESS65]], i64 [[TMP62]], i64 [[ULX_CAPTURE_ACTUAL66]]
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_CAPTURED67]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP64:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP65:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP64]] release, align 8
// CHECK-NEXT: store i64 [[TMP65]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP66:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP66]] monotonic, align 8
+// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP66]] release, align 8
// CHECK-NEXT: store i64 [[TMP67]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP68:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP68]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP69]], ptr [[ULV]], align 8
+// CHECK-NEXT: [[TMP69:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP68]], ptr [[ULX_ATOMIC_EXPECTED_PTR68]], align 8
+// CHECK-NEXT: store i64 [[TMP69]], ptr [[ULX_ATOMIC_DESIRED_PTR69]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED71:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR68]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED72:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR69]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR73:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED71]], i64 [[ULX_CMPXCHG_DESIRED72]] release monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV74:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR73]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV74]], ptr [[ULX_ATOMIC_EXPECTED_PTR70]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS75:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR73]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL76:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR70]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL76]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP70:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP71:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP70]], i64 [[TMP71]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i64, i1 } [[TMP72]], 0
+// CHECK-NEXT: [[TMP71:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP70]] release, align 8
+// CHECK-NEXT: [[TMP72:%.*]] = icmp ult i64 [[TMP71]], [[TMP70]]
+// CHECK-NEXT: [[TMP73:%.*]] = select i1 [[TMP72]], i64 [[TMP70]], i64 [[TMP71]]
// CHECK-NEXT: store i64 [[TMP73]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP74:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP74]] monotonic, align 8
-// CHECK-NEXT: [[TMP76:%.*]] = icmp ult i64 [[TMP75]], [[TMP74]]
+// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP74]] release, align 8
+// CHECK-NEXT: [[TMP76:%.*]] = icmp ugt i64 [[TMP75]], [[TMP74]]
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i64 [[TMP74]], i64 [[TMP75]]
// CHECK-NEXT: store i64 [[TMP77]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP78:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP78]] monotonic, align 8
-// CHECK-NEXT: [[TMP80:%.*]] = icmp ugt i64 [[TMP79]], [[TMP78]]
-// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i64 [[TMP78]], i64 [[TMP79]]
+// CHECK-NEXT: [[TMP79:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP78]], ptr [[ULX_ATOMIC_EXPECTED_PTR77]], align 8
+// CHECK-NEXT: store i64 [[TMP79]], ptr [[ULX_ATOMIC_DESIRED_PTR78]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED80:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR77]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED81:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR78]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR82:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED80]], i64 [[ULX_CMPXCHG_DESIRED81]] release monotonic, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV83:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR82]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV83]], ptr [[ULX_ATOMIC_EXPECTED_PTR79]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS84:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR82]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL85:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR79]], align 8
+// CHECK-NEXT: [[ULX_CAPTURE_CAPTURED86:%.*]] = select i1 [[ULX_CMPXCHG_SUCCESS84]], i64 [[TMP78]], i64 [[ULX_CAPTURE_ACTUAL85]]
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_CAPTURED86]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP80:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP81:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP80]] seq_cst, align 8
// CHECK-NEXT: store i64 [[TMP81]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP82:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP83:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP82]], i64 [[TMP83]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i64, i1 } [[TMP84]], 0
-// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i64, i1 } [[TMP84]], 1
-// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i64 [[TMP82]], i64 [[TMP85]]
-// CHECK-NEXT: store i64 [[TMP87]], ptr [[ULV]], align 8
-// CHECK-NEXT: [[TMP88:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP88]] release, align 8
+// CHECK-NEXT: [[TMP83:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP82]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP83]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP84:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP85:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP84]], ptr [[ULX_ATOMIC_EXPECTED_PTR87]], align 8
+// CHECK-NEXT: store i64 [[TMP85]], ptr [[ULX_ATOMIC_DESIRED_PTR88]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED90:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR87]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED91:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR88]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR92:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED90]], i64 [[ULX_CMPXCHG_DESIRED91]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV93:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR92]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV93]], ptr [[ULX_ATOMIC_EXPECTED_PTR89]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS94:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR92]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL95:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR89]], align 8
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_ACTUAL95]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP86:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP86]] seq_cst, align 8
+// CHECK-NEXT: [[TMP88:%.*]] = icmp ult i64 [[TMP87]], [[TMP86]]
+// CHECK-NEXT: [[TMP89:%.*]] = select i1 [[TMP88]], i64 [[TMP86]], i64 [[TMP87]]
// CHECK-NEXT: store i64 [[TMP89]], ptr [[ULV]], align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP90:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP90]] release, align 8
-// CHECK-NEXT: store i64 [[TMP91]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP92:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP93:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP92]], i64 [[TMP93]] release monotonic, align 8
-// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i64, i1 } [[TMP94]], 0
-// CHECK-NEXT: store i64 [[TMP95]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP96:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP96]] release, align 8
-// CHECK-NEXT: [[TMP98:%.*]] = icmp ult i64 [[TMP97]], [[TMP96]]
-// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i64 [[TMP96]], i64 [[TMP97]]
-// CHECK-NEXT: store i64 [[TMP99]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP100:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP100]] release, align 8
-// CHECK-NEXT: [[TMP102:%.*]] = icmp ugt i64 [[TMP101]], [[TMP100]]
-// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i64 [[TMP100]], i64 [[TMP101]]
-// CHECK-NEXT: store i64 [[TMP103]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP104:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP105:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP104]], i64 [[TMP105]] release monotonic, align 8
-// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i64, i1 } [[TMP106]], 0
-// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP106]], 1
-// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i64 [[TMP104]], i64 [[TMP107]]
-// CHECK-NEXT: store i64 [[TMP109]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP110:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP110]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP111]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP112:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP112]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP113]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP114:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP115:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP114]], i64 [[TMP115]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i64, i1 } [[TMP116]], 0
-// CHECK-NEXT: store i64 [[TMP117]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP118:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw umin ptr [[ULX]], i64 [[TMP118]] seq_cst, align 8
-// CHECK-NEXT: [[TMP120:%.*]] = icmp ult i64 [[TMP119]], [[TMP118]]
-// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i64 [[TMP118]], i64 [[TMP119]]
-// CHECK-NEXT: store i64 [[TMP121]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP122:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP122]] seq_cst, align 8
-// CHECK-NEXT: [[TMP124:%.*]] = icmp ugt i64 [[TMP123]], [[TMP122]]
-// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i64 [[TMP122]], i64 [[TMP123]]
-// CHECK-NEXT: store i64 [[TMP125]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP126:%.*]] = load i64, ptr [[ULE]], align 8
-// CHECK-NEXT: [[TMP127:%.*]] = load i64, ptr [[ULD]], align 8
-// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[ULX]], i64 [[TMP126]], i64 [[TMP127]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i64, i1 } [[TMP128]], 0
-// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i64, i1 } [[TMP128]], 1
-// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i64 [[TMP126]], i64 [[TMP129]]
-// CHECK-NEXT: store i64 [[TMP131]], ptr [[ULV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP132:%.*]] = load i64, ptr [[ULV]], align 8
-// CHECK-NEXT: ret i64 [[TMP132]]
+// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw umax ptr [[ULX]], i64 [[TMP90]] seq_cst, align 8
+// CHECK-NEXT: [[TMP92:%.*]] = icmp ugt i64 [[TMP91]], [[TMP90]]
+// CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP92]], i64 [[TMP90]], i64 [[TMP91]]
+// CHECK-NEXT: store i64 [[TMP93]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP94:%.*]] = load i64, ptr [[ULE]], align 8
+// CHECK-NEXT: [[TMP95:%.*]] = load i64, ptr [[ULD]], align 8
+// CHECK-NEXT: store i64 [[TMP94]], ptr [[ULX_ATOMIC_EXPECTED_PTR96]], align 8
+// CHECK-NEXT: store i64 [[TMP95]], ptr [[ULX_ATOMIC_DESIRED_PTR97]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_EXPECTED99:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR96]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_DESIRED100:%.*]] = load i64, ptr [[ULX_ATOMIC_DESIRED_PTR97]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PAIR101:%.*]] = cmpxchg ptr [[ULX]], i64 [[ULX_CMPXCHG_EXPECTED99]], i64 [[ULX_CMPXCHG_DESIRED100]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_PREV102:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR101]], 0
+// CHECK-NEXT: store i64 [[ULX_CMPXCHG_PREV102]], ptr [[ULX_ATOMIC_EXPECTED_PTR98]], align 8
+// CHECK-NEXT: [[ULX_CMPXCHG_SUCCESS103:%.*]] = extractvalue { i64, i1 } [[ULX_CMPXCHG_PAIR101]], 1
+// CHECK-NEXT: [[ULX_CAPTURE_ACTUAL104:%.*]] = load i64, ptr [[ULX_ATOMIC_EXPECTED_PTR98]], align 8
+// CHECK-NEXT: [[ULX_CAPTURE_CAPTURED105:%.*]] = select i1 [[ULX_CMPXCHG_SUCCESS103]], i64 [[TMP94]], i64 [[ULX_CAPTURE_ACTUAL104]]
+// CHECK-NEXT: store i64 [[ULX_CAPTURE_CAPTURED105]], ptr [[ULV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP96:%.*]] = load i64, ptr [[ULV]], align 8
+// CHECK-NEXT: ret i64 [[TMP96]]
//
//
// CHECK-LABEL: @llxevd(
@@ -27015,6 +36471,42 @@ double fail_dxevd() {
// CHECK-NEXT: [[LLV:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[LLE:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[LLD:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR1:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR2:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR3:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR4:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR11:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR12:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR13:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR20:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR21:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR22:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR30:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR31:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR32:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR39:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR40:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR41:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR49:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR50:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR51:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR58:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR59:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR60:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR68:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR69:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR70:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR77:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR78:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR79:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR87:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR88:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR89:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR96:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_DESIRED_PTR97:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[LLX_ATOMIC_EXPECTED_PTR98:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[LLE]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP0]] monotonic, align 8
// CHECK-NEXT: store i64 [[TMP1]], ptr [[LLV]], align 8
@@ -27023,186 +36515,264 @@ double fail_dxevd() {
// CHECK-NEXT: store i64 [[TMP3]], ptr [[LLV]], align 8
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[LLE]], align 8
// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP4]], i64 [[TMP5]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
-// CHECK-NEXT: store i64 [[TMP7]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP8]] monotonic, align 8
-// CHECK-NEXT: [[TMP10:%.*]] = icmp slt i64 [[TMP9]], [[TMP8]]
-// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP8]], i64 [[TMP9]]
-// CHECK-NEXT: store i64 [[TMP11]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP12]] monotonic, align 8
-// CHECK-NEXT: [[TMP14:%.*]] = icmp sgt i64 [[TMP13]], [[TMP12]]
-// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP12]], i64 [[TMP13]]
-// CHECK-NEXT: store i64 [[TMP15]], ptr [[LLV]], align 8
+// CHECK-NEXT: store i64 [[TMP4]], ptr [[LLX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: store i64 [[TMP5]], ptr [[LLX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED]], i64 [[LLX_CMPXCHG_DESIRED]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV]], ptr [[LLX_ATOMIC_EXPECTED_PTR1]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR1]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP7:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP6]] monotonic, align 8
+// CHECK-NEXT: [[TMP8:%.*]] = icmp slt i64 [[TMP7]], [[TMP6]]
+// CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i64 [[TMP6]], i64 [[TMP7]]
+// CHECK-NEXT: store i64 [[TMP9]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP11:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP10]] monotonic, align 8
+// CHECK-NEXT: [[TMP12:%.*]] = icmp sgt i64 [[TMP11]], [[TMP10]]
+// CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i64 [[TMP10]], i64 [[TMP11]]
+// CHECK-NEXT: store i64 [[TMP13]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP15:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP14]], ptr [[LLX_ATOMIC_EXPECTED_PTR2]], align 8
+// CHECK-NEXT: store i64 [[TMP15]], ptr [[LLX_ATOMIC_DESIRED_PTR3]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED5:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR2]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED6:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR3]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR7:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED5]], i64 [[LLX_CMPXCHG_DESIRED6]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV8:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR7]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV8]], ptr [[LLX_ATOMIC_EXPECTED_PTR4]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS9:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR7]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL10:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR4]], align 8
+// CHECK-NEXT: [[LLX_CAPTURE_CAPTURED:%.*]] = select i1 [[LLX_CMPXCHG_SUCCESS9]], i64 [[TMP14]], i64 [[LLX_CAPTURE_ACTUAL10]]
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_CAPTURED]], ptr [[LLV]], align 8
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP17:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP16]], i64 [[TMP17]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i64, i1 } [[TMP18]], 0
-// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i64, i1 } [[TMP18]], 1
-// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i64 [[TMP16]], i64 [[TMP19]]
-// CHECK-NEXT: store i64 [[TMP21]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP17:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP16]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP17]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP18:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP19:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP18]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP19]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP21:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP20]], ptr [[LLX_ATOMIC_EXPECTED_PTR11]], align 8
+// CHECK-NEXT: store i64 [[TMP21]], ptr [[LLX_ATOMIC_DESIRED_PTR12]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED14:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR11]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED15:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR12]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR16:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED14]], i64 [[LLX_CMPXCHG_DESIRED15]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV17:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR16]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV17]], ptr [[LLX_ATOMIC_EXPECTED_PTR13]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS18:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR16]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL19:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR13]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL19]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP22:%.*]] = load i64, ptr [[LLE]], align 8
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP22]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP23]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP24]] acq_rel, align 8
+// CHECK-NEXT: [[TMP24:%.*]] = icmp slt i64 [[TMP23]], [[TMP22]]
+// CHECK-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], i64 [[TMP22]], i64 [[TMP23]]
// CHECK-NEXT: store i64 [[TMP25]], ptr [[LLV]], align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP26:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP26]], i64 [[TMP27]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i64, i1 } [[TMP28]], 0
+// CHECK-NEXT: [[TMP27:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP26]] acq_rel, align 8
+// CHECK-NEXT: [[TMP28:%.*]] = icmp sgt i64 [[TMP27]], [[TMP26]]
+// CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i64 [[TMP26]], i64 [[TMP27]]
// CHECK-NEXT: store i64 [[TMP29]], ptr [[LLV]], align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP30:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP30]] acq_rel, align 8
-// CHECK-NEXT: [[TMP32:%.*]] = icmp slt i64 [[TMP31]], [[TMP30]]
-// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i64 [[TMP30]], i64 [[TMP31]]
+// CHECK-NEXT: [[TMP31:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP30]], ptr [[LLX_ATOMIC_EXPECTED_PTR20]], align 8
+// CHECK-NEXT: store i64 [[TMP31]], ptr [[LLX_ATOMIC_DESIRED_PTR21]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED23:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR20]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED24:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR21]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR25:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED23]], i64 [[LLX_CMPXCHG_DESIRED24]] acq_rel acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV26:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR25]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV26]], ptr [[LLX_ATOMIC_EXPECTED_PTR22]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS27:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR25]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL28:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR22]], align 8
+// CHECK-NEXT: [[LLX_CAPTURE_CAPTURED29:%.*]] = select i1 [[LLX_CMPXCHG_SUCCESS27]], i64 [[TMP30]], i64 [[LLX_CAPTURE_ACTUAL28]]
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_CAPTURED29]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP33:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP32]] acquire, align 8
// CHECK-NEXT: store i64 [[TMP33]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP34:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP34]] acq_rel, align 8
-// CHECK-NEXT: [[TMP36:%.*]] = icmp sgt i64 [[TMP35]], [[TMP34]]
-// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i64 [[TMP34]], i64 [[TMP35]]
-// CHECK-NEXT: store i64 [[TMP37]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP34]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP35]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP37:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP36]], ptr [[LLX_ATOMIC_EXPECTED_PTR30]], align 8
+// CHECK-NEXT: store i64 [[TMP37]], ptr [[LLX_ATOMIC_DESIRED_PTR31]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED33:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR30]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED34:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR31]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR35:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED33]], i64 [[LLX_CMPXCHG_DESIRED34]] acquire acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV36:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR35]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV36]], ptr [[LLX_ATOMIC_EXPECTED_PTR32]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS37:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR35]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL38:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR32]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL38]], ptr [[LLV]], align 8
// CHECK-NEXT: [[TMP38:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP39:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP38]], i64 [[TMP39]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i64, i1 } [[TMP40]], 0
-// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i64, i1 } [[TMP40]], 1
-// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i64 [[TMP38]], i64 [[TMP41]]
-// CHECK-NEXT: store i64 [[TMP43]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP44]] acquire, align 8
+// CHECK-NEXT: [[TMP39:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP38]] acquire, align 8
+// CHECK-NEXT: [[TMP40:%.*]] = icmp slt i64 [[TMP39]], [[TMP38]]
+// CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i64 [[TMP38]], i64 [[TMP39]]
+// CHECK-NEXT: store i64 [[TMP41]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP42:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP43:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP42]] acquire, align 8
+// CHECK-NEXT: [[TMP44:%.*]] = icmp sgt i64 [[TMP43]], [[TMP42]]
+// CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP44]], i64 [[TMP42]], i64 [[TMP43]]
// CHECK-NEXT: store i64 [[TMP45]], ptr [[LLV]], align 8
// CHECK-NEXT: [[TMP46:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP46]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP47]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP47:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP46]], ptr [[LLX_ATOMIC_EXPECTED_PTR39]], align 8
+// CHECK-NEXT: store i64 [[TMP47]], ptr [[LLX_ATOMIC_DESIRED_PTR40]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED42:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR39]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED43:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR40]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR44:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED42]], i64 [[LLX_CMPXCHG_DESIRED43]] acquire acquire, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV45:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR44]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV45]], ptr [[LLX_ATOMIC_EXPECTED_PTR41]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS46:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR44]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL47:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR41]], align 8
+// CHECK-NEXT: [[LLX_CAPTURE_CAPTURED48:%.*]] = select i1 [[LLX_CMPXCHG_SUCCESS46]], i64 [[TMP46]], i64 [[LLX_CAPTURE_ACTUAL47]]
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_CAPTURED48]], ptr [[LLV]], align 8
// CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP49:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP48]], i64 [[TMP49]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i64, i1 } [[TMP50]], 0
+// CHECK-NEXT: [[TMP49:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP48]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP49]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP50:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP51:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP50]] monotonic, align 8
// CHECK-NEXT: store i64 [[TMP51]], ptr [[LLV]], align 8
// CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP52]] acquire, align 8
-// CHECK-NEXT: [[TMP54:%.*]] = icmp slt i64 [[TMP53]], [[TMP52]]
-// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i64 [[TMP52]], i64 [[TMP53]]
-// CHECK-NEXT: store i64 [[TMP55]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP56]] acquire, align 8
-// CHECK-NEXT: [[TMP58:%.*]] = icmp sgt i64 [[TMP57]], [[TMP56]]
-// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i64 [[TMP56]], i64 [[TMP57]]
-// CHECK-NEXT: store i64 [[TMP59]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP61:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP60]], i64 [[TMP61]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i64, i1 } [[TMP62]], 0
-// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i64, i1 } [[TMP62]], 1
-// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i64 [[TMP60]], i64 [[TMP63]]
+// CHECK-NEXT: [[TMP53:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP52]], ptr [[LLX_ATOMIC_EXPECTED_PTR49]], align 8
+// CHECK-NEXT: store i64 [[TMP53]], ptr [[LLX_ATOMIC_DESIRED_PTR50]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED52:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR49]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED53:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR50]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR54:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED52]], i64 [[LLX_CMPXCHG_DESIRED53]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV55:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR54]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV55]], ptr [[LLX_ATOMIC_EXPECTED_PTR51]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS56:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR54]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL57:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR51]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL57]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP54:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP55:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP54]] monotonic, align 8
+// CHECK-NEXT: [[TMP56:%.*]] = icmp slt i64 [[TMP55]], [[TMP54]]
+// CHECK-NEXT: [[TMP57:%.*]] = select i1 [[TMP56]], i64 [[TMP54]], i64 [[TMP55]]
+// CHECK-NEXT: store i64 [[TMP57]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP58:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP59:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP58]] monotonic, align 8
+// CHECK-NEXT: [[TMP60:%.*]] = icmp sgt i64 [[TMP59]], [[TMP58]]
+// CHECK-NEXT: [[TMP61:%.*]] = select i1 [[TMP60]], i64 [[TMP58]], i64 [[TMP59]]
+// CHECK-NEXT: store i64 [[TMP61]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP62:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP63:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP62]], ptr [[LLX_ATOMIC_EXPECTED_PTR58]], align 8
+// CHECK-NEXT: store i64 [[TMP63]], ptr [[LLX_ATOMIC_DESIRED_PTR59]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED61:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR58]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED62:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR59]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR63:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED61]], i64 [[LLX_CMPXCHG_DESIRED62]] monotonic monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV64:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR63]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV64]], ptr [[LLX_ATOMIC_EXPECTED_PTR60]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS65:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR63]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL66:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR60]], align 8
+// CHECK-NEXT: [[LLX_CAPTURE_CAPTURED67:%.*]] = select i1 [[LLX_CMPXCHG_SUCCESS65]], i64 [[TMP62]], i64 [[LLX_CAPTURE_ACTUAL66]]
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_CAPTURED67]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP64:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP65:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP64]] release, align 8
// CHECK-NEXT: store i64 [[TMP65]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP66:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP66]] monotonic, align 8
+// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP66]] release, align 8
// CHECK-NEXT: store i64 [[TMP67]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP68:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP68]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP69]], ptr [[LLV]], align 8
+// CHECK-NEXT: [[TMP69:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP68]], ptr [[LLX_ATOMIC_EXPECTED_PTR68]], align 8
+// CHECK-NEXT: store i64 [[TMP69]], ptr [[LLX_ATOMIC_DESIRED_PTR69]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED71:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR68]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED72:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR69]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR73:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED71]], i64 [[LLX_CMPXCHG_DESIRED72]] release monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV74:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR73]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV74]], ptr [[LLX_ATOMIC_EXPECTED_PTR70]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS75:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR73]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL76:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR70]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL76]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP70:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP71:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP70]], i64 [[TMP71]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i64, i1 } [[TMP72]], 0
+// CHECK-NEXT: [[TMP71:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP70]] release, align 8
+// CHECK-NEXT: [[TMP72:%.*]] = icmp slt i64 [[TMP71]], [[TMP70]]
+// CHECK-NEXT: [[TMP73:%.*]] = select i1 [[TMP72]], i64 [[TMP70]], i64 [[TMP71]]
// CHECK-NEXT: store i64 [[TMP73]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP74:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP74]] monotonic, align 8
-// CHECK-NEXT: [[TMP76:%.*]] = icmp slt i64 [[TMP75]], [[TMP74]]
+// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP74]] release, align 8
+// CHECK-NEXT: [[TMP76:%.*]] = icmp sgt i64 [[TMP75]], [[TMP74]]
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i64 [[TMP74]], i64 [[TMP75]]
// CHECK-NEXT: store i64 [[TMP77]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP78:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP78]] monotonic, align 8
-// CHECK-NEXT: [[TMP80:%.*]] = icmp sgt i64 [[TMP79]], [[TMP78]]
-// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i64 [[TMP78]], i64 [[TMP79]]
+// CHECK-NEXT: [[TMP79:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP78]], ptr [[LLX_ATOMIC_EXPECTED_PTR77]], align 8
+// CHECK-NEXT: store i64 [[TMP79]], ptr [[LLX_ATOMIC_DESIRED_PTR78]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED80:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR77]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED81:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR78]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR82:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED80]], i64 [[LLX_CMPXCHG_DESIRED81]] release monotonic, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV83:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR82]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV83]], ptr [[LLX_ATOMIC_EXPECTED_PTR79]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS84:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR82]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL85:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR79]], align 8
+// CHECK-NEXT: [[LLX_CAPTURE_CAPTURED86:%.*]] = select i1 [[LLX_CMPXCHG_SUCCESS84]], i64 [[TMP78]], i64 [[LLX_CAPTURE_ACTUAL85]]
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_CAPTURED86]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP80:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP81:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP80]] seq_cst, align 8
// CHECK-NEXT: store i64 [[TMP81]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP82:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP83:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP82]], i64 [[TMP83]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i64, i1 } [[TMP84]], 0
-// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i64, i1 } [[TMP84]], 1
-// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i64 [[TMP82]], i64 [[TMP85]]
-// CHECK-NEXT: store i64 [[TMP87]], ptr [[LLV]], align 8
-// CHECK-NEXT: [[TMP88:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP88]] release, align 8
+// CHECK-NEXT: [[TMP83:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP82]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP83]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP84:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP85:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP84]], ptr [[LLX_ATOMIC_EXPECTED_PTR87]], align 8
+// CHECK-NEXT: store i64 [[TMP85]], ptr [[LLX_ATOMIC_DESIRED_PTR88]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED90:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR87]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED91:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR88]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR92:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED90]], i64 [[LLX_CMPXCHG_DESIRED91]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV93:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR92]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV93]], ptr [[LLX_ATOMIC_EXPECTED_PTR89]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS94:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR92]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL95:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR89]], align 8
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_ACTUAL95]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP86:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP86]] seq_cst, align 8
+// CHECK-NEXT: [[TMP88:%.*]] = icmp slt i64 [[TMP87]], [[TMP86]]
+// CHECK-NEXT: [[TMP89:%.*]] = select i1 [[TMP88]], i64 [[TMP86]], i64 [[TMP87]]
// CHECK-NEXT: store i64 [[TMP89]], ptr [[LLV]], align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP90:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP90]] release, align 8
-// CHECK-NEXT: store i64 [[TMP91]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP92:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP93:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP92]], i64 [[TMP93]] release monotonic, align 8
-// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i64, i1 } [[TMP94]], 0
-// CHECK-NEXT: store i64 [[TMP95]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP96:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP96]] release, align 8
-// CHECK-NEXT: [[TMP98:%.*]] = icmp slt i64 [[TMP97]], [[TMP96]]
-// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i64 [[TMP96]], i64 [[TMP97]]
-// CHECK-NEXT: store i64 [[TMP99]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP100:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP100]] release, align 8
-// CHECK-NEXT: [[TMP102:%.*]] = icmp sgt i64 [[TMP101]], [[TMP100]]
-// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i64 [[TMP100]], i64 [[TMP101]]
-// CHECK-NEXT: store i64 [[TMP103]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP104:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP105:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP104]], i64 [[TMP105]] release monotonic, align 8
-// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i64, i1 } [[TMP106]], 0
-// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP106]], 1
-// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i64 [[TMP104]], i64 [[TMP107]]
-// CHECK-NEXT: store i64 [[TMP109]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP110:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP110]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP111]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP112:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP112]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP113]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP114:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP115:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP114]], i64 [[TMP115]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i64, i1 } [[TMP116]], 0
-// CHECK-NEXT: store i64 [[TMP117]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP118:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw min ptr [[LLX]], i64 [[TMP118]] seq_cst, align 8
-// CHECK-NEXT: [[TMP120:%.*]] = icmp slt i64 [[TMP119]], [[TMP118]]
-// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i64 [[TMP118]], i64 [[TMP119]]
-// CHECK-NEXT: store i64 [[TMP121]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP122:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP122]] seq_cst, align 8
-// CHECK-NEXT: [[TMP124:%.*]] = icmp sgt i64 [[TMP123]], [[TMP122]]
-// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i64 [[TMP122]], i64 [[TMP123]]
-// CHECK-NEXT: store i64 [[TMP125]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP126:%.*]] = load i64, ptr [[LLE]], align 8
-// CHECK-NEXT: [[TMP127:%.*]] = load i64, ptr [[LLD]], align 8
-// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[LLX]], i64 [[TMP126]], i64 [[TMP127]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i64, i1 } [[TMP128]], 0
-// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i64, i1 } [[TMP128]], 1
-// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i64 [[TMP126]], i64 [[TMP129]]
-// CHECK-NEXT: store i64 [[TMP131]], ptr [[LLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP132:%.*]] = load i64, ptr [[LLV]], align 8
-// CHECK-NEXT: ret i64 [[TMP132]]
+// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw max ptr [[LLX]], i64 [[TMP90]] seq_cst, align 8
+// CHECK-NEXT: [[TMP92:%.*]] = icmp sgt i64 [[TMP91]], [[TMP90]]
+// CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP92]], i64 [[TMP90]], i64 [[TMP91]]
+// CHECK-NEXT: store i64 [[TMP93]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP94:%.*]] = load i64, ptr [[LLE]], align 8
+// CHECK-NEXT: [[TMP95:%.*]] = load i64, ptr [[LLD]], align 8
+// CHECK-NEXT: store i64 [[TMP94]], ptr [[LLX_ATOMIC_EXPECTED_PTR96]], align 8
+// CHECK-NEXT: store i64 [[TMP95]], ptr [[LLX_ATOMIC_DESIRED_PTR97]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_EXPECTED99:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR96]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_DESIRED100:%.*]] = load i64, ptr [[LLX_ATOMIC_DESIRED_PTR97]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PAIR101:%.*]] = cmpxchg ptr [[LLX]], i64 [[LLX_CMPXCHG_EXPECTED99]], i64 [[LLX_CMPXCHG_DESIRED100]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_PREV102:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR101]], 0
+// CHECK-NEXT: store i64 [[LLX_CMPXCHG_PREV102]], ptr [[LLX_ATOMIC_EXPECTED_PTR98]], align 8
+// CHECK-NEXT: [[LLX_CMPXCHG_SUCCESS103:%.*]] = extractvalue { i64, i1 } [[LLX_CMPXCHG_PAIR101]], 1
+// CHECK-NEXT: [[LLX_CAPTURE_ACTUAL104:%.*]] = load i64, ptr [[LLX_ATOMIC_EXPECTED_PTR98]], align 8
+// CHECK-NEXT: [[LLX_CAPTURE_CAPTURED105:%.*]] = select i1 [[LLX_CMPXCHG_SUCCESS103]], i64 [[TMP94]], i64 [[LLX_CAPTURE_ACTUAL104]]
+// CHECK-NEXT: store i64 [[LLX_CAPTURE_CAPTURED105]], ptr [[LLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP96:%.*]] = load i64, ptr [[LLV]], align 8
+// CHECK-NEXT: ret i64 [[TMP96]]
//
//
// CHECK-LABEL: @ullxevd(
@@ -27211,6 +36781,42 @@ double fail_dxevd() {
// CHECK-NEXT: [[ULLV:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[ULLE:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[ULLD:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR1:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR2:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR3:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR4:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR11:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR12:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR13:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR20:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR21:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR22:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR30:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR31:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR32:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR39:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR40:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR41:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR49:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR50:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR51:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR58:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR59:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR60:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR68:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR69:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR70:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR77:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR78:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR79:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR87:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR88:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR89:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR96:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_DESIRED_PTR97:%.*]] = alloca i64, align 8
+// CHECK-NEXT: [[ULLX_ATOMIC_EXPECTED_PTR98:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[ULLE]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP0]] monotonic, align 8
// CHECK-NEXT: store i64 [[TMP1]], ptr [[ULLV]], align 8
@@ -27219,186 +36825,264 @@ double fail_dxevd() {
// CHECK-NEXT: store i64 [[TMP3]], ptr [[ULLV]], align 8
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[ULLE]], align 8
// CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP4]], i64 [[TMP5]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
-// CHECK-NEXT: store i64 [[TMP7]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP9:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP8]] monotonic, align 8
-// CHECK-NEXT: [[TMP10:%.*]] = icmp ult i64 [[TMP9]], [[TMP8]]
-// CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP8]], i64 [[TMP9]]
-// CHECK-NEXT: store i64 [[TMP11]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP13:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP12]] monotonic, align 8
-// CHECK-NEXT: [[TMP14:%.*]] = icmp ugt i64 [[TMP13]], [[TMP12]]
-// CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP12]], i64 [[TMP13]]
-// CHECK-NEXT: store i64 [[TMP15]], ptr [[ULLV]], align 8
+// CHECK-NEXT: store i64 [[TMP4]], ptr [[ULLX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: store i64 [[TMP5]], ptr [[ULLX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED]], i64 [[ULLX_CMPXCHG_DESIRED]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV]], ptr [[ULLX_ATOMIC_EXPECTED_PTR1]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR1]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP7:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP6]] monotonic, align 8
+// CHECK-NEXT: [[TMP8:%.*]] = icmp ult i64 [[TMP7]], [[TMP6]]
+// CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i64 [[TMP6]], i64 [[TMP7]]
+// CHECK-NEXT: store i64 [[TMP9]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP11:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP10]] monotonic, align 8
+// CHECK-NEXT: [[TMP12:%.*]] = icmp ugt i64 [[TMP11]], [[TMP10]]
+// CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i64 [[TMP10]], i64 [[TMP11]]
+// CHECK-NEXT: store i64 [[TMP13]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP15:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP14]], ptr [[ULLX_ATOMIC_EXPECTED_PTR2]], align 8
+// CHECK-NEXT: store i64 [[TMP15]], ptr [[ULLX_ATOMIC_DESIRED_PTR3]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED5:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR2]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED6:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR3]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR7:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED5]], i64 [[ULLX_CMPXCHG_DESIRED6]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV8:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR7]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV8]], ptr [[ULLX_ATOMIC_EXPECTED_PTR4]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS9:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR7]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL10:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR4]], align 8
+// CHECK-NEXT: [[ULLX_CAPTURE_CAPTURED:%.*]] = select i1 [[ULLX_CMPXCHG_SUCCESS9]], i64 [[TMP14]], i64 [[ULLX_CAPTURE_ACTUAL10]]
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_CAPTURED]], ptr [[ULLV]], align 8
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP17:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP18:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP16]], i64 [[TMP17]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP19:%.*]] = extractvalue { i64, i1 } [[TMP18]], 0
-// CHECK-NEXT: [[TMP20:%.*]] = extractvalue { i64, i1 } [[TMP18]], 1
-// CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i64 [[TMP16]], i64 [[TMP19]]
-// CHECK-NEXT: store i64 [[TMP21]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP17:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP16]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP17]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP18:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP19:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP18]] acq_rel, align 8
+// CHECK-NEXT: store i64 [[TMP19]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP21:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP20]], ptr [[ULLX_ATOMIC_EXPECTED_PTR11]], align 8
+// CHECK-NEXT: store i64 [[TMP21]], ptr [[ULLX_ATOMIC_DESIRED_PTR12]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED14:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR11]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED15:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR12]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR16:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED14]], i64 [[ULLX_CMPXCHG_DESIRED15]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV17:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR16]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV17]], ptr [[ULLX_ATOMIC_EXPECTED_PTR13]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS18:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR16]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL19:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR13]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL19]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP22:%.*]] = load i64, ptr [[ULLE]], align 8
// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP22]] acq_rel, align 8
-// CHECK-NEXT: store i64 [[TMP23]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP25:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP24]] acq_rel, align 8
+// CHECK-NEXT: [[TMP24:%.*]] = icmp ult i64 [[TMP23]], [[TMP22]]
+// CHECK-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], i64 [[TMP22]], i64 [[TMP23]]
// CHECK-NEXT: store i64 [[TMP25]], ptr [[ULLV]], align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP26:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP27:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP28:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP26]], i64 [[TMP27]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP29:%.*]] = extractvalue { i64, i1 } [[TMP28]], 0
+// CHECK-NEXT: [[TMP27:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP26]] acq_rel, align 8
+// CHECK-NEXT: [[TMP28:%.*]] = icmp ugt i64 [[TMP27]], [[TMP26]]
+// CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i64 [[TMP26]], i64 [[TMP27]]
// CHECK-NEXT: store i64 [[TMP29]], ptr [[ULLV]], align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP30:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP30]] acq_rel, align 8
-// CHECK-NEXT: [[TMP32:%.*]] = icmp ult i64 [[TMP31]], [[TMP30]]
-// CHECK-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i64 [[TMP30]], i64 [[TMP31]]
+// CHECK-NEXT: [[TMP31:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP30]], ptr [[ULLX_ATOMIC_EXPECTED_PTR20]], align 8
+// CHECK-NEXT: store i64 [[TMP31]], ptr [[ULLX_ATOMIC_DESIRED_PTR21]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED23:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR20]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED24:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR21]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR25:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED23]], i64 [[ULLX_CMPXCHG_DESIRED24]] acq_rel acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV26:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR25]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV26]], ptr [[ULLX_ATOMIC_EXPECTED_PTR22]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS27:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR25]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL28:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR22]], align 8
+// CHECK-NEXT: [[ULLX_CAPTURE_CAPTURED29:%.*]] = select i1 [[ULLX_CMPXCHG_SUCCESS27]], i64 [[TMP30]], i64 [[ULLX_CAPTURE_ACTUAL28]]
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_CAPTURED29]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP33:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP32]] acquire, align 8
// CHECK-NEXT: store i64 [[TMP33]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP34:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP34]] acq_rel, align 8
-// CHECK-NEXT: [[TMP36:%.*]] = icmp ugt i64 [[TMP35]], [[TMP34]]
-// CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i64 [[TMP34]], i64 [[TMP35]]
-// CHECK-NEXT: store i64 [[TMP37]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP34]] acquire, align 8
+// CHECK-NEXT: store i64 [[TMP35]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP37:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP36]], ptr [[ULLX_ATOMIC_EXPECTED_PTR30]], align 8
+// CHECK-NEXT: store i64 [[TMP37]], ptr [[ULLX_ATOMIC_DESIRED_PTR31]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED33:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR30]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED34:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR31]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR35:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED33]], i64 [[ULLX_CMPXCHG_DESIRED34]] acquire acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV36:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR35]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV36]], ptr [[ULLX_ATOMIC_EXPECTED_PTR32]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS37:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR35]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL38:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR32]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL38]], ptr [[ULLV]], align 8
// CHECK-NEXT: [[TMP38:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP39:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP40:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP38]], i64 [[TMP39]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP41:%.*]] = extractvalue { i64, i1 } [[TMP40]], 0
-// CHECK-NEXT: [[TMP42:%.*]] = extractvalue { i64, i1 } [[TMP40]], 1
-// CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i64 [[TMP38]], i64 [[TMP41]]
-// CHECK-NEXT: store i64 [[TMP43]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP45:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP44]] acquire, align 8
+// CHECK-NEXT: [[TMP39:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP38]] acquire, align 8
+// CHECK-NEXT: [[TMP40:%.*]] = icmp ult i64 [[TMP39]], [[TMP38]]
+// CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i64 [[TMP38]], i64 [[TMP39]]
+// CHECK-NEXT: store i64 [[TMP41]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP42:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP43:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP42]] acquire, align 8
+// CHECK-NEXT: [[TMP44:%.*]] = icmp ugt i64 [[TMP43]], [[TMP42]]
+// CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP44]], i64 [[TMP42]], i64 [[TMP43]]
// CHECK-NEXT: store i64 [[TMP45]], ptr [[ULLV]], align 8
// CHECK-NEXT: [[TMP46:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP47:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP46]] acquire, align 8
-// CHECK-NEXT: store i64 [[TMP47]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP47:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP46]], ptr [[ULLX_ATOMIC_EXPECTED_PTR39]], align 8
+// CHECK-NEXT: store i64 [[TMP47]], ptr [[ULLX_ATOMIC_DESIRED_PTR40]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED42:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR39]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED43:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR40]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR44:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED42]], i64 [[ULLX_CMPXCHG_DESIRED43]] acquire acquire, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV45:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR44]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV45]], ptr [[ULLX_ATOMIC_EXPECTED_PTR41]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS46:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR44]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL47:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR41]], align 8
+// CHECK-NEXT: [[ULLX_CAPTURE_CAPTURED48:%.*]] = select i1 [[ULLX_CMPXCHG_SUCCESS46]], i64 [[TMP46]], i64 [[ULLX_CAPTURE_ACTUAL47]]
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_CAPTURED48]], ptr [[ULLV]], align 8
// CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP49:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP50:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP48]], i64 [[TMP49]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP51:%.*]] = extractvalue { i64, i1 } [[TMP50]], 0
+// CHECK-NEXT: [[TMP49:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP48]] monotonic, align 8
+// CHECK-NEXT: store i64 [[TMP49]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP50:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP51:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP50]] monotonic, align 8
// CHECK-NEXT: store i64 [[TMP51]], ptr [[ULLV]], align 8
// CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP53:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP52]] acquire, align 8
-// CHECK-NEXT: [[TMP54:%.*]] = icmp ult i64 [[TMP53]], [[TMP52]]
-// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i64 [[TMP52]], i64 [[TMP53]]
-// CHECK-NEXT: store i64 [[TMP55]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP56]] acquire, align 8
-// CHECK-NEXT: [[TMP58:%.*]] = icmp ugt i64 [[TMP57]], [[TMP56]]
-// CHECK-NEXT: [[TMP59:%.*]] = select i1 [[TMP58]], i64 [[TMP56]], i64 [[TMP57]]
-// CHECK-NEXT: store i64 [[TMP59]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP61:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP62:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP60]], i64 [[TMP61]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP63:%.*]] = extractvalue { i64, i1 } [[TMP62]], 0
-// CHECK-NEXT: [[TMP64:%.*]] = extractvalue { i64, i1 } [[TMP62]], 1
-// CHECK-NEXT: [[TMP65:%.*]] = select i1 [[TMP64]], i64 [[TMP60]], i64 [[TMP63]]
+// CHECK-NEXT: [[TMP53:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP52]], ptr [[ULLX_ATOMIC_EXPECTED_PTR49]], align 8
+// CHECK-NEXT: store i64 [[TMP53]], ptr [[ULLX_ATOMIC_DESIRED_PTR50]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED52:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR49]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED53:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR50]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR54:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED52]], i64 [[ULLX_CMPXCHG_DESIRED53]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV55:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR54]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV55]], ptr [[ULLX_ATOMIC_EXPECTED_PTR51]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS56:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR54]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL57:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR51]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL57]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP54:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP55:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP54]] monotonic, align 8
+// CHECK-NEXT: [[TMP56:%.*]] = icmp ult i64 [[TMP55]], [[TMP54]]
+// CHECK-NEXT: [[TMP57:%.*]] = select i1 [[TMP56]], i64 [[TMP54]], i64 [[TMP55]]
+// CHECK-NEXT: store i64 [[TMP57]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP58:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP59:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP58]] monotonic, align 8
+// CHECK-NEXT: [[TMP60:%.*]] = icmp ugt i64 [[TMP59]], [[TMP58]]
+// CHECK-NEXT: [[TMP61:%.*]] = select i1 [[TMP60]], i64 [[TMP58]], i64 [[TMP59]]
+// CHECK-NEXT: store i64 [[TMP61]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP62:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP63:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP62]], ptr [[ULLX_ATOMIC_EXPECTED_PTR58]], align 8
+// CHECK-NEXT: store i64 [[TMP63]], ptr [[ULLX_ATOMIC_DESIRED_PTR59]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED61:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR58]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED62:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR59]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR63:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED61]], i64 [[ULLX_CMPXCHG_DESIRED62]] monotonic monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV64:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR63]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV64]], ptr [[ULLX_ATOMIC_EXPECTED_PTR60]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS65:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR63]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL66:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR60]], align 8
+// CHECK-NEXT: [[ULLX_CAPTURE_CAPTURED67:%.*]] = select i1 [[ULLX_CMPXCHG_SUCCESS65]], i64 [[TMP62]], i64 [[ULLX_CAPTURE_ACTUAL66]]
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_CAPTURED67]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP64:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP65:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP64]] release, align 8
// CHECK-NEXT: store i64 [[TMP65]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP66:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP66]] monotonic, align 8
+// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP66]] release, align 8
// CHECK-NEXT: store i64 [[TMP67]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP68:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP69:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP68]] monotonic, align 8
-// CHECK-NEXT: store i64 [[TMP69]], ptr [[ULLV]], align 8
+// CHECK-NEXT: [[TMP69:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP68]], ptr [[ULLX_ATOMIC_EXPECTED_PTR68]], align 8
+// CHECK-NEXT: store i64 [[TMP69]], ptr [[ULLX_ATOMIC_DESIRED_PTR69]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED71:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR68]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED72:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR69]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR73:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED71]], i64 [[ULLX_CMPXCHG_DESIRED72]] release monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV74:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR73]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV74]], ptr [[ULLX_ATOMIC_EXPECTED_PTR70]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS75:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR73]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL76:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR70]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL76]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP70:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP71:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP72:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP70]], i64 [[TMP71]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP73:%.*]] = extractvalue { i64, i1 } [[TMP72]], 0
+// CHECK-NEXT: [[TMP71:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP70]] release, align 8
+// CHECK-NEXT: [[TMP72:%.*]] = icmp ult i64 [[TMP71]], [[TMP70]]
+// CHECK-NEXT: [[TMP73:%.*]] = select i1 [[TMP72]], i64 [[TMP70]], i64 [[TMP71]]
// CHECK-NEXT: store i64 [[TMP73]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP74:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP74]] monotonic, align 8
-// CHECK-NEXT: [[TMP76:%.*]] = icmp ult i64 [[TMP75]], [[TMP74]]
+// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP74]] release, align 8
+// CHECK-NEXT: [[TMP76:%.*]] = icmp ugt i64 [[TMP75]], [[TMP74]]
// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i64 [[TMP74]], i64 [[TMP75]]
// CHECK-NEXT: store i64 [[TMP77]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP78:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP79:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP78]] monotonic, align 8
-// CHECK-NEXT: [[TMP80:%.*]] = icmp ugt i64 [[TMP79]], [[TMP78]]
-// CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP80]], i64 [[TMP78]], i64 [[TMP79]]
+// CHECK-NEXT: [[TMP79:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP78]], ptr [[ULLX_ATOMIC_EXPECTED_PTR77]], align 8
+// CHECK-NEXT: store i64 [[TMP79]], ptr [[ULLX_ATOMIC_DESIRED_PTR78]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED80:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR77]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED81:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR78]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR82:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED80]], i64 [[ULLX_CMPXCHG_DESIRED81]] release monotonic, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV83:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR82]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV83]], ptr [[ULLX_ATOMIC_EXPECTED_PTR79]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS84:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR82]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL85:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR79]], align 8
+// CHECK-NEXT: [[ULLX_CAPTURE_CAPTURED86:%.*]] = select i1 [[ULLX_CMPXCHG_SUCCESS84]], i64 [[TMP78]], i64 [[ULLX_CAPTURE_ACTUAL85]]
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_CAPTURED86]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP80:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP81:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP80]] seq_cst, align 8
// CHECK-NEXT: store i64 [[TMP81]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP82:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP83:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP84:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP82]], i64 [[TMP83]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP85:%.*]] = extractvalue { i64, i1 } [[TMP84]], 0
-// CHECK-NEXT: [[TMP86:%.*]] = extractvalue { i64, i1 } [[TMP84]], 1
-// CHECK-NEXT: [[TMP87:%.*]] = select i1 [[TMP86]], i64 [[TMP82]], i64 [[TMP85]]
-// CHECK-NEXT: store i64 [[TMP87]], ptr [[ULLV]], align 8
-// CHECK-NEXT: [[TMP88:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP89:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP88]] release, align 8
+// CHECK-NEXT: [[TMP83:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP82]] seq_cst, align 8
+// CHECK-NEXT: store i64 [[TMP83]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP84:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP85:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP84]], ptr [[ULLX_ATOMIC_EXPECTED_PTR87]], align 8
+// CHECK-NEXT: store i64 [[TMP85]], ptr [[ULLX_ATOMIC_DESIRED_PTR88]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED90:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR87]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED91:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR88]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR92:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED90]], i64 [[ULLX_CMPXCHG_DESIRED91]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV93:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR92]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV93]], ptr [[ULLX_ATOMIC_EXPECTED_PTR89]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS94:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR92]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL95:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR89]], align 8
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_ACTUAL95]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP86:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP86]] seq_cst, align 8
+// CHECK-NEXT: [[TMP88:%.*]] = icmp ult i64 [[TMP87]], [[TMP86]]
+// CHECK-NEXT: [[TMP89:%.*]] = select i1 [[TMP88]], i64 [[TMP86]], i64 [[TMP87]]
// CHECK-NEXT: store i64 [[TMP89]], ptr [[ULLV]], align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP90:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP90]] release, align 8
-// CHECK-NEXT: store i64 [[TMP91]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP92:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP93:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP94:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP92]], i64 [[TMP93]] release monotonic, align 8
-// CHECK-NEXT: [[TMP95:%.*]] = extractvalue { i64, i1 } [[TMP94]], 0
-// CHECK-NEXT: store i64 [[TMP95]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP96:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP97:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP96]] release, align 8
-// CHECK-NEXT: [[TMP98:%.*]] = icmp ult i64 [[TMP97]], [[TMP96]]
-// CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP98]], i64 [[TMP96]], i64 [[TMP97]]
-// CHECK-NEXT: store i64 [[TMP99]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP100:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP101:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP100]] release, align 8
-// CHECK-NEXT: [[TMP102:%.*]] = icmp ugt i64 [[TMP101]], [[TMP100]]
-// CHECK-NEXT: [[TMP103:%.*]] = select i1 [[TMP102]], i64 [[TMP100]], i64 [[TMP101]]
-// CHECK-NEXT: store i64 [[TMP103]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP104:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP105:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP106:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP104]], i64 [[TMP105]] release monotonic, align 8
-// CHECK-NEXT: [[TMP107:%.*]] = extractvalue { i64, i1 } [[TMP106]], 0
-// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP106]], 1
-// CHECK-NEXT: [[TMP109:%.*]] = select i1 [[TMP108]], i64 [[TMP104]], i64 [[TMP107]]
-// CHECK-NEXT: store i64 [[TMP109]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP110:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP111:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP110]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP111]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP112:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP112]] seq_cst, align 8
-// CHECK-NEXT: store i64 [[TMP113]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP114:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP115:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP116:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP114]], i64 [[TMP115]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP117:%.*]] = extractvalue { i64, i1 } [[TMP116]], 0
-// CHECK-NEXT: store i64 [[TMP117]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP118:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP119:%.*]] = atomicrmw umin ptr [[ULLX]], i64 [[TMP118]] seq_cst, align 8
-// CHECK-NEXT: [[TMP120:%.*]] = icmp ult i64 [[TMP119]], [[TMP118]]
-// CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP120]], i64 [[TMP118]], i64 [[TMP119]]
-// CHECK-NEXT: store i64 [[TMP121]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP122:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP123:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP122]] seq_cst, align 8
-// CHECK-NEXT: [[TMP124:%.*]] = icmp ugt i64 [[TMP123]], [[TMP122]]
-// CHECK-NEXT: [[TMP125:%.*]] = select i1 [[TMP124]], i64 [[TMP122]], i64 [[TMP123]]
-// CHECK-NEXT: store i64 [[TMP125]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP126:%.*]] = load i64, ptr [[ULLE]], align 8
-// CHECK-NEXT: [[TMP127:%.*]] = load i64, ptr [[ULLD]], align 8
-// CHECK-NEXT: [[TMP128:%.*]] = cmpxchg ptr [[ULLX]], i64 [[TMP126]], i64 [[TMP127]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP129:%.*]] = extractvalue { i64, i1 } [[TMP128]], 0
-// CHECK-NEXT: [[TMP130:%.*]] = extractvalue { i64, i1 } [[TMP128]], 1
-// CHECK-NEXT: [[TMP131:%.*]] = select i1 [[TMP130]], i64 [[TMP126]], i64 [[TMP129]]
-// CHECK-NEXT: store i64 [[TMP131]], ptr [[ULLV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP132:%.*]] = load i64, ptr [[ULLV]], align 8
-// CHECK-NEXT: ret i64 [[TMP132]]
+// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw umax ptr [[ULLX]], i64 [[TMP90]] seq_cst, align 8
+// CHECK-NEXT: [[TMP92:%.*]] = icmp ugt i64 [[TMP91]], [[TMP90]]
+// CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP92]], i64 [[TMP90]], i64 [[TMP91]]
+// CHECK-NEXT: store i64 [[TMP93]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP94:%.*]] = load i64, ptr [[ULLE]], align 8
+// CHECK-NEXT: [[TMP95:%.*]] = load i64, ptr [[ULLD]], align 8
+// CHECK-NEXT: store i64 [[TMP94]], ptr [[ULLX_ATOMIC_EXPECTED_PTR96]], align 8
+// CHECK-NEXT: store i64 [[TMP95]], ptr [[ULLX_ATOMIC_DESIRED_PTR97]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_EXPECTED99:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR96]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_DESIRED100:%.*]] = load i64, ptr [[ULLX_ATOMIC_DESIRED_PTR97]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PAIR101:%.*]] = cmpxchg ptr [[ULLX]], i64 [[ULLX_CMPXCHG_EXPECTED99]], i64 [[ULLX_CMPXCHG_DESIRED100]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_PREV102:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR101]], 0
+// CHECK-NEXT: store i64 [[ULLX_CMPXCHG_PREV102]], ptr [[ULLX_ATOMIC_EXPECTED_PTR98]], align 8
+// CHECK-NEXT: [[ULLX_CMPXCHG_SUCCESS103:%.*]] = extractvalue { i64, i1 } [[ULLX_CMPXCHG_PAIR101]], 1
+// CHECK-NEXT: [[ULLX_CAPTURE_ACTUAL104:%.*]] = load i64, ptr [[ULLX_ATOMIC_EXPECTED_PTR98]], align 8
+// CHECK-NEXT: [[ULLX_CAPTURE_CAPTURED105:%.*]] = select i1 [[ULLX_CMPXCHG_SUCCESS103]], i64 [[TMP94]], i64 [[ULLX_CAPTURE_ACTUAL104]]
+// CHECK-NEXT: store i64 [[ULLX_CAPTURE_CAPTURED105]], ptr [[ULLV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP96:%.*]] = load i64, ptr [[ULLV]], align 8
+// CHECK-NEXT: ret i64 [[TMP96]]
//
//
// CHECK-LABEL: @fxevd(
@@ -27407,6 +37091,42 @@ double fail_dxevd() {
// CHECK-NEXT: [[FV:%.*]] = alloca float, align 4
// CHECK-NEXT: [[FE:%.*]] = alloca float, align 4
// CHECK-NEXT: [[FD:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR1:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR2:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR3:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR4:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR11:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR12:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR13:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR20:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR21:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR22:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR30:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR31:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR32:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR39:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR40:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR41:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR49:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR50:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR51:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR58:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR59:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR60:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR68:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR69:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR70:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR77:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR78:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR79:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR87:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR88:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR89:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR96:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_DESIRED_PTR97:%.*]] = alloca float, align 4
+// CHECK-NEXT: [[FX_ATOMIC_EXPECTED_PTR98:%.*]] = alloca float, align 4
// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[FE]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP0]] monotonic, align 4
// CHECK-NEXT: store float [[TMP1]], ptr [[FV]], align 4
@@ -27415,222 +37135,264 @@ double fail_dxevd() {
// CHECK-NEXT: store float [[TMP3]], ptr [[FV]], align 4
// CHECK-NEXT: [[TMP4:%.*]] = load float, ptr [[FE]], align 4
// CHECK-NEXT: [[TMP5:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast float [[TMP4]] to i32
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast float [[TMP5]] to i32
-// CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP6]], i32 [[TMP7]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i1 } [[TMP8]], 0
-// CHECK-NEXT: [[TMP10:%.*]] = bitcast i32 [[TMP9]] to float
-// CHECK-NEXT: store float [[TMP10]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP11:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP12:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP11]] monotonic, align 4
-// CHECK-NEXT: [[TMP13:%.*]] = fcmp olt float [[TMP12]], [[TMP11]]
-// CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], float [[TMP11]], float [[TMP12]]
-// CHECK-NEXT: store float [[TMP14]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP15:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP16:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP15]] monotonic, align 4
-// CHECK-NEXT: [[TMP17:%.*]] = fcmp ogt float [[TMP16]], [[TMP15]]
-// CHECK-NEXT: [[TMP18:%.*]] = select i1 [[TMP17]], float [[TMP15]], float [[TMP16]]
-// CHECK-NEXT: store float [[TMP18]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP19:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP20:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP21:%.*]] = bitcast float [[TMP19]] to i32
-// CHECK-NEXT: [[TMP22:%.*]] = bitcast float [[TMP20]] to i32
-// CHECK-NEXT: [[TMP23:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP21]], i32 [[TMP22]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP24:%.*]] = extractvalue { i32, i1 } [[TMP23]], 0
-// CHECK-NEXT: [[TMP25:%.*]] = bitcast i32 [[TMP24]] to float
-// CHECK-NEXT: [[TMP26:%.*]] = extractvalue { i32, i1 } [[TMP23]], 1
-// CHECK-NEXT: [[TMP27:%.*]] = select i1 [[TMP26]], float [[TMP19]], float [[TMP25]]
-// CHECK-NEXT: store float [[TMP27]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP28:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP29:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP28]] acq_rel, align 4
+// CHECK-NEXT: store float [[TMP4]], ptr [[FX_ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: store float [[TMP5]], ptr [[FX_ATOMIC_DESIRED_PTR]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED]], i32 [[FX_CMPXCHG_DESIRED]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV]], ptr [[FX_ATOMIC_EXPECTED_PTR1]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR1]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP6:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP7:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP6]] monotonic, align 4
+// CHECK-NEXT: [[TMP8:%.*]] = fcmp olt float [[TMP7]], [[TMP6]]
+// CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], float [[TMP6]], float [[TMP7]]
+// CHECK-NEXT: store float [[TMP9]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP10:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP11:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP10]] monotonic, align 4
+// CHECK-NEXT: [[TMP12:%.*]] = fcmp ogt float [[TMP11]], [[TMP10]]
+// CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], float [[TMP10]], float [[TMP11]]
+// CHECK-NEXT: store float [[TMP13]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP14:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP15:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP14]], ptr [[FX_ATOMIC_EXPECTED_PTR2]], align 4
+// CHECK-NEXT: store float [[TMP15]], ptr [[FX_ATOMIC_DESIRED_PTR3]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED5:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR2]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED6:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR3]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR7:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED5]], i32 [[FX_CMPXCHG_DESIRED6]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV8:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR7]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV8]], ptr [[FX_ATOMIC_EXPECTED_PTR4]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS9:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR7]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL10:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR4]], align 4
+// CHECK-NEXT: [[FX_CAPTURE_CAPTURED:%.*]] = select i1 [[FX_CMPXCHG_SUCCESS9]], float [[TMP14]], float [[FX_CAPTURE_ACTUAL10]]
+// CHECK-NEXT: store float [[FX_CAPTURE_CAPTURED]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP16:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP17:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP16]] acq_rel, align 4
+// CHECK-NEXT: store float [[TMP17]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP18:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP19:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP18]] acq_rel, align 4
+// CHECK-NEXT: store float [[TMP19]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP20:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP21:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP20]], ptr [[FX_ATOMIC_EXPECTED_PTR11]], align 4
+// CHECK-NEXT: store float [[TMP21]], ptr [[FX_ATOMIC_DESIRED_PTR12]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED14:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR11]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED15:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR12]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR16:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED14]], i32 [[FX_CMPXCHG_DESIRED15]] acq_rel acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV17:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR16]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV17]], ptr [[FX_ATOMIC_EXPECTED_PTR13]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS18:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR16]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL19:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR13]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL19]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP22:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP22]] acq_rel, align 4
+// CHECK-NEXT: [[TMP24:%.*]] = fcmp olt float [[TMP23]], [[TMP22]]
+// CHECK-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], float [[TMP22]], float [[TMP23]]
+// CHECK-NEXT: store float [[TMP25]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP26:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP27:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP26]] acq_rel, align 4
+// CHECK-NEXT: [[TMP28:%.*]] = fcmp ogt float [[TMP27]], [[TMP26]]
+// CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], float [[TMP26]], float [[TMP27]]
// CHECK-NEXT: store float [[TMP29]], ptr [[FV]], align 4
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP30:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP30]] acq_rel, align 4
-// CHECK-NEXT: store float [[TMP31]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP31:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP30]], ptr [[FX_ATOMIC_EXPECTED_PTR20]], align 4
+// CHECK-NEXT: store float [[TMP31]], ptr [[FX_ATOMIC_DESIRED_PTR21]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED23:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR20]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED24:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR21]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR25:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED23]], i32 [[FX_CMPXCHG_DESIRED24]] acq_rel acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV26:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR25]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV26]], ptr [[FX_ATOMIC_EXPECTED_PTR22]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS27:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR25]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL28:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR22]], align 4
+// CHECK-NEXT: [[FX_CAPTURE_CAPTURED29:%.*]] = select i1 [[FX_CMPXCHG_SUCCESS27]], float [[TMP30]], float [[FX_CAPTURE_ACTUAL28]]
+// CHECK-NEXT: store float [[FX_CAPTURE_CAPTURED29]], ptr [[FV]], align 4
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP32:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP33:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP34:%.*]] = bitcast float [[TMP32]] to i32
-// CHECK-NEXT: [[TMP35:%.*]] = bitcast float [[TMP33]] to i32
-// CHECK-NEXT: [[TMP36:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP34]], i32 [[TMP35]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP37:%.*]] = extractvalue { i32, i1 } [[TMP36]], 0
-// CHECK-NEXT: [[TMP38:%.*]] = bitcast i32 [[TMP37]] to float
-// CHECK-NEXT: store float [[TMP38]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP39:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP40:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP39]] acq_rel, align 4
-// CHECK-NEXT: [[TMP41:%.*]] = fcmp olt float [[TMP40]], [[TMP39]]
-// CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP41]], float [[TMP39]], float [[TMP40]]
-// CHECK-NEXT: store float [[TMP42]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP43:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP44:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP43]] acq_rel, align 4
-// CHECK-NEXT: [[TMP45:%.*]] = fcmp ogt float [[TMP44]], [[TMP43]]
-// CHECK-NEXT: [[TMP46:%.*]] = select i1 [[TMP45]], float [[TMP43]], float [[TMP44]]
-// CHECK-NEXT: store float [[TMP46]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP47:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP48:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP49:%.*]] = bitcast float [[TMP47]] to i32
-// CHECK-NEXT: [[TMP50:%.*]] = bitcast float [[TMP48]] to i32
-// CHECK-NEXT: [[TMP51:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP49]], i32 [[TMP50]] acq_rel acquire, align 4
-// CHECK-NEXT: [[TMP52:%.*]] = extractvalue { i32, i1 } [[TMP51]], 0
-// CHECK-NEXT: [[TMP53:%.*]] = bitcast i32 [[TMP52]] to float
-// CHECK-NEXT: [[TMP54:%.*]] = extractvalue { i32, i1 } [[TMP51]], 1
-// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], float [[TMP47]], float [[TMP53]]
-// CHECK-NEXT: store float [[TMP55]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP56:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP56]] acquire, align 4
+// CHECK-NEXT: [[TMP33:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP32]] acquire, align 4
+// CHECK-NEXT: store float [[TMP33]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP34:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP34]] acquire, align 4
+// CHECK-NEXT: store float [[TMP35]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP36:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP37:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP36]], ptr [[FX_ATOMIC_EXPECTED_PTR30]], align 4
+// CHECK-NEXT: store float [[TMP37]], ptr [[FX_ATOMIC_DESIRED_PTR31]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED33:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR30]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED34:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR31]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR35:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED33]], i32 [[FX_CMPXCHG_DESIRED34]] acquire acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV36:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR35]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV36]], ptr [[FX_ATOMIC_EXPECTED_PTR32]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS37:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR35]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL38:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR32]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL38]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP38:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP39:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP38]] acquire, align 4
+// CHECK-NEXT: [[TMP40:%.*]] = fcmp olt float [[TMP39]], [[TMP38]]
+// CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], float [[TMP38]], float [[TMP39]]
+// CHECK-NEXT: store float [[TMP41]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP42:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP43:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP42]] acquire, align 4
+// CHECK-NEXT: [[TMP44:%.*]] = fcmp ogt float [[TMP43]], [[TMP42]]
+// CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP44]], float [[TMP42]], float [[TMP43]]
+// CHECK-NEXT: store float [[TMP45]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP46:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP47:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP46]], ptr [[FX_ATOMIC_EXPECTED_PTR39]], align 4
+// CHECK-NEXT: store float [[TMP47]], ptr [[FX_ATOMIC_DESIRED_PTR40]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED42:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR39]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED43:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR40]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR44:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED42]], i32 [[FX_CMPXCHG_DESIRED43]] acquire acquire, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV45:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR44]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV45]], ptr [[FX_ATOMIC_EXPECTED_PTR41]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS46:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR44]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL47:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR41]], align 4
+// CHECK-NEXT: [[FX_CAPTURE_CAPTURED48:%.*]] = select i1 [[FX_CMPXCHG_SUCCESS46]], float [[TMP46]], float [[FX_CAPTURE_ACTUAL47]]
+// CHECK-NEXT: store float [[FX_CAPTURE_CAPTURED48]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP48:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP49:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP48]] monotonic, align 4
+// CHECK-NEXT: store float [[TMP49]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP50:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP51:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP50]] monotonic, align 4
+// CHECK-NEXT: store float [[TMP51]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP52:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP53:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP52]], ptr [[FX_ATOMIC_EXPECTED_PTR49]], align 4
+// CHECK-NEXT: store float [[TMP53]], ptr [[FX_ATOMIC_DESIRED_PTR50]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED52:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR49]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED53:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR50]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR54:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED52]], i32 [[FX_CMPXCHG_DESIRED53]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV55:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR54]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV55]], ptr [[FX_ATOMIC_EXPECTED_PTR51]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS56:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR54]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL57:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR51]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL57]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP54:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP55:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP54]] monotonic, align 4
+// CHECK-NEXT: [[TMP56:%.*]] = fcmp olt float [[TMP55]], [[TMP54]]
+// CHECK-NEXT: [[TMP57:%.*]] = select i1 [[TMP56]], float [[TMP54]], float [[TMP55]]
// CHECK-NEXT: store float [[TMP57]], ptr [[FV]], align 4
// CHECK-NEXT: [[TMP58:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP59:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP58]] acquire, align 4
-// CHECK-NEXT: store float [[TMP59]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP60:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP61:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP62:%.*]] = bitcast float [[TMP60]] to i32
-// CHECK-NEXT: [[TMP63:%.*]] = bitcast float [[TMP61]] to i32
-// CHECK-NEXT: [[TMP64:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP62]], i32 [[TMP63]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP65:%.*]] = extractvalue { i32, i1 } [[TMP64]], 0
-// CHECK-NEXT: [[TMP66:%.*]] = bitcast i32 [[TMP65]] to float
-// CHECK-NEXT: store float [[TMP66]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP67:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP68:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP67]] acquire, align 4
-// CHECK-NEXT: [[TMP69:%.*]] = fcmp olt float [[TMP68]], [[TMP67]]
-// CHECK-NEXT: [[TMP70:%.*]] = select i1 [[TMP69]], float [[TMP67]], float [[TMP68]]
-// CHECK-NEXT: store float [[TMP70]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP71:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP72:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP71]] acquire, align 4
-// CHECK-NEXT: [[TMP73:%.*]] = fcmp ogt float [[TMP72]], [[TMP71]]
-// CHECK-NEXT: [[TMP74:%.*]] = select i1 [[TMP73]], float [[TMP71]], float [[TMP72]]
-// CHECK-NEXT: store float [[TMP74]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP75:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP76:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP77:%.*]] = bitcast float [[TMP75]] to i32
-// CHECK-NEXT: [[TMP78:%.*]] = bitcast float [[TMP76]] to i32
-// CHECK-NEXT: [[TMP79:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP77]], i32 [[TMP78]] acquire acquire, align 4
-// CHECK-NEXT: [[TMP80:%.*]] = extractvalue { i32, i1 } [[TMP79]], 0
-// CHECK-NEXT: [[TMP81:%.*]] = bitcast i32 [[TMP80]] to float
-// CHECK-NEXT: [[TMP82:%.*]] = extractvalue { i32, i1 } [[TMP79]], 1
-// CHECK-NEXT: [[TMP83:%.*]] = select i1 [[TMP82]], float [[TMP75]], float [[TMP81]]
+// CHECK-NEXT: [[TMP59:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP58]] monotonic, align 4
+// CHECK-NEXT: [[TMP60:%.*]] = fcmp ogt float [[TMP59]], [[TMP58]]
+// CHECK-NEXT: [[TMP61:%.*]] = select i1 [[TMP60]], float [[TMP58]], float [[TMP59]]
+// CHECK-NEXT: store float [[TMP61]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP62:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP63:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP62]], ptr [[FX_ATOMIC_EXPECTED_PTR58]], align 4
+// CHECK-NEXT: store float [[TMP63]], ptr [[FX_ATOMIC_DESIRED_PTR59]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED61:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR58]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED62:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR59]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR63:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED61]], i32 [[FX_CMPXCHG_DESIRED62]] monotonic monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV64:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR63]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV64]], ptr [[FX_ATOMIC_EXPECTED_PTR60]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS65:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR63]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL66:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR60]], align 4
+// CHECK-NEXT: [[FX_CAPTURE_CAPTURED67:%.*]] = select i1 [[FX_CMPXCHG_SUCCESS65]], float [[TMP62]], float [[FX_CAPTURE_ACTUAL66]]
+// CHECK-NEXT: store float [[FX_CAPTURE_CAPTURED67]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP64:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP65:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP64]] release, align 4
+// CHECK-NEXT: store float [[TMP65]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP66:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP66]] release, align 4
+// CHECK-NEXT: store float [[TMP67]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP68:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP69:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP68]], ptr [[FX_ATOMIC_EXPECTED_PTR68]], align 4
+// CHECK-NEXT: store float [[TMP69]], ptr [[FX_ATOMIC_DESIRED_PTR69]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED71:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR68]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED72:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR69]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR73:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED71]], i32 [[FX_CMPXCHG_DESIRED72]] release monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV74:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR73]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV74]], ptr [[FX_ATOMIC_EXPECTED_PTR70]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS75:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR73]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL76:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR70]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL76]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP70:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP71:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP70]] release, align 4
+// CHECK-NEXT: [[TMP72:%.*]] = fcmp olt float [[TMP71]], [[TMP70]]
+// CHECK-NEXT: [[TMP73:%.*]] = select i1 [[TMP72]], float [[TMP70]], float [[TMP71]]
+// CHECK-NEXT: store float [[TMP73]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP74:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP74]] release, align 4
+// CHECK-NEXT: [[TMP76:%.*]] = fcmp ogt float [[TMP75]], [[TMP74]]
+// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], float [[TMP74]], float [[TMP75]]
+// CHECK-NEXT: store float [[TMP77]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP78:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP79:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP78]], ptr [[FX_ATOMIC_EXPECTED_PTR77]], align 4
+// CHECK-NEXT: store float [[TMP79]], ptr [[FX_ATOMIC_DESIRED_PTR78]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED80:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR77]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED81:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR78]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR82:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED80]], i32 [[FX_CMPXCHG_DESIRED81]] release monotonic, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV83:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR82]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV83]], ptr [[FX_ATOMIC_EXPECTED_PTR79]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS84:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR82]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL85:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR79]], align 4
+// CHECK-NEXT: [[FX_CAPTURE_CAPTURED86:%.*]] = select i1 [[FX_CMPXCHG_SUCCESS84]], float [[TMP78]], float [[FX_CAPTURE_ACTUAL85]]
+// CHECK-NEXT: store float [[FX_CAPTURE_CAPTURED86]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP80:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP81:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP80]] seq_cst, align 4
+// CHECK-NEXT: store float [[TMP81]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP82:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP83:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP82]] seq_cst, align 4
// CHECK-NEXT: store float [[TMP83]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP84:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP85:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP84]] monotonic, align 4
-// CHECK-NEXT: store float [[TMP85]], ptr [[FV]], align 4
+// CHECK-NEXT: [[TMP85:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP84]], ptr [[FX_ATOMIC_EXPECTED_PTR87]], align 4
+// CHECK-NEXT: store float [[TMP85]], ptr [[FX_ATOMIC_DESIRED_PTR88]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED90:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR87]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED91:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR88]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR92:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED90]], i32 [[FX_CMPXCHG_DESIRED91]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV93:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR92]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV93]], ptr [[FX_ATOMIC_EXPECTED_PTR89]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS94:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR92]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL95:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR89]], align 4
+// CHECK-NEXT: store float [[FX_CAPTURE_ACTUAL95]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP86:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP86]] monotonic, align 4
-// CHECK-NEXT: store float [[TMP87]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP88:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP89:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP90:%.*]] = bitcast float [[TMP88]] to i32
-// CHECK-NEXT: [[TMP91:%.*]] = bitcast float [[TMP89]] to i32
-// CHECK-NEXT: [[TMP92:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP90]], i32 [[TMP91]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP93:%.*]] = extractvalue { i32, i1 } [[TMP92]], 0
-// CHECK-NEXT: [[TMP94:%.*]] = bitcast i32 [[TMP93]] to float
-// CHECK-NEXT: store float [[TMP94]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP95:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP96:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP95]] monotonic, align 4
-// CHECK-NEXT: [[TMP97:%.*]] = fcmp olt float [[TMP96]], [[TMP95]]
-// CHECK-NEXT: [[TMP98:%.*]] = select i1 [[TMP97]], float [[TMP95]], float [[TMP96]]
-// CHECK-NEXT: store float [[TMP98]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP99:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP100:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP99]] monotonic, align 4
-// CHECK-NEXT: [[TMP101:%.*]] = fcmp ogt float [[TMP100]], [[TMP99]]
-// CHECK-NEXT: [[TMP102:%.*]] = select i1 [[TMP101]], float [[TMP99]], float [[TMP100]]
-// CHECK-NEXT: store float [[TMP102]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP103:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP104:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP105:%.*]] = bitcast float [[TMP103]] to i32
-// CHECK-NEXT: [[TMP106:%.*]] = bitcast float [[TMP104]] to i32
-// CHECK-NEXT: [[TMP107:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP105]], i32 [[TMP106]] monotonic monotonic, align 4
-// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i32, i1 } [[TMP107]], 0
-// CHECK-NEXT: [[TMP109:%.*]] = bitcast i32 [[TMP108]] to float
-// CHECK-NEXT: [[TMP110:%.*]] = extractvalue { i32, i1 } [[TMP107]], 1
-// CHECK-NEXT: [[TMP111:%.*]] = select i1 [[TMP110]], float [[TMP103]], float [[TMP109]]
-// CHECK-NEXT: store float [[TMP111]], ptr [[FV]], align 4
-// CHECK-NEXT: [[TMP112:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP112]] release, align 4
-// CHECK-NEXT: store float [[TMP113]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP114:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP115:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP114]] release, align 4
-// CHECK-NEXT: store float [[TMP115]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP116:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP117:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP118:%.*]] = bitcast float [[TMP116]] to i32
-// CHECK-NEXT: [[TMP119:%.*]] = bitcast float [[TMP117]] to i32
-// CHECK-NEXT: [[TMP120:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP118]], i32 [[TMP119]] release monotonic, align 4
-// CHECK-NEXT: [[TMP121:%.*]] = extractvalue { i32, i1 } [[TMP120]], 0
-// CHECK-NEXT: [[TMP122:%.*]] = bitcast i32 [[TMP121]] to float
-// CHECK-NEXT: store float [[TMP122]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP123:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP124:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP123]] release, align 4
-// CHECK-NEXT: [[TMP125:%.*]] = fcmp olt float [[TMP124]], [[TMP123]]
-// CHECK-NEXT: [[TMP126:%.*]] = select i1 [[TMP125]], float [[TMP123]], float [[TMP124]]
-// CHECK-NEXT: store float [[TMP126]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP127:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP128:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP127]] release, align 4
-// CHECK-NEXT: [[TMP129:%.*]] = fcmp ogt float [[TMP128]], [[TMP127]]
-// CHECK-NEXT: [[TMP130:%.*]] = select i1 [[TMP129]], float [[TMP127]], float [[TMP128]]
-// CHECK-NEXT: store float [[TMP130]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP131:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP132:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP133:%.*]] = bitcast float [[TMP131]] to i32
-// CHECK-NEXT: [[TMP134:%.*]] = bitcast float [[TMP132]] to i32
-// CHECK-NEXT: [[TMP135:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP133]], i32 [[TMP134]] release monotonic, align 4
-// CHECK-NEXT: [[TMP136:%.*]] = extractvalue { i32, i1 } [[TMP135]], 0
-// CHECK-NEXT: [[TMP137:%.*]] = bitcast i32 [[TMP136]] to float
-// CHECK-NEXT: [[TMP138:%.*]] = extractvalue { i32, i1 } [[TMP135]], 1
-// CHECK-NEXT: [[TMP139:%.*]] = select i1 [[TMP138]], float [[TMP131]], float [[TMP137]]
-// CHECK-NEXT: store float [[TMP139]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP140:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP141:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP140]] seq_cst, align 4
-// CHECK-NEXT: store float [[TMP141]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP142:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP143:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP142]] seq_cst, align 4
-// CHECK-NEXT: store float [[TMP143]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP144:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP145:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP146:%.*]] = bitcast float [[TMP144]] to i32
-// CHECK-NEXT: [[TMP147:%.*]] = bitcast float [[TMP145]] to i32
-// CHECK-NEXT: [[TMP148:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP146]], i32 [[TMP147]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP149:%.*]] = extractvalue { i32, i1 } [[TMP148]], 0
-// CHECK-NEXT: [[TMP150:%.*]] = bitcast i32 [[TMP149]] to float
-// CHECK-NEXT: store float [[TMP150]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP151:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP152:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP151]] seq_cst, align 4
-// CHECK-NEXT: [[TMP153:%.*]] = fcmp olt float [[TMP152]], [[TMP151]]
-// CHECK-NEXT: [[TMP154:%.*]] = select i1 [[TMP153]], float [[TMP151]], float [[TMP152]]
-// CHECK-NEXT: store float [[TMP154]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP155:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP156:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP155]] seq_cst, align 4
-// CHECK-NEXT: [[TMP157:%.*]] = fcmp ogt float [[TMP156]], [[TMP155]]
-// CHECK-NEXT: [[TMP158:%.*]] = select i1 [[TMP157]], float [[TMP155]], float [[TMP156]]
-// CHECK-NEXT: store float [[TMP158]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP159:%.*]] = load float, ptr [[FE]], align 4
-// CHECK-NEXT: [[TMP160:%.*]] = load float, ptr [[FD]], align 4
-// CHECK-NEXT: [[TMP161:%.*]] = bitcast float [[TMP159]] to i32
-// CHECK-NEXT: [[TMP162:%.*]] = bitcast float [[TMP160]] to i32
-// CHECK-NEXT: [[TMP163:%.*]] = cmpxchg ptr [[FX]], i32 [[TMP161]], i32 [[TMP162]] seq_cst seq_cst, align 4
-// CHECK-NEXT: [[TMP164:%.*]] = extractvalue { i32, i1 } [[TMP163]], 0
-// CHECK-NEXT: [[TMP165:%.*]] = bitcast i32 [[TMP164]] to float
-// CHECK-NEXT: [[TMP166:%.*]] = extractvalue { i32, i1 } [[TMP163]], 1
-// CHECK-NEXT: [[TMP167:%.*]] = select i1 [[TMP166]], float [[TMP159]], float [[TMP165]]
-// CHECK-NEXT: store float [[TMP167]], ptr [[FV]], align 4
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP168:%.*]] = load float, ptr [[FV]], align 4
-// CHECK-NEXT: ret float [[TMP168]]
+// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw fmin ptr [[FX]], float [[TMP86]] seq_cst, align 4
+// CHECK-NEXT: [[TMP88:%.*]] = fcmp olt float [[TMP87]], [[TMP86]]
+// CHECK-NEXT: [[TMP89:%.*]] = select i1 [[TMP88]], float [[TMP86]], float [[TMP87]]
+// CHECK-NEXT: store float [[TMP89]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP90:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw fmax ptr [[FX]], float [[TMP90]] seq_cst, align 4
+// CHECK-NEXT: [[TMP92:%.*]] = fcmp ogt float [[TMP91]], [[TMP90]]
+// CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP92]], float [[TMP90]], float [[TMP91]]
+// CHECK-NEXT: store float [[TMP93]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP94:%.*]] = load float, ptr [[FE]], align 4
+// CHECK-NEXT: [[TMP95:%.*]] = load float, ptr [[FD]], align 4
+// CHECK-NEXT: store float [[TMP94]], ptr [[FX_ATOMIC_EXPECTED_PTR96]], align 4
+// CHECK-NEXT: store float [[TMP95]], ptr [[FX_ATOMIC_DESIRED_PTR97]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_EXPECTED99:%.*]] = load i32, ptr [[FX_ATOMIC_EXPECTED_PTR96]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_DESIRED100:%.*]] = load i32, ptr [[FX_ATOMIC_DESIRED_PTR97]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PAIR101:%.*]] = cmpxchg ptr [[FX]], i32 [[FX_CMPXCHG_EXPECTED99]], i32 [[FX_CMPXCHG_DESIRED100]] seq_cst seq_cst, align 4
+// CHECK-NEXT: [[FX_CMPXCHG_PREV102:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR101]], 0
+// CHECK-NEXT: store i32 [[FX_CMPXCHG_PREV102]], ptr [[FX_ATOMIC_EXPECTED_PTR98]], align 4
+// CHECK-NEXT: [[FX_CMPXCHG_SUCCESS103:%.*]] = extractvalue { i32, i1 } [[FX_CMPXCHG_PAIR101]], 1
+// CHECK-NEXT: [[FX_CAPTURE_ACTUAL104:%.*]] = load float, ptr [[FX_ATOMIC_EXPECTED_PTR98]], align 4
+// CHECK-NEXT: [[FX_CAPTURE_CAPTURED105:%.*]] = select i1 [[FX_CMPXCHG_SUCCESS103]], float [[TMP94]], float [[FX_CAPTURE_ACTUAL104]]
+// CHECK-NEXT: store float [[FX_CAPTURE_CAPTURED105]], ptr [[FV]], align 4
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP96:%.*]] = load float, ptr [[FV]], align 4
+// CHECK-NEXT: ret float [[TMP96]]
//
//
// CHECK-LABEL: @dxevd(
@@ -27639,6 +37401,42 @@ double fail_dxevd() {
// CHECK-NEXT: [[DV:%.*]] = alloca double, align 8
// CHECK-NEXT: [[DE:%.*]] = alloca double, align 8
// CHECK-NEXT: [[DD:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR1:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR2:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR3:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR4:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR11:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR12:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR13:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR20:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR21:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR22:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR30:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR31:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR32:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR39:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR40:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR41:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR49:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR50:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR51:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR58:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR59:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR60:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR68:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR69:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR70:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR77:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR78:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR79:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR87:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR88:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR89:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR96:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR97:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR98:%.*]] = alloca double, align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[DE]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP0]] monotonic, align 8
// CHECK-NEXT: store double [[TMP1]], ptr [[DV]], align 8
@@ -27647,222 +37445,573 @@ double fail_dxevd() {
// CHECK-NEXT: store double [[TMP3]], ptr [[DV]], align 8
// CHECK-NEXT: [[TMP4:%.*]] = load double, ptr [[DE]], align 8
// CHECK-NEXT: [[TMP5:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP6:%.*]] = bitcast double [[TMP4]] to i64
-// CHECK-NEXT: [[TMP7:%.*]] = bitcast double [[TMP5]] to i64
-// CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP6]], i64 [[TMP7]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i64, i1 } [[TMP8]], 0
-// CHECK-NEXT: [[TMP10:%.*]] = bitcast i64 [[TMP9]] to double
-// CHECK-NEXT: store double [[TMP10]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP11:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP12:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP11]] monotonic, align 8
-// CHECK-NEXT: [[TMP13:%.*]] = fcmp olt double [[TMP12]], [[TMP11]]
-// CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP13]], double [[TMP11]], double [[TMP12]]
-// CHECK-NEXT: store double [[TMP14]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP15:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP16:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP15]] monotonic, align 8
-// CHECK-NEXT: [[TMP17:%.*]] = fcmp ogt double [[TMP16]], [[TMP15]]
-// CHECK-NEXT: [[TMP18:%.*]] = select i1 [[TMP17]], double [[TMP15]], double [[TMP16]]
-// CHECK-NEXT: store double [[TMP18]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP19:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP20:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP21:%.*]] = bitcast double [[TMP19]] to i64
-// CHECK-NEXT: [[TMP22:%.*]] = bitcast double [[TMP20]] to i64
-// CHECK-NEXT: [[TMP23:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP21]], i64 [[TMP22]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP24:%.*]] = extractvalue { i64, i1 } [[TMP23]], 0
-// CHECK-NEXT: [[TMP25:%.*]] = bitcast i64 [[TMP24]] to double
-// CHECK-NEXT: [[TMP26:%.*]] = extractvalue { i64, i1 } [[TMP23]], 1
-// CHECK-NEXT: [[TMP27:%.*]] = select i1 [[TMP26]], double [[TMP19]], double [[TMP25]]
-// CHECK-NEXT: store double [[TMP27]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP28:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP29:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP28]] acq_rel, align 8
+// CHECK-NEXT: store double [[TMP4]], ptr [[DX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: store double [[TMP5]], ptr [[DX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED]], i64 [[DX_CMPXCHG_DESIRED]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV]], ptr [[DX_ATOMIC_EXPECTED_PTR1]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR1]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP6:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP7:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP6]] monotonic, align 8
+// CHECK-NEXT: [[TMP8:%.*]] = fcmp olt double [[TMP7]], [[TMP6]]
+// CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], double [[TMP6]], double [[TMP7]]
+// CHECK-NEXT: store double [[TMP9]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP10:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP11:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP10]] monotonic, align 8
+// CHECK-NEXT: [[TMP12:%.*]] = fcmp ogt double [[TMP11]], [[TMP10]]
+// CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], double [[TMP10]], double [[TMP11]]
+// CHECK-NEXT: store double [[TMP13]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP14:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP15:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP14]], ptr [[DX_ATOMIC_EXPECTED_PTR2]], align 8
+// CHECK-NEXT: store double [[TMP15]], ptr [[DX_ATOMIC_DESIRED_PTR3]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED5:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR2]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR3]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR7:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED5]], i64 [[DX_CMPXCHG_DESIRED6]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV8:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR7]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV8]], ptr [[DX_ATOMIC_EXPECTED_PTR4]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS9:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR7]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL10:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR4]], align 8
+// CHECK-NEXT: [[DX_CAPTURE_CAPTURED:%.*]] = select i1 [[DX_CMPXCHG_SUCCESS9]], double [[TMP14]], double [[DX_CAPTURE_ACTUAL10]]
+// CHECK-NEXT: store double [[DX_CAPTURE_CAPTURED]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP16:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP17:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP16]] acq_rel, align 8
+// CHECK-NEXT: store double [[TMP17]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP18:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP19:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP18]] acq_rel, align 8
+// CHECK-NEXT: store double [[TMP19]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP20:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP21:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP20]], ptr [[DX_ATOMIC_EXPECTED_PTR11]], align 8
+// CHECK-NEXT: store double [[TMP21]], ptr [[DX_ATOMIC_DESIRED_PTR12]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED14:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR11]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED15:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR12]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR16:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED14]], i64 [[DX_CMPXCHG_DESIRED15]] acq_rel acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV17:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR16]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV17]], ptr [[DX_ATOMIC_EXPECTED_PTR13]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS18:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR16]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL19:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR13]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL19]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP22:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP23:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP22]] acq_rel, align 8
+// CHECK-NEXT: [[TMP24:%.*]] = fcmp olt double [[TMP23]], [[TMP22]]
+// CHECK-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], double [[TMP22]], double [[TMP23]]
+// CHECK-NEXT: store double [[TMP25]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP26:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP27:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP26]] acq_rel, align 8
+// CHECK-NEXT: [[TMP28:%.*]] = fcmp ogt double [[TMP27]], [[TMP26]]
+// CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], double [[TMP26]], double [[TMP27]]
// CHECK-NEXT: store double [[TMP29]], ptr [[DV]], align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP30:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP30]] acq_rel, align 8
-// CHECK-NEXT: store double [[TMP31]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP31:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP30]], ptr [[DX_ATOMIC_EXPECTED_PTR20]], align 8
+// CHECK-NEXT: store double [[TMP31]], ptr [[DX_ATOMIC_DESIRED_PTR21]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED23:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR20]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED24:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR21]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR25:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED23]], i64 [[DX_CMPXCHG_DESIRED24]] acq_rel acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV26:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR25]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV26]], ptr [[DX_ATOMIC_EXPECTED_PTR22]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS27:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR25]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL28:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR22]], align 8
+// CHECK-NEXT: [[DX_CAPTURE_CAPTURED29:%.*]] = select i1 [[DX_CMPXCHG_SUCCESS27]], double [[TMP30]], double [[DX_CAPTURE_ACTUAL28]]
+// CHECK-NEXT: store double [[DX_CAPTURE_CAPTURED29]], ptr [[DV]], align 8
// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP32:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP33:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP34:%.*]] = bitcast double [[TMP32]] to i64
-// CHECK-NEXT: [[TMP35:%.*]] = bitcast double [[TMP33]] to i64
-// CHECK-NEXT: [[TMP36:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP34]], i64 [[TMP35]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP37:%.*]] = extractvalue { i64, i1 } [[TMP36]], 0
-// CHECK-NEXT: [[TMP38:%.*]] = bitcast i64 [[TMP37]] to double
-// CHECK-NEXT: store double [[TMP38]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP39:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP40:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP39]] acq_rel, align 8
-// CHECK-NEXT: [[TMP41:%.*]] = fcmp olt double [[TMP40]], [[TMP39]]
-// CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP41]], double [[TMP39]], double [[TMP40]]
-// CHECK-NEXT: store double [[TMP42]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP43:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP44:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP43]] acq_rel, align 8
-// CHECK-NEXT: [[TMP45:%.*]] = fcmp ogt double [[TMP44]], [[TMP43]]
-// CHECK-NEXT: [[TMP46:%.*]] = select i1 [[TMP45]], double [[TMP43]], double [[TMP44]]
-// CHECK-NEXT: store double [[TMP46]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP47:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP48:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP49:%.*]] = bitcast double [[TMP47]] to i64
-// CHECK-NEXT: [[TMP50:%.*]] = bitcast double [[TMP48]] to i64
-// CHECK-NEXT: [[TMP51:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP49]], i64 [[TMP50]] acq_rel acquire, align 8
-// CHECK-NEXT: [[TMP52:%.*]] = extractvalue { i64, i1 } [[TMP51]], 0
-// CHECK-NEXT: [[TMP53:%.*]] = bitcast i64 [[TMP52]] to double
-// CHECK-NEXT: [[TMP54:%.*]] = extractvalue { i64, i1 } [[TMP51]], 1
-// CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], double [[TMP47]], double [[TMP53]]
-// CHECK-NEXT: store double [[TMP55]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP56:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP57:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP56]] acquire, align 8
+// CHECK-NEXT: [[TMP33:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP32]] acquire, align 8
+// CHECK-NEXT: store double [[TMP33]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP34:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP35:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP34]] acquire, align 8
+// CHECK-NEXT: store double [[TMP35]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP36:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP37:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP36]], ptr [[DX_ATOMIC_EXPECTED_PTR30]], align 8
+// CHECK-NEXT: store double [[TMP37]], ptr [[DX_ATOMIC_DESIRED_PTR31]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED33:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR30]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED34:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR31]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR35:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED33]], i64 [[DX_CMPXCHG_DESIRED34]] acquire acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV36:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR35]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV36]], ptr [[DX_ATOMIC_EXPECTED_PTR32]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS37:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR35]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL38:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR32]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL38]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP38:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP39:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP38]] acquire, align 8
+// CHECK-NEXT: [[TMP40:%.*]] = fcmp olt double [[TMP39]], [[TMP38]]
+// CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], double [[TMP38]], double [[TMP39]]
+// CHECK-NEXT: store double [[TMP41]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP42:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP43:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP42]] acquire, align 8
+// CHECK-NEXT: [[TMP44:%.*]] = fcmp ogt double [[TMP43]], [[TMP42]]
+// CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP44]], double [[TMP42]], double [[TMP43]]
+// CHECK-NEXT: store double [[TMP45]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP46:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP47:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP46]], ptr [[DX_ATOMIC_EXPECTED_PTR39]], align 8
+// CHECK-NEXT: store double [[TMP47]], ptr [[DX_ATOMIC_DESIRED_PTR40]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED42:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR39]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED43:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR40]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR44:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED42]], i64 [[DX_CMPXCHG_DESIRED43]] acquire acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV45:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR44]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV45]], ptr [[DX_ATOMIC_EXPECTED_PTR41]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS46:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR44]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL47:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR41]], align 8
+// CHECK-NEXT: [[DX_CAPTURE_CAPTURED48:%.*]] = select i1 [[DX_CMPXCHG_SUCCESS46]], double [[TMP46]], double [[DX_CAPTURE_ACTUAL47]]
+// CHECK-NEXT: store double [[DX_CAPTURE_CAPTURED48]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP48:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP49:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP48]] monotonic, align 8
+// CHECK-NEXT: store double [[TMP49]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP50:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP51:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP50]] monotonic, align 8
+// CHECK-NEXT: store double [[TMP51]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP52:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP53:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP52]], ptr [[DX_ATOMIC_EXPECTED_PTR49]], align 8
+// CHECK-NEXT: store double [[TMP53]], ptr [[DX_ATOMIC_DESIRED_PTR50]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED52:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR49]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED53:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR50]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR54:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED52]], i64 [[DX_CMPXCHG_DESIRED53]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV55:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR54]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV55]], ptr [[DX_ATOMIC_EXPECTED_PTR51]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS56:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR54]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL57:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR51]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL57]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP54:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP55:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP54]] monotonic, align 8
+// CHECK-NEXT: [[TMP56:%.*]] = fcmp olt double [[TMP55]], [[TMP54]]
+// CHECK-NEXT: [[TMP57:%.*]] = select i1 [[TMP56]], double [[TMP54]], double [[TMP55]]
// CHECK-NEXT: store double [[TMP57]], ptr [[DV]], align 8
// CHECK-NEXT: [[TMP58:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP59:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP58]] acquire, align 8
-// CHECK-NEXT: store double [[TMP59]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP60:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP61:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP62:%.*]] = bitcast double [[TMP60]] to i64
-// CHECK-NEXT: [[TMP63:%.*]] = bitcast double [[TMP61]] to i64
-// CHECK-NEXT: [[TMP64:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP62]], i64 [[TMP63]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP65:%.*]] = extractvalue { i64, i1 } [[TMP64]], 0
-// CHECK-NEXT: [[TMP66:%.*]] = bitcast i64 [[TMP65]] to double
-// CHECK-NEXT: store double [[TMP66]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP67:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP68:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP67]] acquire, align 8
-// CHECK-NEXT: [[TMP69:%.*]] = fcmp olt double [[TMP68]], [[TMP67]]
-// CHECK-NEXT: [[TMP70:%.*]] = select i1 [[TMP69]], double [[TMP67]], double [[TMP68]]
-// CHECK-NEXT: store double [[TMP70]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP71:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP72:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP71]] acquire, align 8
-// CHECK-NEXT: [[TMP73:%.*]] = fcmp ogt double [[TMP72]], [[TMP71]]
-// CHECK-NEXT: [[TMP74:%.*]] = select i1 [[TMP73]], double [[TMP71]], double [[TMP72]]
-// CHECK-NEXT: store double [[TMP74]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP75:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP76:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP77:%.*]] = bitcast double [[TMP75]] to i64
-// CHECK-NEXT: [[TMP78:%.*]] = bitcast double [[TMP76]] to i64
-// CHECK-NEXT: [[TMP79:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP77]], i64 [[TMP78]] acquire acquire, align 8
-// CHECK-NEXT: [[TMP80:%.*]] = extractvalue { i64, i1 } [[TMP79]], 0
-// CHECK-NEXT: [[TMP81:%.*]] = bitcast i64 [[TMP80]] to double
-// CHECK-NEXT: [[TMP82:%.*]] = extractvalue { i64, i1 } [[TMP79]], 1
-// CHECK-NEXT: [[TMP83:%.*]] = select i1 [[TMP82]], double [[TMP75]], double [[TMP81]]
+// CHECK-NEXT: [[TMP59:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP58]] monotonic, align 8
+// CHECK-NEXT: [[TMP60:%.*]] = fcmp ogt double [[TMP59]], [[TMP58]]
+// CHECK-NEXT: [[TMP61:%.*]] = select i1 [[TMP60]], double [[TMP58]], double [[TMP59]]
+// CHECK-NEXT: store double [[TMP61]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP62:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP63:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP62]], ptr [[DX_ATOMIC_EXPECTED_PTR58]], align 8
+// CHECK-NEXT: store double [[TMP63]], ptr [[DX_ATOMIC_DESIRED_PTR59]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED61:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR58]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED62:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR59]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR63:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED61]], i64 [[DX_CMPXCHG_DESIRED62]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV64:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR63]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV64]], ptr [[DX_ATOMIC_EXPECTED_PTR60]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS65:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR63]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL66:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR60]], align 8
+// CHECK-NEXT: [[DX_CAPTURE_CAPTURED67:%.*]] = select i1 [[DX_CMPXCHG_SUCCESS65]], double [[TMP62]], double [[DX_CAPTURE_ACTUAL66]]
+// CHECK-NEXT: store double [[DX_CAPTURE_CAPTURED67]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP64:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP65:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP64]] release, align 8
+// CHECK-NEXT: store double [[TMP65]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP66:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP67:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP66]] release, align 8
+// CHECK-NEXT: store double [[TMP67]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP68:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP69:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP68]], ptr [[DX_ATOMIC_EXPECTED_PTR68]], align 8
+// CHECK-NEXT: store double [[TMP69]], ptr [[DX_ATOMIC_DESIRED_PTR69]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED71:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR68]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED72:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR69]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR73:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED71]], i64 [[DX_CMPXCHG_DESIRED72]] release monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV74:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR73]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV74]], ptr [[DX_ATOMIC_EXPECTED_PTR70]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS75:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR73]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL76:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR70]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL76]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP70:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP71:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP70]] release, align 8
+// CHECK-NEXT: [[TMP72:%.*]] = fcmp olt double [[TMP71]], [[TMP70]]
+// CHECK-NEXT: [[TMP73:%.*]] = select i1 [[TMP72]], double [[TMP70]], double [[TMP71]]
+// CHECK-NEXT: store double [[TMP73]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP74:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP75:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP74]] release, align 8
+// CHECK-NEXT: [[TMP76:%.*]] = fcmp ogt double [[TMP75]], [[TMP74]]
+// CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], double [[TMP74]], double [[TMP75]]
+// CHECK-NEXT: store double [[TMP77]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP78:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP79:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP78]], ptr [[DX_ATOMIC_EXPECTED_PTR77]], align 8
+// CHECK-NEXT: store double [[TMP79]], ptr [[DX_ATOMIC_DESIRED_PTR78]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED80:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR77]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED81:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR78]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR82:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED80]], i64 [[DX_CMPXCHG_DESIRED81]] release monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV83:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR82]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV83]], ptr [[DX_ATOMIC_EXPECTED_PTR79]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS84:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR82]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL85:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR79]], align 8
+// CHECK-NEXT: [[DX_CAPTURE_CAPTURED86:%.*]] = select i1 [[DX_CMPXCHG_SUCCESS84]], double [[TMP78]], double [[DX_CAPTURE_ACTUAL85]]
+// CHECK-NEXT: store double [[DX_CAPTURE_CAPTURED86]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP80:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP81:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP80]] seq_cst, align 8
+// CHECK-NEXT: store double [[TMP81]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP82:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP83:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP82]] seq_cst, align 8
// CHECK-NEXT: store double [[TMP83]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP84:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP85:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP84]] monotonic, align 8
-// CHECK-NEXT: store double [[TMP85]], ptr [[DV]], align 8
+// CHECK-NEXT: [[TMP85:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP84]], ptr [[DX_ATOMIC_EXPECTED_PTR87]], align 8
+// CHECK-NEXT: store double [[TMP85]], ptr [[DX_ATOMIC_DESIRED_PTR88]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED90:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR87]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED91:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR88]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR92:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED90]], i64 [[DX_CMPXCHG_DESIRED91]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV93:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR92]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV93]], ptr [[DX_ATOMIC_EXPECTED_PTR89]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS94:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR92]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL95:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR89]], align 8
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL95]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
// CHECK-NEXT: [[TMP86:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP86]] monotonic, align 8
-// CHECK-NEXT: store double [[TMP87]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP88:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP89:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP90:%.*]] = bitcast double [[TMP88]] to i64
-// CHECK-NEXT: [[TMP91:%.*]] = bitcast double [[TMP89]] to i64
-// CHECK-NEXT: [[TMP92:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP90]], i64 [[TMP91]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP93:%.*]] = extractvalue { i64, i1 } [[TMP92]], 0
-// CHECK-NEXT: [[TMP94:%.*]] = bitcast i64 [[TMP93]] to double
-// CHECK-NEXT: store double [[TMP94]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP95:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP96:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP95]] monotonic, align 8
-// CHECK-NEXT: [[TMP97:%.*]] = fcmp olt double [[TMP96]], [[TMP95]]
-// CHECK-NEXT: [[TMP98:%.*]] = select i1 [[TMP97]], double [[TMP95]], double [[TMP96]]
-// CHECK-NEXT: store double [[TMP98]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP99:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP100:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP99]] monotonic, align 8
-// CHECK-NEXT: [[TMP101:%.*]] = fcmp ogt double [[TMP100]], [[TMP99]]
-// CHECK-NEXT: [[TMP102:%.*]] = select i1 [[TMP101]], double [[TMP99]], double [[TMP100]]
-// CHECK-NEXT: store double [[TMP102]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP103:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP104:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP105:%.*]] = bitcast double [[TMP103]] to i64
-// CHECK-NEXT: [[TMP106:%.*]] = bitcast double [[TMP104]] to i64
-// CHECK-NEXT: [[TMP107:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP105]], i64 [[TMP106]] monotonic monotonic, align 8
-// CHECK-NEXT: [[TMP108:%.*]] = extractvalue { i64, i1 } [[TMP107]], 0
-// CHECK-NEXT: [[TMP109:%.*]] = bitcast i64 [[TMP108]] to double
-// CHECK-NEXT: [[TMP110:%.*]] = extractvalue { i64, i1 } [[TMP107]], 1
-// CHECK-NEXT: [[TMP111:%.*]] = select i1 [[TMP110]], double [[TMP103]], double [[TMP109]]
-// CHECK-NEXT: store double [[TMP111]], ptr [[DV]], align 8
-// CHECK-NEXT: [[TMP112:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP113:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP112]] release, align 8
-// CHECK-NEXT: store double [[TMP113]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP114:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP115:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP114]] release, align 8
-// CHECK-NEXT: store double [[TMP115]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP116:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP117:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP118:%.*]] = bitcast double [[TMP116]] to i64
-// CHECK-NEXT: [[TMP119:%.*]] = bitcast double [[TMP117]] to i64
-// CHECK-NEXT: [[TMP120:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP118]], i64 [[TMP119]] release monotonic, align 8
-// CHECK-NEXT: [[TMP121:%.*]] = extractvalue { i64, i1 } [[TMP120]], 0
-// CHECK-NEXT: [[TMP122:%.*]] = bitcast i64 [[TMP121]] to double
-// CHECK-NEXT: store double [[TMP122]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP123:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP124:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP123]] release, align 8
-// CHECK-NEXT: [[TMP125:%.*]] = fcmp olt double [[TMP124]], [[TMP123]]
-// CHECK-NEXT: [[TMP126:%.*]] = select i1 [[TMP125]], double [[TMP123]], double [[TMP124]]
-// CHECK-NEXT: store double [[TMP126]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP127:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP128:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP127]] release, align 8
-// CHECK-NEXT: [[TMP129:%.*]] = fcmp ogt double [[TMP128]], [[TMP127]]
-// CHECK-NEXT: [[TMP130:%.*]] = select i1 [[TMP129]], double [[TMP127]], double [[TMP128]]
-// CHECK-NEXT: store double [[TMP130]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP131:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP132:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP133:%.*]] = bitcast double [[TMP131]] to i64
-// CHECK-NEXT: [[TMP134:%.*]] = bitcast double [[TMP132]] to i64
-// CHECK-NEXT: [[TMP135:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP133]], i64 [[TMP134]] release monotonic, align 8
-// CHECK-NEXT: [[TMP136:%.*]] = extractvalue { i64, i1 } [[TMP135]], 0
-// CHECK-NEXT: [[TMP137:%.*]] = bitcast i64 [[TMP136]] to double
-// CHECK-NEXT: [[TMP138:%.*]] = extractvalue { i64, i1 } [[TMP135]], 1
-// CHECK-NEXT: [[TMP139:%.*]] = select i1 [[TMP138]], double [[TMP131]], double [[TMP137]]
-// CHECK-NEXT: store double [[TMP139]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP140:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP141:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP140]] seq_cst, align 8
-// CHECK-NEXT: store double [[TMP141]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP142:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP143:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP142]] seq_cst, align 8
-// CHECK-NEXT: store double [[TMP143]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP144:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP145:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP146:%.*]] = bitcast double [[TMP144]] to i64
-// CHECK-NEXT: [[TMP147:%.*]] = bitcast double [[TMP145]] to i64
-// CHECK-NEXT: [[TMP148:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP146]], i64 [[TMP147]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP149:%.*]] = extractvalue { i64, i1 } [[TMP148]], 0
-// CHECK-NEXT: [[TMP150:%.*]] = bitcast i64 [[TMP149]] to double
-// CHECK-NEXT: store double [[TMP150]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP151:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP152:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP151]] seq_cst, align 8
-// CHECK-NEXT: [[TMP153:%.*]] = fcmp olt double [[TMP152]], [[TMP151]]
-// CHECK-NEXT: [[TMP154:%.*]] = select i1 [[TMP153]], double [[TMP151]], double [[TMP152]]
-// CHECK-NEXT: store double [[TMP154]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP155:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP156:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP155]] seq_cst, align 8
-// CHECK-NEXT: [[TMP157:%.*]] = fcmp ogt double [[TMP156]], [[TMP155]]
-// CHECK-NEXT: [[TMP158:%.*]] = select i1 [[TMP157]], double [[TMP155]], double [[TMP156]]
-// CHECK-NEXT: store double [[TMP158]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP159:%.*]] = load double, ptr [[DE]], align 8
-// CHECK-NEXT: [[TMP160:%.*]] = load double, ptr [[DD]], align 8
-// CHECK-NEXT: [[TMP161:%.*]] = bitcast double [[TMP159]] to i64
-// CHECK-NEXT: [[TMP162:%.*]] = bitcast double [[TMP160]] to i64
-// CHECK-NEXT: [[TMP163:%.*]] = cmpxchg ptr [[DX]], i64 [[TMP161]], i64 [[TMP162]] seq_cst seq_cst, align 8
-// CHECK-NEXT: [[TMP164:%.*]] = extractvalue { i64, i1 } [[TMP163]], 0
-// CHECK-NEXT: [[TMP165:%.*]] = bitcast i64 [[TMP164]] to double
-// CHECK-NEXT: [[TMP166:%.*]] = extractvalue { i64, i1 } [[TMP163]], 1
-// CHECK-NEXT: [[TMP167:%.*]] = select i1 [[TMP166]], double [[TMP159]], double [[TMP165]]
-// CHECK-NEXT: store double [[TMP167]], ptr [[DV]], align 8
-// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
-// CHECK-NEXT: [[TMP168:%.*]] = load double, ptr [[DV]], align 8
-// CHECK-NEXT: ret double [[TMP168]]
+// CHECK-NEXT: [[TMP87:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP86]] seq_cst, align 8
+// CHECK-NEXT: [[TMP88:%.*]] = fcmp olt double [[TMP87]], [[TMP86]]
+// CHECK-NEXT: [[TMP89:%.*]] = select i1 [[TMP88]], double [[TMP86]], double [[TMP87]]
+// CHECK-NEXT: store double [[TMP89]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP90:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP91:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP90]] seq_cst, align 8
+// CHECK-NEXT: [[TMP92:%.*]] = fcmp ogt double [[TMP91]], [[TMP90]]
+// CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP92]], double [[TMP90]], double [[TMP91]]
+// CHECK-NEXT: store double [[TMP93]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP94:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP95:%.*]] = load double, ptr [[DD]], align 8
+// CHECK-NEXT: store double [[TMP94]], ptr [[DX_ATOMIC_EXPECTED_PTR96]], align 8
+// CHECK-NEXT: store double [[TMP95]], ptr [[DX_ATOMIC_DESIRED_PTR97]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED99:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR96]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED100:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR97]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR101:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED99]], i64 [[DX_CMPXCHG_DESIRED100]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV102:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR101]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV102]], ptr [[DX_ATOMIC_EXPECTED_PTR98]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS103:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR101]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL104:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR98]], align 8
+// CHECK-NEXT: [[DX_CAPTURE_CAPTURED105:%.*]] = select i1 [[DX_CMPXCHG_SUCCESS103]], double [[TMP94]], double [[DX_CAPTURE_ACTUAL104]]
+// CHECK-NEXT: store double [[DX_CAPTURE_CAPTURED105]], ptr [[DV]], align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP96:%.*]] = load double, ptr [[DV]], align 8
+// CHECK-NEXT: ret double [[TMP96]]
+//
+//
+// CHECK-LABEL: @fail_dxevd(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[DX:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DV:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DE:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DD:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR1:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR2:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR3:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR4:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR13:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR14:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR15:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR24:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR25:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR26:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR35:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR36:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR37:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR46:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR47:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR48:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR57:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR58:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR59:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR68:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR69:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR70:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR79:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR80:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR81:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR90:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR91:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR92:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR101:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR102:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR103:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR112:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR113:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR114:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR123:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR124:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR125:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR134:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR135:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR136:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR145:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_DESIRED_PTR146:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[DX_ATOMIC_EXPECTED_PTR147:%.*]] = alloca double, align 8
+// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[DV]], align 8
+// CHECK-NEXT: store double [[TMP0]], ptr [[DX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: store double [[TMP1]], ptr [[DX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED]], i64 [[DX_CMPXCHG_DESIRED]] monotonic monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV]], ptr [[DX_ATOMIC_EXPECTED_PTR1]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR1]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS]], label [[DX_ATOMIC_EXIT:%.*]], label [[DX_ATOMIC_CONT:%.*]]
+// CHECK: dx.atomic.cont:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL]], ptr [[DD]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT]]
+// CHECK: dx.atomic.exit:
+// CHECK-NEXT: [[TMP2:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP3:%.*]] = load double, ptr [[DV]], align 8
+// CHECK-NEXT: store double [[TMP2]], ptr [[DX_ATOMIC_EXPECTED_PTR2]], align 8
+// CHECK-NEXT: store double [[TMP3]], ptr [[DX_ATOMIC_DESIRED_PTR3]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED5:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR2]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED6:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR3]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR7:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED5]], i64 [[DX_CMPXCHG_DESIRED6]] acquire monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV8:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR7]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV8]], ptr [[DX_ATOMIC_EXPECTED_PTR4]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS9:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR7]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL10:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR4]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS9]], label [[DX_ATOMIC_EXIT11:%.*]], label [[DX_ATOMIC_CONT12:%.*]]
+// CHECK: dx.atomic.cont12:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL10]], ptr [[DD]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT11]]
+// CHECK: dx.atomic.exit11:
+// CHECK-NEXT: [[TMP4:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP5:%.*]] = load double, ptr [[DV]], align 8
+// CHECK-NEXT: store double [[TMP4]], ptr [[DX_ATOMIC_EXPECTED_PTR13]], align 8
+// CHECK-NEXT: store double [[TMP5]], ptr [[DX_ATOMIC_DESIRED_PTR14]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED16:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR13]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED17:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR14]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR18:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED16]], i64 [[DX_CMPXCHG_DESIRED17]] release monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV19:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR18]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV19]], ptr [[DX_ATOMIC_EXPECTED_PTR15]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS20:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR18]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL21:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR15]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS20]], label [[DX_ATOMIC_EXIT22:%.*]], label [[DX_ATOMIC_CONT23:%.*]]
+// CHECK: dx.atomic.cont23:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL21]], ptr [[DD]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT22]]
+// CHECK: dx.atomic.exit22:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP6:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP7:%.*]] = load double, ptr [[DV]], align 8
+// CHECK-NEXT: store double [[TMP6]], ptr [[DX_ATOMIC_EXPECTED_PTR24]], align 8
+// CHECK-NEXT: store double [[TMP7]], ptr [[DX_ATOMIC_DESIRED_PTR25]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED27:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR24]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED28:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR25]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR29:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED27]], i64 [[DX_CMPXCHG_DESIRED28]] acq_rel monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV30:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR29]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV30]], ptr [[DX_ATOMIC_EXPECTED_PTR26]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS31:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR29]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL32:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR26]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS31]], label [[DX_ATOMIC_EXIT33:%.*]], label [[DX_ATOMIC_CONT34:%.*]]
+// CHECK: dx.atomic.cont34:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL32]], ptr [[DD]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT33]]
+// CHECK: dx.atomic.exit33:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP8:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP9:%.*]] = load double, ptr [[DV]], align 8
+// CHECK-NEXT: store double [[TMP8]], ptr [[DX_ATOMIC_EXPECTED_PTR35]], align 8
+// CHECK-NEXT: store double [[TMP9]], ptr [[DX_ATOMIC_DESIRED_PTR36]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED38:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR35]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED39:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR36]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR40:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED38]], i64 [[DX_CMPXCHG_DESIRED39]] seq_cst monotonic, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV41:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR40]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV41]], ptr [[DX_ATOMIC_EXPECTED_PTR37]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS42:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR40]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL43:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR37]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS42]], label [[DX_ATOMIC_EXIT44:%.*]], label [[DX_ATOMIC_CONT45:%.*]]
+// CHECK: dx.atomic.cont45:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL43]], ptr [[DD]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT44]]
+// CHECK: dx.atomic.exit44:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP10:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP11:%.*]] = load double, ptr [[DV]], align 8
+// CHECK-NEXT: store double [[TMP10]], ptr [[DX_ATOMIC_EXPECTED_PTR46]], align 8
+// CHECK-NEXT: store double [[TMP11]], ptr [[DX_ATOMIC_DESIRED_PTR47]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED49:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR46]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED50:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR47]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR51:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED49]], i64 [[DX_CMPXCHG_DESIRED50]] acquire acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV52:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR51]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV52]], ptr [[DX_ATOMIC_EXPECTED_PTR48]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS53:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR51]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL54:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR48]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS53]], label [[DX_ATOMIC_EXIT55:%.*]], label [[DX_ATOMIC_CONT56:%.*]]
+// CHECK: dx.atomic.cont56:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL54]], ptr [[DD]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT55]]
+// CHECK: dx.atomic.exit55:
+// CHECK-NEXT: [[TMP12:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP13:%.*]] = load double, ptr [[DV]], align 8
+// CHECK-NEXT: store double [[TMP12]], ptr [[DX_ATOMIC_EXPECTED_PTR57]], align 8
+// CHECK-NEXT: store double [[TMP13]], ptr [[DX_ATOMIC_DESIRED_PTR58]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED60:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR57]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED61:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR58]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR62:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED60]], i64 [[DX_CMPXCHG_DESIRED61]] acquire acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV63:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR62]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV63]], ptr [[DX_ATOMIC_EXPECTED_PTR59]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS64:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR62]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL65:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR59]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS64]], label [[DX_ATOMIC_EXIT66:%.*]], label [[DX_ATOMIC_CONT67:%.*]]
+// CHECK: dx.atomic.cont67:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL65]], ptr [[DD]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT66]]
+// CHECK: dx.atomic.exit66:
+// CHECK-NEXT: [[TMP14:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP15:%.*]] = load double, ptr [[DV]], align 8
+// CHECK-NEXT: store double [[TMP14]], ptr [[DX_ATOMIC_EXPECTED_PTR68]], align 8
+// CHECK-NEXT: store double [[TMP15]], ptr [[DX_ATOMIC_DESIRED_PTR69]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED71:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR68]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED72:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR69]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR73:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED71]], i64 [[DX_CMPXCHG_DESIRED72]] acq_rel acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV74:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR73]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV74]], ptr [[DX_ATOMIC_EXPECTED_PTR70]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS75:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR73]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL76:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR70]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS75]], label [[DX_ATOMIC_EXIT77:%.*]], label [[DX_ATOMIC_CONT78:%.*]]
+// CHECK: dx.atomic.cont78:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL76]], ptr [[DD]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT77]]
+// CHECK: dx.atomic.exit77:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP16:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP17:%.*]] = load double, ptr [[DV]], align 8
+// CHECK-NEXT: store double [[TMP16]], ptr [[DX_ATOMIC_EXPECTED_PTR79]], align 8
+// CHECK-NEXT: store double [[TMP17]], ptr [[DX_ATOMIC_DESIRED_PTR80]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED82:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR79]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED83:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR80]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR84:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED82]], i64 [[DX_CMPXCHG_DESIRED83]] acq_rel acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV85:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR84]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV85]], ptr [[DX_ATOMIC_EXPECTED_PTR81]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS86:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR84]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL87:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR81]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS86]], label [[DX_ATOMIC_EXIT88:%.*]], label [[DX_ATOMIC_CONT89:%.*]]
+// CHECK: dx.atomic.cont89:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL87]], ptr [[DD]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT88]]
+// CHECK: dx.atomic.exit88:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP18:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP19:%.*]] = load double, ptr [[DV]], align 8
+// CHECK-NEXT: store double [[TMP18]], ptr [[DX_ATOMIC_EXPECTED_PTR90]], align 8
+// CHECK-NEXT: store double [[TMP19]], ptr [[DX_ATOMIC_DESIRED_PTR91]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED93:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR90]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED94:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR91]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR95:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED93]], i64 [[DX_CMPXCHG_DESIRED94]] seq_cst acquire, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV96:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR95]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV96]], ptr [[DX_ATOMIC_EXPECTED_PTR92]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS97:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR95]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL98:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR92]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS97]], label [[DX_ATOMIC_EXIT99:%.*]], label [[DX_ATOMIC_CONT100:%.*]]
+// CHECK: dx.atomic.cont100:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL98]], ptr [[DD]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT99]]
+// CHECK: dx.atomic.exit99:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP20:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP21:%.*]] = load double, ptr [[DV]], align 8
+// CHECK-NEXT: store double [[TMP20]], ptr [[DX_ATOMIC_EXPECTED_PTR101]], align 8
+// CHECK-NEXT: store double [[TMP21]], ptr [[DX_ATOMIC_DESIRED_PTR102]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED104:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR101]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED105:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR102]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR106:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED104]], i64 [[DX_CMPXCHG_DESIRED105]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV107:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR106]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV107]], ptr [[DX_ATOMIC_EXPECTED_PTR103]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS108:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR106]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL109:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR103]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS108]], label [[DX_ATOMIC_EXIT110:%.*]], label [[DX_ATOMIC_CONT111:%.*]]
+// CHECK: dx.atomic.cont111:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL109]], ptr [[DD]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT110]]
+// CHECK: dx.atomic.exit110:
+// CHECK-NEXT: [[TMP22:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP23:%.*]] = load double, ptr [[DV]], align 8
+// CHECK-NEXT: store double [[TMP22]], ptr [[DX_ATOMIC_EXPECTED_PTR112]], align 8
+// CHECK-NEXT: store double [[TMP23]], ptr [[DX_ATOMIC_DESIRED_PTR113]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED115:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR112]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED116:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR113]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR117:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED115]], i64 [[DX_CMPXCHG_DESIRED116]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV118:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR117]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV118]], ptr [[DX_ATOMIC_EXPECTED_PTR114]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS119:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR117]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL120:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR114]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS119]], label [[DX_ATOMIC_EXIT121:%.*]], label [[DX_ATOMIC_CONT122:%.*]]
+// CHECK: dx.atomic.cont122:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL120]], ptr [[DD]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT121]]
+// CHECK: dx.atomic.exit121:
+// CHECK-NEXT: [[TMP24:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP25:%.*]] = load double, ptr [[DV]], align 8
+// CHECK-NEXT: store double [[TMP24]], ptr [[DX_ATOMIC_EXPECTED_PTR123]], align 8
+// CHECK-NEXT: store double [[TMP25]], ptr [[DX_ATOMIC_DESIRED_PTR124]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED126:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR123]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED127:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR124]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR128:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED126]], i64 [[DX_CMPXCHG_DESIRED127]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV129:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR128]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV129]], ptr [[DX_ATOMIC_EXPECTED_PTR125]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS130:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR128]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL131:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR125]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS130]], label [[DX_ATOMIC_EXIT132:%.*]], label [[DX_ATOMIC_CONT133:%.*]]
+// CHECK: dx.atomic.cont133:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL131]], ptr [[DD]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT132]]
+// CHECK: dx.atomic.exit132:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP26:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP27:%.*]] = load double, ptr [[DV]], align 8
+// CHECK-NEXT: store double [[TMP26]], ptr [[DX_ATOMIC_EXPECTED_PTR134]], align 8
+// CHECK-NEXT: store double [[TMP27]], ptr [[DX_ATOMIC_DESIRED_PTR135]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED137:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR134]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED138:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR135]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR139:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED137]], i64 [[DX_CMPXCHG_DESIRED138]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV140:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR139]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV140]], ptr [[DX_ATOMIC_EXPECTED_PTR136]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS141:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR139]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL142:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR136]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS141]], label [[DX_ATOMIC_EXIT143:%.*]], label [[DX_ATOMIC_CONT144:%.*]]
+// CHECK: dx.atomic.cont144:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL142]], ptr [[DD]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT143]]
+// CHECK: dx.atomic.exit143:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP28:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP29:%.*]] = load double, ptr [[DV]], align 8
+// CHECK-NEXT: store double [[TMP28]], ptr [[DX_ATOMIC_EXPECTED_PTR145]], align 8
+// CHECK-NEXT: store double [[TMP29]], ptr [[DX_ATOMIC_DESIRED_PTR146]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_EXPECTED148:%.*]] = load i64, ptr [[DX_ATOMIC_EXPECTED_PTR145]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_DESIRED149:%.*]] = load i64, ptr [[DX_ATOMIC_DESIRED_PTR146]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PAIR150:%.*]] = cmpxchg ptr [[DX]], i64 [[DX_CMPXCHG_EXPECTED148]], i64 [[DX_CMPXCHG_DESIRED149]] seq_cst seq_cst, align 8
+// CHECK-NEXT: [[DX_CMPXCHG_PREV151:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR150]], 0
+// CHECK-NEXT: store i64 [[DX_CMPXCHG_PREV151]], ptr [[DX_ATOMIC_EXPECTED_PTR147]], align 8
+// CHECK-NEXT: [[DX_CMPXCHG_SUCCESS152:%.*]] = extractvalue { i64, i1 } [[DX_CMPXCHG_PAIR150]], 1
+// CHECK-NEXT: [[DX_CAPTURE_ACTUAL153:%.*]] = load double, ptr [[DX_ATOMIC_EXPECTED_PTR147]], align 8
+// CHECK-NEXT: br i1 [[DX_CMPXCHG_SUCCESS152]], label [[DX_ATOMIC_EXIT154:%.*]], label [[DX_ATOMIC_CONT155:%.*]]
+// CHECK: dx.atomic.cont155:
+// CHECK-NEXT: store double [[DX_CAPTURE_ACTUAL153]], ptr [[DD]], align 8
+// CHECK-NEXT: br label [[DX_ATOMIC_EXIT154]]
+// CHECK: dx.atomic.exit154:
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP30:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP31:%.*]] = atomicrmw fmax ptr [[DX]], double [[TMP30]] seq_cst, align 8
+// CHECK-NEXT: call void @__kmpc_flush(ptr @[[GLOB1]])
+// CHECK-NEXT: [[TMP32:%.*]] = load double, ptr [[DE]], align 8
+// CHECK-NEXT: [[TMP33:%.*]] = atomicrmw fmin ptr [[DX]], double [[TMP32]] monotonic, align 8
+// CHECK-NEXT: [[TMP34:%.*]] = load double, ptr [[DX]], align 8
+// CHECK-NEXT: ret double [[TMP34]]
//
//
// SIMD-ONLY0-LABEL: @foo(
@@ -62024,89 +72173,234 @@ double fail_dxevd() {
// SIMD-ONLY0-NEXT: [[TMP180:%.*]] = load double, ptr [[DV]], align 8
// SIMD-ONLY0-NEXT: ret double [[TMP180]]
//
-// CHECK-LABEL: {{.+}}fail_dxevd{{.+}}
-// CHECK-NEXT: entry:
-// CHECK: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK-NEXT: {{.+}}cmpxchg ptr {{.+}} monotonic monotonic{{.+}}
-// CHECK: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK: {{.+}}cmpxchg ptr {{.+}} acquire monotonic{{.+}}
-// CHECK: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK: {{.+}}cmpxchg ptr {{.+}} release monotonic{{.+}}
-// CHECK: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK: {{.+}}cmpxchg ptr {{.+}} acq_rel monotonic{{.+}}
-// CHECK: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK-NEXT: {{.+}}cmpxchg ptr {{.+}} seq_cst monotonic{{.+}}
-// CHECK: {{.+}}__kmpc_flush{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK: {{.+}}cmpxchg ptr {{.+}} monotonic acquire{{.+}}
-// CHECK: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK: {{.+}}cmpxchg ptr {{.+}} acquire acquire{{.+}}
-// CHECK: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK: {{.+}}cmpxchg ptr {{.+}} release acquire{{.+}}
-// CHECK: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK: {{.+}}cmpxchg ptr {{.+}} acq_rel acquire{{.+}}
-// CHECK: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK: {{.+}}cmpxchg ptr {{.+}} seq_cst acquire{{.+}}
-// CHECK: {{.+}}__kmpc_flush{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK: {{.+}}cmpxchg ptr {{.+}} monotonic seq_cst{{.+}}
-// CHECK: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK: {{.+}}cmpxchg ptr {{.+}} acquire seq_cst{{.+}}
-// CHECK: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK: {{.+}}cmpxchg ptr {{.+}} release seq_cst{{.+}}
-// CHECK: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK: {{.+}}cmpxchg ptr {{.+}} acq_rel seq_cst{{.+}}
-// CHECK: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK-NEXT: {{.+}} bitcast double{{.+}}
-// CHECK: {{.+}}cmpxchg ptr {{.+}} seq_cst seq_cst{{.+}}
-// CHECK: call void {{.+}}__kmpc_flush{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} atomicrmw fmax {{.+}} seq_cst{{.+}}
-// CHECK-NEXT: call void {{.+}}__kmpc_flush{{.+}}
-// CHECK-NEXT: {{.+}} load double,{{.+}}
-// CHECK-NEXT: {{.+}} atomicrmw fmin {{.+}} monotonic{{.+}}
-// CHECK: ret double {{.+}}
+//
+// SIMD-ONLY0-LABEL: @fail_dxevd(
+// SIMD-ONLY0-NEXT: entry:
+// SIMD-ONLY0-NEXT: [[DX:%.*]] = alloca double, align 8
+// SIMD-ONLY0-NEXT: [[DV:%.*]] = alloca double, align 8
+// SIMD-ONLY0-NEXT: [[DE:%.*]] = alloca double, align 8
+// SIMD-ONLY0-NEXT: [[DD:%.*]] = alloca double, align 8
+// SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: [[CMP:%.*]] = fcmp oeq double [[TMP0]], [[TMP1]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+// SIMD-ONLY0: if.then:
+// SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load double, ptr [[DV]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP2]], ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END:%.*]]
+// SIMD-ONLY0: if.else:
+// SIMD-ONLY0-NEXT: [[TMP3:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP3]], ptr [[DD]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END]]
+// SIMD-ONLY0: if.end:
+// SIMD-ONLY0-NEXT: [[TMP4:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: [[CMP1:%.*]] = fcmp oeq double [[TMP4]], [[TMP5]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP1]], label [[IF_THEN2:%.*]], label [[IF_ELSE3:%.*]]
+// SIMD-ONLY0: if.then2:
+// SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load double, ptr [[DV]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP6]], ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END4:%.*]]
+// SIMD-ONLY0: if.else3:
+// SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP7]], ptr [[DD]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END4]]
+// SIMD-ONLY0: if.end4:
+// SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: [[CMP5:%.*]] = fcmp oeq double [[TMP8]], [[TMP9]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP5]], label [[IF_THEN6:%.*]], label [[IF_ELSE7:%.*]]
+// SIMD-ONLY0: if.then6:
+// SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load double, ptr [[DV]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP10]], ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END8:%.*]]
+// SIMD-ONLY0: if.else7:
+// SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP11]], ptr [[DD]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END8]]
+// SIMD-ONLY0: if.end8:
+// SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP13:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: [[CMP9:%.*]] = fcmp oeq double [[TMP12]], [[TMP13]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP9]], label [[IF_THEN10:%.*]], label [[IF_ELSE11:%.*]]
+// SIMD-ONLY0: if.then10:
+// SIMD-ONLY0-NEXT: [[TMP14:%.*]] = load double, ptr [[DV]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP14]], ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END12:%.*]]
+// SIMD-ONLY0: if.else11:
+// SIMD-ONLY0-NEXT: [[TMP15:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP15]], ptr [[DD]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END12]]
+// SIMD-ONLY0: if.end12:
+// SIMD-ONLY0-NEXT: [[TMP16:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP17:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: [[CMP13:%.*]] = fcmp oeq double [[TMP16]], [[TMP17]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP13]], label [[IF_THEN14:%.*]], label [[IF_ELSE15:%.*]]
+// SIMD-ONLY0: if.then14:
+// SIMD-ONLY0-NEXT: [[TMP18:%.*]] = load double, ptr [[DV]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP18]], ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END16:%.*]]
+// SIMD-ONLY0: if.else15:
+// SIMD-ONLY0-NEXT: [[TMP19:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP19]], ptr [[DD]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END16]]
+// SIMD-ONLY0: if.end16:
+// SIMD-ONLY0-NEXT: [[TMP20:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP21:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: [[CMP17:%.*]] = fcmp oeq double [[TMP20]], [[TMP21]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP17]], label [[IF_THEN18:%.*]], label [[IF_ELSE19:%.*]]
+// SIMD-ONLY0: if.then18:
+// SIMD-ONLY0-NEXT: [[TMP22:%.*]] = load double, ptr [[DV]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP22]], ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END20:%.*]]
+// SIMD-ONLY0: if.else19:
+// SIMD-ONLY0-NEXT: [[TMP23:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP23]], ptr [[DD]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END20]]
+// SIMD-ONLY0: if.end20:
+// SIMD-ONLY0-NEXT: [[TMP24:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP25:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: [[CMP21:%.*]] = fcmp oeq double [[TMP24]], [[TMP25]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP21]], label [[IF_THEN22:%.*]], label [[IF_ELSE23:%.*]]
+// SIMD-ONLY0: if.then22:
+// SIMD-ONLY0-NEXT: [[TMP26:%.*]] = load double, ptr [[DV]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP26]], ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END24:%.*]]
+// SIMD-ONLY0: if.else23:
+// SIMD-ONLY0-NEXT: [[TMP27:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP27]], ptr [[DD]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END24]]
+// SIMD-ONLY0: if.end24:
+// SIMD-ONLY0-NEXT: [[TMP28:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP29:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: [[CMP25:%.*]] = fcmp oeq double [[TMP28]], [[TMP29]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP25]], label [[IF_THEN26:%.*]], label [[IF_ELSE27:%.*]]
+// SIMD-ONLY0: if.then26:
+// SIMD-ONLY0-NEXT: [[TMP30:%.*]] = load double, ptr [[DV]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP30]], ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END28:%.*]]
+// SIMD-ONLY0: if.else27:
+// SIMD-ONLY0-NEXT: [[TMP31:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP31]], ptr [[DD]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END28]]
+// SIMD-ONLY0: if.end28:
+// SIMD-ONLY0-NEXT: [[TMP32:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP33:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: [[CMP29:%.*]] = fcmp oeq double [[TMP32]], [[TMP33]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP29]], label [[IF_THEN30:%.*]], label [[IF_ELSE31:%.*]]
+// SIMD-ONLY0: if.then30:
+// SIMD-ONLY0-NEXT: [[TMP34:%.*]] = load double, ptr [[DV]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP34]], ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END32:%.*]]
+// SIMD-ONLY0: if.else31:
+// SIMD-ONLY0-NEXT: [[TMP35:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP35]], ptr [[DD]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END32]]
+// SIMD-ONLY0: if.end32:
+// SIMD-ONLY0-NEXT: [[TMP36:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP37:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: [[CMP33:%.*]] = fcmp oeq double [[TMP36]], [[TMP37]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP33]], label [[IF_THEN34:%.*]], label [[IF_ELSE35:%.*]]
+// SIMD-ONLY0: if.then34:
+// SIMD-ONLY0-NEXT: [[TMP38:%.*]] = load double, ptr [[DV]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP38]], ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END36:%.*]]
+// SIMD-ONLY0: if.else35:
+// SIMD-ONLY0-NEXT: [[TMP39:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP39]], ptr [[DD]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END36]]
+// SIMD-ONLY0: if.end36:
+// SIMD-ONLY0-NEXT: [[TMP40:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP41:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: [[CMP37:%.*]] = fcmp oeq double [[TMP40]], [[TMP41]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP37]], label [[IF_THEN38:%.*]], label [[IF_ELSE39:%.*]]
+// SIMD-ONLY0: if.then38:
+// SIMD-ONLY0-NEXT: [[TMP42:%.*]] = load double, ptr [[DV]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP42]], ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END40:%.*]]
+// SIMD-ONLY0: if.else39:
+// SIMD-ONLY0-NEXT: [[TMP43:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP43]], ptr [[DD]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END40]]
+// SIMD-ONLY0: if.end40:
+// SIMD-ONLY0-NEXT: [[TMP44:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP45:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: [[CMP41:%.*]] = fcmp oeq double [[TMP44]], [[TMP45]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP41]], label [[IF_THEN42:%.*]], label [[IF_ELSE43:%.*]]
+// SIMD-ONLY0: if.then42:
+// SIMD-ONLY0-NEXT: [[TMP46:%.*]] = load double, ptr [[DV]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP46]], ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END44:%.*]]
+// SIMD-ONLY0: if.else43:
+// SIMD-ONLY0-NEXT: [[TMP47:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP47]], ptr [[DD]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END44]]
+// SIMD-ONLY0: if.end44:
+// SIMD-ONLY0-NEXT: [[TMP48:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP49:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: [[CMP45:%.*]] = fcmp oeq double [[TMP48]], [[TMP49]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP45]], label [[IF_THEN46:%.*]], label [[IF_ELSE47:%.*]]
+// SIMD-ONLY0: if.then46:
+// SIMD-ONLY0-NEXT: [[TMP50:%.*]] = load double, ptr [[DV]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP50]], ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END48:%.*]]
+// SIMD-ONLY0: if.else47:
+// SIMD-ONLY0-NEXT: [[TMP51:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP51]], ptr [[DD]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END48]]
+// SIMD-ONLY0: if.end48:
+// SIMD-ONLY0-NEXT: [[TMP52:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP53:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: [[CMP49:%.*]] = fcmp oeq double [[TMP52]], [[TMP53]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP49]], label [[IF_THEN50:%.*]], label [[IF_ELSE51:%.*]]
+// SIMD-ONLY0: if.then50:
+// SIMD-ONLY0-NEXT: [[TMP54:%.*]] = load double, ptr [[DV]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP54]], ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END52:%.*]]
+// SIMD-ONLY0: if.else51:
+// SIMD-ONLY0-NEXT: [[TMP55:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP55]], ptr [[DD]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END52]]
+// SIMD-ONLY0: if.end52:
+// SIMD-ONLY0-NEXT: [[TMP56:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP57:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: [[CMP53:%.*]] = fcmp oeq double [[TMP56]], [[TMP57]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP53]], label [[IF_THEN54:%.*]], label [[IF_ELSE55:%.*]]
+// SIMD-ONLY0: if.then54:
+// SIMD-ONLY0-NEXT: [[TMP58:%.*]] = load double, ptr [[DV]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP58]], ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END56:%.*]]
+// SIMD-ONLY0: if.else55:
+// SIMD-ONLY0-NEXT: [[TMP59:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: store double [[TMP59]], ptr [[DD]], align 8
+// SIMD-ONLY0-NEXT: br label [[IF_END56]]
+// SIMD-ONLY0: if.end56:
+// SIMD-ONLY0-NEXT: [[TMP60:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP61:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: [[CMP57:%.*]] = fcmp olt double [[TMP60]], [[TMP61]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP57]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// SIMD-ONLY0: cond.true:
+// SIMD-ONLY0-NEXT: [[TMP62:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: br label [[COND_END:%.*]]
+// SIMD-ONLY0: cond.false:
+// SIMD-ONLY0-NEXT: [[TMP63:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: br label [[COND_END]]
+// SIMD-ONLY0: cond.end:
+// SIMD-ONLY0-NEXT: [[COND:%.*]] = phi double [ [[TMP62]], [[COND_TRUE]] ], [ [[TMP63]], [[COND_FALSE]] ]
+// SIMD-ONLY0-NEXT: store double [[COND]], ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP64:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP65:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: [[CMP58:%.*]] = fcmp ogt double [[TMP64]], [[TMP65]]
+// SIMD-ONLY0-NEXT: br i1 [[CMP58]], label [[COND_TRUE59:%.*]], label [[COND_FALSE60:%.*]]
+// SIMD-ONLY0: cond.true59:
+// SIMD-ONLY0-NEXT: [[TMP66:%.*]] = load double, ptr [[DE]], align 8
+// SIMD-ONLY0-NEXT: br label [[COND_END61:%.*]]
+// SIMD-ONLY0: cond.false60:
+// SIMD-ONLY0-NEXT: [[TMP67:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: br label [[COND_END61]]
+// SIMD-ONLY0: cond.end61:
+// SIMD-ONLY0-NEXT: [[COND62:%.*]] = phi double [ [[TMP66]], [[COND_TRUE59]] ], [ [[TMP67]], [[COND_FALSE60]] ]
+// SIMD-ONLY0-NEXT: store double [[COND62]], ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: [[TMP68:%.*]] = load double, ptr [[DX]], align 8
+// SIMD-ONLY0-NEXT: ret double [[TMP68]]
+//
diff --git a/flang/lib/Semantics/CMakeLists.txt b/flang/lib/Semantics/CMakeLists.txt
index 00108dde49dbd..c94c6a5a70183 100644
--- a/flang/lib/Semantics/CMakeLists.txt
+++ b/flang/lib/Semantics/CMakeLists.txt
@@ -1,31 +1,10 @@
-add_flang_library(FortranSemantics
+add_flang_library(FortranSemantics PARTIAL_SOURCES_INTENDED
assignment.cpp
attr.cpp
canonicalize-acc.cpp
canonicalize-directives.cpp
canonicalize-do.cpp
canonicalize-omp.cpp
- check-acc-structure.cpp
- check-allocate.cpp
- check-arithmeticif.cpp
- check-call.cpp
- check-case.cpp
- check-coarray.cpp
- check-cuda.cpp
- check-data.cpp
- check-deallocate.cpp
- check-declarations.cpp
- check-do-forall.cpp
- check-if-stmt.cpp
- check-io.cpp
- check-namelist.cpp
- check-nullify.cpp
- check-omp-structure.cpp
- check-purity.cpp
- check-return.cpp
- check-select-rank.cpp
- check-select-type.cpp
- check-stop.cpp
compute-offsets.cpp
data-to-inits.cpp
definable.cpp
@@ -63,3 +42,45 @@ add_flang_library(FortranSemantics
FrontendOpenACC
TargetParser
)
+
+
+add_flang_library(FortranSemanticsCheck PARTIAL_SOURCES_INTENDED
+ check-acc-structure.cpp
+ check-allocate.cpp
+ check-arithmeticif.cpp
+ check-call.cpp
+ check-case.cpp
+ check-coarray.cpp
+ check-cuda.cpp
+ check-data.cpp
+ check-deallocate.cpp
+ check-declarations.cpp
+ check-do-forall.cpp
+ check-if-stmt.cpp
+ check-io.cpp
+ check-namelist.cpp
+ check-nullify.cpp
+ check-omp-structure.cpp
+ check-purity.cpp
+ check-return.cpp
+ check-select-rank.cpp
+ check-select-type.cpp
+ check-stop.cpp
+
+ DEPENDS
+ acc_gen
+ omp_gen
+
+ LINK_LIBS
+ FortranSupport
+ FortranParser
+ FortranEvaluate
+
+ LINK_COMPONENTS
+ Support
+ FrontendOpenMP
+ FrontendOpenACC
+ TargetParser
+)
+
+target_link_libraries(FortranSemantics PUBLIC FortranSemanticsCheck)
diff --git a/flang/test/Integration/OpenMP/atomic-capture-complex.f90 b/flang/test/Integration/OpenMP/atomic-capture-complex.f90
index 4ffd18097d79e..45cae12848be0 100644
--- a/flang/test/Integration/OpenMP/atomic-capture-complex.f90
+++ b/flang/test/Integration/OpenMP/atomic-capture-complex.f90
@@ -6,39 +6,43 @@
! added to this directory and sub-directories.
!===----------------------------------------------------------------------===!
-!RUN: %if x86-registered-target %{ %flang_fc1 -triple x86_64-unknown-linux-gnu -emit-llvm -fopenmp %s -o - | FileCheck --check-prefixes=CHECK,X86 %s %}
-!RUN: %if aarch64-registerd-target %{ %flang_fc1 -triple aarch64-unknown-linux-gnu -emit-llvm -fopenmp %s -o - | FileCheck --check-prefixes=CHECK,AARCH64 %s %}
+!RUN: %if x86-registered-target %{ %flang_fc1 -triple x86_64-unknown-linux-gnu -emit-llvm -fopenmp -mllvm --disable-llvm %s -o - | FileCheck %s %}
+!RUN: %if aarch64-registerd-target %{ %flang_fc1 -triple aarch64-unknown-linux-gnu -emit-llvm -fopenmp -mllvm --disable-llvm %s -o - | FileCheck %s %}
-!CHECK: %[[X_NEW_VAL:.*]] = alloca { float, float }, align 8
-!CHECK: %[[VAL_1:.*]] = alloca { float, float }, i64 1, align 8
-!CHECK: %[[ORIG_VAL:.*]] = alloca { float, float }, i64 1, align 8
-!CHECK: store { float, float } { float 2.000000e+00, float 2.000000e+00 }, ptr %[[ORIG_VAL]], align 4
-!CHECK: br label %entry
-
-!CHECK: entry:
-!CHECK: %[[ATOMIC_TEMP_LOAD:.*]] = alloca { float, float }, align 8
-!CHECK: call void @__atomic_load(i64 8, ptr %[[ORIG_VAL]], ptr %[[ATOMIC_TEMP_LOAD]], i32 0)
-!CHECK: %[[PHI_NODE_ENTRY_1:.*]] = load { float, float }, ptr %[[ATOMIC_TEMP_LOAD]], align 8
-!CHECK: br label %.atomic.cont
-
-!CHECK: .atomic.cont
-!CHECK: %[[VAL_4:.*]] = phi { float, float } [ %[[PHI_NODE_ENTRY_1]], %entry ], [ %{{.*}}, %.atomic.cont ]
-!CHECK: %[[VAL_5:.*]] = extractvalue { float, float } %[[VAL_4]], 0
-!CHECK: %[[VAL_6:.*]] = extractvalue { float, float } %[[VAL_4]], 1
-!CHECK: %[[VAL_7:.*]] = fadd contract float %[[VAL_5]], 1.000000e+00
-!CHECK: %[[VAL_8:.*]] = fadd contract float %[[VAL_6]], 1.000000e+00
-!CHECK: %[[VAL_9:.*]] = insertvalue { float, float } undef, float %[[VAL_7]], 0
-!CHECK: %[[VAL_10:.*]] = insertvalue { float, float } %[[VAL_9]], float %[[VAL_8]], 1
-!CHECK: store { float, float } %[[VAL_10]], ptr %[[X_NEW_VAL]], align 4
-!CHECK: %[[VAL_11:.*]] = call i1 @__atomic_compare_exchange(i64 8, ptr %[[ORIG_VAL]], ptr %[[ATOMIC_TEMP_LOAD]], ptr %[[X_NEW_VAL]],
-!i32 2, i32 2)
-!CHECK: %[[VAL_12:.*]] = load { float, float }, ptr %[[ATOMIC_TEMP_LOAD]], align 4
-!CHECK: br i1 %[[VAL_11]], label %.atomic.exit, label %.atomic.cont
-
-!CHECK: .atomic.exit
-!AARCH64: %[[LCSSA:.*]] = phi { float, float } [ %[[VAL_10]], %.atomic.cont ]
-!AARCH64: store { float, float } %[[LCSSA]], ptr %[[VAL_1]], align 4
-!X86: store { float, float } %[[VAL_10]], ptr %[[VAL_1]], align 4
+! CHECK-LABEL: define {{.*}}@_QQmain(
+! CHECK-NEXT: %[[DOTATOMIC_ORIG_PTR:.+]] = alloca { float, float }, align 8
+! CHECK-NEXT: %[[DOTATOMIC_UPD_PTR:.+]] = alloca { float, float }, align 8
+! CHECK-NEXT: %[[TMP1:.+]] = alloca { float, float }, i64 1, align 8
+! CHECK-NEXT: %[[TMP2:.+]] = alloca { float, float }, i64 1, align 8
+! CHECK-NEXT: store { float, float } { float 2.000000e+00, float 2.000000e+00 }, ptr %[[TMP2]], align 4
+! CHECK-NEXT: br label %[[ENTRY:.+]]
+! CHECK-EMPTY:
+! CHECK-NEXT: [[ENTRY]]:
+! CHECK-NEXT: %[[DOTATOMIC_LOAD:.+]] = load atomic i64, ptr %[[TMP2]] monotonic, align 8
+! CHECK-NEXT: store i64 %[[DOTATOMIC_LOAD]], ptr %[[DOTATOMIC_ORIG_PTR]], align 8
+! CHECK-NEXT: br label %[[DOTATOMIC_RETRY:.+]]
+! CHECK-EMPTY:
+! CHECK-NEXT: [[DOTATOMIC_RETRY]]:
+! CHECK-NEXT: %[[DOTATOMIC_ORIG:.+]] = load { float, float }, ptr %[[DOTATOMIC_ORIG_PTR]], align 4
+! CHECK-NEXT: %[[TMP3:.+]] = extractvalue { float, float } %[[DOTATOMIC_ORIG]], 0
+! CHECK-NEXT: %[[TMP4:.+]] = extractvalue { float, float } %[[DOTATOMIC_ORIG]], 1
+! CHECK-NEXT: %[[TMP5:.+]] = fadd contract float %[[TMP3]], 1.000000e+00
+! CHECK-NEXT: %[[TMP6:.+]] = fadd contract float %[[TMP4]], 1.000000e+00
+! CHECK-NEXT: %[[TMP7:.+]] = insertvalue { float, float } undef, float %[[TMP5]], 0
+! CHECK-NEXT: %[[TMP8:.+]] = insertvalue { float, float } %[[TMP7]], float %[[TMP6]], 1
+! CHECK-NEXT: store { float, float } %[[TMP8]], ptr %[[DOTATOMIC_UPD_PTR]], align 4
+! CHECK-NEXT: %[[DOTCMPXCHG_EXPECTED:.+]] = load i64, ptr %[[DOTATOMIC_ORIG_PTR]], align 8
+! CHECK-NEXT: %[[DOTCMPXCHG_DESIRED:.+]] = load i64, ptr %[[DOTATOMIC_UPD_PTR]], align 8
+! CHECK-NEXT: %[[DOTCMPXCHG_PAIR:.+]] = cmpxchg weak ptr %[[TMP2]], i64 %[[DOTCMPXCHG_EXPECTED]], i64 %[[DOTCMPXCHG_DESIRED]] monotonic monotonic, align 8
+! CHECK-NEXT: %[[DOTCMPXCHG_PREV:.+]] = extractvalue { i64, i1 } %[[DOTCMPXCHG_PAIR]], 0
+! CHECK-NEXT: store i64 %[[DOTCMPXCHG_PREV]], ptr %[[DOTATOMIC_ORIG_PTR]], align 8
+! CHECK-NEXT: %[[DOTCMPXCHG_SUCCESS:.+]] = extractvalue { i64, i1 } %[[DOTCMPXCHG_PAIR]], 1
+! CHECK-NEXT: br i1 %[[DOTCMPXCHG_SUCCESS]], label %[[DOTATOMIC_DONE:.+]], label %[[DOTATOMIC_RETRY]]
+! CHECK-EMPTY:
+! CHECK-NEXT: [[DOTATOMIC_DONE]]:
+! CHECK-NEXT: store { float, float } %[[TMP8]], ptr %[[TMP1]], align 4
+! CHECK-NEXT: ret void
+! CHECK-NEXT: }
program main
complex*8 ia, ib
diff --git a/llvm/include/llvm/Analysis/TargetLibraryInfo.def b/llvm/include/llvm/Analysis/TargetLibraryInfo.def
index db566b8ee610e..53fb11aff8a44 100644
--- a/llvm/include/llvm/Analysis/TargetLibraryInfo.def
+++ b/llvm/include/llvm/Analysis/TargetLibraryInfo.def
@@ -462,11 +462,91 @@ TLI_DEFINE_ENUM_INTERNAL(atomic_load)
TLI_DEFINE_STRING_INTERNAL("__atomic_load")
TLI_DEFINE_SIG_INTERNAL(Void, SizeT, Ptr, Ptr, Int)
+/// int8_t __atomic_load_1(void *ptr, int memorder);
+TLI_DEFINE_ENUM_INTERNAL(atomic_load_1)
+TLI_DEFINE_STRING_INTERNAL("__atomic_load_1")
+TLI_DEFINE_SIG_INTERNAL(Int8, Ptr, Int)
+
+/// int16_t __atomic_load_2(void *ptr, int memorder);
+TLI_DEFINE_ENUM_INTERNAL(atomic_load_2)
+TLI_DEFINE_STRING_INTERNAL("__atomic_load_2")
+TLI_DEFINE_SIG_INTERNAL(Int16, Ptr, Int)
+
+/// int32_t __atomic_load_4(void *ptr, int memorder);
+TLI_DEFINE_ENUM_INTERNAL(atomic_load_4)
+TLI_DEFINE_STRING_INTERNAL("__atomic_load_4")
+TLI_DEFINE_SIG_INTERNAL(Int32, Ptr, Int)
+
+/// int64_t __atomic_load_8(void *ptr int memorder);
+TLI_DEFINE_ENUM_INTERNAL(atomic_load_8)
+TLI_DEFINE_STRING_INTERNAL("__atomic_load_8")
+TLI_DEFINE_SIG_INTERNAL(Int64, Ptr, Int)
+
+/// int128_t __atomic_load_16(void *ptr, int memorder);
+TLI_DEFINE_ENUM_INTERNAL(atomic_load_16)
+TLI_DEFINE_STRING_INTERNAL("__atomic_load_16")
+TLI_DEFINE_SIG_INTERNAL(Int128, Ptr, Int)
+
/// void __atomic_store(size_t size, void *mptr, void *vptr, int smodel);
TLI_DEFINE_ENUM_INTERNAL(atomic_store)
TLI_DEFINE_STRING_INTERNAL("__atomic_store")
TLI_DEFINE_SIG_INTERNAL(Void, SizeT, Ptr, Ptr, Int)
+/// void __atomic_store_1(void *ptr, int8_t val, int smodel);
+TLI_DEFINE_ENUM_INTERNAL(atomic_store_1)
+TLI_DEFINE_STRING_INTERNAL("__atomic_store_1")
+TLI_DEFINE_SIG_INTERNAL(Void, Ptr, Int8, Int)
+
+/// void __atomic_store_2(void *ptr, int16_t val, int smodel);
+TLI_DEFINE_ENUM_INTERNAL(atomic_store_2)
+TLI_DEFINE_STRING_INTERNAL("__atomic_store_2")
+TLI_DEFINE_SIG_INTERNAL(Void, Ptr, Int16, Int)
+
+/// void __atomic_store_4(void *ptr, int32_t val, int smodel);
+TLI_DEFINE_ENUM_INTERNAL(atomic_store_4)
+TLI_DEFINE_STRING_INTERNAL("__atomic_store_4")
+TLI_DEFINE_SIG_INTERNAL(Void, Ptr, Int32, Int)
+
+/// void __atomic_store_8(void *ptr, int64_t val, int smodel);
+TLI_DEFINE_ENUM_INTERNAL(atomic_store_8)
+TLI_DEFINE_STRING_INTERNAL("__atomic_store_8")
+TLI_DEFINE_SIG_INTERNAL(Void, Ptr, Int64, Int)
+
+/// void __atomic_store_16(void *ptr, int128_t val, int smodel);
+TLI_DEFINE_ENUM_INTERNAL(atomic_store_16)
+TLI_DEFINE_STRING_INTERNAL("__atomic_store_16")
+TLI_DEFINE_SIG_INTERNAL(Void, Ptr, Int128, Int)
+
+/// bool __atomic_compare_exchange(size_t size, void *ptr, void *expected, void *desired, int success, int failure);
+TLI_DEFINE_ENUM_INTERNAL(atomic_compare_exchange)
+TLI_DEFINE_STRING_INTERNAL("__atomic_compare_exchange")
+TLI_DEFINE_SIG_INTERNAL(Bool, SizeT, Ptr, Ptr, Ptr, Int, Int)
+
+/// bool __atomic_compare_exchange_1(void *ptr, void *expected, uint8_t desired, int success, int failure);
+TLI_DEFINE_ENUM_INTERNAL(atomic_compare_exchange_1)
+TLI_DEFINE_STRING_INTERNAL("__atomic_compare_exchange_1")
+TLI_DEFINE_SIG_INTERNAL(Bool, Ptr, Ptr, Int8, Int, Int)
+
+/// bool __atomic_compare_exchange_2(void *ptr, void *expected, uint16_t desired, int success, int failure);
+TLI_DEFINE_ENUM_INTERNAL(atomic_compare_exchange_2)
+TLI_DEFINE_STRING_INTERNAL("__atomic_compare_exchange_2")
+TLI_DEFINE_SIG_INTERNAL(Bool, Ptr, Ptr, Int16, Int, Int)
+
+/// bool __atomic_compare_exchange_4(void *ptr, void *expected, uint32_t desired, int success, int failure);
+TLI_DEFINE_ENUM_INTERNAL(atomic_compare_exchange_4)
+TLI_DEFINE_STRING_INTERNAL("__atomic_compare_exchange_4")
+TLI_DEFINE_SIG_INTERNAL(Bool, Ptr, Ptr, Int32, Int, Int)
+
+/// bool __atomic_compare_exchange_8(void *ptr, void *expected, uint64_t desired, int success, int failure);
+TLI_DEFINE_ENUM_INTERNAL(atomic_compare_exchange_8)
+TLI_DEFINE_STRING_INTERNAL("__atomic_compare_exchange_8")
+TLI_DEFINE_SIG_INTERNAL(Bool, Ptr, Ptr, Int64, Int, Int)
+
+/// bool __atomic_compare_exchange_16(void *ptr, void *expected, uint128_t desired, int success, int failure);
+TLI_DEFINE_ENUM_INTERNAL(atomic_compare_exchange_16)
+TLI_DEFINE_STRING_INTERNAL("__atomic_compare_exchange_16")
+TLI_DEFINE_SIG_INTERNAL(Bool, Ptr, Ptr, Int128, Int, Int)
+
/// double __cosh_finite(double x);
TLI_DEFINE_ENUM_INTERNAL(cosh_finite)
TLI_DEFINE_STRING_INTERNAL("__cosh_finite")
diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h b/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
index 80b4aa2bd2855..eaaac4489cd4a 100644
--- a/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
+++ b/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
@@ -3215,7 +3215,6 @@ class OpenMPIRBuilder {
/// Emit atomic update for constructs: X = X BinOp Expr ,or X = Expr BinOp X
/// For complex Operations: X = UpdateOp(X) => CmpExch X, old_X, UpdateOp(X)
- /// Only Scalar data types.
///
/// \param AllocaIP The insertion point to be used for alloca
/// instructions.
@@ -3236,7 +3235,7 @@ class OpenMPIRBuilder {
/// (e.g. true for X = X BinOp Expr)
///
/// \returns A pair of the old value of X before the update, and the value
- /// used for the update.
+ /// after the update.
Expected<std::pair<Value *, Value *>>
emitAtomicUpdate(InsertPointTy AllocaIP, Value *X, Type *XElemTy, Value *Expr,
AtomicOrdering AO, AtomicRMWInst::BinOp RMWOp,
@@ -3258,7 +3257,7 @@ class OpenMPIRBuilder {
bool IsVolatile = false;
};
- /// Emit atomic Read for : V = X --- Only Scalar data types.
+ /// Emit atomic Read for : V = X.
///
/// \param Loc The insert and source location description.
/// \param X The target pointer to be atomically read
@@ -3268,9 +3267,9 @@ class OpenMPIRBuilder {
/// instructions.
///
/// \return Insertion point after generated atomic read IR.
- InsertPointTy createAtomicRead(const LocationDescription &Loc,
- AtomicOpValue &X, AtomicOpValue &V,
- AtomicOrdering AO);
+ InsertPointOrErrorTy createAtomicRead(const LocationDescription &Loc,
+ AtomicOpValue &X, AtomicOpValue &V,
+ AtomicOrdering AO);
/// Emit atomic write for : X = Expr --- Only Scalar data types.
///
@@ -3281,9 +3280,10 @@ class OpenMPIRBuilder {
/// instructions.
///
/// \return Insertion point after generated atomic Write IR.
- InsertPointTy createAtomicWrite(const LocationDescription &Loc,
- AtomicOpValue &X, Value *Expr,
- AtomicOrdering AO);
+ InsertPointOrErrorTy createAtomicWrite(const LocationDescription &Loc,
+ InsertPointTy AllocaIP,
+ AtomicOpValue &X, Value *Expr,
+ AtomicOrdering AO);
/// Emit atomic update for constructs: X = X BinOp Expr ,or X = Expr BinOp X
/// For complex Operations: X = UpdateOp(X) => CmpExch X, old_X, UpdateOp(X)
@@ -3392,18 +3392,17 @@ class OpenMPIRBuilder {
/// the case the comparison is '=='.
///
/// \return Insertion point after generated atomic capture IR.
- InsertPointTy
- createAtomicCompare(const LocationDescription &Loc, AtomicOpValue &X,
- AtomicOpValue &V, AtomicOpValue &R, Value *E, Value *D,
- AtomicOrdering AO, omp::OMPAtomicCompareOp Op,
- bool IsXBinopExpr, bool IsPostfixUpdate, bool IsFailOnly);
- InsertPointTy createAtomicCompare(const LocationDescription &Loc,
- AtomicOpValue &X, AtomicOpValue &V,
- AtomicOpValue &R, Value *E, Value *D,
- AtomicOrdering AO,
- omp::OMPAtomicCompareOp Op,
- bool IsXBinopExpr, bool IsPostfixUpdate,
- bool IsFailOnly, AtomicOrdering Failure);
+ InsertPointOrErrorTy
+ createAtomicCompare(const LocationDescription &Loc, InsertPointTy AllocaIP,
+ AtomicOpValue &X, AtomicOpValue &V, AtomicOpValue &R,
+ Value *E, Value *D, AtomicOrdering AO,
+ omp::OMPAtomicCompareOp Op, bool IsXBinopExpr,
+ bool IsPostfixUpdate, bool IsFailOnly);
+ InsertPointOrErrorTy createAtomicCompare(
+ const LocationDescription &Loc, InsertPointTy AllocaIP, AtomicOpValue &X,
+ AtomicOpValue &V, AtomicOpValue &R, Value *E, Value *D, AtomicOrdering AO,
+ omp::OMPAtomicCompareOp Op, bool IsXBinopExpr, bool IsPostfixUpdate,
+ bool IsFailOnly, AtomicOrdering Failure);
/// Create the control flow structure of a canonical OpenMP loop.
///
diff --git a/llvm/include/llvm/Support/AtomicOrdering.h b/llvm/include/llvm/Support/AtomicOrdering.h
index e08c1b262a92b..010bc06bb8570 100644
--- a/llvm/include/llvm/Support/AtomicOrdering.h
+++ b/llvm/include/llvm/Support/AtomicOrdering.h
@@ -158,6 +158,28 @@ inline AtomicOrderingCABI toCABI(AtomicOrdering AO) {
return lookup[static_cast<size_t>(AO)];
}
+inline AtomicOrdering fromCABI(AtomicOrderingCABI AO) {
+ // Acquire is the the closest but still stronger ordering of consume.
+ static const AtomicOrdering lookup[8] = {
+ /* relaxed */ AtomicOrdering::Monotonic,
+ /* consume */ AtomicOrdering::Acquire,
+ /* acquire */ AtomicOrdering::Acquire,
+ /* release */ AtomicOrdering::Release,
+ /* acq_rel */ AtomicOrdering::AcquireRelease,
+ /* acq_seq */ AtomicOrdering::SequentiallyConsistent,
+ };
+ return lookup[static_cast<size_t>(AO)];
+}
+
+inline AtomicOrdering fromCABI(int64_t AO) {
+ if (!isValidAtomicOrderingCABI(AO)) {
+ // This fallback is what CGAtomic does
+ return AtomicOrdering::Monotonic;
+ }
+ assert(isValidAtomicOrderingCABI(AO));
+ return fromCABI(static_cast<AtomicOrderingCABI>(AO));
+}
+
} // end namespace llvm
#endif // LLVM_SUPPORT_ATOMICORDERING_H
diff --git a/llvm/include/llvm/Transforms/Utils/BuildBuiltins.h b/llvm/include/llvm/Transforms/Utils/BuildBuiltins.h
new file mode 100644
index 0000000000000..feeb9f12b41c5
--- /dev/null
+++ b/llvm/include/llvm/Transforms/Utils/BuildBuiltins.h
@@ -0,0 +1,283 @@
+//===- BuildBuiltins.h - Utility builder for builtins ---------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements some functions for lowering compiler builtins,
+// specifically for atomics. Currently, LLVM-IR has no representation of atomics
+// that can be used independent of its arguments:
+//
+// * The instructions load atomic, store atomic, atomicrmw, and cmpxchg can only
+// be used with constant memory model, sync scope, data sizes (that must be
+// power-of-2), volatile and weak property, and should not be used with data
+// types that are untypically large which may slow down the compiler.
+//
+// * libcall (in GCC's case: libatomic; LLVM: Compiler-RT) functions work with
+// any data size, but are slower. Specialized functions for a selected number
+// of data sizes exist as well. They do not support sync scopes, the volatile
+// or weakness property. These functions may be implemented using a lock and
+// availability depends on the target triple (e.g. GPU devices cannot
+// implement a global lock by design).
+//
+// Whe want to mimic Clang's behaviour:
+//
+// * Prefer atomic instructions over libcall functions whenever possible. When a
+// target backend does not support atomic instructions natively,
+// AtomicExpandPass, LowerAtomicPass, or some backend-specific pass lower will
+// convert such instructions to a libcall function call. The reverse is not
+// the case, i.e. once a libcall function is emitted, there is no pass that
+// optimizes it into an instruction.
+//
+// * When passed a non-constant enum argument which the instruction requires to
+// be constant, then emit a switch case for each enum case.
+//
+// Clang currently doesn't actually check whether the target actually supports
+// atomic libcall functions so it will always fall back to a libcall function
+// even if the target does not support it. That is, emitting an atomic builtin
+// may fail and a frontend needs to handle this case.
+//
+// Clang also assumes that the maximum supported data size of atomic instruction
+// is 16, despite this is target-dependent and should be queried using
+// TargetLowing::getMaxAtomicSizeInBitsSupported(). However, TargetMachine
+// (which is a factory for TargetLowing) is not available during Clang's CodeGen
+// phase, it is only created for the LLVM pass pipeline.
+//
+// The functions in this file are intended to handle the complexity of builtins
+// so frontends do not need to care about the details. A major difference betwee
+// the cases is that the IR instructions take values directly as an llvm::Value
+// (except the atomic address of course), but the libcall functions almost
+// always take pointers to those values. Since we cannot assume that everything
+// can be passed an llvm::Value (LLVM does not handle large types such as i4096
+// well), our abstraction passes everything as pointer which is load'ed when
+// needed. The caller is responsible to emit a temporary AllocaInst and store if
+// it needs to pass an llvm::Value. Mem2Reg/SROA will easily remove any
+// unnecessary store/load pairs.
+//
+// In the future LLVM may introduce more generic atomic constructs that is
+// lowered by an LLVM pass, such as AtomicExpandPass. Once this exist, the
+// emitBuiltin functions in this file become trivial.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_TRANSFORMS_UTILS_BUILDBUILTINS_H
+#define LLVM_TRANSFORMS_UTILS_BUILDBUILTINS_H
+
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/Twine.h"
+#include "llvm/Support/Alignment.h"
+#include "llvm/Support/AtomicOrdering.h"
+#include "llvm/Support/Error.h"
+#include <cstdint>
+#include <variant>
+
+namespace llvm {
+class Value;
+class TargetLibraryInfo;
+class DataLayout;
+class IRBuilderBase;
+class Type;
+class TargetLowering;
+
+namespace SyncScope {
+typedef uint8_t ID;
+}
+
+/// Options for controlling atomic builtins.
+struct AtomicEmitOptions {
+ AtomicEmitOptions(const DataLayout &DL, const TargetLibraryInfo *TLI,
+ const TargetLowering *TL = nullptr)
+ : DL(DL), TLI(TLI), TL(TL) {}
+
+ /// The target's data layout.
+ const DataLayout &DL;
+
+ /// The target's libcall library availability.
+ const TargetLibraryInfo *TLI;
+
+ /// Used to determine which instructions thetarget support. If omitted,
+ /// assumes all accesses up to a size of 16 bytes are supported.
+ const TargetLowering *TL = nullptr;
+
+ /// Whether an LLVM instruction can be emitted. LLVM instructions include:
+ /// * load atomic
+ /// * store atomic
+ /// * cmpxchg
+ /// * atomicrmw
+ ///
+ /// Atomic LLVM intructions have several restructions on when they can be
+ /// used, including:
+ /// * Properties such as IsWeak,Memorder,Scope must be constant.
+ /// * Must be an integer or pointer type. Some cases also allow float types.
+ /// * Size must be a power-of-two number of bytes.
+ /// * Size must be at most the size of atomics supported by the target.
+ /// * Size should not be too large (e.g. i4096) since LLVM does not scale
+ /// will with huge types.
+ ///
+ /// Even with all these limitations adhered to, AtomicExpandPass may still
+ /// lower the instruction to a libcall function if the target does not support
+ /// it.
+ ///
+ /// See also:
+ /// * https://llvm.org/docs/Atomics.html
+ /// * https://llvm.org/docs/LangRef.html#i-load
+ /// * https://llvm.org/docs/LangRef.html#i-store
+ /// * https://llvm.org/docs/LangRef.html#cmpxchg-instruction
+ /// * https://llvm.org/docs/LangRef.html#i-atomicrmw
+ bool AllowInstruction = true;
+
+ /// Whether a switch can be emitted to work around the requirement of
+ /// properties of an instruction must be constant. That is, for each possible
+ /// value of the property, jump to a version of that instruction encoding that
+ /// property.
+ bool AllowSwitch = true;
+
+ /// Allow emitting calls to constant-sized libcall functions, such as
+ /// * __atomic_load_n
+ /// * __atomic_store_n
+ /// * __atomic_compare_exchange_n
+ /// where n is as size supported by the target, typically 1,2,4,8,16
+ ///
+ /// See also:
+ /// * https://llvm.org/docs/Atomics.html
+ /// * https://gcc.gnu.org/wiki/Atomic/GCCMM/LIbrary#GCC_intrinsics
+ bool AllowSizedLibcall = true;
+
+ /// Allow emitting call to variable-sized libcall functions, such as
+ // / * __atomic_load
+ /// * __atomic_store
+ /// * __atomic_compare_exchange
+ ///
+ /// Note that the signatures of these libcall functions are different from the
+ /// compiler builtins of the same name.
+ ///
+ /// See also:
+ /// * https://llvm.org/docs/Atomics.html
+ /// * https://gcc.gnu.org/wiki/Atomic/GCCMM/LIbrary#GCC_intrinsics
+ bool AllowLibcall = true;
+
+ // TODO: Add additional lowerings:
+ // * __sync_* libcalls
+ // * Using a lock on systems that do not support libcall functions
+ // (e.g. Windows)
+ // * Differently named atomic primitives
+ // (e.g. InterlockedCompareExchange on Windows)
+};
+
+/// Emit the __atomic_load builtin. This may either be lowered to the load LLVM
+/// instruction, or to one of the following libcall functions: __atomic_load_1,
+/// __atomic_load_2, __atomic_load_4, __atomic_load_8, __atomic_load_16,
+/// __atomic_load.
+///
+/// Also see:
+/// * https://llvm.org/docs/Atomics.html
+/// * https://llvm.org/docs/LangRef.html#load-instruction
+/// * https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html
+/// * https://gcc.gnu.org/wiki/Atomic/GCCMM/LIbrary#GCC_intrinsics
+Error emitAtomicLoadBuiltin(
+ Value *AtomicPtr, Value *RetPtr, bool IsVolatile,
+ std::variant<Value *, AtomicOrdering, AtomicOrderingCABI> Memorder,
+ SyncScope::ID Scope, Type *DataTy, std::optional<uint64_t> DataSize,
+ std::optional<uint64_t> AvailableSize, MaybeAlign Align,
+ IRBuilderBase &Builder, AtomicEmitOptions EmitOptions,
+ llvm::Twine Name = Twine());
+
+/// Emit the __atomic_store builtin. It may either be lowered to the store LLVM
+/// instruction, or to one of the following libcall functions: __atomic_store_1,
+/// __atomic_store_2, __atomic_store_4, __atomic_store_8, __atomic_store_16,
+/// __atomic_static.
+///
+/// Also see:
+/// * https://llvm.org/docs/Atomics.html
+/// * https://llvm.org/docs/LangRef.html#store-instruction
+/// * https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html
+/// * https://gcc.gnu.org/wiki/Atomic/GCCMM/LIbrary#GCC_intrinsics
+Error emitAtomicStoreBuiltin(
+ Value *AtomicPtr, Value *ValPtr, bool IsVolatile,
+ std::variant<Value *, AtomicOrdering, AtomicOrderingCABI> Memorder,
+ SyncScope::ID Scope, Type *DataTy, std::optional<uint64_t> DataSize,
+ std::optional<uint64_t> AvailableSize, MaybeAlign Align,
+ IRBuilderBase &Builder, AtomicEmitOptions EmitOptions,
+ llvm::Twine Name = Twine());
+
+/// Emit the __atomic_compare_exchange builtin. This may either be
+/// lowered to the cmpxchg LLVM instruction, or to one of the following libcall
+/// functions: __atomic_compare_exchange_1, __atomic_compare_exchange_2,
+/// __atomic_compare_exchange_4, __atomic_compare_exchange_8,
+/// __atomic_compare_exchange_16, __atomic_compare_exchange.
+///
+/// Also see:
+/// * https://llvm.org/docs/Atomics.html
+/// * https://llvm.org/docs/LangRef.html#cmpxchg-instruction
+/// * https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html
+/// * https://gcc.gnu.org/wiki/Atomic/GCCMM/LIbrary#GCC_intrinsics
+///
+/// @param AtomicPtr The memory location accessed atomically.
+/// @Param ExpectedPtr Pointer to the data expected at \p Ptr. The exchange will
+/// only happen if the value at \p Ptr is equal to this
+/// (unless IsWeak is set). Data at \p ExpectedPtr may or may
+/// not be be overwritten, so do not use after this call.
+/// @Param DesiredPtr Pointer to the data that the data at \p Ptr is replaced
+/// with.
+/// @param IsWeak If true, the exchange may not happen even if the data at
+/// \p Ptr equals to \p ExpectedPtr.
+/// @param IsVolatile Whether to mark the access as volatile.
+/// @param SuccessMemorder If the exchange succeeds, memory is affected
+/// according to the memory model.
+/// @param FailureMemorder If the exchange fails, memory is affected according
+/// to the memory model. It is considered an atomic "read"
+/// for the purpose of identifying release sequences. Must
+/// not be release, acquire-release, and at most as strong as
+/// \p SuccessMemorder.
+/// @param Scope (optional) The synchronization scope (domain of threads
+/// where this access has to be atomic, e.g. CUDA
+/// warp/block/grid-level atomics) of this access. Defaults
+/// to system scope.
+/// @param DataTy (optional) Type of the value to be accessed. cmpxchg
+/// supports integer and pointers only. If any other type or
+/// omitted, type-prunes to an integer the holds at least \p
+/// DataSize bytes.
+/// @param ActualPtr (optional) Receives the value at \p Ptr before the atomic
+/// exchange is attempted. This means:
+/// In case of success:
+/// The value at \p Ptr before the update. That is, the
+/// value passed behind \p ExpectedPtr.
+/// In case of failure
+/// (including spurious failures if IsWeak):
+/// The current value at \p Ptr, i.e. the operation
+/// effectively was an atomic load of that value using
+/// FailureMemorder semantics.
+/// Can be the same as ExpectedPtr in which case after the
+/// call returns \p ExpectedPtr/\p ActualPtr will be the
+/// value as defined above (in contrast to being undefined).
+/// @param DataSize Number of bytes to be exchanged.
+/// @param AvailableSize The total size that can be used for the atomic
+/// operation. It may include trailing padding in addition to
+/// the data type's size to allow the use power-of-two
+/// instructions/calls.
+/// @param Align (optional) Known alignment of /p Ptr. If omitted,
+/// alignment is inferred from /p Ptr itself and falls back
+/// to no alignment.
+/// @param Builder User to emit instructions.
+/// @param EmitOptions For controlling what IR is emitted.
+/// @param Name (optional) Stem for generated instruction names.
+///
+/// @return A boolean value that indicates whether the exchange has happened
+/// (true) or not (false), or an error if the atomic operation could not
+/// be emitted.
+Expected<Value *> emitAtomicCompareExchangeBuiltin(
+ Value *AtomicPtr, Value *ExpectedPtr, Value *DesiredPtr,
+ std::variant<Value *, bool> IsWeak, bool IsVolatile,
+ std::variant<Value *, AtomicOrdering, AtomicOrderingCABI> SuccessMemorder,
+ std::variant<std::monostate, Value *, AtomicOrdering, AtomicOrderingCABI>
+ FailureMemorder,
+ SyncScope::ID Scope, Value *PrevPtr, Type *DataTy,
+ std::optional<uint64_t> DataSize, std::optional<uint64_t> AvailableSize,
+ MaybeAlign Align, IRBuilderBase &Builder, AtomicEmitOptions EmitOptions,
+ llvm::Twine Name = Twine());
+
+} // namespace llvm
+
+#endif /* LLVM_TRANSFORMS_UTILS_BUILDBUILTINS_H */
diff --git a/llvm/include/llvm/Transforms/Utils/BuildLibCalls.h b/llvm/include/llvm/Transforms/Utils/BuildLibCalls.h
index a8fb38e726004..d419e6c775d9f 100644
--- a/llvm/include/llvm/Transforms/Utils/BuildLibCalls.h
+++ b/llvm/include/llvm/Transforms/Utils/BuildLibCalls.h
@@ -192,6 +192,53 @@ namespace llvm {
Value *emitVSPrintf(Value *Dest, Value *Fmt, Value *VAList, IRBuilderBase &B,
const TargetLibraryInfo *TLI);
+ /// Emit a call to the __atomic_load function.
+ /// Defined here:
+ /// https://llvm.org/docs/Atomics.html#libcalls-atomic
+ /// https://gcc.gnu.org/wiki/Atomic/GCCMM/LIbrary#list_of_library_routines
+ Value *emitAtomicLoad(Value *Size, Value *Ptr, Value *Ret, Value *Memorder,
+ IRBuilderBase &B, const DataLayout &DL,
+ const TargetLibraryInfo *TLI);
+
+ /// Variant of __atomic_load where \p Size is either 1, 2, 4, 8, or 16.
+ Value *emitAtomicLoadN(size_t Size, Value *Ptr, Value *Memorder,
+ IRBuilderBase &B, const DataLayout &DL,
+ const TargetLibraryInfo *TLI);
+
+ /// Emit a call to the __atomic_store function.
+ /// Defined here:
+ /// https://llvm.org/docs/Atomics.html#libcalls-atomic
+ /// https://gcc.gnu.org/wiki/Atomic/GCCMM/LIbrary#list_of_library_routines
+ Value *emitAtomicStore(Value *Size, Value *Ptr, Value *ValPtr,
+ Value *Memorder, IRBuilderBase &B,
+ const DataLayout &DL, const TargetLibraryInfo *TLI);
+
+ /// Variant of __atomic_store where \p Size is either 1, 2, 4, 8, or 16.
+ Value *emitAtomicStoreN(size_t Size, Value *Ptr, Value *Val, Value *Memorder,
+ IRBuilderBase &B, const DataLayout &DL,
+ const TargetLibraryInfo *TLI);
+
+ /// Emit a call to the __atomic_compare_exchange function.
+ /// Defined here:
+ /// https://llvm.org/docs/Atomics.html#libcalls-atomic
+ /// https://gcc.gnu.org/wiki/Atomic/GCCMM/LIbrary#list_of_library_routines
+ ///
+ /// NOTE: Signature is different to the builtins defined here:
+ /// https://gcc.gnu.org/wiki/Atomic/GCCMM/LIbrary#GCC_intrinsics
+ Value *emitAtomicCompareExchange(Value *Size, Value *Ptr, Value *Expected,
+ Value *Desired, Value *SuccessMemorder,
+ Value *FailureMemorder, IRBuilderBase &B,
+ const DataLayout &DL,
+ const TargetLibraryInfo *TLI);
+
+ /// Variant of __atomic_compare_exchange where \p Size is either 1, 2, 4, 8,
+ /// or 16.
+ Value *emitAtomicCompareExchangeN(size_t Size, Value *Ptr, Value *Expected,
+ Value *Desired, Value *SuccessMemorder,
+ Value *FailureMemorder, IRBuilderBase &B,
+ const DataLayout &DL,
+ const TargetLibraryInfo *TLI);
+
/// Emit a call to the unary function named 'Name' (e.g. 'floor'). This
/// function is known to take a single of type matching 'Op' and returns one
/// value with the same type. If 'Op' is a long double, 'l' is added as the
diff --git a/llvm/lib/Analysis/TargetLibraryInfo.cpp b/llvm/lib/Analysis/TargetLibraryInfo.cpp
index 8557901192e40..6ec2c4909c316 100644
--- a/llvm/lib/Analysis/TargetLibraryInfo.cpp
+++ b/llvm/lib/Analysis/TargetLibraryInfo.cpp
@@ -60,6 +60,7 @@ std::string VecDesc::getVectorFunctionABIVariantString() const {
enum FuncArgTypeID : char {
Void = 0, // Must be zero.
Bool, // 8 bits on all targets
+ Int8,
Int16,
Int32,
Int,
@@ -67,6 +68,7 @@ enum FuncArgTypeID : char {
Long, // Either 32 or 64 bits.
IntX, // Any integer type.
Int64,
+ Int128,
LLong, // 64 bits on all targets.
SizeT, // size_t.
SSizeT, // POSIX ssize_t.
@@ -828,7 +830,23 @@ static void initializeLibCalls(TargetLibraryInfoImpl &TLI, const Triple &T,
// Miscellaneous other functions not provided.
TLI.setUnavailable(LibFunc_atomic_load);
+ TLI.setUnavailable(LibFunc_atomic_load_1);
+ TLI.setUnavailable(LibFunc_atomic_load_2);
+ TLI.setUnavailable(LibFunc_atomic_load_4);
+ TLI.setUnavailable(LibFunc_atomic_load_8);
+ TLI.setUnavailable(LibFunc_atomic_load_16);
TLI.setUnavailable(LibFunc_atomic_store);
+ TLI.setUnavailable(LibFunc_atomic_store_1);
+ TLI.setUnavailable(LibFunc_atomic_store_2);
+ TLI.setUnavailable(LibFunc_atomic_store_4);
+ TLI.setUnavailable(LibFunc_atomic_store_8);
+ TLI.setUnavailable(LibFunc_atomic_store_16);
+ TLI.setUnavailable(LibFunc_atomic_compare_exchange);
+ TLI.setUnavailable(LibFunc_atomic_compare_exchange_1);
+ TLI.setUnavailable(LibFunc_atomic_compare_exchange_2);
+ TLI.setUnavailable(LibFunc_atomic_compare_exchange_4);
+ TLI.setUnavailable(LibFunc_atomic_compare_exchange_8);
+ TLI.setUnavailable(LibFunc_atomic_compare_exchange_16);
TLI.setUnavailable(LibFunc___kmpc_alloc_shared);
TLI.setUnavailable(LibFunc___kmpc_free_shared);
TLI.setUnavailable(LibFunc_dunder_strndup);
@@ -1024,6 +1042,7 @@ static bool matchType(FuncArgTypeID ArgTy, const Type *Ty, unsigned IntBits,
case Void:
return Ty->isVoidTy();
case Bool:
+ case Int8:
return Ty->isIntegerTy(8);
case Int16:
return Ty->isIntegerTy(16);
@@ -1040,6 +1059,8 @@ static bool matchType(FuncArgTypeID ArgTy, const Type *Ty, unsigned IntBits,
return Ty->isIntegerTy() && Ty->getPrimitiveSizeInBits() >= IntBits;
case Int64:
return Ty->isIntegerTy(64);
+ case Int128:
+ return Ty->isIntegerTy(128);
case LLong:
return Ty->isIntegerTy(64);
case SizeT:
diff --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
index e34e93442ff85..5851222922285 100644
--- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
@@ -54,6 +54,7 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
+#include "llvm/Transforms/Utils/BuildBuiltins.h"
#include "llvm/Transforms/Utils/Cloning.h"
#include "llvm/Transforms/Utils/CodeExtractor.h"
#include "llvm/Transforms/Utils/LoopPeel.h"
@@ -8606,7 +8607,7 @@ bool OpenMPIRBuilder::checkAndEmitFlushAfterAtomic(
return Flush;
}
-OpenMPIRBuilder::InsertPointTy
+OpenMPIRBuilder::InsertPointOrErrorTy
OpenMPIRBuilder::createAtomicRead(const LocationDescription &Loc,
AtomicOpValue &X, AtomicOpValue &V,
AtomicOrdering AO) {
@@ -8615,78 +8616,79 @@ OpenMPIRBuilder::createAtomicRead(const LocationDescription &Loc,
assert(X.Var->getType()->isPointerTy() &&
"OMP Atomic expects a pointer to target memory");
+ assert(V.Var->getType()->isPointerTy() &&
+ "Expecting a pointer for atomic load result");
Type *XElemTy = X.ElemTy;
- assert((XElemTy->isFloatingPointTy() || XElemTy->isIntegerTy() ||
- XElemTy->isPointerTy() || XElemTy->isStructTy()) &&
- "OMP atomic read expected a scalar type");
-
- Value *XRead = nullptr;
-
- if (XElemTy->isIntegerTy()) {
- LoadInst *XLD =
- Builder.CreateLoad(XElemTy, X.Var, X.IsVolatile, "omp.atomic.read");
- XLD->setAtomic(AO);
- XRead = cast<Value>(XLD);
- } else if (XElemTy->isStructTy()) {
- // FIXME: Add checks to ensure __atomic_load is emitted iff the
- // target does not support `atomicrmw` of the size of the struct
- LoadInst *OldVal = Builder.CreateLoad(XElemTy, X.Var, "omp.atomic.read");
- OldVal->setAtomic(AO);
- const DataLayout &LoadDL = OldVal->getModule()->getDataLayout();
- unsigned LoadSize =
- LoadDL.getTypeStoreSize(OldVal->getPointerOperand()->getType());
- OpenMPIRBuilder::AtomicInfo atomicInfo(
- &Builder, XElemTy, LoadSize * 8, LoadSize * 8, OldVal->getAlign(),
- OldVal->getAlign(), true /* UseLibcall */, X.Var);
- auto AtomicLoadRes = atomicInfo.EmitAtomicLoadLibcall(AO);
- XRead = AtomicLoadRes.first;
- OldVal->eraseFromParent();
- } else {
- // We need to perform atomic op as integer
- IntegerType *IntCastTy =
- IntegerType::get(M.getContext(), XElemTy->getScalarSizeInBits());
- LoadInst *XLoad =
- Builder.CreateLoad(IntCastTy, X.Var, X.IsVolatile, "omp.atomic.load");
- XLoad->setAtomic(AO);
- if (XElemTy->isFloatingPointTy()) {
- XRead = Builder.CreateBitCast(XLoad, XElemTy, "atomic.flt.cast");
- } else {
- XRead = Builder.CreateIntToPtr(XLoad, XElemTy, "atomic.ptr.cast");
- }
- }
+
+ // TODO: Get TLI and TL from frontend
+ Triple T(Builder.GetInsertBlock()->getModule()->getTargetTriple());
+ TargetLibraryInfoImpl TLII(T);
+ TargetLibraryInfo TLI(TLII);
+ const DataLayout &DL = Builder.GetInsertBlock()->getDataLayout();
+ Twine Name = X.Var->getName();
+
+ Error ALResult = emitAtomicLoadBuiltin(
+ X.Var,
+ /*RetPtr=*/V.Var,
+ /*IsVolatile=*/X.IsVolatile || V.IsVolatile,
+ /*Memorder=*/AO,
+ /*SyncScope=*/static_cast<SyncScope::ID>(SyncScope::System),
+ /*DataTy=*/XElemTy,
+ /*DataSize=*/{},
+ /*AvailableSize=*/{},
+ /*Align=*/{},
+ /*Builder=*/Builder,
+ /*EmitOptions=*/AtomicEmitOptions(DL, &TLI),
+ /*Name=*/Name + ".atomic.read");
+ if (ALResult)
+ return std::move(ALResult);
+
checkAndEmitFlushAfterAtomic(Loc, AO, AtomicKind::Read);
- if (XRead->getType() != V.Var->getType())
- XRead = emitImplicitCast(Builder, XRead, V.Var);
- Builder.CreateStore(XRead, V.Var, V.IsVolatile);
+
return Builder.saveIP();
}
-OpenMPIRBuilder::InsertPointTy
+OpenMPIRBuilder::InsertPointOrErrorTy
OpenMPIRBuilder::createAtomicWrite(const LocationDescription &Loc,
- AtomicOpValue &X, Value *Expr,
- AtomicOrdering AO) {
+ InsertPointTy AllocaIP, AtomicOpValue &X,
+ Value *Expr, AtomicOrdering AO) {
if (!updateToLocation(Loc))
return Loc.IP;
+ assert(!isConflictIP(Loc.IP, AllocaIP) && "IPs must not be ambiguous");
assert(X.Var->getType()->isPointerTy() &&
"OMP Atomic expects a pointer to target memory");
Type *XElemTy = X.ElemTy;
- assert((XElemTy->isFloatingPointTy() || XElemTy->isIntegerTy() ||
- XElemTy->isPointerTy()) &&
- "OMP atomic write expected a scalar type");
- if (XElemTy->isIntegerTy()) {
- StoreInst *XSt = Builder.CreateStore(Expr, X.Var, X.IsVolatile);
- XSt->setAtomic(AO);
- } else {
- // We need to bitcast and perform atomic op as integers
- IntegerType *IntCastTy =
- IntegerType::get(M.getContext(), XElemTy->getScalarSizeInBits());
- Value *ExprCast =
- Builder.CreateBitCast(Expr, IntCastTy, "atomic.src.int.cast");
- StoreInst *XSt = Builder.CreateStore(ExprCast, X.Var, X.IsVolatile);
- XSt->setAtomic(AO);
- }
+ // TODO: Get TLI and TL from frontend
+ Triple T(Builder.GetInsertBlock()->getModule()->getTargetTriple());
+ TargetLibraryInfoImpl TLII(T);
+ TargetLibraryInfo TLI(TLII);
+ const DataLayout &DL = Builder.GetInsertBlock()->getDataLayout();
+ Twine Name = X.Var->getName();
+
+ // Reserve some stack space.
+ InsertPointTy ContIP = Builder.saveIP();
+ Builder.restoreIP(AllocaIP);
+ Value *ValPtr = Builder.CreateAlloca(XElemTy, nullptr, Name + ".atomic.val");
+ Builder.restoreIP(ContIP);
+
+ Builder.CreateStore(Expr, ValPtr);
+ Error ASResult = emitAtomicStoreBuiltin(
+ X.Var,
+ /*ValPtr=*/ValPtr,
+ /*IsVolatile=*/X.IsVolatile,
+ /*Memorder=*/AO,
+ /*SyncScope=*/static_cast<SyncScope::ID>(SyncScope::System),
+ /*DataTy=*/XElemTy,
+ /*DataSize=*/{},
+ /*AvailableSize=*/{},
+ /*Align=*/{},
+ /*Builder=*/Builder,
+ /*EmitOptions=*/AtomicEmitOptions(DL, &TLI),
+ /*Name=*/Name + ".atomic.write");
+ if (ASResult)
+ return ASResult;
checkAndEmitFlushAfterAtomic(Loc, AO, AtomicKind::Write);
return Builder.saveIP();
@@ -8704,10 +8706,6 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createAtomicUpdate(
Type *XTy = X.Var->getType();
assert(XTy->isPointerTy() &&
"OMP Atomic expects a pointer to target memory");
- Type *XElemTy = X.ElemTy;
- assert((XElemTy->isFloatingPointTy() || XElemTy->isIntegerTy() ||
- XElemTy->isPointerTy()) &&
- "OMP atomic update expected a scalar type");
assert((RMWOp != AtomicRMWInst::Max) && (RMWOp != AtomicRMWInst::Min) &&
(RMWOp != AtomicRMWInst::UMax) && (RMWOp != AtomicRMWInst::UMin) &&
"OpenMP atomic does not support LT or GT operations");
@@ -8761,8 +8759,8 @@ Expected<std::pair<Value *, Value *>> OpenMPIRBuilder::emitAtomicUpdate(
InsertPointTy AllocaIP, Value *X, Type *XElemTy, Value *Expr,
AtomicOrdering AO, AtomicRMWInst::BinOp RMWOp,
AtomicUpdateCallbackTy &UpdateOp, bool VolatileX, bool IsXBinopExpr) {
- // TODO: handle the case where XElemTy is not byte-sized or not a power of 2
- // or a complex datatype.
+ assert(XElemTy && "Argument must not be NULL");
+
bool emitRMWOp = false;
switch (RMWOp) {
case AtomicRMWInst::Add:
@@ -8774,7 +8772,7 @@ Expected<std::pair<Value *, Value *>> OpenMPIRBuilder::emitAtomicUpdate(
emitRMWOp = XElemTy;
break;
case AtomicRMWInst::Sub:
- emitRMWOp = (IsXBinopExpr && XElemTy);
+ emitRMWOp = IsXBinopExpr;
break;
default:
emitRMWOp = false;
@@ -8791,124 +8789,89 @@ Expected<std::pair<Value *, Value *>> OpenMPIRBuilder::emitAtomicUpdate(
Res.second = Res.first;
else
Res.second = emitRMWOpAsInstruction(Res.first, Expr, RMWOp);
- } else if (RMWOp == llvm::AtomicRMWInst::BinOp::BAD_BINOP &&
- XElemTy->isStructTy()) {
- LoadInst *OldVal =
- Builder.CreateLoad(XElemTy, X, X->getName() + ".atomic.load");
- OldVal->setAtomic(AO);
- const DataLayout &LoadDL = OldVal->getModule()->getDataLayout();
- unsigned LoadSize =
- LoadDL.getTypeStoreSize(OldVal->getPointerOperand()->getType());
-
- OpenMPIRBuilder::AtomicInfo atomicInfo(
- &Builder, XElemTy, LoadSize * 8, LoadSize * 8, OldVal->getAlign(),
- OldVal->getAlign(), true /* UseLibcall */, X);
- auto AtomicLoadRes = atomicInfo.EmitAtomicLoadLibcall(AO);
- BasicBlock *CurBB = Builder.GetInsertBlock();
- Instruction *CurBBTI = CurBB->getTerminator();
- CurBBTI = CurBBTI ? CurBBTI : Builder.CreateUnreachable();
- BasicBlock *ExitBB =
- CurBB->splitBasicBlock(CurBBTI, X->getName() + ".atomic.exit");
- BasicBlock *ContBB = CurBB->splitBasicBlock(CurBB->getTerminator(),
- X->getName() + ".atomic.cont");
- ContBB->getTerminator()->eraseFromParent();
- Builder.restoreIP(AllocaIP);
- AllocaInst *NewAtomicAddr = Builder.CreateAlloca(XElemTy);
- NewAtomicAddr->setName(X->getName() + "x.new.val");
- Builder.SetInsertPoint(ContBB);
- llvm::PHINode *PHI = Builder.CreatePHI(OldVal->getType(), 2);
- PHI->addIncoming(AtomicLoadRes.first, CurBB);
- Value *OldExprVal = PHI;
- Expected<Value *> CBResult = UpdateOp(OldExprVal, Builder);
- if (!CBResult)
- return CBResult.takeError();
- Value *Upd = *CBResult;
- Builder.CreateStore(Upd, NewAtomicAddr);
- AtomicOrdering Failure =
- llvm::AtomicCmpXchgInst::getStrongestFailureOrdering(AO);
- auto Result = atomicInfo.EmitAtomicCompareExchangeLibcall(
- AtomicLoadRes.second, NewAtomicAddr, AO, Failure);
- LoadInst *PHILoad = Builder.CreateLoad(XElemTy, Result.first);
- PHI->addIncoming(PHILoad, Builder.GetInsertBlock());
- Builder.CreateCondBr(Result.second, ExitBB, ContBB);
- OldVal->eraseFromParent();
- Res.first = OldExprVal;
- Res.second = Upd;
-
- if (UnreachableInst *ExitTI =
- dyn_cast<UnreachableInst>(ExitBB->getTerminator())) {
- CurBBTI->eraseFromParent();
- Builder.SetInsertPoint(ExitBB);
- } else {
- Builder.SetInsertPoint(ExitTI);
- }
- } else {
- IntegerType *IntCastTy =
- IntegerType::get(M.getContext(), XElemTy->getScalarSizeInBits());
- LoadInst *OldVal =
- Builder.CreateLoad(IntCastTy, X, X->getName() + ".atomic.load");
- OldVal->setAtomic(AO);
- // CurBB
- // | /---\
- // ContBB |
- // | \---/
- // ExitBB
- BasicBlock *CurBB = Builder.GetInsertBlock();
- Instruction *CurBBTI = CurBB->getTerminator();
- CurBBTI = CurBBTI ? CurBBTI : Builder.CreateUnreachable();
- BasicBlock *ExitBB =
- CurBB->splitBasicBlock(CurBBTI, X->getName() + ".atomic.exit");
- BasicBlock *ContBB = CurBB->splitBasicBlock(CurBB->getTerminator(),
- X->getName() + ".atomic.cont");
- ContBB->getTerminator()->eraseFromParent();
- Builder.restoreIP(AllocaIP);
- AllocaInst *NewAtomicAddr = Builder.CreateAlloca(XElemTy);
- NewAtomicAddr->setName(X->getName() + "x.new.val");
- Builder.SetInsertPoint(ContBB);
- llvm::PHINode *PHI = Builder.CreatePHI(OldVal->getType(), 2);
- PHI->addIncoming(OldVal, CurBB);
- bool IsIntTy = XElemTy->isIntegerTy();
- Value *OldExprVal = PHI;
- if (!IsIntTy) {
- if (XElemTy->isFloatingPointTy()) {
- OldExprVal = Builder.CreateBitCast(PHI, XElemTy,
- X->getName() + ".atomic.fltCast");
- } else {
- OldExprVal = Builder.CreateIntToPtr(PHI, XElemTy,
- X->getName() + ".atomic.ptrCast");
- }
- }
-
- Expected<Value *> CBResult = UpdateOp(OldExprVal, Builder);
- if (!CBResult)
- return CBResult.takeError();
- Value *Upd = *CBResult;
- Builder.CreateStore(Upd, NewAtomicAddr);
- LoadInst *DesiredVal = Builder.CreateLoad(IntCastTy, NewAtomicAddr);
- AtomicOrdering Failure =
- llvm::AtomicCmpXchgInst::getStrongestFailureOrdering(AO);
- AtomicCmpXchgInst *Result = Builder.CreateAtomicCmpXchg(
- X, PHI, DesiredVal, llvm::MaybeAlign(), AO, Failure);
- Result->setVolatile(VolatileX);
- Value *PreviousVal = Builder.CreateExtractValue(Result, /*Idxs=*/0);
- Value *SuccessFailureVal = Builder.CreateExtractValue(Result, /*Idxs=*/1);
- PHI->addIncoming(PreviousVal, Builder.GetInsertBlock());
- Builder.CreateCondBr(SuccessFailureVal, ExitBB, ContBB);
-
- Res.first = OldExprVal;
- Res.second = Upd;
-
- // set Insertion point in exit block
- if (UnreachableInst *ExitTI =
- dyn_cast<UnreachableInst>(ExitBB->getTerminator())) {
- CurBBTI->eraseFromParent();
- Builder.SetInsertPoint(ExitBB);
- } else {
- Builder.SetInsertPoint(ExitTI);
- }
+ return Res;
}
- return Res;
+ // TODO: Get TLI and TL from frontend
+ Triple T(Builder.GetInsertBlock()->getModule()->getTargetTriple());
+ TargetLibraryInfoImpl TLII(T);
+ TargetLibraryInfo TLI(TLII);
+ const DataLayout &DL = Builder.GetInsertBlock()->getDataLayout();
+ Twine Name(X->getName());
+
+ // Reserve some stack space.
+ InsertPointTy InitIP = Builder.saveIP();
+ Builder.restoreIP(AllocaIP);
+ AllocaInst *ExpectedOrActualPtr =
+ Builder.CreateAlloca(XElemTy, nullptr, Name + ".atomic.expected.ptr");
+ AllocaInst *DesiredPtr =
+ Builder.CreateAlloca(XElemTy, nullptr, Name + ".atomic.desired.ptr");
+ Builder.restoreIP(InitIP);
+
+ // Old value for first transaction. Every followup-transaction will use the
+ // actual value from cmpxchg.
+ Error ALResult = emitAtomicLoadBuiltin(
+ /*AtomicPtr*/ X,
+ /*RetPtr=*/ExpectedOrActualPtr,
+ /*IsVolatile=*/false,
+ /*Memorder=*/AO,
+ /*SyncScope=*/static_cast<SyncScope::ID>(SyncScope::System),
+ /*DataTy=*/XElemTy,
+ /*DataSize=*/{},
+ /*AvailableSize=*/{},
+ /*Align=*/{},
+ /*Builder=*/Builder,
+ /*EmitOptions=*/AtomicEmitOptions(DL, &TLI),
+ /*Name=*/Name);
+ if (ALResult)
+ return std::move(ALResult);
+
+ // Create new CFG.
+ BasicBlock *DoneBB = splitBBWithSuffix(Builder, false, ".atomic.done");
+ BasicBlock *RetryBB = splitBBWithSuffix(Builder, true, ".atomic.retry");
+
+ // Emit the update transaction...
+ Builder.SetInsertPoint(RetryBB);
+
+ // 1. Let the user code compute the new value.
+ Value *OrigVal =
+ Builder.CreateLoad(XElemTy, ExpectedOrActualPtr, Name + ".atomic.orig");
+ Expected<Value *> CBResult = UpdateOp(OrigVal, Builder);
+ if (!CBResult)
+ return CBResult.takeError();
+ Value *UpdVal = *CBResult;
+ Builder.CreateStore(UpdVal, DesiredPtr);
+
+ // 2. AtomicCompareExchange to replace OrigVal with UpdVal.
+ // IsWeak=true because even with a spurious failure, we will just try again.
+ Expected<Value *> ACEResult = emitAtomicCompareExchangeBuiltin(
+ /*Ptr=*/X,
+ /*ExpectedPtr=*/ExpectedOrActualPtr,
+ /*DesiredPtr=*/DesiredPtr,
+ /*IsWeak=*/true,
+ /*IsVolatile=*/false,
+ /*SuccessMemorder=*/AO,
+ /*FailureMemorder=*/{},
+ /*SyncScope=*/static_cast<SyncScope::ID>(SyncScope::System),
+ /*ActualPtr=*/ExpectedOrActualPtr,
+ /*DataTy=*/XElemTy,
+ /*DataSize=*/{},
+ /*AvailableSize=*/{},
+ /*Align=*/{},
+ /*Builder=*/Builder,
+ /*EmitOptions=*/AtomicEmitOptions(DL, &TLI),
+ /*Name=*/Name);
+ if (!ACEResult)
+ return ACEResult.takeError();
+ Value *Success = *ACEResult;
+
+ // 3. Repeat transaction until successful.
+ Builder.CreateCondBr(Success, DoneBB, RetryBB);
+
+ // Continue with user code when the update transaction was successful.
+ Builder.SetInsertPoint(DoneBB);
+
+ return std::make_pair(OrigVal, UpdVal);
}
OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createAtomicCapture(
@@ -8923,10 +8886,6 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createAtomicCapture(
Type *XTy = X.Var->getType();
assert(XTy->isPointerTy() &&
"OMP Atomic expects a pointer to target memory");
- Type *XElemTy = X.ElemTy;
- assert((XElemTy->isFloatingPointTy() || XElemTy->isIntegerTy() ||
- XElemTy->isPointerTy()) &&
- "OMP atomic capture expected a scalar type");
assert((RMWOp != AtomicRMWInst::Max) && (RMWOp != AtomicRMWInst::Min) &&
"OpenMP atomic does not support LT or GT operations");
});
@@ -8949,20 +8908,20 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createAtomicCapture(
return Builder.saveIP();
}
-OpenMPIRBuilder::InsertPointTy OpenMPIRBuilder::createAtomicCompare(
- const LocationDescription &Loc, AtomicOpValue &X, AtomicOpValue &V,
- AtomicOpValue &R, Value *E, Value *D, AtomicOrdering AO,
+OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createAtomicCompare(
+ const LocationDescription &Loc, InsertPointTy AllocaIP, AtomicOpValue &X,
+ AtomicOpValue &V, AtomicOpValue &R, Value *E, Value *D, AtomicOrdering AO,
omp::OMPAtomicCompareOp Op, bool IsXBinopExpr, bool IsPostfixUpdate,
bool IsFailOnly) {
AtomicOrdering Failure = AtomicCmpXchgInst::getStrongestFailureOrdering(AO);
- return createAtomicCompare(Loc, X, V, R, E, D, AO, Op, IsXBinopExpr,
+ return createAtomicCompare(Loc, AllocaIP, X, V, R, E, D, AO, Op, IsXBinopExpr,
IsPostfixUpdate, IsFailOnly, Failure);
}
-OpenMPIRBuilder::InsertPointTy OpenMPIRBuilder::createAtomicCompare(
- const LocationDescription &Loc, AtomicOpValue &X, AtomicOpValue &V,
- AtomicOpValue &R, Value *E, Value *D, AtomicOrdering AO,
+OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createAtomicCompare(
+ const LocationDescription &Loc, InsertPointTy AllocaIP, AtomicOpValue &X,
+ AtomicOpValue &V, AtomicOpValue &R, Value *E, Value *D, AtomicOrdering AO,
omp::OMPAtomicCompareOp Op, bool IsXBinopExpr, bool IsPostfixUpdate,
bool IsFailOnly, AtomicOrdering Failure) {
@@ -8980,6 +8939,88 @@ OpenMPIRBuilder::InsertPointTy OpenMPIRBuilder::createAtomicCompare(
bool IsInteger = E->getType()->isIntegerTy();
if (Op == OMPAtomicCompareOp::EQ) {
+#if 1
+ // TODO: Get TLI and TL from frontend
+ Triple T(Builder.GetInsertBlock()->getModule()->getTargetTriple());
+ TargetLibraryInfoImpl TLII(T);
+ TargetLibraryInfo TLI(TLII);
+ const DataLayout &DL = Builder.GetInsertBlock()->getDataLayout();
+ Twine Name(X.Var->getName());
+
+ Type *XElemTy = X.ElemTy;
+
+ // Reserve some stack space.
+ InsertPointTy InitIP = Builder.saveIP();
+ Builder.restoreIP(AllocaIP);
+ AllocaInst *ExpectedPtr =
+ Builder.CreateAlloca(XElemTy, nullptr, Name + ".atomic.expected.ptr");
+ AllocaInst *DesiredPtr =
+ Builder.CreateAlloca(XElemTy, nullptr, Name + ".atomic.desired.ptr");
+ AllocaInst *ActualPtr =
+ Builder.CreateAlloca(XElemTy, nullptr, Name + ".atomic.expected.ptr");
+ Builder.restoreIP(InitIP);
+
+ Builder.CreateStore(E, ExpectedPtr);
+ Builder.CreateStore(D, DesiredPtr);
+
+ Expected<Value *> ACEResult = emitAtomicCompareExchangeBuiltin(
+ /*Ptr=*/X.Var,
+ /*ExpectedPtr=*/ExpectedPtr,
+ /*DesiredPtr=*/DesiredPtr,
+ /*IsWeak=*/false,
+ /*IsVolatile=*/X.IsVolatile,
+ /*SuccessMemorder=*/AO,
+ /*FailureMemorder=*/Failure,
+ /*SyncScope=*/static_cast<SyncScope::ID>(SyncScope::System),
+ /*ActualPtr=*/ActualPtr,
+ /*DataTy=*/XElemTy,
+ /*DataSize=*/{},
+ /*AvailableSize=*/{},
+ /*Align=*/{},
+ /*Builder=*/Builder,
+ /*EmitOptions=*/AtomicEmitOptions(DL, &TLI),
+ /*Name=*/Name);
+ if (!ACEResult)
+ return ACEResult.takeError();
+ Value *SuccessOrFail = *ACEResult;
+
+ if (V.Var) {
+ Value *OldValue =
+ Builder.CreateLoad(XElemTy, ActualPtr, Name + ".capture.actual");
+ if (IsPostfixUpdate) {
+ Builder.CreateStore(OldValue, V.Var, V.IsVolatile);
+ } else if (IsFailOnly) {
+ // Must store only of the cmpxchg was successful
+ BasicBlock *ExitBB = splitBB(Builder, true, Name + ".atomic.exit");
+ BasicBlock *ContBB = splitBB(Builder, false, Name + ".atomic.cont");
+ Builder.CreateCondBr(SuccessOrFail, ExitBB, ContBB);
+
+ Builder.SetInsertPoint(ContBB->getTerminator());
+ Builder.CreateStore(OldValue, V.Var);
+
+ Builder.SetInsertPoint(ExitBB, ExitBB->begin());
+ } else {
+ Value *CapturedValue = Builder.CreateSelect(SuccessOrFail, E, OldValue,
+ Name + ".capture.captured");
+ Builder.CreateStore(CapturedValue, V.Var, V.IsVolatile);
+ }
+ }
+
+ // The comparison result has to be stored.
+ if (R.Var) {
+ assert(R.Var->getType()->isPointerTy() &&
+ "R.var must be of pointer type");
+ assert(R.ElemTy->isIntegerTy() && "R must be of integral type");
+
+ Value *ResultCast = R.IsSigned
+ ? Builder.CreateSExt(SuccessOrFail, R.ElemTy)
+ : Builder.CreateZExt(SuccessOrFail, R.ElemTy);
+ Builder.CreateStore(ResultCast, R.Var, R.IsVolatile);
+ }
+
+#else
+
+ // TODO: Use emitAtomicCompareExchangeBuiltin(...)
AtomicCmpXchgInst *Result = nullptr;
if (!IsInteger) {
IntegerType *IntCastTy =
@@ -9043,6 +9084,7 @@ OpenMPIRBuilder::InsertPointTy OpenMPIRBuilder::createAtomicCompare(
}
}
}
+
// The comparison result has to be stored.
if (R.Var) {
assert(R.Var->getType()->isPointerTy() &&
@@ -9055,6 +9097,8 @@ OpenMPIRBuilder::InsertPointTy OpenMPIRBuilder::createAtomicCompare(
: Builder.CreateZExt(SuccessFailureVal, R.ElemTy);
Builder.CreateStore(ResultCast, R.Var, R.IsVolatile);
}
+#endif
+
} else {
assert((Op == OMPAtomicCompareOp::MAX || Op == OMPAtomicCompareOp::MIN) &&
"Op should be either max or min at this point");
diff --git a/llvm/lib/Transforms/Utils/BuildBuiltins.cpp b/llvm/lib/Transforms/Utils/BuildBuiltins.cpp
new file mode 100644
index 0000000000000..c46c0cab85542
--- /dev/null
+++ b/llvm/lib/Transforms/Utils/BuildBuiltins.cpp
@@ -0,0 +1,826 @@
+//===- BuildBuiltins.cpp - Utility builder for builtins -------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Transforms/Utils/BuildBuiltins.h"
+#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/IR/IRBuilder.h"
+#include "llvm/IR/LLVMContext.h"
+#include "llvm/Transforms/Utils/BuildLibCalls.h"
+
+using namespace llvm;
+
+namespace {
+static IntegerType *getIntTy(IRBuilderBase &B, const TargetLibraryInfo *TLI) {
+ return B.getIntNTy(TLI->getIntSize());
+}
+
+static IntegerType *getSizeTTy(IRBuilderBase &B, const TargetLibraryInfo *TLI) {
+ const Module *M = B.GetInsertBlock()->getModule();
+ return B.getIntNTy(TLI->getSizeTSize(*M));
+}
+
+/// In order to use one of the sized library calls such as
+/// __atomic_fetch_add_4, the alignment must be sufficient, the size
+/// must be one of the potentially-specialized sizes, and the value
+/// type must actually exist in C on the target (otherwise, the
+/// function wouldn't actually be defined.)
+static bool canUseSizedAtomicCall(unsigned Size, Align Alignment,
+ const DataLayout &DL) {
+ // TODO: "LargestSize" is an approximation for "largest type that
+ // you can express in C". It seems to be the case that int128 is
+ // supported on all 64-bit platforms, otherwise only up to 64-bit
+ // integers are supported. If we get this wrong, then we'll try to
+ // call a sized libcall that doesn't actually exist. There should
+ // really be some more reliable way in LLVM of determining integer
+ // sizes which are valid in the target's C ABI...
+ unsigned LargestSize = DL.getLargestLegalIntTypeSizeInBits() >= 64 ? 16 : 8;
+ return Alignment >= Size &&
+ (Size == 1 || Size == 2 || Size == 4 || Size == 8 || Size == 16) &&
+ Size <= LargestSize;
+}
+
+// Helper to check if a type is in a variant
+template <typename T, typename Variant> struct is_in_variant;
+
+template <typename T, typename... Types>
+struct is_in_variant<T, std::variant<Types...>>
+ : std::disjunction<std::is_same<T, Types>...> {};
+
+/// Alternative to std::holds_alternative that works even if the std::variant
+/// cannot hold T.
+template <typename T, typename Variant>
+constexpr bool holds_alternative_if_exists(const Variant &v) {
+ if constexpr (is_in_variant<T, Variant>::value) {
+ return std::holds_alternative<T>(v);
+ } else {
+ // Type T is not in the variant, return false or handle accordingly
+ return false;
+ }
+}
+
+/// Common code for emitting an atomic builtin (load, store, cmpxchg).
+class AtomicEmitter {
+public:
+ AtomicEmitter(
+ Value *Ptr, std::variant<Value *, bool> IsWeak, bool IsVolatile,
+ std::variant<Value *, AtomicOrdering, AtomicOrderingCABI> SuccessMemorder,
+ std::variant<std::monostate, Value *, AtomicOrdering, AtomicOrderingCABI>
+ FailureMemorder,
+ SyncScope::ID Scope, Type *DataTy, std::optional<uint64_t> DataSize,
+ std::optional<uint64_t> AvailableSize, MaybeAlign Align,
+ IRBuilderBase &Builder, AtomicEmitOptions EmitOptions, llvm::Twine Name)
+ : Ctx(Builder.getContext()), CurFn(Builder.GetInsertBlock()->getParent()),
+ AtomicPtr(Ptr), IsWeak(IsWeak), IsVolatile(IsVolatile),
+ SuccessMemorder(SuccessMemorder), FailureMemorder(FailureMemorder),
+ Scope(Scope), DataTy(DataTy), DataSize(DataSize),
+ AvailableSize(AvailableSize), Align(Align), Builder(Builder),
+ EmitOptions(std::move(EmitOptions)), Name(Name) {}
+
+protected:
+ LLVMContext &Ctx;
+ Function *CurFn;
+
+ Value *AtomicPtr;
+ std::variant<Value *, bool> IsWeak;
+ bool IsVolatile;
+ std::variant<Value *, AtomicOrdering, AtomicOrderingCABI> SuccessMemorder;
+ std::variant<std::monostate, Value *, AtomicOrdering, AtomicOrderingCABI>
+ FailureMemorder;
+ SyncScope::ID Scope;
+ Type *DataTy;
+ std::optional<uint64_t> DataSize = std::nullopt;
+ std::optional<uint64_t> AvailableSize;
+ uint64_t PreferredSize;
+ MaybeAlign Align;
+ IRBuilderBase &Builder;
+ AtomicEmitOptions EmitOptions;
+ llvm::Twine Name;
+
+ Type *CoercedTy = nullptr;
+ Type *InstCoercedTy = nullptr;
+
+ llvm::Align EffectiveAlign;
+ std::optional<AtomicOrdering> SuccessMemorderConst;
+ Value *SuccessMemorderCABI;
+ std::optional<AtomicOrdering> FailureMemorderConst;
+ Value *FailureMemorderCABI;
+ std::optional<bool> IsWeakConst;
+ Value *IsWeakVal;
+
+ BasicBlock *createBasicBlock(const Twine &BBName) {
+ return BasicBlock::Create(Ctx, Name + BBName, CurFn);
+ };
+
+ virtual bool supportsInstOnFloat() const { return true; }
+
+ virtual void prepareInst() {}
+
+ virtual Value *emitInst(bool IsWeak, AtomicOrdering SuccessMemorder,
+ AtomicOrdering FailureMemorder) = 0;
+
+ Value *emitFailureMemorderSwitch(bool IsWeak,
+ AtomicOrdering SuccessMemorder) {
+ if (FailureMemorderConst) {
+ // FIXME: (from CGAtomic)
+ // 31.7.2.18: "The failure argument shall not be memory_order_release
+ // nor memory_order_acq_rel". Fallback to monotonic.
+ //
+ // Prior to c++17, "the failure argument shall be no stronger than the
+ // success argument". This condition has been lifted and the only
+ // precondition is 31.7.2.18. Effectively treat this as a DR and skip
+ // language version checks.
+ return emitInst(IsWeak, SuccessMemorder, *FailureMemorderConst);
+ }
+
+ Type *BoolTy = Builder.getInt1Ty();
+
+ // Create all the relevant BB's
+ BasicBlock *MonotonicBB = createBasicBlock("monotonic_fail");
+ BasicBlock *AcquireBB = createBasicBlock("acquire_fail");
+ BasicBlock *SeqCstBB = createBasicBlock("seqcst_fail");
+ BasicBlock *ContBB = createBasicBlock("atomic.continue");
+
+ // MonotonicBB is arbitrarily chosen as the default case; in practice,
+ // this doesn't matter unless someone is crazy enough to use something
+ // that doesn't fold to a constant for the ordering.
+ llvm::SwitchInst *SI =
+ Builder.CreateSwitch(FailureMemorderCABI, MonotonicBB);
+ // Implemented as acquire, since it's the closest in LLVM.
+ SI->addCase(
+ Builder.getInt32(static_cast<int32_t>(AtomicOrderingCABI::consume)),
+ AcquireBB);
+ SI->addCase(
+ Builder.getInt32(static_cast<int32_t>(AtomicOrderingCABI::acquire)),
+ AcquireBB);
+ SI->addCase(
+ Builder.getInt32(static_cast<int32_t>(AtomicOrderingCABI::seq_cst)),
+ SeqCstBB);
+
+ // Emit all the different atomics
+ Builder.SetInsertPoint(MonotonicBB);
+ Value *MonotonicResult =
+ emitInst(IsWeak, SuccessMemorder, AtomicOrdering::Monotonic);
+ BasicBlock *MonotonicSourceBB = Builder.GetInsertBlock();
+ Builder.CreateBr(ContBB);
+
+ Builder.SetInsertPoint(AcquireBB);
+ Value *AcquireResult =
+ emitInst(IsWeak, SuccessMemorder, AtomicOrdering::Acquire);
+ BasicBlock *AcquireSourceBB = Builder.GetInsertBlock();
+ Builder.CreateBr(ContBB);
+
+ Builder.SetInsertPoint(SeqCstBB);
+ Value *SeqCstResult = emitInst(IsWeak, SuccessMemorder,
+ AtomicOrdering::SequentiallyConsistent);
+ BasicBlock *SeqCstSourceBB = Builder.GetInsertBlock();
+ Builder.CreateBr(ContBB);
+
+ Builder.SetInsertPoint(ContBB);
+ PHINode *Result = Builder.CreatePHI(BoolTy, 3, Name + ".cmpxchg.success");
+ Result->addIncoming(MonotonicResult, MonotonicSourceBB);
+ Result->addIncoming(AcquireResult, AcquireSourceBB);
+ Result->addIncoming(SeqCstResult, SeqCstSourceBB);
+ return Result;
+ };
+
+ Value *emitSuccessMemorderSwitch(bool IsWeak) {
+ if (SuccessMemorderConst)
+ return emitFailureMemorderSwitch(IsWeak, *SuccessMemorderConst);
+
+ Type *BoolTy = Builder.getInt1Ty();
+
+ // Create all the relevant BB's
+ BasicBlock *MonotonicBB = createBasicBlock(".monotonic");
+ BasicBlock *AcquireBB = createBasicBlock(".acquire");
+ BasicBlock *ReleaseBB = createBasicBlock(".release");
+ BasicBlock *AcqRelBB = createBasicBlock(".acqrel");
+ BasicBlock *SeqCstBB = createBasicBlock(".seqcst");
+ BasicBlock *ContBB = createBasicBlock(".atomic.continue");
+
+ // Create the switch for the split
+ // MonotonicBB is arbitrarily chosen as the default case; in practice,
+ // this doesn't matter unless someone is crazy enough to use something
+ // that doesn't fold to a constant for the ordering.
+ Value *Order =
+ Builder.CreateIntCast(SuccessMemorderCABI, Builder.getInt32Ty(), false);
+ llvm::SwitchInst *SI = Builder.CreateSwitch(Order, MonotonicBB);
+
+ Builder.SetInsertPoint(ContBB);
+ PHINode *Result = Builder.CreatePHI(BoolTy, 5, Name + ".cmpxchg.success");
+
+ // Emit all the different atomics
+ Builder.SetInsertPoint(MonotonicBB);
+ Value *MonotonicResult =
+ emitFailureMemorderSwitch(IsWeak, AtomicOrdering::Monotonic);
+ Result->addIncoming(MonotonicResult, MonotonicBB);
+ Builder.CreateBr(ContBB);
+
+ Builder.SetInsertPoint(AcquireBB);
+ Value *AcquireResult =
+ emitFailureMemorderSwitch(IsWeak, AtomicOrdering::Acquire);
+ Builder.CreateBr(ContBB);
+ SI->addCase(
+ Builder.getInt32(static_cast<uint32_t>(AtomicOrderingCABI::consume)),
+ Builder.GetInsertBlock());
+ SI->addCase(
+ Builder.getInt32(static_cast<uint32_t>(AtomicOrderingCABI::acquire)),
+ Builder.GetInsertBlock());
+ Result->addIncoming(AcquireResult, AcquireBB);
+
+ Builder.SetInsertPoint(ReleaseBB);
+ Value *ReleaseResult =
+ emitFailureMemorderSwitch(IsWeak, AtomicOrdering::Release);
+ Builder.CreateBr(ContBB);
+ SI->addCase(
+ Builder.getInt32(static_cast<uint32_t>(AtomicOrderingCABI::release)),
+ Builder.GetInsertBlock());
+ Result->addIncoming(ReleaseResult, Builder.GetInsertBlock());
+
+ Builder.SetInsertPoint(AcqRelBB);
+ Value *AcqRelResult =
+ emitFailureMemorderSwitch(IsWeak, AtomicOrdering::AcquireRelease);
+ Builder.CreateBr(ContBB);
+ SI->addCase(
+ Builder.getInt32(static_cast<uint32_t>(AtomicOrderingCABI::acq_rel)),
+ AcqRelBB);
+ Result->addIncoming(AcqRelResult, Builder.GetInsertBlock());
+
+ Builder.SetInsertPoint(SeqCstBB);
+ Value *SeqCstResult = emitFailureMemorderSwitch(
+ IsWeak, AtomicOrdering::SequentiallyConsistent);
+ Builder.CreateBr(ContBB);
+ SI->addCase(
+ Builder.getInt32(static_cast<uint32_t>(AtomicOrderingCABI::seq_cst)),
+ SeqCstBB);
+ Result->addIncoming(SeqCstResult, Builder.GetInsertBlock());
+
+ Builder.SetInsertPoint(Result->getNextNode());
+ return Result;
+ };
+
+ Value *emitWeakSwitch() {
+ if (IsWeakConst)
+ return emitSuccessMemorderSwitch(*IsWeakConst);
+
+ Type *BoolTy = Builder.getInt1Ty();
+
+ // Create all the relevant BB's
+ BasicBlock *StrongBB = createBasicBlock(".cmpxchg.strong");
+ BasicBlock *WeakBB = createBasicBlock(".cmpxchg.weak");
+ BasicBlock *ContBB = createBasicBlock(".cmpxchg.continue");
+
+ // FIXME: Why is this a switch?
+ llvm::SwitchInst *SI = Builder.CreateSwitch(IsWeakVal, WeakBB);
+ SI->addCase(Builder.getInt1(false), StrongBB);
+
+ Builder.SetInsertPoint(StrongBB);
+ Value *StrongResult = emitSuccessMemorderSwitch(false);
+ BasicBlock *StrongSourceBB = Builder.GetInsertBlock();
+ Builder.CreateBr(ContBB);
+
+ Builder.SetInsertPoint(WeakBB);
+ Value *WeakResult = emitSuccessMemorderSwitch(true);
+ BasicBlock *WeakSourceBB = Builder.GetInsertBlock();
+ Builder.CreateBr(ContBB);
+
+ Builder.SetInsertPoint(ContBB);
+ PHINode *Result =
+ Builder.CreatePHI(BoolTy, 2, Name + ".cmpxchg.isweak.success");
+ Result->addIncoming(WeakResult, WeakSourceBB);
+ Result->addIncoming(StrongResult, StrongSourceBB);
+ return Result;
+ };
+
+ virtual Expected<Value *> emitSizedLibcall() = 0;
+
+ virtual Expected<Value *> emitLibcall() = 0;
+
+ virtual Expected<Value *> makeFallbackError() = 0;
+
+ Expected<Value *> emit() {
+ assert(AtomicPtr->getType()->isPointerTy() &&
+ "Atomic must apply on pointer");
+ assert(EmitOptions.TLI && "TargetLibraryInfo is mandatory");
+
+ unsigned MaxAtomicSizeSupported = 16;
+ if (EmitOptions.TL)
+ MaxAtomicSizeSupported =
+ EmitOptions.TL->getMaxAtomicSizeInBitsSupported() / 8;
+
+ // Automatically derive data size. It is still possible to be unknown after
+ // this with SVE types, but neither atomic instructions nor libcall
+ // functions support that. After this, *DataSize can be assume to have a
+ // value.
+ if (!DataSize) {
+ TypeSize DS = EmitOptions.DL.getTypeStoreSize(DataTy);
+ assert(DS.isFixed() && "Atomics on scalable types are invalid");
+ DataSize = DS.getFixedValue();
+ }
+
+ // At least DataSize is available
+ // After this, *AvailableSize can be assume to have a value.
+ AvailableSize = AvailableSize.value_or(*DataSize);
+ assert(*DataSize <= *AvailableSize);
+
+ // Choose a preferred size between DataSize and AvailableSize which is
+ // power-of-2 and at most MaxAtomicSizeSupported
+ PreferredSize = *DataSize;
+ uint64_t PowerOfTwo = PowerOf2Ceil(*DataSize);
+ if (*DataSize <= PowerOfTwo && PowerOfTwo <= *AvailableSize &&
+ PowerOfTwo <= MaxAtomicSizeSupported)
+ PreferredSize = PowerOfTwo;
+
+#ifndef NDEBUG
+ if (DataTy) {
+ // 'long double' (80-bit extended precision) behaves strange here.
+ // DL.getTypeStoreSize says it is 10 bytes
+ // Clang says it is 12 bytes
+ // So AtomicExpandPass will disagree with CGAtomic (except for cmpxchg
+ // which does not support floats, so AtomicExpandPass doesn't even know it
+ // originally was an FP80)
+ TypeSize DS = EmitOptions.DL.getTypeStoreSize(DataTy);
+ assert(DS.getKnownMinValue() <= *DataSize &&
+ "Must access at least all the relevant bits of the data, possibly "
+ "some more for padding");
+ }
+#endif
+
+ if (Align) {
+ EffectiveAlign = *Align;
+ } else {
+ // https://llvm.org/docs/LangRef.html#cmpxchg-instruction
+ //
+ // The alignment is only optional when parsing textual IR; for in-memory
+ // IR, it is always present. If unspecified, the alignment is assumed to
+ // be equal to the size of the ‘<value>’ type.
+ //
+ // We prefer safety here and assume no alignment, unless
+ // getPointerAlignment() can determine the actual alignment.
+ // TODO: Would be great if this could determine alignment through a GEP
+ EffectiveAlign = AtomicPtr->getPointerAlignment(EmitOptions.DL);
+ }
+
+ Type *IntTy = getIntTy(Builder, EmitOptions.TLI);
+
+ // Only use the original data type if it is compatible with the atomic
+ // instruction (and sized libcall function) and matches the preferred size.
+ // No type punning needed when using the libcall function while only takes
+ // pointers.
+ CoercedTy = DataTy;
+ // If we have rounded-up the data size, unconditionally coerce to a
+ // different type.
+ if (*DataSize != PreferredSize)
+ CoercedTy = IntegerType::get(Ctx, PreferredSize * 8);
+
+ // Additional type requirements when using an atomic instruction.
+ // Since we don't know the size of SVE instructions, can only use keep the
+ // original type.
+ if (CoercedTy->isIntegerTy() || CoercedTy->isPointerTy() ||
+ (supportsInstOnFloat() && CoercedTy->isFloatingPointTy()))
+ InstCoercedTy = CoercedTy;
+ else
+ InstCoercedTy = IntegerType::get(Ctx, PreferredSize * 8);
+
+ // For resolving the SuccessMemorder/FailureMemorder arguments. If it is
+ // constant, determine the AtomicOrdering for use with the cmpxchg
+ // instruction. Also determines the llvm::Value to be passed to
+ // __atomic_compare_exchange in case cmpxchg is not legal.
+ auto processMemorder = [&](auto MemorderVariant)
+ -> std::pair<std::optional<AtomicOrdering>, Value *> {
+ if (holds_alternative_if_exists<std::monostate>(MemorderVariant)) {
+ // Derive FailureMemorder from SucccessMemorder
+ if (SuccessMemorderConst) {
+ AtomicOrdering MOFailure =
+ AtomicCmpXchgInst::getStrongestFailureOrdering(
+ *SuccessMemorderConst);
+ MemorderVariant = MOFailure;
+ }
+ }
+
+ if (std::holds_alternative<AtomicOrdering>(MemorderVariant)) {
+ auto Memorder = std::get<AtomicOrdering>(MemorderVariant);
+ return std::make_pair(
+ Memorder,
+ ConstantInt::get(IntTy, static_cast<uint64_t>(toCABI(Memorder))));
+ }
+
+ if (std::holds_alternative<AtomicOrderingCABI>(MemorderVariant)) {
+ auto MemorderCABI = std::get<AtomicOrderingCABI>(MemorderVariant);
+ return std::make_pair(
+ fromCABI(MemorderCABI),
+ ConstantInt::get(IntTy, static_cast<uint64_t>(MemorderCABI)));
+ }
+
+ auto *MemorderCABI = std::get<Value *>(MemorderVariant);
+ if (auto *MO = dyn_cast<ConstantInt>(MemorderCABI)) {
+ uint64_t MOInt = MO->getZExtValue();
+ return std::make_pair(fromCABI(MOInt), MO);
+ }
+
+ return std::make_pair(std::nullopt, MemorderCABI);
+ };
+
+ auto processIsWeak =
+ [&](auto WeakVariant) -> std::pair<std::optional<bool>, Value *> {
+ if (std::holds_alternative<bool>(WeakVariant)) {
+ bool IsWeakBool = std::get<bool>(WeakVariant);
+ return std::make_pair(IsWeakBool, Builder.getInt1(IsWeakBool));
+ }
+
+ auto *BoolVal = std::get<Value *>(WeakVariant);
+ if (auto *BoolConst = dyn_cast<ConstantInt>(BoolVal)) {
+ uint64_t IsWeakBool = BoolConst->getZExtValue();
+ return std::make_pair(IsWeakBool != 0, BoolVal);
+ }
+
+ return std::make_pair(std::nullopt, BoolVal);
+ };
+
+ std::tie(IsWeakConst, IsWeakVal) = processIsWeak(IsWeak);
+ std::tie(SuccessMemorderConst, SuccessMemorderCABI) =
+ processMemorder(SuccessMemorder);
+ std::tie(FailureMemorderConst, FailureMemorderCABI) =
+ processMemorder(FailureMemorder);
+
+ // Fix malformed inputs. We do not want to emit illegal IR.
+ //
+ // https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html
+ //
+ // [failure_memorder] This memory order cannot be __ATOMIC_RELEASE nor
+ // __ATOMIC_ACQ_REL. It also cannot be a stronger order than that
+ // specified by success_memorder.
+ //
+ // https://llvm.org/docs/LangRef.html#cmpxchg-instruction
+ //
+ // Both ordering parameters must be at least monotonic, the failure
+ // ordering cannot be either release or acq_rel.
+ //
+ if (FailureMemorderConst &&
+ ((*FailureMemorderConst == AtomicOrdering::Release) ||
+ (*FailureMemorderConst == AtomicOrdering::AcquireRelease))) {
+ // Fall back to monotonic atomic when illegal value is passed. As with the
+ // dynamic case below, it is an arbitrary choice.
+ FailureMemorderConst = AtomicOrdering::Monotonic;
+ }
+ if (FailureMemorderConst && SuccessMemorderConst &&
+ !isAtLeastOrStrongerThan(*SuccessMemorderConst,
+ *FailureMemorderConst)) {
+ // Make SuccessMemorder as least as strong as FailureMemorder
+ SuccessMemorderConst =
+ getMergedAtomicOrdering(*SuccessMemorderConst, *FailureMemorderConst);
+ }
+
+ // https://llvm.org/docs/LangRef.html#cmpxchg-instruction
+ //
+ // The type of ‘<cmp>’ must be an integer or pointer type whose bit width
+ // is a power of two greater than or equal to eight and less than or equal
+ // to a target-specific size limit.
+ bool CanUseInst = PreferredSize <= MaxAtomicSizeSupported &&
+ llvm::isPowerOf2_64(PreferredSize) && InstCoercedTy;
+ bool CanUseSingleInst = CanUseInst && SuccessMemorderConst &&
+ FailureMemorderConst && IsWeakConst;
+ bool CanUseSizedLibcall =
+ canUseSizedAtomicCall(PreferredSize, EffectiveAlign, EmitOptions.DL) &&
+ Scope == SyncScope::System;
+ bool CanUseLibcall = Scope == SyncScope::System;
+
+ if (CanUseSingleInst && EmitOptions.AllowInstruction) {
+ prepareInst();
+ return emitInst(*IsWeakConst, *SuccessMemorderConst,
+ *FailureMemorderConst);
+ }
+
+ // Switching only needed for cmpxchg instruction which requires constant
+ // arguments.
+ // FIXME: If AtomicExpandPass later considers the cmpxchg not lowerable for
+ // the given target, it will also generate a call to the
+ // __atomic_compare_exchange function. In that case the switching was very
+ // unnecessary but cannot be undone.
+ if (CanUseInst && EmitOptions.AllowSwitch && EmitOptions.AllowInstruction) {
+ prepareInst();
+ return emitWeakSwitch();
+ }
+
+ // Fallback to a libcall function. From here on IsWeak/Scope/IsVolatile is
+ // ignored. IsWeak is assumed to be false, Scope is assumed to be
+ // SyncScope::System (strongest possible assumption synchronizing with
+ // everything, instead of just a subset of sibling threads), and volatile
+ // does not apply to function calls.
+
+ if (CanUseSizedLibcall && EmitOptions.AllowSizedLibcall) {
+ Expected<Value *> SizedLibcallResult = emitSizedLibcall();
+ if (SizedLibcallResult)
+ return SizedLibcallResult;
+ }
+
+ if (CanUseLibcall && EmitOptions.AllowLibcall) {
+ Expected<Value *> LibcallResult = emitSizedLibcall();
+ if (LibcallResult)
+ return LibcallResult;
+ }
+
+ return makeFallbackError();
+ }
+};
+
+class AtomicLoadEmitter final : public AtomicEmitter {
+public:
+ using AtomicEmitter::AtomicEmitter;
+
+ Error emitLoad(Value *RetPtr) {
+ assert(RetPtr->getType()->isPointerTy());
+ this->RetPtr = RetPtr;
+ return emit().takeError();
+ }
+
+protected:
+ Value *RetPtr;
+
+ Value *emitInst(bool IsWeak, AtomicOrdering SuccessMemorder,
+ AtomicOrdering FailureMemorder) override {
+ LoadInst *AtomicInst = Builder.CreateLoad(
+ InstCoercedTy, AtomicPtr, IsVolatile, Name + ".atomic.load");
+ AtomicInst->setAtomic(SuccessMemorder, Scope);
+ AtomicInst->setAlignment(EffectiveAlign);
+
+ // Store loaded result to where the caller expects it.
+ // FIXME: Do we need to zero the padding, if any?
+ Builder.CreateStore(AtomicInst, RetPtr, IsVolatile);
+ return nullptr;
+ }
+
+ Expected<Value *> emitSizedLibcall() override {
+ Value *LoadResult =
+ emitAtomicLoadN(PreferredSize, AtomicPtr, SuccessMemorderCABI, Builder,
+ EmitOptions.DL, EmitOptions.TLI);
+ LoadResult->setName(Name);
+ if (LoadResult) {
+ Builder.CreateStore(LoadResult, RetPtr);
+ return nullptr;
+ }
+
+ // emitAtomicLoadN can return nullptr if the backend does not
+ // support sized libcalls. Fall back to the non-sized libcall and remove the
+ // unused load again.
+ return make_error<StringError>("__atomic_load_N libcall absent",
+ inconvertibleErrorCode());
+ }
+
+ Expected<Value *> emitLibcall() override {
+ // Fallback to a libcall function. From here on IsWeak/Scope/IsVolatile is
+ // ignored. IsWeak is assumed to be false, Scope is assumed to be
+ // SyncScope::System (strongest possible assumption synchronizing with
+ // everything, instead of just a subset of sibling threads), and volatile
+ // does not apply to function calls.
+
+ Value *DataSizeVal =
+ ConstantInt::get(getSizeTTy(Builder, EmitOptions.TLI), *DataSize);
+ Value *LoadCall =
+ emitAtomicLoad(DataSizeVal, AtomicPtr, RetPtr, SuccessMemorderCABI,
+ Builder, EmitOptions.DL, EmitOptions.TLI);
+ if (!LoadCall)
+ return make_error<StringError>("__atomic_load libcall absent",
+ inconvertibleErrorCode());
+
+ LoadCall->setName(Name);
+ return nullptr;
+ }
+
+ Expected<Value *> makeFallbackError() override {
+ return make_error<StringError>(
+ "__atomic_laod builtin not supported by any available means",
+ inconvertibleErrorCode());
+ }
+};
+
+class AtomicStoreEmitter final : public AtomicEmitter {
+public:
+ using AtomicEmitter::AtomicEmitter;
+
+ Error emitStore(Value *ValPtr) {
+ assert(ValPtr->getType()->isPointerTy());
+ this->ValPtr = ValPtr;
+ return emit().takeError();
+ }
+
+protected:
+ Value *ValPtr;
+ Value *Val;
+
+ void prepareInst() override {
+ Val = Builder.CreateLoad(InstCoercedTy, ValPtr, Name + ".atomic.val");
+ }
+
+ Value *emitInst(bool IsWeak, AtomicOrdering SuccessMemorder,
+ AtomicOrdering FailureMemorder) override {
+ StoreInst *AtomicInst = Builder.CreateStore(Val, AtomicPtr, IsVolatile);
+ AtomicInst->setAtomic(SuccessMemorder, Scope);
+ AtomicInst->setAlignment(EffectiveAlign);
+ return nullptr;
+ }
+
+ Expected<Value *> emitSizedLibcall() override {
+ Val = Builder.CreateLoad(CoercedTy, ValPtr, Name + ".atomic.val");
+ Value *StoreCall =
+ emitAtomicStoreN(*DataSize, AtomicPtr, Val, SuccessMemorderCABI,
+ Builder, EmitOptions.DL, EmitOptions.TLI);
+ StoreCall->setName(Name);
+ if (StoreCall)
+ return nullptr;
+
+ // emitAtomiStoreN can return nullptr if the backend does not
+ // support sized libcalls. Fall back to the non-sized libcall and remove the
+ // unused load again.
+ return make_error<StringError>("__atomic_store_N libcall absent",
+ inconvertibleErrorCode());
+ }
+
+ Expected<Value *> emitLibcall() override {
+ // Fallback to a libcall function. From here on IsWeak/Scope/IsVolatile is
+ // ignored. IsWeak is assumed to be false, Scope is assumed to be
+ // SyncScope::System (strongest possible assumption synchronizing with
+ // everything, instead of just a subset of sibling threads), and volatile
+ // does not apply to function calls.
+
+ Value *DataSizeVal =
+ ConstantInt::get(getSizeTTy(Builder, EmitOptions.TLI), *DataSize);
+ Value *StoreCall =
+ emitAtomicStore(DataSizeVal, AtomicPtr, ValPtr, SuccessMemorderCABI,
+ Builder, EmitOptions.DL, EmitOptions.TLI);
+ if (!StoreCall)
+ return make_error<StringError>("__atomic_store libcall absent",
+ inconvertibleErrorCode());
+
+ return nullptr;
+ }
+
+ Expected<Value *> makeFallbackError() override {
+ return make_error<StringError>(
+ "__atomic_store builtin not supported by any available means",
+ inconvertibleErrorCode());
+ }
+};
+
+class AtomicCompareExchangeEmitter final : public AtomicEmitter {
+public:
+ using AtomicEmitter::AtomicEmitter;
+
+ Expected<Value *> emitCmpXchg(Value *ExpectedPtr, Value *DesiredPtr,
+ Value *ActualPtr) {
+ assert(ExpectedPtr->getType()->isPointerTy());
+ assert(DesiredPtr->getType()->isPointerTy());
+ assert(!ActualPtr || ActualPtr->getType()->isPointerTy());
+ assert(AtomicPtr != ExpectedPtr);
+ assert(AtomicPtr != DesiredPtr);
+ assert(AtomicPtr != ActualPtr);
+ assert(ActualPtr != DesiredPtr);
+
+ this->ExpectedPtr = ExpectedPtr;
+ this->DesiredPtr = DesiredPtr;
+ this->ActualPtr = ActualPtr;
+ return emit();
+ }
+
+protected:
+ Value *ExpectedPtr;
+ Value *DesiredPtr;
+ Value *ActualPtr;
+ Value *ExpectedVal;
+ Value *DesiredVal;
+
+ bool supportsInstOnFloat() const override { return false; }
+
+ void prepareInst() override {
+ ExpectedVal = Builder.CreateLoad(InstCoercedTy, ExpectedPtr,
+ Name + ".cmpxchg.expected");
+ DesiredVal = Builder.CreateLoad(InstCoercedTy, DesiredPtr,
+ Name + ".cmpxchg.desired");
+ }
+
+ Value *emitInst(bool IsWeak, AtomicOrdering SuccessMemorder,
+ AtomicOrdering FailureMemorder) override {
+ AtomicCmpXchgInst *AtomicInst =
+ Builder.CreateAtomicCmpXchg(AtomicPtr, ExpectedVal, DesiredVal, Align,
+ SuccessMemorder, FailureMemorder, Scope);
+ AtomicInst->setName(Name + ".cmpxchg.pair");
+ AtomicInst->setAlignment(EffectiveAlign);
+ AtomicInst->setWeak(IsWeak);
+ AtomicInst->setVolatile(IsVolatile);
+
+ if (ActualPtr) {
+ Value *ActualVal = Builder.CreateExtractValue(AtomicInst, /*Idxs=*/0,
+ Name + ".cmpxchg.prev");
+ Builder.CreateStore(ActualVal, ActualPtr);
+ }
+ Value *SuccessFailureVal = Builder.CreateExtractValue(
+ AtomicInst, /*Idxs=*/1, Name + ".cmpxchg.success");
+
+ assert(SuccessFailureVal->getType()->isIntegerTy(1));
+ return SuccessFailureVal;
+ }
+
+ Expected<Value *> emitSizedLibcall() override {
+ LoadInst *DesiredVal =
+ Builder.CreateLoad(IntegerType::get(Ctx, PreferredSize * 8), DesiredPtr,
+ Name + ".cmpxchg.desired");
+ Value *SuccessResult = emitAtomicCompareExchangeN(
+ PreferredSize, AtomicPtr, ExpectedPtr, DesiredVal, SuccessMemorderCABI,
+ FailureMemorderCABI, Builder, EmitOptions.DL, EmitOptions.TLI);
+ if (SuccessResult) {
+ Value *SuccessBool =
+ Builder.CreateCmp(CmpInst::Predicate::ICMP_EQ, SuccessResult,
+ Builder.getInt8(0), Name + ".cmpxchg.success");
+
+ if (ActualPtr && ActualPtr != ExpectedPtr)
+ Builder.CreateMemCpy(ActualPtr, {}, ExpectedPtr, {}, *DataSize);
+ return SuccessBool;
+ }
+
+ // emitAtomicCompareExchangeN can return nullptr if the backend does not
+ // support sized libcalls. Fall back to the non-sized libcall and remove the
+ // unused load again.
+ DesiredVal->eraseFromParent();
+ return make_error<StringError>("__atomic_compare_exchange_N libcall absent",
+ inconvertibleErrorCode());
+ }
+
+ Expected<Value *> emitLibcall() override {
+ // FIXME: Some AMDGCN regression tests the addrspace, but
+ // __atomic_compare_exchange by definition is addrsspace(0) and
+ // emitAtomicCompareExchange will complain about it.
+ if (AtomicPtr->getType()->getPointerAddressSpace() ||
+ ExpectedPtr->getType()->getPointerAddressSpace() ||
+ DesiredPtr->getType()->getPointerAddressSpace())
+ return Builder.getInt1(false);
+
+ Value *SuccessResult = emitAtomicCompareExchange(
+ ConstantInt::get(getSizeTTy(Builder, EmitOptions.TLI), *DataSize),
+ AtomicPtr, ExpectedPtr, DesiredPtr, SuccessMemorderCABI,
+ FailureMemorderCABI, Builder, EmitOptions.DL, EmitOptions.TLI);
+ if (!SuccessResult)
+ return make_error<StringError>("__atomic_compare_exchange libcall absent",
+ inconvertibleErrorCode());
+
+ Value *SuccessBool =
+ Builder.CreateCmp(CmpInst::Predicate::ICMP_EQ, SuccessResult,
+ Builder.getInt8(0), Name + ".cmpxchg.success");
+
+ if (ActualPtr && ActualPtr != ExpectedPtr)
+ Builder.CreateMemCpy(ActualPtr, {}, ExpectedPtr, {}, *DataSize);
+ return SuccessBool;
+ }
+
+ Expected<Value *> makeFallbackError() override {
+ return make_error<StringError>("__atomic_compare_exchange builtin not "
+ "supported by any available means",
+ inconvertibleErrorCode());
+ }
+};
+
+} // namespace
+
+Error llvm::emitAtomicLoadBuiltin(
+ Value *AtomicPtr, Value *RetPtr, bool IsVolatile,
+ std::variant<Value *, AtomicOrdering, AtomicOrderingCABI> Memorder,
+ SyncScope::ID Scope, Type *DataTy, std::optional<uint64_t> DataSize,
+ std::optional<uint64_t> AvailableSize, MaybeAlign Align,
+ IRBuilderBase &Builder, AtomicEmitOptions EmitOptions, llvm::Twine Name) {
+ AtomicLoadEmitter Emitter(AtomicPtr, false, IsVolatile, Memorder, {}, Scope,
+ DataTy, DataSize, AvailableSize, Align, Builder,
+ EmitOptions, Name);
+ return Emitter.emitLoad(RetPtr);
+}
+
+Error llvm::emitAtomicStoreBuiltin(
+ Value *AtomicPtr, Value *ValPtr, bool IsVolatile,
+ std::variant<Value *, AtomicOrdering, AtomicOrderingCABI> Memorder,
+ SyncScope::ID Scope, Type *DataTy, std::optional<uint64_t> DataSize,
+ std::optional<uint64_t> AvailableSize, MaybeAlign Align,
+ IRBuilderBase &Builder, AtomicEmitOptions EmitOptions, llvm::Twine Name) {
+ AtomicStoreEmitter Emitter(AtomicPtr, false, IsVolatile, Memorder, {}, Scope,
+ DataTy, DataSize, AvailableSize, Align, Builder,
+ EmitOptions, Name);
+ return Emitter.emitStore(ValPtr);
+}
+
+Expected<Value *> llvm::emitAtomicCompareExchangeBuiltin(
+ Value *AtomicPtr, Value *ExpectedPtr, Value *DesiredPtr,
+ std::variant<Value *, bool> IsWeak, bool IsVolatile,
+ std::variant<Value *, AtomicOrdering, AtomicOrderingCABI> SuccessMemorder,
+ std::variant<std::monostate, Value *, AtomicOrdering, AtomicOrderingCABI>
+ FailureMemorder,
+ SyncScope::ID Scope, Value *PrevPtr, Type *DataTy,
+ std::optional<uint64_t> DataSize, std::optional<uint64_t> AvailableSize,
+ MaybeAlign Align, IRBuilderBase &Builder, AtomicEmitOptions EmitOptions,
+ llvm::Twine Name) {
+ AtomicCompareExchangeEmitter Emitter(
+ AtomicPtr, IsWeak, IsVolatile, SuccessMemorder, FailureMemorder, Scope,
+ DataTy, DataSize, AvailableSize, Align, Builder, EmitOptions, Name);
+ return Emitter.emitCmpXchg(ExpectedPtr, DesiredPtr, PrevPtr);
+}
diff --git a/llvm/lib/Transforms/Utils/BuildLibCalls.cpp b/llvm/lib/Transforms/Utils/BuildLibCalls.cpp
index 7a5326c255831..3e232586b661a 100644
--- a/llvm/lib/Transforms/Utils/BuildLibCalls.cpp
+++ b/llvm/lib/Transforms/Utils/BuildLibCalls.cpp
@@ -1315,6 +1315,28 @@ bool llvm::inferNonMandatoryLibFuncAttrs(Function &F,
Changed |= setDoesNotCapture(F, 2);
Changed |= setWillReturn(F);
break;
+ case LibFunc_atomic_load:
+ case LibFunc_atomic_load_1:
+ case LibFunc_atomic_load_2:
+ case LibFunc_atomic_load_4:
+ case LibFunc_atomic_load_8:
+ case LibFunc_atomic_load_16:
+ case LibFunc_atomic_store:
+ case LibFunc_atomic_store_1:
+ case LibFunc_atomic_store_2:
+ case LibFunc_atomic_store_4:
+ case LibFunc_atomic_store_8:
+ case LibFunc_atomic_store_16:
+ case LibFunc_atomic_compare_exchange:
+ case LibFunc_atomic_compare_exchange_1:
+ case LibFunc_atomic_compare_exchange_2:
+ case LibFunc_atomic_compare_exchange_4:
+ case LibFunc_atomic_compare_exchange_8:
+ case LibFunc_atomic_compare_exchange_16:
+ Changed |= setArgsNoUndef(F);
+ Changed |= setDoesNotThrow(F);
+ Changed |= setWillReturn(F);
+ break;
default:
// FIXME: It'd be really nice to cover all the library functions we're
// aware of here.
@@ -1412,6 +1434,49 @@ FunctionCallee llvm::getOrInsertLibFunc(Module *M, const TargetLibraryInfo &TLI,
setArgExtAttr(*F, 2, TLI);
break;
+ case LibFunc_atomic_load:
+ setArgExtAttr(*F, 4, TLI); // Memorder
+ break;
+
+ case LibFunc_atomic_load_1:
+ case LibFunc_atomic_load_2:
+ case LibFunc_atomic_load_4:
+ case LibFunc_atomic_load_8:
+ case LibFunc_atomic_load_16:
+ setRetExtAttr(*F, TLI); // return
+ setArgExtAttr(*F, 3, TLI); // Memorder
+ break;
+
+ case LibFunc_atomic_store:
+ setArgExtAttr(*F, 4, TLI); // Memorder
+ break;
+
+ case LibFunc_atomic_store_1:
+ case LibFunc_atomic_store_2:
+ case LibFunc_atomic_store_4:
+ case LibFunc_atomic_store_8:
+ case LibFunc_atomic_store_16:
+ setArgExtAttr(*F, 2, TLI); // Val
+ setArgExtAttr(*F, 3, TLI); // Memorder
+ break;
+
+ case LibFunc_atomic_compare_exchange:
+ setRetExtAttr(*F, TLI); // return
+ setArgExtAttr(*F, 4, TLI); // SuccessMemorder
+ setArgExtAttr(*F, 5, TLI); // FailureMemorder
+ break;
+
+ case LibFunc_atomic_compare_exchange_1:
+ case LibFunc_atomic_compare_exchange_2:
+ case LibFunc_atomic_compare_exchange_4:
+ case LibFunc_atomic_compare_exchange_8:
+ case LibFunc_atomic_compare_exchange_16:
+ setRetExtAttr(*F, TLI); // return
+ setArgExtAttr(*F, 2, TLI); // Desired
+ setArgExtAttr(*F, 3, TLI); // SuccessMemorder
+ setArgExtAttr(*F, 4, TLI); // FailureMemorder
+ break;
+
// These are functions that are known to not need any argument extension
// on any target: A size_t argument (which may be an i32 on some targets)
// should not trigger the assert below.
@@ -1767,6 +1832,153 @@ Value *llvm::emitVSPrintf(Value *Dest, Value *Fmt, Value *VAList,
{Dest, Fmt, VAList}, B, TLI);
}
+Value *llvm::emitAtomicLoad(Value *Size, Value *Ptr, Value *Ret,
+ Value *Memorder, IRBuilderBase &B,
+ const DataLayout &DL,
+ const TargetLibraryInfo *TLI) {
+ Type *VoidTy = B.getVoidTy();
+ Type *SizeTTy = getSizeTTy(B, TLI);
+ Type *PtrTy = B.getPtrTy();
+ Type *IntTy = getIntTy(B, TLI);
+ return emitLibCall(LibFunc_atomic_load, VoidTy,
+ {SizeTTy, PtrTy, PtrTy, IntTy}, {Size, Ptr, Ret, Memorder},
+ B, TLI);
+}
+
+Value *llvm::emitAtomicLoadN(size_t Size, Value *Ptr, Value *Memorder,
+ IRBuilderBase &B, const DataLayout &DL,
+ const TargetLibraryInfo *TLI) {
+ LibFunc TheLibFunc;
+ switch (Size) {
+ case 1:
+ TheLibFunc = LibFunc_atomic_load_1;
+ break;
+ case 2:
+ TheLibFunc = LibFunc_atomic_load_2;
+ break;
+ case 4:
+ TheLibFunc = LibFunc_atomic_load_4;
+ break;
+ case 8:
+ TheLibFunc = LibFunc_atomic_load_8;
+ break;
+ case 16:
+ TheLibFunc = LibFunc_atomic_load_16;
+ break;
+ default:
+ // emitLibCall below is also allowed to return nullptr, e.g. if
+ // TargetLibraryInfo says the backend does not support the libcall function.
+ return nullptr;
+ }
+
+ Type *PtrTy = B.getPtrTy();
+ Type *ValTy = B.getIntNTy(Size * 8);
+ Type *IntTy = getIntTy(B, TLI);
+ return emitLibCall(TheLibFunc, ValTy, {PtrTy, IntTy}, {Ptr, Memorder}, B,
+ TLI);
+}
+
+Value *llvm::emitAtomicStore(Value *Size, Value *Ptr, Value *ValPtr,
+ Value *Memorder, IRBuilderBase &B,
+ const DataLayout &DL,
+ const TargetLibraryInfo *TLI) {
+ Type *VoidTy = B.getVoidTy();
+ Type *SizeTTy = getSizeTTy(B, TLI);
+ Type *PtrTy = B.getPtrTy();
+ Type *IntTy = getIntTy(B, TLI);
+ return emitLibCall(LibFunc_atomic_store, VoidTy,
+ {SizeTTy, PtrTy, PtrTy, IntTy},
+ {Size, Ptr, ValPtr, Memorder}, B, TLI);
+}
+
+Value *llvm::emitAtomicStoreN(size_t Size, Value *Ptr, Value *Val,
+ Value *Memorder, IRBuilderBase &B,
+ const DataLayout &DL,
+ const TargetLibraryInfo *TLI) {
+ LibFunc TheLibFunc;
+ switch (Size) {
+ case 1:
+ TheLibFunc = LibFunc_atomic_store_1;
+ break;
+ case 2:
+ TheLibFunc = LibFunc_atomic_store_2;
+ break;
+ case 4:
+ TheLibFunc = LibFunc_atomic_store_4;
+ break;
+ case 8:
+ TheLibFunc = LibFunc_atomic_store_8;
+ break;
+ case 16:
+ TheLibFunc = LibFunc_atomic_store_16;
+ break;
+ default:
+ // emitLibCall below is also allowed to return nullptr, e.g. if
+ // TargetLibraryInfo says the backend does not support the libcall function.
+ return nullptr;
+ }
+
+ Type *VoidTy = B.getVoidTy();
+ Type *PtrTy = B.getPtrTy();
+ Type *ValTy = B.getIntNTy(Size * 8);
+ Type *IntTy = getIntTy(B, TLI);
+ return emitLibCall(TheLibFunc, VoidTy, {PtrTy, ValTy, IntTy},
+ {Ptr, Val, Memorder}, B, TLI);
+}
+
+Value *llvm::emitAtomicCompareExchange(Value *Size, Value *Ptr, Value *Expected,
+ Value *Desired, Value *SuccessMemorder,
+ Value *FailureMemorder, IRBuilderBase &B,
+ const DataLayout &DL,
+ const TargetLibraryInfo *TLI) {
+ Type *BoolTy = B.getInt8Ty();
+ Type *SizeTTy = getSizeTTy(B, TLI);
+ Type *PtrTy = B.getPtrTy();
+ Type *IntTy = getIntTy(B, TLI);
+ return emitLibCall(
+ LibFunc_atomic_compare_exchange, BoolTy,
+ {SizeTTy, PtrTy, PtrTy, PtrTy, IntTy, IntTy},
+ {Size, Ptr, Expected, Desired, SuccessMemorder, FailureMemorder}, B, TLI);
+}
+
+Value *llvm::emitAtomicCompareExchangeN(size_t Size, Value *Ptr,
+ Value *Expected, Value *Desired,
+ Value *SuccessMemorder,
+ Value *FailureMemorder,
+ IRBuilderBase &B, const DataLayout &DL,
+ const TargetLibraryInfo *TLI) {
+ LibFunc TheLibFunc;
+ switch (Size) {
+ case 1:
+ TheLibFunc = LibFunc_atomic_compare_exchange_1;
+ break;
+ case 2:
+ TheLibFunc = LibFunc_atomic_compare_exchange_2;
+ break;
+ case 4:
+ TheLibFunc = LibFunc_atomic_compare_exchange_4;
+ break;
+ case 8:
+ TheLibFunc = LibFunc_atomic_compare_exchange_8;
+ break;
+ case 16:
+ TheLibFunc = LibFunc_atomic_compare_exchange_16;
+ break;
+ default:
+ // emitLibCall below is also allowed to return nullptr, e.g. if
+ // TargetLibraryInfo says the backend does not support the libcall function.
+ return nullptr;
+ }
+
+ Type *BoolTy = B.getInt8Ty();
+ Type *PtrTy = B.getPtrTy();
+ Type *ValTy = B.getIntNTy(Size * 8);
+ Type *IntTy = getIntTy(B, TLI);
+ return emitLibCall(TheLibFunc, BoolTy, {PtrTy, PtrTy, ValTy, IntTy, IntTy},
+ {Ptr, Expected, Desired, SuccessMemorder, FailureMemorder},
+ B, TLI);
+}
+
/// Append a suffix to the function name according to the type of 'Op'.
static void appendTypeSuffix(Value *Op, StringRef &Name,
SmallString<20> &NameBuffer) {
diff --git a/llvm/lib/Transforms/Utils/CMakeLists.txt b/llvm/lib/Transforms/Utils/CMakeLists.txt
index 78cad0d253be8..cc85126911d32 100644
--- a/llvm/lib/Transforms/Utils/CMakeLists.txt
+++ b/llvm/lib/Transforms/Utils/CMakeLists.txt
@@ -5,6 +5,7 @@ add_llvm_component_library(LLVMTransformUtils
AssumeBundleBuilder.cpp
BasicBlockUtils.cpp
BreakCriticalEdges.cpp
+ BuildBuiltins.cpp
BuildLibCalls.cpp
BypassSlowDivision.cpp
CallPromotionUtils.cpp
diff --git a/llvm/test/tools/llvm-tli-checker/ps4-tli-check.yaml b/llvm/test/tools/llvm-tli-checker/ps4-tli-check.yaml
index 2d23b15d74b17..a9e5b8bbf67bf 100644
--- a/llvm/test/tools/llvm-tli-checker/ps4-tli-check.yaml
+++ b/llvm/test/tools/llvm-tli-checker/ps4-tli-check.yaml
@@ -54,10 +54,10 @@
## the exact count first; the two directives should add up to that.
## Yes, this means additions to TLI will fail this test, but the argument
## to -COUNT can't be an expression.
-# AVAIL: TLI knows 523 symbols, 289 available
+# AVAIL: TLI knows 539 symbols, 289 available
# AVAIL-COUNT-289: {{^}} available
# AVAIL-NOT: {{^}} available
-# UNAVAIL-COUNT-234: not available
+# UNAVAIL-COUNT-250: not available
# UNAVAIL-NOT: not available
## This is a large file so it's worth telling lit to stop here.
diff --git a/llvm/unittests/Analysis/TargetLibraryInfoTest.cpp b/llvm/unittests/Analysis/TargetLibraryInfoTest.cpp
index 97722483aefe0..4f77a9017fc51 100644
--- a/llvm/unittests/Analysis/TargetLibraryInfoTest.cpp
+++ b/llvm/unittests/Analysis/TargetLibraryInfoTest.cpp
@@ -592,7 +592,25 @@ TEST_F(TargetLibraryInfoTest, ValidProto) {
"declare i8* @memrchr(i8*, i32, i64)\n"
"declare void @__atomic_load(i64, i8*, i8*, i32)\n"
+ "declare i8 @__atomic_load_1(ptr, i32)\n"
+ "declare i16 @__atomic_load_2(ptr, i32)\n"
+ "declare i32 @__atomic_load_4(ptr, i32)\n"
+ "declare i64 @__atomic_load_8(ptr, i32)\n"
+ "declare i128 @__atomic_load_16(ptr, i32)\n"
+
"declare void @__atomic_store(i64, i8*, i8*, i32)\n"
+ "declare void @__atomic_store_1(ptr, i8, i32)\n"
+ "declare void @__atomic_store_2(ptr, i16, i32)\n"
+ "declare void @__atomic_store_4(ptr, i32, i32)\n"
+ "declare void @__atomic_store_8(ptr, i64, i32)\n"
+ "declare void @__atomic_store_16(ptr, i128, i32)\n"
+
+ "declare i8 @__atomic_compare_exchange(i64, ptr, ptr, ptr, i32, i32)\n"
+ "declare i8 @__atomic_compare_exchange_1(ptr, ptr, i8, i32, i32)\n"
+ "declare i8 @__atomic_compare_exchange_2(ptr, ptr, i16, i32, i32)\n"
+ "declare i8 @__atomic_compare_exchange_4(ptr, ptr, i32, i32, i32)\n"
+ "declare i8 @__atomic_compare_exchange_8(ptr, ptr, i64, i32, i32)\n"
+ "declare i8 @__atomic_compare_exchange_16(ptr, ptr, i128, i32, i32)\n"
// These are similar to the FILE* fgetc/fputc.
"declare i32 @_IO_getc(%struct*)\n"
diff --git a/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp b/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
index 27c0e0bf80255..23f518fccd4b9 100644
--- a/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
+++ b/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
@@ -198,6 +198,78 @@ static omp::ScheduleKind getSchedKind(omp::OMPScheduleType SchedType) {
}
}
+/// Look for all instructions that may have written the value at \p Ptr when
+/// executing \p StartFrom. In other words, computes the reaching defintions
+/// without relying MemorySSA in a naive way.
+static void
+followBackwardsLookForWrites(Value *Ptr, BasicBlock *BB,
+ BasicBlock::reverse_iterator StartFrom,
+ DenseSet<BasicBlock *> &Visited,
+ SmallVectorImpl<Instruction *> &WriteAccs) {
+ for (Instruction &I : make_range(StartFrom, BB->rend())) {
+ if (!I.mayHaveSideEffects())
+ continue;
+ if (isa<LoadInst>(I))
+ continue;
+
+ if (auto *SI = dyn_cast<StoreInst>(&I)) {
+ if (SI->getPointerOperand() == Ptr) {
+ WriteAccs.push_back(SI);
+ return;
+ }
+ continue;
+ } else if (auto *CmpXchg = dyn_cast<AtomicCmpXchgInst>(&I)) {
+ if (CmpXchg->getPointerOperand() == Ptr) {
+ WriteAccs.push_back(CmpXchg);
+ return;
+ }
+ } else if (auto *ARMW = dyn_cast<AtomicRMWInst>(&I)) {
+ if (ARMW->getPointerOperand() == Ptr) {
+ WriteAccs.push_back(ARMW);
+ return;
+ }
+ }
+
+ // TODO: Consider other instructions that may write to \p Ptr.
+ }
+
+ // If there is no instruction in \p BB writing to \p Ptr, look further into \p
+ // BB's predecessors.
+ Visited.insert(BB);
+ for (BasicBlock *Pred : predecessors(BB)) {
+ if (Visited.contains(Pred))
+ continue;
+
+ followBackwardsLookForWrites(Ptr, Pred, Pred->rbegin(), Visited, WriteAccs);
+ }
+};
+
+/// Compute which instruction has written the value at \p Ptr when executing \p
+/// BeforeInst. Assumes that there is just a single such instruction.
+static Instruction *getUniquePreviousStore(Value *Ptr,
+ Instruction *BeforeInst) {
+ DenseSet<BasicBlock *> Visited;
+ SmallVector<Instruction *, 1> WriteAccs;
+ followBackwardsLookForWrites(Ptr, BeforeInst->getParent(),
+ BeforeInst->getReverseIterator(), Visited,
+ WriteAccs);
+ if (WriteAccs.size() == 1)
+ return WriteAccs.front();
+ return nullptr;
+}
+
+/// Compute which instruction has written the value at \p Ptr when execution of
+/// \p FromBB ended. Assumes that there is just a single such instruction.
+static Instruction *getUniquePreviousStore(Value *Ptr, BasicBlock *FromBB) {
+ DenseSet<BasicBlock *> Visited;
+ SmallVector<Instruction *, 1> WriteAccs;
+ followBackwardsLookForWrites(Ptr, FromBB, FromBB->rbegin(), Visited,
+ WriteAccs);
+ if (WriteAccs.size() == 1)
+ return WriteAccs.front();
+ return nullptr;
+}
+
class OpenMPIRBuilderTest : public testing::Test {
protected:
void SetUp() override {
@@ -3790,27 +3862,56 @@ TEST_F(OpenMPIRBuilderTest, OMPAtomicReadFlt) {
OpenMPIRBuilder::AtomicOpValue X = {XVal, Float32, false, false};
OpenMPIRBuilder::AtomicOpValue V = {VVal, Float32, false, false};
- Builder.restoreIP(OMPBuilder.createAtomicRead(Loc, X, V, AO));
-
- IntegerType *IntCastTy =
- IntegerType::get(M->getContext(), Float32->getScalarSizeInBits());
-
- LoadInst *AtomicLoad = cast<LoadInst>(VVal->getNextNode());
- EXPECT_TRUE(AtomicLoad->isAtomic());
- EXPECT_EQ(AtomicLoad->getPointerOperand(), XVal);
-
- BitCastInst *CastToFlt = cast<BitCastInst>(AtomicLoad->getNextNode());
- EXPECT_EQ(CastToFlt->getSrcTy(), IntCastTy);
- EXPECT_EQ(CastToFlt->getDestTy(), Float32);
- EXPECT_EQ(CastToFlt->getOperand(0), AtomicLoad);
-
- StoreInst *StoreofAtomic = cast<StoreInst>(CastToFlt->getNextNode());
- EXPECT_EQ(StoreofAtomic->getValueOperand(), CastToFlt);
- EXPECT_EQ(StoreofAtomic->getPointerOperand(), VVal);
+ ASSERT_EXPECTED_INIT(OpenMPIRBuilder::InsertPointTy, AfterReadIP,
+ OMPBuilder.createAtomicRead(Loc, X, V, AO));
+ Builder.restoreIP(AfterReadIP);
Builder.CreateRetVoid();
OMPBuilder.finalize();
EXPECT_FALSE(verifyModule(*M, &errs()));
+
+ {
+ // clang-format off
+ // %AtomicVar = alloca float, align 4
+ // %AtomicRead = alloca float, align 4
+ // %.atomic.load = load atomic float, ptr %AtomicVar monotonic, align 4, !dbg !5
+ // store float %.atomic.load, ptr %AtomicRead, align 4, !dbg !5
+ // clang-format on
+
+ // Follow use-def and load-store chains to discover instructions
+ StoreInst *Store = cast<StoreInst>(getUniquePreviousStore(VVal, BB));
+ LoadInst *AtomicLoad = cast<LoadInst>(Store->getValueOperand());
+ AllocaInst *Atomicvar = cast<AllocaInst>(AtomicLoad->getPointerOperand());
+
+ // %AtomicVar = alloca float, align 4
+ EXPECT_EQ(Atomicvar->getParent(), BB);
+ EXPECT_FALSE(Atomicvar->isArrayAllocation());
+ EXPECT_EQ(Atomicvar->getAddressSpace(), 0);
+ EXPECT_EQ(Atomicvar->getAlign(), 4);
+ EXPECT_TRUE(Atomicvar->getAllocatedType()->isFloatTy());
+
+ // %AtomicRead = alloca float, align 4
+ EXPECT_EQ(VVal->getParent(), BB);
+ EXPECT_FALSE(VVal->isArrayAllocation());
+ EXPECT_EQ(VVal->getAddressSpace(), 0);
+ EXPECT_EQ(VVal->getAlign(), 4);
+ EXPECT_TRUE(VVal->getAllocatedType()->isFloatTy());
+
+ // %.atomic.load = load atomic float, ptr %AtomicVar monotonic, align 4,
+ // !dbg !5
+ EXPECT_EQ(AtomicLoad->getParent(), BB);
+ EXPECT_FALSE(AtomicLoad->isVolatile());
+ EXPECT_EQ(AtomicLoad->getAlign(), 4);
+ EXPECT_EQ(AtomicLoad->getOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(AtomicLoad->getSyncScopeID(), SyncScope::System);
+ EXPECT_EQ(AtomicLoad->getPointerOperand(), Atomicvar);
+
+ // store float %.atomic.load, ptr %AtomicRead, align 4, !dbg !5
+ EXPECT_EQ(Store->getParent(), BB);
+ EXPECT_TRUE(Store->isSimple());
+ EXPECT_EQ(Store->getValueOperand(), AtomicLoad);
+ EXPECT_EQ(Store->getPointerOperand(), VVal);
+ }
}
TEST_F(OpenMPIRBuilderTest, OMPAtomicReadInt) {
@@ -3832,7 +3933,9 @@ TEST_F(OpenMPIRBuilderTest, OMPAtomicReadInt) {
BasicBlock *EntryBB = BB;
- Builder.restoreIP(OMPBuilder.createAtomicRead(Loc, X, V, AO));
+ ASSERT_EXPECTED_INIT(OpenMPIRBuilder::InsertPointTy, AfterReadIP,
+ OMPBuilder.createAtomicRead(Loc, X, V, AO));
+ Builder.restoreIP(AfterReadIP);
LoadInst *AtomicLoad = nullptr;
StoreInst *StoreofAtomic = nullptr;
@@ -3874,25 +3977,73 @@ TEST_F(OpenMPIRBuilderTest, OMPAtomicWriteFlt) {
Type *Float32 = Type::getFloatTy(Ctx);
AllocaInst *XVal = Builder.CreateAlloca(Float32);
XVal->setName("AtomicVar");
+ OpenMPIRBuilder::InsertPointTy AllocaIP(XVal->getParent(),
+ XVal->getIterator());
OpenMPIRBuilder::AtomicOpValue X = {XVal, Float32, false, false};
AtomicOrdering AO = AtomicOrdering::Monotonic;
Constant *ValToWrite = ConstantFP::get(Float32, 1.0);
- Builder.restoreIP(OMPBuilder.createAtomicWrite(Loc, X, ValToWrite, AO));
-
- IntegerType *IntCastTy =
- IntegerType::get(M->getContext(), Float32->getScalarSizeInBits());
-
- Value *ExprCast = Builder.CreateBitCast(ValToWrite, IntCastTy);
-
- StoreInst *StoreofAtomic = cast<StoreInst>(XVal->getNextNode());
- EXPECT_EQ(StoreofAtomic->getValueOperand(), ExprCast);
- EXPECT_EQ(StoreofAtomic->getPointerOperand(), XVal);
- EXPECT_TRUE(StoreofAtomic->isAtomic());
+ ASSERT_EXPECTED_INIT(
+ OpenMPIRBuilder::InsertPointTy, AfterWriteIP,
+ OMPBuilder.createAtomicWrite(Loc, AllocaIP, X, ValToWrite, AO));
+ Builder.restoreIP(AfterWriteIP);
Builder.CreateRetVoid();
OMPBuilder.finalize();
EXPECT_FALSE(verifyModule(*M, &errs()));
+
+ {
+ // %AtomicVar.atomic.val = alloca float, align 4
+ // %AtomicVar = alloca float, align 4
+ // store float 1.000000e+00, ptr %AtomicVar.atomic.val, align 4
+ // %.atomic.val = load float, ptr %AtomicVar.atomic.val, align 4
+ // store atomic float %.atomic.val, ptr %AtomicVar monotonic, align 4
+
+ // Follow use-def and load-store chains to discover instructions
+ StoreInst *Store1 = cast<StoreInst>(getUniquePreviousStore(XVal, BB));
+ LoadInst *AtomicVal = cast<LoadInst>(Store1->getValueOperand());
+ AllocaInst *AtomicvarAtomicVal =
+ cast<AllocaInst>(AtomicVal->getPointerOperand());
+ StoreInst *Store2 =
+ cast<StoreInst>(getUniquePreviousStore(AtomicvarAtomicVal, AtomicVal));
+
+ // %AtomicVar.atomic.val = alloca float, align 4
+ EXPECT_EQ(AtomicvarAtomicVal->getParent(), BB);
+ EXPECT_FALSE(AtomicvarAtomicVal->isArrayAllocation());
+ EXPECT_EQ(AtomicvarAtomicVal->getAddressSpace(), 0);
+ EXPECT_EQ(AtomicvarAtomicVal->getAlign(), 4);
+ EXPECT_TRUE(AtomicvarAtomicVal->getAllocatedType()->isFloatTy());
+
+ // %AtomicVar = alloca float, align 4
+ EXPECT_EQ(XVal->getParent(), BB);
+ EXPECT_FALSE(XVal->isArrayAllocation());
+ EXPECT_EQ(XVal->getAddressSpace(), 0);
+ EXPECT_EQ(XVal->getAlign(), 4);
+ EXPECT_TRUE(XVal->getAllocatedType()->isFloatTy());
+
+ // store float 1.000000e+00, ptr %AtomicVar.atomic.val, align 4
+ EXPECT_EQ(Store2->getParent(), BB);
+ EXPECT_TRUE(Store2->isSimple());
+ EXPECT_FLOAT_EQ(cast<ConstantFP>(Store2->getValueOperand())
+ ->getValueAPF()
+ .convertToFloat(),
+ 1.0f);
+ EXPECT_EQ(Store2->getPointerOperand(), AtomicvarAtomicVal);
+
+ // %.atomic.val = load float, ptr %AtomicVar.atomic.val, align 4
+ EXPECT_EQ(AtomicVal->getParent(), BB);
+ EXPECT_TRUE(AtomicVal->isSimple());
+ EXPECT_EQ(AtomicVal->getPointerOperand(), AtomicvarAtomicVal);
+
+ // store atomic float %.atomic.val, ptr %AtomicVar monotonic, align 4
+ EXPECT_EQ(Store1->getParent(), BB);
+ EXPECT_FALSE(Store1->isVolatile());
+ EXPECT_EQ(Store1->getAlign(), 4);
+ EXPECT_EQ(Store1->getOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(Store1->getSyncScopeID(), SyncScope::System);
+ EXPECT_EQ(Store1->getValueOperand(), AtomicVal);
+ EXPECT_EQ(Store1->getPointerOperand(), XVal);
+ }
}
TEST_F(OpenMPIRBuilderTest, OMPAtomicWriteInt) {
@@ -3907,32 +4058,76 @@ TEST_F(OpenMPIRBuilderTest, OMPAtomicWriteInt) {
IntegerType *Int32 = Type::getInt32Ty(Ctx);
AllocaInst *XVal = Builder.CreateAlloca(Int32);
XVal->setName("AtomicVar");
+ OpenMPIRBuilder::InsertPointTy AllocaIP(XVal->getParent(),
+ XVal->getIterator());
OpenMPIRBuilder::AtomicOpValue X = {XVal, Int32, false, false};
AtomicOrdering AO = AtomicOrdering::Monotonic;
ConstantInt *ValToWrite = ConstantInt::get(Type::getInt32Ty(Ctx), 1U);
BasicBlock *EntryBB = BB;
- Builder.restoreIP(OMPBuilder.createAtomicWrite(Loc, X, ValToWrite, AO));
-
- StoreInst *StoreofAtomic = nullptr;
-
- for (Instruction &Cur : *EntryBB) {
- if (isa<StoreInst>(Cur)) {
- StoreofAtomic = cast<StoreInst>(&Cur);
- if (StoreofAtomic->getPointerOperand() == XVal)
- continue;
- StoreofAtomic = nullptr;
- }
- }
-
- EXPECT_NE(StoreofAtomic, nullptr);
- EXPECT_TRUE(StoreofAtomic->isAtomic());
- EXPECT_EQ(StoreofAtomic->getValueOperand(), ValToWrite);
+ ASSERT_EXPECTED_INIT(
+ OpenMPIRBuilder::InsertPointTy, AfterWriteIP,
+ OMPBuilder.createAtomicWrite(Loc, AllocaIP, X, ValToWrite, AO));
+ Builder.restoreIP(AfterWriteIP);
Builder.CreateRetVoid();
OMPBuilder.finalize();
EXPECT_FALSE(verifyModule(*M, &errs()));
+
+ {
+ // %AtomicVar.atomic.val = alloca i32, align 4
+ // %AtomicVar = alloca i32, align 4
+ // store i32 1, ptr %AtomicVar.atomic.val, align 4
+ // %.atomic.val = load i32, ptr %AtomicVar.atomic.val, align 4
+ // store atomic i32 %.atomic.val, ptr %AtomicVar monotonic, align 4
+
+ // Follow use-def and load-store chains to discover instructions
+ StoreInst *Store1 = cast<StoreInst>(getUniquePreviousStore(XVal, EntryBB));
+ LoadInst *AtomicVal = cast<LoadInst>(Store1->getValueOperand());
+ AllocaInst *AtomicvarAtomicVal =
+ cast<AllocaInst>(AtomicVal->getPointerOperand());
+ StoreInst *Store2 =
+ cast<StoreInst>(getUniquePreviousStore(AtomicvarAtomicVal, AtomicVal));
+
+ // %AtomicVar.atomic.val = alloca i32, align 4
+ EXPECT_EQ(AtomicvarAtomicVal->getParent(), EntryBB);
+ EXPECT_FALSE(AtomicvarAtomicVal->isArrayAllocation());
+ EXPECT_EQ(AtomicvarAtomicVal->getAddressSpace(), 0);
+ EXPECT_EQ(AtomicvarAtomicVal->getAlign(), 4);
+ Type *AtomicvarAtomicValTy = AtomicvarAtomicVal->getAllocatedType();
+ EXPECT_TRUE(AtomicvarAtomicValTy->isIntegerTy());
+ EXPECT_EQ(AtomicvarAtomicValTy->getIntegerBitWidth(), 32);
+
+ // %AtomicVar = alloca i32, align 4
+ EXPECT_EQ(XVal->getParent(), EntryBB);
+ EXPECT_FALSE(XVal->isArrayAllocation());
+ EXPECT_EQ(XVal->getAddressSpace(), 0);
+ EXPECT_EQ(XVal->getAlign(), 4);
+ Type *XValTy = XVal->getAllocatedType();
+ EXPECT_TRUE(XValTy->isIntegerTy());
+ EXPECT_EQ(XValTy->getIntegerBitWidth(), 32);
+
+ // store i32 1, ptr %AtomicVar.atomic.val, align 4
+ EXPECT_EQ(Store2->getParent(), EntryBB);
+ EXPECT_TRUE(Store2->isSimple());
+ EXPECT_EQ(cast<ConstantInt>(Store2->getValueOperand())->getZExtValue(), 1);
+ EXPECT_EQ(Store2->getPointerOperand(), AtomicvarAtomicVal);
+
+ // %.atomic.val = load i32, ptr %AtomicVar.atomic.val, align 4
+ EXPECT_EQ(AtomicVal->getParent(), EntryBB);
+ EXPECT_TRUE(AtomicVal->isSimple());
+ EXPECT_EQ(AtomicVal->getPointerOperand(), AtomicvarAtomicVal);
+
+ // store atomic i32 %.atomic.val, ptr %AtomicVar monotonic, align 4
+ EXPECT_EQ(Store1->getParent(), EntryBB);
+ EXPECT_FALSE(Store1->isVolatile());
+ EXPECT_EQ(Store1->getAlign(), 4);
+ EXPECT_EQ(Store1->getOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(Store1->getSyncScopeID(), SyncScope::System);
+ EXPECT_EQ(Store1->getValueOperand(), AtomicVal);
+ EXPECT_EQ(Store1->getPointerOperand(), XVal);
+ }
}
TEST_F(OpenMPIRBuilderTest, OMPAtomicUpdate) {
@@ -3946,7 +4141,8 @@ TEST_F(OpenMPIRBuilderTest, OMPAtomicUpdate) {
IntegerType *Int32 = Type::getInt32Ty(M->getContext());
AllocaInst *XVal = Builder.CreateAlloca(Int32);
XVal->setName("AtomicVar");
- Builder.CreateStore(ConstantInt::get(Type::getInt32Ty(Ctx), 0U), XVal);
+ ConstantInt *ExpectedVal = ConstantInt::get(Type::getInt32Ty(Ctx), 0U);
+ Builder.CreateStore(ExpectedVal, XVal);
OpenMPIRBuilder::AtomicOpValue X = {XVal, Int32, false, false};
AtomicOrdering AO = AtomicOrdering::Monotonic;
ConstantInt *ConstVal = ConstantInt::get(Type::getInt32Ty(Ctx), 1U);
@@ -3968,41 +4164,173 @@ TEST_F(OpenMPIRBuilderTest, OMPAtomicUpdate) {
AO, RMWOp, UpdateOp,
IsXLHSInRHSPart));
Builder.restoreIP(AfterIP);
- BasicBlock *ContBB = EntryBB->getSingleSuccessor();
- BranchInst *ContTI = dyn_cast<BranchInst>(ContBB->getTerminator());
- EXPECT_NE(ContTI, nullptr);
- BasicBlock *EndBB = ContTI->getSuccessor(0);
- EXPECT_TRUE(ContTI->isConditional());
- EXPECT_EQ(ContTI->getSuccessor(1), ContBB);
- EXPECT_NE(EndBB, nullptr);
-
- PHINode *Phi = dyn_cast<PHINode>(&ContBB->front());
- EXPECT_NE(Phi, nullptr);
- EXPECT_EQ(Phi->getNumIncomingValues(), 2U);
- EXPECT_EQ(Phi->getIncomingBlock(0), EntryBB);
- EXPECT_EQ(Phi->getIncomingBlock(1), ContBB);
-
- EXPECT_EQ(Sub->getNumUses(), 1U);
- StoreInst *St = dyn_cast<StoreInst>(Sub->user_back());
- AllocaInst *UpdateTemp = dyn_cast<AllocaInst>(St->getPointerOperand());
-
- ExtractValueInst *ExVI1 =
- dyn_cast<ExtractValueInst>(Phi->getIncomingValueForBlock(ContBB));
- EXPECT_NE(ExVI1, nullptr);
- AtomicCmpXchgInst *CmpExchg =
- dyn_cast<AtomicCmpXchgInst>(ExVI1->getAggregateOperand());
- EXPECT_NE(CmpExchg, nullptr);
- EXPECT_EQ(CmpExchg->getPointerOperand(), XVal);
- EXPECT_EQ(CmpExchg->getCompareOperand(), Phi);
- EXPECT_EQ(CmpExchg->getSuccessOrdering(), AtomicOrdering::Monotonic);
-
- LoadInst *Ld = dyn_cast<LoadInst>(CmpExchg->getNewValOperand());
- EXPECT_NE(Ld, nullptr);
- EXPECT_EQ(UpdateTemp, Ld->getPointerOperand());
+ auto ExitBB = Builder.GetInsertBlock();
Builder.CreateRetVoid();
OMPBuilder.finalize();
EXPECT_FALSE(verifyModule(*M, &errs()));
+
+ {
+ // clang-format off
+ // %AtomicVar.atomic.expected.ptr = alloca i32, align 4
+ // %AtomicVar.atomic.desired.ptr = alloca i32, align 4
+ // %AtomicVar = alloca i32, align 4
+ // store i32 0, ptr %AtomicVar, align 4
+ // %.atomic.load = load atomic i32, ptr %AtomicVar monotonic, align 4
+ // store i32 %.atomic.load, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // br label %.atomic.retry
+ //
+ // .atomic.retry: ; preds = %.atomic.retry, %1
+ // %AtomicVar.atomic.orig = load i32, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // %2 = sub i32 1, %AtomicVar.atomic.orig
+ // store i32 %2, ptr %AtomicVar.atomic.desired.ptr, align 4
+ // %.cmpxchg.expected = load i32, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // %.cmpxchg.desired = load i32, ptr %AtomicVar.atomic.desired.ptr, align 4
+ // %.cmpxchg.pair = cmpxchg weak ptr %AtomicVar, i32 %.cmpxchg.expected, i32 %.cmpxchg.desired monotonic monotonic, align 4
+ // %.cmpxchg.prev = extractvalue { i32, i1 } %.cmpxchg.pair, 0
+ // store i32 %.cmpxchg.prev, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // %.cmpxchg.success = extractvalue { i32, i1 } %.cmpxchg.pair, 1
+ // br i1 %.cmpxchg.success, label %.atomic.done, label %.atomic.retry
+ //
+ // .atomic.done: ; preds = %.atomic.retry
+ // ret void
+ // clang-format on
+
+ // Discover control flow graph
+ BranchInst *Branch1 = cast<BranchInst>(EntryBB->getTerminator());
+ BasicBlock *AtomicRetry = cast<BasicBlock>(EntryBB->getUniqueSuccessor());
+ BranchInst *Branch2 = cast<BranchInst>(AtomicRetry->getTerminator());
+ ReturnInst *Return = cast<ReturnInst>(ExitBB->getTerminator());
+
+ // Follow use-def chains to discover instructions
+ ExtractValueInst *CmpxchgSuccess =
+ cast<ExtractValueInst>(Branch2->getOperand(0));
+ AtomicCmpXchgInst *CmpxchgPair =
+ cast<AtomicCmpXchgInst>(CmpxchgSuccess->getOperand(0));
+ LoadInst *CmpxchgDesired = cast<LoadInst>(CmpxchgPair->getNewValOperand());
+ AllocaInst *AtomicvarAtomicDesiredPtr =
+ cast<AllocaInst>(CmpxchgDesired->getPointerOperand());
+ LoadInst *CmpxchgExpected =
+ cast<LoadInst>(CmpxchgPair->getCompareOperand());
+ AllocaInst *AtomicvarAtomicExpectedPtr =
+ cast<AllocaInst>(CmpxchgExpected->getPointerOperand());
+ StoreInst *Store1 = cast<StoreInst>(
+ getUniquePreviousStore(AtomicvarAtomicDesiredPtr, CmpxchgDesired));
+ BinaryOperator *BO = cast<BinaryOperator>(Store1->getValueOperand());
+ LoadInst *AtomicvarAtomicOrig = cast<LoadInst>(BO->getOperand(1));
+ StoreInst *Store2 = cast<StoreInst>(
+ getUniquePreviousStore(AtomicvarAtomicExpectedPtr, CmpxchgExpected));
+ LoadInst *AtomicLoad = cast<LoadInst>(Store2->getValueOperand());
+ StoreInst *Store3 =
+ cast<StoreInst>(getUniquePreviousStore(XVal, AtomicLoad));
+
+ // %AtomicVar.atomic.expected.ptr = alloca i32, align 4
+ EXPECT_EQ(AtomicvarAtomicExpectedPtr->getParent(), EntryBB);
+ EXPECT_FALSE(AtomicvarAtomicExpectedPtr->isArrayAllocation());
+ EXPECT_EQ(AtomicvarAtomicExpectedPtr->getAddressSpace(), 0);
+ EXPECT_EQ(AtomicvarAtomicExpectedPtr->getAlign(), 4);
+ Type *AtomicvarAtomicExpectedPtrTy =
+ AtomicvarAtomicExpectedPtr->getAllocatedType();
+ EXPECT_TRUE(AtomicvarAtomicExpectedPtrTy->isIntegerTy());
+ EXPECT_EQ(AtomicvarAtomicExpectedPtrTy->getIntegerBitWidth(), 32);
+
+ // %AtomicVar.atomic.desired.ptr = alloca i32, align 4
+ EXPECT_EQ(AtomicvarAtomicDesiredPtr->getParent(), EntryBB);
+ EXPECT_FALSE(AtomicvarAtomicDesiredPtr->isArrayAllocation());
+ EXPECT_EQ(AtomicvarAtomicDesiredPtr->getAddressSpace(), 0);
+ EXPECT_EQ(AtomicvarAtomicDesiredPtr->getAlign(), 4);
+ Type *AtomicvarAtomicDesiredPtrTy =
+ AtomicvarAtomicDesiredPtr->getAllocatedType();
+ EXPECT_TRUE(AtomicvarAtomicDesiredPtrTy->isIntegerTy());
+ EXPECT_EQ(AtomicvarAtomicDesiredPtrTy->getIntegerBitWidth(), 32);
+
+ // %AtomicVar = alloca i32, align 4
+ EXPECT_EQ(XVal->getParent(), EntryBB);
+ EXPECT_FALSE(XVal->isArrayAllocation());
+ EXPECT_EQ(XVal->getAddressSpace(), 0);
+ EXPECT_EQ(XVal->getAlign(), 4);
+ Type *XValTy = XVal->getAllocatedType();
+ EXPECT_TRUE(XValTy->isIntegerTy());
+ EXPECT_EQ(XValTy->getIntegerBitWidth(), 32);
+
+ // store i32 0, ptr %AtomicVar, align 4
+ EXPECT_EQ(Store3->getParent(), EntryBB);
+ EXPECT_TRUE(Store3->isSimple());
+ EXPECT_EQ(cast<ConstantInt>(Store3->getValueOperand())->getZExtValue(), 0);
+ EXPECT_EQ(Store3->getPointerOperand(), XVal);
+
+ // %.atomic.load = load atomic i32, ptr %AtomicVar monotonic, align 4
+ EXPECT_EQ(AtomicLoad->getParent(), EntryBB);
+ EXPECT_FALSE(AtomicLoad->isVolatile());
+ EXPECT_EQ(AtomicLoad->getAlign(), 4);
+ EXPECT_EQ(AtomicLoad->getOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(AtomicLoad->getSyncScopeID(), SyncScope::System);
+ EXPECT_EQ(AtomicLoad->getPointerOperand(), XVal);
+
+ // store i32 %.atomic.load, ptr %AtomicVar.atomic.expected.ptr, align 4
+ EXPECT_EQ(Store2->getParent(), EntryBB);
+ EXPECT_TRUE(Store2->isSimple());
+ EXPECT_EQ(Store2->getValueOperand(), AtomicLoad);
+ EXPECT_EQ(Store2->getPointerOperand(), AtomicvarAtomicExpectedPtr);
+
+ // br label %.atomic.retry
+ EXPECT_EQ(Branch1->getParent(), EntryBB);
+ EXPECT_TRUE(Branch1->isUnconditional());
+
+ // %AtomicVar.atomic.orig = load i32, ptr %AtomicVar.atomic.expected.ptr,
+ // align 4
+ EXPECT_EQ(AtomicvarAtomicOrig->getParent(), AtomicRetry);
+ EXPECT_TRUE(AtomicvarAtomicOrig->isSimple());
+ EXPECT_EQ(AtomicvarAtomicOrig->getPointerOperand(),
+ AtomicvarAtomicExpectedPtr);
+
+ // %2 = sub i32 1, %AtomicVar.atomic.orig
+ EXPECT_EQ(BO->getParent(), AtomicRetry);
+ EXPECT_EQ(cast<ConstantInt>(BO->getOperand(0))->getZExtValue(), 1);
+ EXPECT_EQ(BO->getOperand(1), AtomicvarAtomicOrig);
+
+ // store i32 %2, ptr %AtomicVar.atomic.desired.ptr, align 4
+ EXPECT_EQ(Store1->getParent(), AtomicRetry);
+ EXPECT_TRUE(Store1->isSimple());
+ EXPECT_EQ(Store1->getValueOperand(), BO);
+ EXPECT_EQ(Store1->getPointerOperand(), AtomicvarAtomicDesiredPtr);
+
+ // %.cmpxchg.expected = load i32, ptr %AtomicVar.atomic.expected.ptr, align
+ // 4
+ EXPECT_EQ(CmpxchgExpected->getParent(), AtomicRetry);
+ EXPECT_TRUE(CmpxchgExpected->isSimple());
+ EXPECT_EQ(CmpxchgExpected->getPointerOperand(), AtomicvarAtomicExpectedPtr);
+
+ // %.cmpxchg.desired = load i32, ptr %AtomicVar.atomic.desired.ptr, align 4
+ EXPECT_EQ(CmpxchgDesired->getParent(), AtomicRetry);
+ EXPECT_TRUE(CmpxchgDesired->isSimple());
+ EXPECT_EQ(CmpxchgDesired->getPointerOperand(), AtomicvarAtomicDesiredPtr);
+
+ // %.cmpxchg.pair = cmpxchg weak ptr %AtomicVar, i32 %.cmpxchg.expected, i32
+ // %.cmpxchg.desired monotonic monotonic, align 4
+ EXPECT_EQ(CmpxchgPair->getParent(), AtomicRetry);
+ EXPECT_FALSE(CmpxchgPair->isVolatile());
+ EXPECT_TRUE(CmpxchgPair->isWeak());
+ EXPECT_EQ(CmpxchgPair->getSuccessOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(CmpxchgPair->getFailureOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(CmpxchgPair->getSyncScopeID(), SyncScope::System);
+ EXPECT_EQ(CmpxchgPair->getAlign(), 4);
+ EXPECT_EQ(CmpxchgPair->getPointerOperand(), XVal);
+ EXPECT_EQ(CmpxchgPair->getCompareOperand(), CmpxchgExpected);
+ EXPECT_EQ(CmpxchgPair->getNewValOperand(), CmpxchgDesired);
+
+ // %.cmpxchg.success = extractvalue { i32, i1 } %.cmpxchg.pair, 1
+ EXPECT_EQ(CmpxchgSuccess->getParent(), AtomicRetry);
+ EXPECT_EQ(CmpxchgSuccess->getOperand(0), CmpxchgPair);
+
+ // br i1 %.cmpxchg.success, label %.atomic.done, label %.atomic.retry
+ EXPECT_EQ(Branch2->getParent(), AtomicRetry);
+ EXPECT_TRUE(Branch2->isConditional());
+ EXPECT_EQ(Branch2->getOperand(0), CmpxchgSuccess);
+
+ // ret void
+ EXPECT_EQ(Return->getParent(), ExitBB);
+ }
}
TEST_F(OpenMPIRBuilderTest, OMPAtomicUpdateFloat) {
@@ -4016,7 +4344,8 @@ TEST_F(OpenMPIRBuilderTest, OMPAtomicUpdateFloat) {
Type *FloatTy = Type::getFloatTy(M->getContext());
AllocaInst *XVal = Builder.CreateAlloca(FloatTy);
XVal->setName("AtomicVar");
- Builder.CreateStore(ConstantFP::get(Type::getFloatTy(Ctx), 0.0), XVal);
+ Constant *ExpectedVal = ConstantFP::get(Type::getFloatTy(Ctx), 0.0);
+ Builder.CreateStore(ExpectedVal, XVal);
OpenMPIRBuilder::AtomicOpValue X = {XVal, FloatTy, false, false};
AtomicOrdering AO = AtomicOrdering::Monotonic;
Constant *ConstVal = ConstantFP::get(Type::getFloatTy(Ctx), 1.0);
@@ -4038,40 +4367,171 @@ TEST_F(OpenMPIRBuilderTest, OMPAtomicUpdateFloat) {
AO, RMWOp, UpdateOp,
IsXLHSInRHSPart));
Builder.restoreIP(AfterIP);
- BasicBlock *ContBB = EntryBB->getSingleSuccessor();
- BranchInst *ContTI = dyn_cast<BranchInst>(ContBB->getTerminator());
- EXPECT_NE(ContTI, nullptr);
- BasicBlock *EndBB = ContTI->getSuccessor(0);
- EXPECT_TRUE(ContTI->isConditional());
- EXPECT_EQ(ContTI->getSuccessor(1), ContBB);
- EXPECT_NE(EndBB, nullptr);
-
- PHINode *Phi = dyn_cast<PHINode>(&ContBB->front());
- EXPECT_NE(Phi, nullptr);
- EXPECT_EQ(Phi->getNumIncomingValues(), 2U);
- EXPECT_EQ(Phi->getIncomingBlock(0), EntryBB);
- EXPECT_EQ(Phi->getIncomingBlock(1), ContBB);
-
- EXPECT_EQ(Sub->getNumUses(), 1U);
- StoreInst *St = dyn_cast<StoreInst>(Sub->user_back());
- AllocaInst *UpdateTemp = dyn_cast<AllocaInst>(St->getPointerOperand());
-
- ExtractValueInst *ExVI1 =
- dyn_cast<ExtractValueInst>(Phi->getIncomingValueForBlock(ContBB));
- EXPECT_NE(ExVI1, nullptr);
- AtomicCmpXchgInst *CmpExchg =
- dyn_cast<AtomicCmpXchgInst>(ExVI1->getAggregateOperand());
- EXPECT_NE(CmpExchg, nullptr);
- EXPECT_EQ(CmpExchg->getPointerOperand(), XVal);
- EXPECT_EQ(CmpExchg->getCompareOperand(), Phi);
- EXPECT_EQ(CmpExchg->getSuccessOrdering(), AtomicOrdering::Monotonic);
-
- LoadInst *Ld = dyn_cast<LoadInst>(CmpExchg->getNewValOperand());
- EXPECT_NE(Ld, nullptr);
- EXPECT_EQ(UpdateTemp, Ld->getPointerOperand());
+ BasicBlock *ExitBB = Builder.GetInsertBlock();
+
Builder.CreateRetVoid();
OMPBuilder.finalize();
EXPECT_FALSE(verifyModule(*M, &errs()));
+
+ {
+ // clang-format off
+ // %AtomicVar.atomic.expected.ptr = alloca float, align 4
+ // %AtomicVar.atomic.desired.ptr = alloca float, align 4
+ // %AtomicVar = alloca float, align 4
+ // store float 0.000000e+00, ptr %AtomicVar, align 4
+ // %.atomic.load = load atomic float, ptr %AtomicVar monotonic, align 4
+ // store float %.atomic.load, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // br label %.atomic.retry
+ //
+ // .atomic.retry: ; preds = %.atomic.retry, %1
+ // %AtomicVar.atomic.orig = load float, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // %2 = fsub float 1.000000e+00, %AtomicVar.atomic.orig
+ // store float %2, ptr %AtomicVar.atomic.desired.ptr, align 4
+ // %.cmpxchg.expected = load i32, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // %.cmpxchg.desired = load i32, ptr %AtomicVar.atomic.desired.ptr, align 4
+ // %.cmpxchg.pair = cmpxchg weak ptr %AtomicVar, i32 %.cmpxchg.expected, i32 %.cmpxchg.desired monotonic monotonic, align 4
+ // %.cmpxchg.prev = extractvalue { i32, i1 } %.cmpxchg.pair, 0
+ // store i32 %.cmpxchg.prev, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // %.cmpxchg.success = extractvalue { i32, i1 } %.cmpxchg.pair, 1
+ // br i1 %.cmpxchg.success, label %.atomic.done, label %.atomic.retry
+ //
+ // .atomic.done: ; preds = %.atomic.retry
+ // ret void
+ // clang-format on
+
+ // Discover control flow graph
+ BranchInst *Branch1 = cast<BranchInst>(EntryBB->getTerminator());
+ BasicBlock *AtomicRetry = cast<BasicBlock>(EntryBB->getUniqueSuccessor());
+ BranchInst *Branch2 = cast<BranchInst>(AtomicRetry->getTerminator());
+ ReturnInst *Return = cast<ReturnInst>(ExitBB->getTerminator());
+
+ // Follow use-def chains to discover instructions
+ ExtractValueInst *CmpxchgSuccess =
+ cast<ExtractValueInst>(Branch2->getOperand(0));
+ AtomicCmpXchgInst *CmpxchgPair =
+ cast<AtomicCmpXchgInst>(CmpxchgSuccess->getOperand(0));
+ LoadInst *CmpxchgDesired = cast<LoadInst>(CmpxchgPair->getNewValOperand());
+ AllocaInst *AtomicvarAtomicDesiredPtr =
+ cast<AllocaInst>(CmpxchgDesired->getPointerOperand());
+ LoadInst *CmpxchgExpected =
+ cast<LoadInst>(CmpxchgPair->getCompareOperand());
+ AllocaInst *AtomicvarAtomicExpectedPtr =
+ cast<AllocaInst>(CmpxchgExpected->getPointerOperand());
+ StoreInst *Store1 = cast<StoreInst>(
+ getUniquePreviousStore(AtomicvarAtomicDesiredPtr, CmpxchgDesired));
+ BinaryOperator *BO = cast<BinaryOperator>(Store1->getValueOperand());
+ LoadInst *AtomicvarAtomicOrig = cast<LoadInst>(BO->getOperand(1));
+ StoreInst *Store2 = cast<StoreInst>(
+ getUniquePreviousStore(AtomicvarAtomicExpectedPtr, CmpxchgExpected));
+ LoadInst *AtomicLoad = cast<LoadInst>(Store2->getValueOperand());
+ StoreInst *Store3 =
+ cast<StoreInst>(getUniquePreviousStore(XVal, AtomicLoad));
+
+ // %AtomicVar.atomic.expected.ptr = alloca float, align 4
+ EXPECT_EQ(AtomicvarAtomicExpectedPtr->getParent(), EntryBB);
+ EXPECT_FALSE(AtomicvarAtomicExpectedPtr->isArrayAllocation());
+ EXPECT_EQ(AtomicvarAtomicExpectedPtr->getAddressSpace(), 0);
+ EXPECT_EQ(AtomicvarAtomicExpectedPtr->getAlign(), 4);
+ EXPECT_TRUE(AtomicvarAtomicExpectedPtr->getAllocatedType()->isFloatTy());
+
+ // %AtomicVar.atomic.desired.ptr = alloca float, align 4
+ EXPECT_EQ(AtomicvarAtomicDesiredPtr->getParent(), EntryBB);
+ EXPECT_FALSE(AtomicvarAtomicDesiredPtr->isArrayAllocation());
+ EXPECT_EQ(AtomicvarAtomicDesiredPtr->getAddressSpace(), 0);
+ EXPECT_EQ(AtomicvarAtomicDesiredPtr->getAlign(), 4);
+ EXPECT_TRUE(AtomicvarAtomicDesiredPtr->getAllocatedType()->isFloatTy());
+
+ // %AtomicVar = alloca float, align 4
+ EXPECT_EQ(XVal->getParent(), EntryBB);
+ EXPECT_FALSE(XVal->isArrayAllocation());
+ EXPECT_EQ(XVal->getAddressSpace(), 0);
+ EXPECT_EQ(XVal->getAlign(), 4);
+ EXPECT_TRUE(XVal->getAllocatedType()->isFloatTy());
+
+ // store float 0.000000e+00, ptr %AtomicVar, align 4
+ EXPECT_EQ(Store3->getParent(), EntryBB);
+ EXPECT_TRUE(Store3->isSimple());
+ EXPECT_FLOAT_EQ(cast<ConstantFP>(Store3->getValueOperand())
+ ->getValueAPF()
+ .convertToFloat(),
+ 0.0f);
+ EXPECT_EQ(Store3->getPointerOperand(), XVal);
+
+ // %.atomic.load = load atomic float, ptr %AtomicVar monotonic, align 4
+ EXPECT_EQ(AtomicLoad->getParent(), EntryBB);
+ EXPECT_FALSE(AtomicLoad->isVolatile());
+ EXPECT_EQ(AtomicLoad->getAlign(), 4);
+ EXPECT_EQ(AtomicLoad->getOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(AtomicLoad->getSyncScopeID(), SyncScope::System);
+ EXPECT_EQ(AtomicLoad->getPointerOperand(), XVal);
+
+ // store float %.atomic.load, ptr %AtomicVar.atomic.expected.ptr, align 4
+ EXPECT_EQ(Store2->getParent(), EntryBB);
+ EXPECT_TRUE(Store2->isSimple());
+ EXPECT_EQ(Store2->getValueOperand(), AtomicLoad);
+ EXPECT_EQ(Store2->getPointerOperand(), AtomicvarAtomicExpectedPtr);
+
+ // br label %.atomic.retry
+ EXPECT_EQ(Branch1->getParent(), EntryBB);
+ EXPECT_TRUE(Branch1->isUnconditional());
+
+ // %AtomicVar.atomic.orig = load float, ptr
+ // %AtomicVar.atomic.expected.ptr, align 4
+ EXPECT_EQ(AtomicvarAtomicOrig->getParent(), AtomicRetry);
+ EXPECT_TRUE(AtomicvarAtomicOrig->isSimple());
+ EXPECT_EQ(AtomicvarAtomicOrig->getPointerOperand(),
+ AtomicvarAtomicExpectedPtr);
+
+ // %2 = fsub float 1.000000e+00, %AtomicVar.atomic.orig
+ EXPECT_EQ(BO->getParent(), AtomicRetry);
+ EXPECT_FLOAT_EQ(
+ cast<ConstantFP>(BO->getOperand(0))->getValueAPF().convertToFloat(),
+ 1.0f);
+ EXPECT_EQ(BO->getOperand(1), AtomicvarAtomicOrig);
+
+ // store float %2, ptr %AtomicVar.atomic.desired.ptr, align 4
+ EXPECT_EQ(Store1->getParent(), AtomicRetry);
+ EXPECT_TRUE(Store1->isSimple());
+ EXPECT_EQ(Store1->getValueOperand(), BO);
+ EXPECT_EQ(Store1->getPointerOperand(), AtomicvarAtomicDesiredPtr);
+
+ // %.cmpxchg.expected = load i32, ptr %AtomicVar.atomic.expected.ptr,
+ // align 4
+ EXPECT_EQ(CmpxchgExpected->getParent(), AtomicRetry);
+ EXPECT_TRUE(CmpxchgExpected->isSimple());
+ EXPECT_EQ(CmpxchgExpected->getPointerOperand(), AtomicvarAtomicExpectedPtr);
+
+ // %.cmpxchg.desired = load i32, ptr %AtomicVar.atomic.desired.ptr, align
+ // 4
+ EXPECT_EQ(CmpxchgDesired->getParent(), AtomicRetry);
+ EXPECT_TRUE(CmpxchgDesired->isSimple());
+ EXPECT_EQ(CmpxchgDesired->getPointerOperand(), AtomicvarAtomicDesiredPtr);
+
+ // %.cmpxchg.pair = cmpxchg weak ptr %AtomicVar, i32 %.cmpxchg.expected,
+ // i32 %.cmpxchg.desired monotonic monotonic, align 4
+ EXPECT_EQ(CmpxchgPair->getParent(), AtomicRetry);
+ EXPECT_FALSE(CmpxchgPair->isVolatile());
+ EXPECT_TRUE(CmpxchgPair->isWeak());
+ EXPECT_EQ(CmpxchgPair->getSuccessOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(CmpxchgPair->getFailureOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(CmpxchgPair->getSyncScopeID(), SyncScope::System);
+ EXPECT_EQ(CmpxchgPair->getAlign(), 4);
+ EXPECT_EQ(CmpxchgPair->getPointerOperand(), XVal);
+ EXPECT_EQ(CmpxchgPair->getCompareOperand(), CmpxchgExpected);
+ EXPECT_EQ(CmpxchgPair->getNewValOperand(), CmpxchgDesired);
+
+ // %.cmpxchg.success = extractvalue { i32, i1 } %.cmpxchg.pair, 1
+ EXPECT_EQ(CmpxchgSuccess->getParent(), AtomicRetry);
+ EXPECT_EQ(CmpxchgSuccess->getOperand(0), CmpxchgPair);
+
+ // br i1 %.cmpxchg.success, label %.atomic.done, label %.atomic.retry
+ EXPECT_EQ(Branch2->getParent(), AtomicRetry);
+ EXPECT_TRUE(Branch2->isConditional());
+ EXPECT_EQ(Branch2->getOperand(0), CmpxchgSuccess);
+
+ // ret void
+ EXPECT_EQ(Return->getParent(), ExitBB);
+ }
}
TEST_F(OpenMPIRBuilderTest, OMPAtomicUpdateIntr) {
@@ -4085,7 +4545,8 @@ TEST_F(OpenMPIRBuilderTest, OMPAtomicUpdateIntr) {
Type *IntTy = Type::getInt32Ty(M->getContext());
AllocaInst *XVal = Builder.CreateAlloca(IntTy);
XVal->setName("AtomicVar");
- Builder.CreateStore(ConstantInt::get(Type::getInt32Ty(Ctx), 0), XVal);
+ ConstantInt *ExpectedVal = ConstantInt::get(Type::getInt32Ty(Ctx), 0);
+ Builder.CreateStore(ExpectedVal, XVal);
OpenMPIRBuilder::AtomicOpValue X = {XVal, IntTy, false, false};
AtomicOrdering AO = AtomicOrdering::Monotonic;
Constant *ConstVal = ConstantInt::get(Type::getInt32Ty(Ctx), 1);
@@ -4107,41 +4568,174 @@ TEST_F(OpenMPIRBuilderTest, OMPAtomicUpdateIntr) {
AO, RMWOp, UpdateOp,
IsXLHSInRHSPart));
Builder.restoreIP(AfterIP);
- BasicBlock *ContBB = EntryBB->getSingleSuccessor();
- BranchInst *ContTI = dyn_cast<BranchInst>(ContBB->getTerminator());
- EXPECT_NE(ContTI, nullptr);
- BasicBlock *EndBB = ContTI->getSuccessor(0);
- EXPECT_TRUE(ContTI->isConditional());
- EXPECT_EQ(ContTI->getSuccessor(1), ContBB);
- EXPECT_NE(EndBB, nullptr);
-
- PHINode *Phi = dyn_cast<PHINode>(&ContBB->front());
- EXPECT_NE(Phi, nullptr);
- EXPECT_EQ(Phi->getNumIncomingValues(), 2U);
- EXPECT_EQ(Phi->getIncomingBlock(0), EntryBB);
- EXPECT_EQ(Phi->getIncomingBlock(1), ContBB);
-
- EXPECT_EQ(Sub->getNumUses(), 1U);
- StoreInst *St = dyn_cast<StoreInst>(Sub->user_back());
- AllocaInst *UpdateTemp = dyn_cast<AllocaInst>(St->getPointerOperand());
-
- ExtractValueInst *ExVI1 =
- dyn_cast<ExtractValueInst>(Phi->getIncomingValueForBlock(ContBB));
- EXPECT_NE(ExVI1, nullptr);
- AtomicCmpXchgInst *CmpExchg =
- dyn_cast<AtomicCmpXchgInst>(ExVI1->getAggregateOperand());
- EXPECT_NE(CmpExchg, nullptr);
- EXPECT_EQ(CmpExchg->getPointerOperand(), XVal);
- EXPECT_EQ(CmpExchg->getCompareOperand(), Phi);
- EXPECT_EQ(CmpExchg->getSuccessOrdering(), AtomicOrdering::Monotonic);
-
- LoadInst *Ld = dyn_cast<LoadInst>(CmpExchg->getNewValOperand());
- EXPECT_NE(Ld, nullptr);
- EXPECT_EQ(UpdateTemp, Ld->getPointerOperand());
+ BasicBlock *ExitBB = Builder.GetInsertBlock();
Builder.CreateRetVoid();
OMPBuilder.finalize();
EXPECT_FALSE(verifyModule(*M, &errs()));
+
+ {
+ // clang-format off
+ // %AtomicVar.atomic.expected.ptr = alloca i32, align 4
+ // %AtomicVar.atomic.desired.ptr = alloca i32, align 4
+ // %AtomicVar = alloca i32, align 4
+ // store i32 0, ptr %AtomicVar, align 4
+ // %.atomic.load = load atomic i32, ptr %AtomicVar monotonic, align 4
+ // store i32 %.atomic.load, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // br label %.atomic.retry
+ //
+ // .atomic.retry: ; preds = %.atomic.retry, %1
+ // %AtomicVar.atomic.orig = load i32, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // %2 = sub i32 1, %AtomicVar.atomic.orig
+ // store i32 %2, ptr %AtomicVar.atomic.desired.ptr, align 4
+ // %.cmpxchg.expected = load i32, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // %.cmpxchg.desired = load i32, ptr %AtomicVar.atomic.desired.ptr, align 4
+ // %.cmpxchg.pair = cmpxchg weak ptr %AtomicVar, i32 %.cmpxchg.expected, i32 %.cmpxchg.desired monotonic monotonic, align 4
+ // %.cmpxchg.prev = extractvalue { i32, i1 } %.cmpxchg.pair, 0
+ // store i32 %.cmpxchg.prev, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // %.cmpxchg.success = extractvalue { i32, i1 } %.cmpxchg.pair, 1
+ // br i1 %.cmpxchg.success, label %.atomic.done, label %.atomic.retry
+ //
+ // .atomic.done: ; preds = %.atomic.retry
+ // ret void
+ // clang-format on
+
+ // Discover control flow graph
+ BranchInst *Branch1 = cast<BranchInst>(EntryBB->getTerminator());
+ BasicBlock *AtomicRetry = cast<BasicBlock>(EntryBB->getUniqueSuccessor());
+ BranchInst *Branch2 = cast<BranchInst>(AtomicRetry->getTerminator());
+ ReturnInst *Return = cast<ReturnInst>(ExitBB->getTerminator());
+
+ // Follow use-def chains to discover instructions
+ ExtractValueInst *CmpxchgSuccess =
+ cast<ExtractValueInst>(Branch2->getOperand(0));
+ AtomicCmpXchgInst *CmpxchgPair =
+ cast<AtomicCmpXchgInst>(CmpxchgSuccess->getOperand(0));
+ LoadInst *CmpxchgDesired = cast<LoadInst>(CmpxchgPair->getNewValOperand());
+ AllocaInst *AtomicvarAtomicDesiredPtr =
+ cast<AllocaInst>(CmpxchgDesired->getPointerOperand());
+ LoadInst *CmpxchgExpected =
+ cast<LoadInst>(CmpxchgPair->getCompareOperand());
+ AllocaInst *AtomicvarAtomicExpectedPtr =
+ cast<AllocaInst>(CmpxchgExpected->getPointerOperand());
+ StoreInst *Store1 = cast<StoreInst>(
+ getUniquePreviousStore(AtomicvarAtomicDesiredPtr, CmpxchgDesired));
+ BinaryOperator *BO = cast<BinaryOperator>(Store1->getValueOperand());
+ LoadInst *AtomicvarAtomicOrig = cast<LoadInst>(BO->getOperand(1));
+ StoreInst *Store2 = cast<StoreInst>(
+ getUniquePreviousStore(AtomicvarAtomicExpectedPtr, CmpxchgExpected));
+ LoadInst *AtomicLoad = cast<LoadInst>(Store2->getValueOperand());
+ StoreInst *Store3 =
+ cast<StoreInst>(getUniquePreviousStore(XVal, AtomicLoad));
+
+ // %AtomicVar.atomic.expected.ptr = alloca i32, align 4
+ EXPECT_EQ(AtomicvarAtomicExpectedPtr->getParent(), EntryBB);
+ EXPECT_FALSE(AtomicvarAtomicExpectedPtr->isArrayAllocation());
+ EXPECT_EQ(AtomicvarAtomicExpectedPtr->getAddressSpace(), 0);
+ EXPECT_EQ(AtomicvarAtomicExpectedPtr->getAlign(), 4);
+ Type *AtomicvarAtomicExpectedPtrTy =
+ AtomicvarAtomicExpectedPtr->getAllocatedType();
+ EXPECT_TRUE(AtomicvarAtomicExpectedPtrTy->isIntegerTy());
+ EXPECT_EQ(AtomicvarAtomicExpectedPtrTy->getIntegerBitWidth(), 32);
+
+ // %AtomicVar.atomic.desired.ptr = alloca i32, align 4
+ EXPECT_EQ(AtomicvarAtomicDesiredPtr->getParent(), EntryBB);
+ EXPECT_FALSE(AtomicvarAtomicDesiredPtr->isArrayAllocation());
+ EXPECT_EQ(AtomicvarAtomicDesiredPtr->getAddressSpace(), 0);
+ EXPECT_EQ(AtomicvarAtomicDesiredPtr->getAlign(), 4);
+ Type *AtomicvarAtomicDesiredPtrTy =
+ AtomicvarAtomicDesiredPtr->getAllocatedType();
+ EXPECT_TRUE(AtomicvarAtomicDesiredPtrTy->isIntegerTy());
+ EXPECT_EQ(AtomicvarAtomicDesiredPtrTy->getIntegerBitWidth(), 32);
+
+ // %AtomicVar = alloca i32, align 4
+ EXPECT_EQ(XVal->getParent(), EntryBB);
+ EXPECT_FALSE(XVal->isArrayAllocation());
+ EXPECT_EQ(XVal->getAddressSpace(), 0);
+ EXPECT_EQ(XVal->getAlign(), 4);
+ Type *XValTy = XVal->getAllocatedType();
+ EXPECT_TRUE(XValTy->isIntegerTy());
+ EXPECT_EQ(XValTy->getIntegerBitWidth(), 32);
+
+ // store i32 0, ptr %AtomicVar, align 4
+ EXPECT_EQ(Store3->getParent(), EntryBB);
+ EXPECT_TRUE(Store3->isSimple());
+ EXPECT_EQ(cast<ConstantInt>(Store3->getValueOperand())->getZExtValue(), 0);
+ EXPECT_EQ(Store3->getPointerOperand(), XVal);
+
+ // %.atomic.load = load atomic i32, ptr %AtomicVar monotonic, align 4
+ EXPECT_EQ(AtomicLoad->getParent(), EntryBB);
+ EXPECT_FALSE(AtomicLoad->isVolatile());
+ EXPECT_EQ(AtomicLoad->getAlign(), 4);
+ EXPECT_EQ(AtomicLoad->getOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(AtomicLoad->getSyncScopeID(), SyncScope::System);
+ EXPECT_EQ(AtomicLoad->getPointerOperand(), XVal);
+
+ // store i32 %.atomic.load, ptr %AtomicVar.atomic.expected.ptr, align 4
+ EXPECT_EQ(Store2->getParent(), EntryBB);
+ EXPECT_TRUE(Store2->isSimple());
+ EXPECT_EQ(Store2->getValueOperand(), AtomicLoad);
+ EXPECT_EQ(Store2->getPointerOperand(), AtomicvarAtomicExpectedPtr);
+
+ // br label %.atomic.retry
+ EXPECT_EQ(Branch1->getParent(), EntryBB);
+ EXPECT_TRUE(Branch1->isUnconditional());
+
+ // %AtomicVar.atomic.orig = load i32, ptr
+ // %AtomicVar.atomic.expected.ptr, align 4
+ EXPECT_EQ(AtomicvarAtomicOrig->getParent(), AtomicRetry);
+ EXPECT_TRUE(AtomicvarAtomicOrig->isSimple());
+ EXPECT_EQ(AtomicvarAtomicOrig->getPointerOperand(),
+ AtomicvarAtomicExpectedPtr);
+
+ // %2 = sub i32 1, %AtomicVar.atomic.orig
+ EXPECT_EQ(BO->getParent(), AtomicRetry);
+ EXPECT_EQ(cast<ConstantInt>(BO->getOperand(0))->getZExtValue(), 1);
+ EXPECT_EQ(BO->getOperand(1), AtomicvarAtomicOrig);
+
+ // store i32 %2, ptr %AtomicVar.atomic.desired.ptr, align 4
+ EXPECT_EQ(Store1->getParent(), AtomicRetry);
+ EXPECT_TRUE(Store1->isSimple());
+ EXPECT_EQ(Store1->getValueOperand(), BO);
+ EXPECT_EQ(Store1->getPointerOperand(), AtomicvarAtomicDesiredPtr);
+
+ // %.cmpxchg.expected = load i32, ptr %AtomicVar.atomic.expected.ptr,
+ // align 4
+ EXPECT_EQ(CmpxchgExpected->getParent(), AtomicRetry);
+ EXPECT_TRUE(CmpxchgExpected->isSimple());
+ EXPECT_EQ(CmpxchgExpected->getPointerOperand(), AtomicvarAtomicExpectedPtr);
+
+ // %.cmpxchg.desired = load i32, ptr %AtomicVar.atomic.desired.ptr,
+ // align 4
+ EXPECT_EQ(CmpxchgDesired->getParent(), AtomicRetry);
+ EXPECT_TRUE(CmpxchgDesired->isSimple());
+ EXPECT_EQ(CmpxchgDesired->getPointerOperand(), AtomicvarAtomicDesiredPtr);
+
+ // %.cmpxchg.pair = cmpxchg weak ptr %AtomicVar, i32 %.cmpxchg.expected,
+ // i32 %.cmpxchg.desired monotonic monotonic, align 4
+ EXPECT_EQ(CmpxchgPair->getParent(), AtomicRetry);
+ EXPECT_FALSE(CmpxchgPair->isVolatile());
+ EXPECT_TRUE(CmpxchgPair->isWeak());
+ EXPECT_EQ(CmpxchgPair->getSuccessOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(CmpxchgPair->getFailureOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(CmpxchgPair->getSyncScopeID(), SyncScope::System);
+ EXPECT_EQ(CmpxchgPair->getAlign(), 4);
+ EXPECT_EQ(CmpxchgPair->getPointerOperand(), XVal);
+ EXPECT_EQ(CmpxchgPair->getCompareOperand(), CmpxchgExpected);
+ EXPECT_EQ(CmpxchgPair->getNewValOperand(), CmpxchgDesired);
+
+ // %.cmpxchg.success = extractvalue { i32, i1 } %.cmpxchg.pair, 1
+ EXPECT_EQ(CmpxchgSuccess->getParent(), AtomicRetry);
+ EXPECT_EQ(CmpxchgSuccess->getOperand(0), CmpxchgPair);
+
+ // br i1 %.cmpxchg.success, label %.atomic.done, label %.atomic.retry
+ EXPECT_EQ(Branch2->getParent(), AtomicRetry);
+ EXPECT_TRUE(Branch2->isConditional());
+ EXPECT_EQ(Branch2->getOperand(0), CmpxchgSuccess);
+
+ // ret void
+ EXPECT_EQ(Return->getParent(), ExitBB);
+ }
}
TEST_F(OpenMPIRBuilderTest, OMPAtomicCapture) {
@@ -4207,9 +4801,10 @@ TEST_F(OpenMPIRBuilderTest, OMPAtomicCompare) {
LLVMContext &Ctx = M->getContext();
IntegerType *Int32 = Type::getInt32Ty(Ctx);
AllocaInst *XVal = Builder.CreateAlloca(Int32);
+ IRBuilder<>::InsertPoint AllocaIP(&F->getEntryBlock(),
+ F->getEntryBlock().getFirstInsertionPt());
XVal->setName("x");
- StoreInst *Init =
- Builder.CreateStore(ConstantInt::get(Type::getInt32Ty(Ctx), 0U), XVal);
+ Builder.CreateStore(ConstantInt::get(Type::getInt32Ty(Ctx), 0U), XVal);
OpenMPIRBuilder::AtomicOpValue XSigned = {XVal, Int32, true, false};
OpenMPIRBuilder::AtomicOpValue XUnsigned = {XVal, Int32, false, false};
@@ -4222,38 +4817,116 @@ TEST_F(OpenMPIRBuilderTest, OMPAtomicCompare) {
OMPAtomicCompareOp OpMax = OMPAtomicCompareOp::MAX;
OMPAtomicCompareOp OpEQ = OMPAtomicCompareOp::EQ;
- Builder.restoreIP(OMPBuilder.createAtomicCompare(
- Builder, XSigned, V, R, Expr, nullptr, AO, OpMax, true, false, false));
- Builder.restoreIP(OMPBuilder.createAtomicCompare(
- Builder, XUnsigned, V, R, Expr, nullptr, AO, OpMax, false, false, false));
- Builder.restoreIP(OMPBuilder.createAtomicCompare(
- Builder, XSigned, V, R, Expr, D, AO, OpEQ, true, false, false));
+ BasicBlock *BB1 = splitBB(Builder, true);
+ Builder.SetInsertPoint(BB1, BB1->begin());
+ ASSERT_EXPECTED_INIT(
+ OpenMPIRBuilder::InsertPointTy, AfterIP1,
+ OMPBuilder.createAtomicCompare(Builder, AllocaIP, XSigned, V, R, Expr,
+ nullptr, AO, OpMax, true, false, false));
+ Builder.restoreIP(AfterIP1);
+
+ BasicBlock *BB2 = splitBB(Builder, true);
+ Builder.SetInsertPoint(BB2, BB2->begin());
+ ASSERT_EXPECTED_INIT(
+ OpenMPIRBuilder::InsertPointTy, AfterIP2,
+ OMPBuilder.createAtomicCompare(Builder, AllocaIP, XUnsigned, V, R, Expr,
+ nullptr, AO, OpMax, false, false, false));
+ Builder.restoreIP(AfterIP2);
+
+ BasicBlock *BB3 = splitBB(Builder, true);
+ Builder.SetInsertPoint(BB3, BB3->begin());
+ ASSERT_EXPECTED_INIT(
+ OpenMPIRBuilder::InsertPointTy, AfterIP3,
+ OMPBuilder.createAtomicCompare(Builder, AllocaIP, XSigned, V, R, Expr, D,
+ AO, OpEQ, true, false, false));
+ Builder.restoreIP(AfterIP3);
BasicBlock *EntryBB = BB;
- EXPECT_EQ(EntryBB->getParent()->size(), 1U);
- EXPECT_EQ(EntryBB->size(), 5U);
-
- AtomicRMWInst *ARWM1 = dyn_cast<AtomicRMWInst>(Init->getNextNode());
- EXPECT_NE(ARWM1, nullptr);
- EXPECT_EQ(ARWM1->getPointerOperand(), XVal);
- EXPECT_EQ(ARWM1->getValOperand(), Expr);
- EXPECT_EQ(ARWM1->getOperation(), AtomicRMWInst::Min);
-
- AtomicRMWInst *ARWM2 = dyn_cast<AtomicRMWInst>(ARWM1->getNextNode());
- EXPECT_NE(ARWM2, nullptr);
- EXPECT_EQ(ARWM2->getPointerOperand(), XVal);
- EXPECT_EQ(ARWM2->getValOperand(), Expr);
- EXPECT_EQ(ARWM2->getOperation(), AtomicRMWInst::UMax);
-
- AtomicCmpXchgInst *AXCHG = dyn_cast<AtomicCmpXchgInst>(ARWM2->getNextNode());
- EXPECT_NE(AXCHG, nullptr);
- EXPECT_EQ(AXCHG->getPointerOperand(), XVal);
- EXPECT_EQ(AXCHG->getCompareOperand(), Expr);
- EXPECT_EQ(AXCHG->getNewValOperand(), D);
+ EXPECT_EQ(EntryBB->getParent()->size(), 4U);
+ EXPECT_EQ(EntryBB->size(), 6U);
Builder.CreateRetVoid();
OMPBuilder.finalize();
EXPECT_FALSE(verifyModule(*M, &errs()));
+
+ {
+ // Follow use-def and load-store chains to discover instructions
+ AtomicRMWInst *AtomicRMW =
+ cast<AtomicRMWInst>(getUniquePreviousStore(XVal, BB1));
+
+ // %3 = atomicrmw min ptr %x, i32 1 monotonic, align 4
+ EXPECT_EQ(AtomicRMW->getParent(), BB1);
+ EXPECT_EQ(AtomicRMW->getOperation(), AtomicRMWInst::Min);
+ EXPECT_FALSE(AtomicRMW->isVolatile());
+ EXPECT_EQ(AtomicRMW->getOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(AtomicRMW->getSyncScopeID(), SyncScope::System);
+ EXPECT_EQ(AtomicRMW->getAlign(), 4);
+ EXPECT_EQ(AtomicRMW->getPointerOperand(), XVal);
+ EXPECT_EQ(cast<ConstantInt>(AtomicRMW->getValOperand())->getZExtValue(), 1);
+ }
+
+ {
+ // clang-format off
+ // store i32 1, ptr %x.atomic.expected.ptr, align 4
+ // store i32 1, ptr %x.atomic.desired.ptr, align 4
+ // %.cmpxchg.expected = load i32, ptr %x.atomic.expected.ptr, align 4
+ // %.cmpxchg.desired = load i32, ptr %x.atomic.desired.ptr, align 4
+ // %.cmpxchg.pair = cmpxchg ptr %x, i32 %.cmpxchg.expected, i32 %.cmpxchg.desired monotonic monotonic, align 4
+ // %.cmpxchg.prev = extractvalue { i32, i1 } %.cmpxchg.pair, 0
+ // store i32 %.cmpxchg.prev, ptr %x.atomic.expected.ptr1, align 4
+ // %.cmpxchg.success = extractvalue { i32, i1 } %.cmpxchg.pair, 1
+ // clang-format on
+
+ // Follow use-def and load-store chains to discover instructions
+ AtomicCmpXchgInst *CmpxchgPair =
+ cast<AtomicCmpXchgInst>(getUniquePreviousStore(XVal, BB3));
+ LoadInst *CmpxchgDesired = cast<LoadInst>(CmpxchgPair->getNewValOperand());
+ AllocaInst *XAtomicDesiredPtr =
+ cast<AllocaInst>(CmpxchgDesired->getPointerOperand());
+ LoadInst *CmpxchgExpected =
+ cast<LoadInst>(CmpxchgPair->getCompareOperand());
+ AllocaInst *XAtomicExpectedPtr =
+ cast<AllocaInst>(CmpxchgExpected->getPointerOperand());
+ StoreInst *Store1 = cast<StoreInst>(
+ getUniquePreviousStore(XAtomicDesiredPtr, CmpxchgDesired));
+ StoreInst *Store2 = cast<StoreInst>(
+ getUniquePreviousStore(XAtomicExpectedPtr, CmpxchgExpected));
+
+ // store i32 1, ptr %x.atomic.expected.ptr, align 4
+ EXPECT_EQ(Store2->getParent(), BB3);
+ EXPECT_TRUE(Store2->isSimple());
+ EXPECT_EQ(cast<ConstantInt>(Store2->getValueOperand())->getZExtValue(), 1);
+ EXPECT_EQ(Store2->getPointerOperand(), XAtomicExpectedPtr);
+
+ // store i32 1, ptr %x.atomic.desired.ptr, align 4
+ EXPECT_EQ(Store1->getParent(), BB3);
+ EXPECT_TRUE(Store1->isSimple());
+ EXPECT_EQ(cast<ConstantInt>(Store1->getValueOperand())->getZExtValue(), 1);
+ EXPECT_EQ(Store1->getPointerOperand(), XAtomicDesiredPtr);
+
+ // %.cmpxchg.expected = load i32, ptr %x.atomic.expected.ptr, align 4
+ EXPECT_EQ(CmpxchgExpected->getParent(), BB3);
+ EXPECT_TRUE(CmpxchgExpected->isSimple());
+ EXPECT_EQ(CmpxchgExpected->getPointerOperand(), XAtomicExpectedPtr);
+
+ // %.cmpxchg.desired = load i32, ptr %x.atomic.desired.ptr, align 4
+ EXPECT_EQ(CmpxchgDesired->getParent(), BB3);
+ EXPECT_TRUE(CmpxchgDesired->isSimple());
+ EXPECT_EQ(CmpxchgDesired->getPointerOperand(), XAtomicDesiredPtr);
+
+ // %.cmpxchg.pair = cmpxchg ptr %x, i32 %.cmpxchg.expected, i32
+ // %.cmpxchg.desired monotonic monotonic, align 4
+ EXPECT_EQ(CmpxchgPair->getParent(), BB3);
+ EXPECT_FALSE(CmpxchgPair->isVolatile());
+ EXPECT_FALSE(CmpxchgPair->isWeak());
+ EXPECT_EQ(CmpxchgPair->getSuccessOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(CmpxchgPair->getFailureOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(CmpxchgPair->getSyncScopeID(), SyncScope::System);
+ EXPECT_EQ(CmpxchgPair->getAlign(), 4);
+ EXPECT_EQ(CmpxchgPair->getPointerOperand(), XVal);
+ EXPECT_EQ(CmpxchgPair->getCompareOperand(), CmpxchgExpected);
+ EXPECT_EQ(CmpxchgPair->getNewValOperand(), CmpxchgDesired);
+ }
}
TEST_F(OpenMPIRBuilderTest, OMPAtomicCompareCapture) {
@@ -4262,8 +4935,6 @@ TEST_F(OpenMPIRBuilderTest, OMPAtomicCompareCapture) {
F->setName("func");
IRBuilder<> Builder(BB);
- OpenMPIRBuilder::LocationDescription Loc({Builder.saveIP(), DL});
-
LLVMContext &Ctx = M->getContext();
IntegerType *Int32 = Type::getInt32Ty(Ctx);
AllocaInst *XVal = Builder.CreateAlloca(Int32);
@@ -4288,223 +4959,329 @@ TEST_F(OpenMPIRBuilderTest, OMPAtomicCompareCapture) {
OMPAtomicCompareOp OpMax = OMPAtomicCompareOp::MAX;
OMPAtomicCompareOp OpEQ = OMPAtomicCompareOp::EQ;
+ IRBuilder<>::InsertPoint AllocaIP(&F->getEntryBlock(),
+ F->getEntryBlock().getFirstInsertionPt());
+ OpenMPIRBuilder::LocationDescription Loc({Builder.saveIP(), DL});
+
// { cond-update-stmt v = x; }
- Builder.restoreIP(OMPBuilder.createAtomicCompare(
- Builder, X, V, NoR, Expr, D, AO, OpEQ, /* IsXBinopExpr */ true,
- /* IsPostfixUpdate */ false,
- /* IsFailOnly */ false));
+ ASSERT_EXPECTED_INIT(
+ OpenMPIRBuilder::InsertPointTy, AfterIP1,
+ OMPBuilder.createAtomicCompare(Builder, AllocaIP, X, V, NoR, Expr, D, AO,
+ OpEQ, /* IsXBinopExpr */ true,
+ /* IsPostfixUpdate */ false,
+ /* IsFailOnly */ false));
+ Builder.restoreIP(AfterIP1);
+
// { v = x; cond-update-stmt }
- Builder.restoreIP(OMPBuilder.createAtomicCompare(
- Builder, X, V, NoR, Expr, D, AO, OpEQ, /* IsXBinopExpr */ true,
- /* IsPostfixUpdate */ true,
- /* IsFailOnly */ false));
+ ASSERT_EXPECTED_INIT(
+ OpenMPIRBuilder::InsertPointTy, AfterIP2,
+ OMPBuilder.createAtomicCompare(Builder, AllocaIP, X, V, NoR, Expr, D, AO,
+ OpEQ, /* IsXBinopExpr */ true,
+ /* IsPostfixUpdate */ true,
+ /* IsFailOnly */ false));
+ Builder.restoreIP(AfterIP2);
+
// if(x == e) { x = d; } else { v = x; }
- Builder.restoreIP(OMPBuilder.createAtomicCompare(
- Builder, X, V, NoR, Expr, D, AO, OpEQ, /* IsXBinopExpr */ true,
- /* IsPostfixUpdate */ false,
- /* IsFailOnly */ true));
+ ASSERT_EXPECTED_INIT(
+ OpenMPIRBuilder::InsertPointTy, AfterIP3,
+ OMPBuilder.createAtomicCompare(Builder, AllocaIP, X, V, NoR, Expr, D, AO,
+ OpEQ, /* IsXBinopExpr */ true,
+ /* IsPostfixUpdate */ false,
+ /* IsFailOnly */ true));
+ Builder.restoreIP(AfterIP3);
+
// { r = x == e; if(r) { x = d; } }
- Builder.restoreIP(OMPBuilder.createAtomicCompare(
- Builder, X, NoV, R, Expr, D, AO, OpEQ, /* IsXBinopExpr */ true,
- /* IsPostfixUpdate */ false,
- /* IsFailOnly */ false));
+ ASSERT_EXPECTED_INIT(
+ OpenMPIRBuilder::InsertPointTy, AfterIP4,
+ OMPBuilder.createAtomicCompare(Builder, AllocaIP, X, NoV, R, Expr, D, AO,
+ OpEQ, /* IsXBinopExpr */ true,
+ /* IsPostfixUpdate */ false,
+ /* IsFailOnly */ false));
+ Builder.restoreIP(AfterIP4);
+
// { r = x == e; if(r) { x = d; } else { v = x; } }
- Builder.restoreIP(OMPBuilder.createAtomicCompare(
- Builder, X, V, R, Expr, D, AO, OpEQ, /* IsXBinopExpr */ true,
- /* IsPostfixUpdate */ false,
- /* IsFailOnly */ true));
+ ASSERT_EXPECTED_INIT(
+ OpenMPIRBuilder::InsertPointTy, AfterIP5,
+ OMPBuilder.createAtomicCompare(Builder, AllocaIP, X, V, R, Expr, D, AO,
+ OpEQ, /* IsXBinopExpr */ true,
+ /* IsPostfixUpdate */ false,
+ /* IsFailOnly */ true));
+ Builder.restoreIP(AfterIP5);
// { v = x; cond-update-stmt }
- Builder.restoreIP(OMPBuilder.createAtomicCompare(
- Builder, X, V, NoR, Expr, nullptr, AO, OpMax, /* IsXBinopExpr */ true,
- /* IsPostfixUpdate */ true,
- /* IsFailOnly */ false));
- // { cond-update-stmt v = x; }
- Builder.restoreIP(OMPBuilder.createAtomicCompare(
- Builder, X, V, NoR, Expr, nullptr, AO, OpMax, /* IsXBinopExpr */ false,
- /* IsPostfixUpdate */ false,
- /* IsFailOnly */ false));
+ ASSERT_EXPECTED_INIT(OpenMPIRBuilder::InsertPointTy, AfterIP6,
+ OMPBuilder.createAtomicCompare(
+ Builder, AllocaIP, X, V, NoR, Expr, nullptr, AO,
+ OpMax, /* IsXBinopExpr */ true,
+ /* IsPostfixUpdate */ true,
+ /* IsFailOnly */ false));
+ Builder.restoreIP(AfterIP6);
- BasicBlock *EntryBB = BB;
- EXPECT_EQ(EntryBB->getParent()->size(), 5U);
- BasicBlock *Cont1 = dyn_cast<BasicBlock>(EntryBB->getNextNode());
- EXPECT_NE(Cont1, nullptr);
- BasicBlock *Exit1 = dyn_cast<BasicBlock>(Cont1->getNextNode());
- EXPECT_NE(Exit1, nullptr);
- BasicBlock *Cont2 = dyn_cast<BasicBlock>(Exit1->getNextNode());
- EXPECT_NE(Cont2, nullptr);
- BasicBlock *Exit2 = dyn_cast<BasicBlock>(Cont2->getNextNode());
- EXPECT_NE(Exit2, nullptr);
-
- AtomicCmpXchgInst *CmpXchg1 =
- dyn_cast<AtomicCmpXchgInst>(Init->getNextNode());
- EXPECT_NE(CmpXchg1, nullptr);
- EXPECT_EQ(CmpXchg1->getPointerOperand(), XVal);
- EXPECT_EQ(CmpXchg1->getCompareOperand(), Expr);
- EXPECT_EQ(CmpXchg1->getNewValOperand(), D);
- ExtractValueInst *ExtVal1 =
- dyn_cast<ExtractValueInst>(CmpXchg1->getNextNode());
- EXPECT_NE(ExtVal1, nullptr);
- EXPECT_EQ(ExtVal1->getAggregateOperand(), CmpXchg1);
- EXPECT_EQ(ExtVal1->getIndices(), ArrayRef<unsigned int>(0U));
- ExtractValueInst *ExtVal2 =
- dyn_cast<ExtractValueInst>(ExtVal1->getNextNode());
- EXPECT_NE(ExtVal2, nullptr);
- EXPECT_EQ(ExtVal2->getAggregateOperand(), CmpXchg1);
- EXPECT_EQ(ExtVal2->getIndices(), ArrayRef<unsigned int>(1U));
- SelectInst *Sel1 = dyn_cast<SelectInst>(ExtVal2->getNextNode());
- EXPECT_NE(Sel1, nullptr);
- EXPECT_EQ(Sel1->getCondition(), ExtVal2);
- EXPECT_EQ(Sel1->getTrueValue(), Expr);
- EXPECT_EQ(Sel1->getFalseValue(), ExtVal1);
- StoreInst *Store1 = dyn_cast<StoreInst>(Sel1->getNextNode());
- EXPECT_NE(Store1, nullptr);
- EXPECT_EQ(Store1->getPointerOperand(), VVal);
- EXPECT_EQ(Store1->getValueOperand(), Sel1);
-
- AtomicCmpXchgInst *CmpXchg2 =
- dyn_cast<AtomicCmpXchgInst>(Store1->getNextNode());
- EXPECT_NE(CmpXchg2, nullptr);
- EXPECT_EQ(CmpXchg2->getPointerOperand(), XVal);
- EXPECT_EQ(CmpXchg2->getCompareOperand(), Expr);
- EXPECT_EQ(CmpXchg2->getNewValOperand(), D);
- ExtractValueInst *ExtVal3 =
- dyn_cast<ExtractValueInst>(CmpXchg2->getNextNode());
- EXPECT_NE(ExtVal3, nullptr);
- EXPECT_EQ(ExtVal3->getAggregateOperand(), CmpXchg2);
- EXPECT_EQ(ExtVal3->getIndices(), ArrayRef<unsigned int>(0U));
- StoreInst *Store2 = dyn_cast<StoreInst>(ExtVal3->getNextNode());
- EXPECT_NE(Store2, nullptr);
- EXPECT_EQ(Store2->getPointerOperand(), VVal);
- EXPECT_EQ(Store2->getValueOperand(), ExtVal3);
-
- AtomicCmpXchgInst *CmpXchg3 =
- dyn_cast<AtomicCmpXchgInst>(Store2->getNextNode());
- EXPECT_NE(CmpXchg3, nullptr);
- EXPECT_EQ(CmpXchg3->getPointerOperand(), XVal);
- EXPECT_EQ(CmpXchg3->getCompareOperand(), Expr);
- EXPECT_EQ(CmpXchg3->getNewValOperand(), D);
- ExtractValueInst *ExtVal4 =
- dyn_cast<ExtractValueInst>(CmpXchg3->getNextNode());
- EXPECT_NE(ExtVal4, nullptr);
- EXPECT_EQ(ExtVal4->getAggregateOperand(), CmpXchg3);
- EXPECT_EQ(ExtVal4->getIndices(), ArrayRef<unsigned int>(0U));
- ExtractValueInst *ExtVal5 =
- dyn_cast<ExtractValueInst>(ExtVal4->getNextNode());
- EXPECT_NE(ExtVal5, nullptr);
- EXPECT_EQ(ExtVal5->getAggregateOperand(), CmpXchg3);
- EXPECT_EQ(ExtVal5->getIndices(), ArrayRef<unsigned int>(1U));
- BranchInst *Br1 = dyn_cast<BranchInst>(ExtVal5->getNextNode());
- EXPECT_NE(Br1, nullptr);
- EXPECT_EQ(Br1->isConditional(), true);
- EXPECT_EQ(Br1->getCondition(), ExtVal5);
- EXPECT_EQ(Br1->getSuccessor(0), Exit1);
- EXPECT_EQ(Br1->getSuccessor(1), Cont1);
-
- StoreInst *Store3 = dyn_cast<StoreInst>(&Cont1->front());
- EXPECT_NE(Store3, nullptr);
- EXPECT_EQ(Store3->getPointerOperand(), VVal);
- EXPECT_EQ(Store3->getValueOperand(), ExtVal4);
- BranchInst *Br2 = dyn_cast<BranchInst>(Store3->getNextNode());
- EXPECT_NE(Br2, nullptr);
- EXPECT_EQ(Br2->isUnconditional(), true);
- EXPECT_EQ(Br2->getSuccessor(0), Exit1);
-
- AtomicCmpXchgInst *CmpXchg4 = dyn_cast<AtomicCmpXchgInst>(&Exit1->front());
- EXPECT_NE(CmpXchg4, nullptr);
- EXPECT_EQ(CmpXchg4->getPointerOperand(), XVal);
- EXPECT_EQ(CmpXchg4->getCompareOperand(), Expr);
- EXPECT_EQ(CmpXchg4->getNewValOperand(), D);
- ExtractValueInst *ExtVal6 =
- dyn_cast<ExtractValueInst>(CmpXchg4->getNextNode());
- EXPECT_NE(ExtVal6, nullptr);
- EXPECT_EQ(ExtVal6->getAggregateOperand(), CmpXchg4);
- EXPECT_EQ(ExtVal6->getIndices(), ArrayRef<unsigned int>(1U));
- ZExtInst *ZExt1 = dyn_cast<ZExtInst>(ExtVal6->getNextNode());
- EXPECT_NE(ZExt1, nullptr);
- EXPECT_EQ(ZExt1->getDestTy(), Int32);
- StoreInst *Store4 = dyn_cast<StoreInst>(ZExt1->getNextNode());
- EXPECT_NE(Store4, nullptr);
- EXPECT_EQ(Store4->getPointerOperand(), RVal);
- EXPECT_EQ(Store4->getValueOperand(), ZExt1);
-
- AtomicCmpXchgInst *CmpXchg5 =
- dyn_cast<AtomicCmpXchgInst>(Store4->getNextNode());
- EXPECT_NE(CmpXchg5, nullptr);
- EXPECT_EQ(CmpXchg5->getPointerOperand(), XVal);
- EXPECT_EQ(CmpXchg5->getCompareOperand(), Expr);
- EXPECT_EQ(CmpXchg5->getNewValOperand(), D);
- ExtractValueInst *ExtVal7 =
- dyn_cast<ExtractValueInst>(CmpXchg5->getNextNode());
- EXPECT_NE(ExtVal7, nullptr);
- EXPECT_EQ(ExtVal7->getAggregateOperand(), CmpXchg5);
- EXPECT_EQ(ExtVal7->getIndices(), ArrayRef<unsigned int>(0U));
- ExtractValueInst *ExtVal8 =
- dyn_cast<ExtractValueInst>(ExtVal7->getNextNode());
- EXPECT_NE(ExtVal8, nullptr);
- EXPECT_EQ(ExtVal8->getAggregateOperand(), CmpXchg5);
- EXPECT_EQ(ExtVal8->getIndices(), ArrayRef<unsigned int>(1U));
- BranchInst *Br3 = dyn_cast<BranchInst>(ExtVal8->getNextNode());
- EXPECT_NE(Br3, nullptr);
- EXPECT_EQ(Br3->isConditional(), true);
- EXPECT_EQ(Br3->getCondition(), ExtVal8);
- EXPECT_EQ(Br3->getSuccessor(0), Exit2);
- EXPECT_EQ(Br3->getSuccessor(1), Cont2);
-
- StoreInst *Store5 = dyn_cast<StoreInst>(&Cont2->front());
- EXPECT_NE(Store5, nullptr);
- EXPECT_EQ(Store5->getPointerOperand(), VVal);
- EXPECT_EQ(Store5->getValueOperand(), ExtVal7);
- BranchInst *Br4 = dyn_cast<BranchInst>(Store5->getNextNode());
- EXPECT_NE(Br4, nullptr);
- EXPECT_EQ(Br4->isUnconditional(), true);
- EXPECT_EQ(Br4->getSuccessor(0), Exit2);
-
- ExtractValueInst *ExtVal9 = dyn_cast<ExtractValueInst>(&Exit2->front());
- EXPECT_NE(ExtVal9, nullptr);
- EXPECT_EQ(ExtVal9->getAggregateOperand(), CmpXchg5);
- EXPECT_EQ(ExtVal9->getIndices(), ArrayRef<unsigned int>(1U));
- ZExtInst *ZExt2 = dyn_cast<ZExtInst>(ExtVal9->getNextNode());
- EXPECT_NE(ZExt2, nullptr);
- EXPECT_EQ(ZExt2->getDestTy(), Int32);
- StoreInst *Store6 = dyn_cast<StoreInst>(ZExt2->getNextNode());
- EXPECT_NE(Store6, nullptr);
- EXPECT_EQ(Store6->getPointerOperand(), RVal);
- EXPECT_EQ(Store6->getValueOperand(), ZExt2);
-
- AtomicRMWInst *ARWM1 = dyn_cast<AtomicRMWInst>(Store6->getNextNode());
- EXPECT_NE(ARWM1, nullptr);
- EXPECT_EQ(ARWM1->getPointerOperand(), XVal);
- EXPECT_EQ(ARWM1->getValOperand(), Expr);
- EXPECT_EQ(ARWM1->getOperation(), AtomicRMWInst::Min);
- StoreInst *Store7 = dyn_cast<StoreInst>(ARWM1->getNextNode());
- EXPECT_NE(Store7, nullptr);
- EXPECT_EQ(Store7->getPointerOperand(), VVal);
- EXPECT_EQ(Store7->getValueOperand(), ARWM1);
-
- AtomicRMWInst *ARWM2 = dyn_cast<AtomicRMWInst>(Store7->getNextNode());
- EXPECT_NE(ARWM2, nullptr);
- EXPECT_EQ(ARWM2->getPointerOperand(), XVal);
- EXPECT_EQ(ARWM2->getValOperand(), Expr);
- EXPECT_EQ(ARWM2->getOperation(), AtomicRMWInst::Max);
- CmpInst *Cmp1 = dyn_cast<CmpInst>(ARWM2->getNextNode());
- EXPECT_NE(Cmp1, nullptr);
- EXPECT_EQ(Cmp1->getPredicate(), CmpInst::ICMP_SGT);
- EXPECT_EQ(Cmp1->getOperand(0), ARWM2);
- EXPECT_EQ(Cmp1->getOperand(1), Expr);
- SelectInst *Sel2 = dyn_cast<SelectInst>(Cmp1->getNextNode());
- EXPECT_NE(Sel2, nullptr);
- EXPECT_EQ(Sel2->getCondition(), Cmp1);
- EXPECT_EQ(Sel2->getTrueValue(), Expr);
- EXPECT_EQ(Sel2->getFalseValue(), ARWM2);
- StoreInst *Store8 = dyn_cast<StoreInst>(Sel2->getNextNode());
- EXPECT_NE(Store8, nullptr);
- EXPECT_EQ(Store8->getPointerOperand(), VVal);
- EXPECT_EQ(Store8->getValueOperand(), Sel2);
+ // { cond-update-stmt v = x; }
+ ASSERT_EXPECTED_INIT(OpenMPIRBuilder::InsertPointTy, AfterIP7,
+ OMPBuilder.createAtomicCompare(
+ Builder, AllocaIP, X, V, NoR, Expr, nullptr, AO,
+ OpMax, /* IsXBinopExpr */ false,
+ /* IsPostfixUpdate */ false,
+ /* IsFailOnly */ false));
+ Builder.restoreIP(AfterIP7);
Builder.CreateRetVoid();
OMPBuilder.finalize();
EXPECT_FALSE(verifyModule(*M, &errs()));
+
+ BasicBlock *EntryBB = BB;
+ {
+ // clang-format off
+ // %x.atomic.expected.ptr = alloca i32, align 4
+ // %x.atomic.desired.ptr = alloca i32, align 4
+ // %x.atomic.expected.ptr1 = alloca i32, align 4
+ // %x.atomic.expected.ptr2 = alloca i32, align 4
+ // %x.atomic.desired.ptr3 = alloca i32, align 4
+ // %x.atomic.expected.ptr4 = alloca i32, align 4
+ // %x.atomic.expected.ptr11 = alloca i32, align 4
+ // %x.atomic.desired.ptr12 = alloca i32, align 4
+ // %x.atomic.expected.ptr13 = alloca i32, align 4
+ // %x.atomic.expected.ptr20 = alloca i32, align 4
+ // %x.atomic.desired.ptr21 = alloca i32, align 4
+ // %x.atomic.expected.ptr22 = alloca i32, align 4
+ // %x.atomic.expected.ptr28 = alloca i32, align 4
+ // %x.atomic.desired.ptr29 = alloca i32, align 4
+ // %x.atomic.expected.ptr30 = alloca i32, align 4
+ // %x = alloca i32, align 4
+ // %v = alloca i32, align 4
+ // %r = alloca i32, align 4
+ // store i32 0, ptr %x, align 4
+ // store i32 1, ptr %x.atomic.expected.ptr, align 4
+ // store i32 1, ptr %x.atomic.desired.ptr, align 4
+ // %.cmpxchg.expected = load i32, ptr %x.atomic.expected.ptr, align 4
+ // %.cmpxchg.desired = load i32, ptr %x.atomic.desired.ptr, align 4
+ // %.cmpxchg.pair = cmpxchg ptr %x, i32 %.cmpxchg.expected, i32 %.cmpxchg.desired monotonic monotonic, align 4
+ // %.cmpxchg.prev = extractvalue { i32, i1 } %.cmpxchg.pair, 0
+ // store i32 %.cmpxchg.prev, ptr %x.atomic.expected.ptr1, align 4
+ // %.cmpxchg.success = extractvalue { i32, i1 } %.cmpxchg.pair, 1
+ // %x.capture.actual = load i32, ptr %x.atomic.expected.ptr1, align 4
+ // %x.capture.captured = select i1 %.cmpxchg.success, i32 1, i32 %x.capture.actual
+ // store i32 %x.capture.captured, ptr %v, align 4
+ // store i32 1, ptr %x.atomic.expected.ptr2, align 4
+ // store i32 1, ptr %x.atomic.desired.ptr3, align 4
+ // %.cmpxchg.expected5 = load i32, ptr %x.atomic.expected.ptr2, align 4
+ // %.cmpxchg.desired6 = load i32, ptr %x.atomic.desired.ptr3, align 4
+ // %.cmpxchg.pair7 = cmpxchg ptr %x, i32 %.cmpxchg.expected5, i32 %.cmpxchg.desired6 monotonic monotonic, align 4
+ // %.cmpxchg.prev8 = extractvalue { i32, i1 } %.cmpxchg.pair7, 0
+ // store i32 %.cmpxchg.prev8, ptr %x.atomic.expected.ptr4, align 4
+ // %.cmpxchg.success9 = extractvalue { i32, i1 } %.cmpxchg.pair7, 1
+ // %x.capture.actual10 = load i32, ptr %x.atomic.expected.ptr4, align 4
+ // store i32 %x.capture.actual10, ptr %v, align 4
+ // store i32 1, ptr %x.atomic.expected.ptr11, align 4
+ // store i32 1, ptr %x.atomic.desired.ptr12, align 4
+ // %.cmpxchg.expected14 = load i32, ptr %x.atomic.expected.ptr11, align 4
+ // %.cmpxchg.desired15 = load i32, ptr %x.atomic.desired.ptr12, align 4
+ // %.cmpxchg.pair16 = cmpxchg ptr %x, i32 %.cmpxchg.expected14, i32 %.cmpxchg.desired15 monotonic monotonic, align 4
+ // %.cmpxchg.prev17 = extractvalue { i32, i1 } %.cmpxchg.pair16, 0
+ // store i32 %.cmpxchg.prev17, ptr %x.atomic.expected.ptr13, align 4
+ // %.cmpxchg.success18 = extractvalue { i32, i1 } %.cmpxchg.pair16, 1
+ // %x.capture.actual19 = load i32, ptr %x.atomic.expected.ptr13, align 4
+ // clang-format on
+
+ // Follow use-def and load-store chains to discover instructions
+ AtomicCmpXchgInst *CmpxchgPair16 =
+ cast<AtomicCmpXchgInst>(getUniquePreviousStore(XVal, EntryBB));
+ LoadInst *CmpxchgDesired15 =
+ cast<LoadInst>(CmpxchgPair16->getNewValOperand());
+ AllocaInst *XAtomicDesiredPtr12 =
+ cast<AllocaInst>(CmpxchgDesired15->getPointerOperand());
+ LoadInst *CmpxchgExpected14 =
+ cast<LoadInst>(CmpxchgPair16->getCompareOperand());
+ AllocaInst *XAtomicExpectedPtr11 =
+ cast<AllocaInst>(CmpxchgExpected14->getPointerOperand());
+ StoreInst *Store1 = cast<StoreInst>(
+ getUniquePreviousStore(XAtomicDesiredPtr12, CmpxchgDesired15));
+ StoreInst *Store2 = cast<StoreInst>(
+ getUniquePreviousStore(XAtomicExpectedPtr11, CmpxchgExpected14));
+ StoreInst *Store3 = cast<StoreInst>(getUniquePreviousStore(VVal, EntryBB));
+ LoadInst *XCaptureActual10 = cast<LoadInst>(Store3->getValueOperand());
+ AllocaInst *XAtomicExpectedPtr4 =
+ cast<AllocaInst>(XCaptureActual10->getPointerOperand());
+ StoreInst *Store4 = cast<StoreInst>(
+ getUniquePreviousStore(XAtomicExpectedPtr4, XCaptureActual10));
+ ExtractValueInst *CmpxchgPrev8 =
+ cast<ExtractValueInst>(Store4->getValueOperand());
+ AtomicCmpXchgInst *CmpxchgPair7 =
+ cast<AtomicCmpXchgInst>(CmpxchgPrev8->getOperand(0));
+ LoadInst *CmpxchgDesired6 =
+ cast<LoadInst>(CmpxchgPair7->getNewValOperand());
+ AllocaInst *XAtomicDesiredPtr3 =
+ cast<AllocaInst>(CmpxchgDesired6->getPointerOperand());
+ LoadInst *CmpxchgExpected5 =
+ cast<LoadInst>(CmpxchgPair7->getCompareOperand());
+ AllocaInst *XAtomicExpectedPtr2 =
+ cast<AllocaInst>(CmpxchgExpected5->getPointerOperand());
+ StoreInst *Store5 = cast<StoreInst>(
+ getUniquePreviousStore(XAtomicDesiredPtr3, CmpxchgDesired6));
+ StoreInst *Store6 = cast<StoreInst>(
+ getUniquePreviousStore(XAtomicExpectedPtr2, CmpxchgExpected5));
+
+ // %x.atomic.expected.ptr2 = alloca i32, align 4
+ EXPECT_EQ(XAtomicExpectedPtr2->getParent(), EntryBB);
+ EXPECT_FALSE(XAtomicExpectedPtr2->isArrayAllocation());
+ EXPECT_EQ(XAtomicExpectedPtr2->getAddressSpace(), 0);
+ EXPECT_EQ(XAtomicExpectedPtr2->getAlign(), 4);
+ Type *XAtomicExpectedPtr2Ty = XAtomicExpectedPtr2->getAllocatedType();
+ EXPECT_TRUE(XAtomicExpectedPtr2Ty->isIntegerTy());
+ EXPECT_EQ(XAtomicExpectedPtr2Ty->getIntegerBitWidth(), 32);
+
+ // %x.atomic.desired.ptr3 = alloca i32, align 4
+ EXPECT_EQ(XAtomicDesiredPtr3->getParent(), EntryBB);
+ EXPECT_FALSE(XAtomicDesiredPtr3->isArrayAllocation());
+ EXPECT_EQ(XAtomicDesiredPtr3->getAddressSpace(), 0);
+ EXPECT_EQ(XAtomicDesiredPtr3->getAlign(), 4);
+ Type *XAtomicDesiredPtr3Ty = XAtomicDesiredPtr3->getAllocatedType();
+ EXPECT_TRUE(XAtomicDesiredPtr3Ty->isIntegerTy());
+ EXPECT_EQ(XAtomicDesiredPtr3Ty->getIntegerBitWidth(), 32);
+
+ // %x.atomic.expected.ptr4 = alloca i32, align 4
+ EXPECT_EQ(XAtomicExpectedPtr4->getParent(), EntryBB);
+ EXPECT_FALSE(XAtomicExpectedPtr4->isArrayAllocation());
+ EXPECT_EQ(XAtomicExpectedPtr4->getAddressSpace(), 0);
+ EXPECT_EQ(XAtomicExpectedPtr4->getAlign(), 4);
+ Type *XAtomicExpectedPtr4Ty = XAtomicExpectedPtr4->getAllocatedType();
+ EXPECT_TRUE(XAtomicExpectedPtr4Ty->isIntegerTy());
+ EXPECT_EQ(XAtomicExpectedPtr4Ty->getIntegerBitWidth(), 32);
+
+ // %x.atomic.expected.ptr11 = alloca i32, align 4
+ EXPECT_EQ(XAtomicExpectedPtr11->getParent(), EntryBB);
+ EXPECT_FALSE(XAtomicExpectedPtr11->isArrayAllocation());
+ EXPECT_EQ(XAtomicExpectedPtr11->getAddressSpace(), 0);
+ EXPECT_EQ(XAtomicExpectedPtr11->getAlign(), 4);
+ Type *XAtomicExpectedPtr11Ty = XAtomicExpectedPtr11->getAllocatedType();
+ EXPECT_TRUE(XAtomicExpectedPtr11Ty->isIntegerTy());
+ EXPECT_EQ(XAtomicExpectedPtr11Ty->getIntegerBitWidth(), 32);
+
+ // %x.atomic.desired.ptr12 = alloca i32, align 4
+ EXPECT_EQ(XAtomicDesiredPtr12->getParent(), EntryBB);
+ EXPECT_FALSE(XAtomicDesiredPtr12->isArrayAllocation());
+ EXPECT_EQ(XAtomicDesiredPtr12->getAddressSpace(), 0);
+ EXPECT_EQ(XAtomicDesiredPtr12->getAlign(), 4);
+ Type *XAtomicDesiredPtr12Ty = XAtomicDesiredPtr12->getAllocatedType();
+ EXPECT_TRUE(XAtomicDesiredPtr12Ty->isIntegerTy());
+ EXPECT_EQ(XAtomicDesiredPtr12Ty->getIntegerBitWidth(), 32);
+
+ // %x = alloca i32, align 4
+ EXPECT_EQ(XVal->getParent(), EntryBB);
+ EXPECT_FALSE(XVal->isArrayAllocation());
+ EXPECT_EQ(XVal->getAddressSpace(), 0);
+ EXPECT_EQ(XVal->getAlign(), 4);
+ Type *XValTy = XVal->getAllocatedType();
+ EXPECT_TRUE(XValTy->isIntegerTy());
+ EXPECT_EQ(XValTy->getIntegerBitWidth(), 32);
+
+ // %v = alloca i32, align 4
+ EXPECT_EQ(VVal->getParent(), EntryBB);
+ EXPECT_FALSE(VVal->isArrayAllocation());
+ EXPECT_EQ(VVal->getAddressSpace(), 0);
+ EXPECT_EQ(VVal->getAlign(), 4);
+ Type *VValTy = VVal->getAllocatedType();
+ EXPECT_TRUE(VValTy->isIntegerTy());
+ EXPECT_EQ(VValTy->getIntegerBitWidth(), 32);
+
+ // store i32 0, ptr %x, align 4
+ EXPECT_EQ(Init->getParent(), EntryBB);
+ EXPECT_TRUE(Init->isSimple());
+ EXPECT_EQ(cast<ConstantInt>(Init->getOperand(0))->getZExtValue(), 0);
+ EXPECT_EQ(Init->getOperand(1), XVal);
+
+ // store i32 1, ptr %x.atomic.expected.ptr2, align 4
+ EXPECT_EQ(Store6->getParent(), EntryBB);
+ EXPECT_TRUE(Store6->isSimple());
+ EXPECT_EQ(cast<ConstantInt>(Store6->getValueOperand())->getZExtValue(), 1);
+ EXPECT_EQ(Store6->getPointerOperand(), XAtomicExpectedPtr2);
+
+ // store i32 1, ptr %x.atomic.desired.ptr3, align 4
+ EXPECT_EQ(Store5->getParent(), EntryBB);
+ EXPECT_TRUE(Store5->isSimple());
+ EXPECT_EQ(cast<ConstantInt>(Store5->getValueOperand())->getZExtValue(), 1);
+ EXPECT_EQ(Store5->getPointerOperand(), XAtomicDesiredPtr3);
+
+ // %.cmpxchg.expected5 = load i32, ptr %x.atomic.expected.ptr2, align 4
+ EXPECT_EQ(CmpxchgExpected5->getParent(), EntryBB);
+ EXPECT_TRUE(CmpxchgExpected5->isSimple());
+ EXPECT_EQ(CmpxchgExpected5->getPointerOperand(), XAtomicExpectedPtr2);
+
+ // %.cmpxchg.desired6 = load i32, ptr %x.atomic.desired.ptr3, align 4
+ EXPECT_EQ(CmpxchgDesired6->getParent(), EntryBB);
+ EXPECT_TRUE(CmpxchgDesired6->isSimple());
+ EXPECT_EQ(CmpxchgDesired6->getPointerOperand(), XAtomicDesiredPtr3);
+
+ // %.cmpxchg.pair7 = cmpxchg ptr %x, i32 %.cmpxchg.expected5, i32
+ // %.cmpxchg.desired6 monotonic monotonic, align 4
+ EXPECT_EQ(CmpxchgPair7->getParent(), EntryBB);
+ EXPECT_FALSE(CmpxchgPair7->isVolatile());
+ EXPECT_FALSE(CmpxchgPair7->isWeak());
+ EXPECT_EQ(CmpxchgPair7->getSuccessOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(CmpxchgPair7->getFailureOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(CmpxchgPair7->getSyncScopeID(), SyncScope::System);
+ EXPECT_EQ(CmpxchgPair7->getAlign(), 4);
+ EXPECT_EQ(CmpxchgPair7->getPointerOperand(), XVal);
+ EXPECT_EQ(CmpxchgPair7->getCompareOperand(), CmpxchgExpected5);
+ EXPECT_EQ(CmpxchgPair7->getNewValOperand(), CmpxchgDesired6);
+
+ // %.cmpxchg.prev8 = extractvalue { i32, i1 } %.cmpxchg.pair7, 0
+ EXPECT_EQ(CmpxchgPrev8->getParent(), EntryBB);
+ EXPECT_EQ(CmpxchgPrev8->getOperand(0), CmpxchgPair7);
+
+ // store i32 %.cmpxchg.prev8, ptr %x.atomic.expected.ptr4, align 4
+ EXPECT_EQ(Store4->getParent(), EntryBB);
+ EXPECT_TRUE(Store4->isSimple());
+ EXPECT_EQ(Store4->getValueOperand(), CmpxchgPrev8);
+ EXPECT_EQ(Store4->getPointerOperand(), XAtomicExpectedPtr4);
+
+ // %x.capture.actual10 = load i32, ptr %x.atomic.expected.ptr4, align 4
+ EXPECT_EQ(XCaptureActual10->getParent(), EntryBB);
+ EXPECT_TRUE(XCaptureActual10->isSimple());
+ EXPECT_EQ(XCaptureActual10->getPointerOperand(), XAtomicExpectedPtr4);
+
+ // store i32 %x.capture.actual10, ptr %v, align 4
+ EXPECT_EQ(Store3->getParent(), EntryBB);
+ EXPECT_TRUE(Store3->isSimple());
+ EXPECT_EQ(Store3->getValueOperand(), XCaptureActual10);
+ EXPECT_EQ(Store3->getPointerOperand(), VVal);
+
+ // store i32 1, ptr %x.atomic.expected.ptr11, align 4
+ EXPECT_EQ(Store2->getParent(), EntryBB);
+ EXPECT_TRUE(Store2->isSimple());
+ EXPECT_EQ(cast<ConstantInt>(Store2->getValueOperand())->getZExtValue(), 1);
+ EXPECT_EQ(Store2->getPointerOperand(), XAtomicExpectedPtr11);
+
+ // store i32 1, ptr %x.atomic.desired.ptr12, align 4
+ EXPECT_EQ(Store1->getParent(), EntryBB);
+ EXPECT_TRUE(Store1->isSimple());
+ EXPECT_EQ(cast<ConstantInt>(Store1->getValueOperand())->getZExtValue(), 1);
+ EXPECT_EQ(Store1->getPointerOperand(), XAtomicDesiredPtr12);
+
+ // %.cmpxchg.expected14 = load i32, ptr %x.atomic.expected.ptr11, align 4
+ EXPECT_EQ(CmpxchgExpected14->getParent(), EntryBB);
+ EXPECT_TRUE(CmpxchgExpected14->isSimple());
+ EXPECT_EQ(CmpxchgExpected14->getPointerOperand(), XAtomicExpectedPtr11);
+
+ // %.cmpxchg.desired15 = load i32, ptr %x.atomic.desired.ptr12, align 4
+ EXPECT_EQ(CmpxchgDesired15->getParent(), EntryBB);
+ EXPECT_TRUE(CmpxchgDesired15->isSimple());
+ EXPECT_EQ(CmpxchgDesired15->getPointerOperand(), XAtomicDesiredPtr12);
+
+ // %.cmpxchg.pair16 = cmpxchg ptr %x, i32 %.cmpxchg.expected14, i32
+ // %.cmpxchg.desired15 monotonic monotonic, align 4
+ EXPECT_EQ(CmpxchgPair16->getParent(), EntryBB);
+ EXPECT_FALSE(CmpxchgPair16->isVolatile());
+ EXPECT_FALSE(CmpxchgPair16->isWeak());
+ EXPECT_EQ(CmpxchgPair16->getSuccessOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(CmpxchgPair16->getFailureOrdering(), AtomicOrdering::Monotonic);
+ EXPECT_EQ(CmpxchgPair16->getSyncScopeID(), SyncScope::System);
+ EXPECT_EQ(CmpxchgPair16->getAlign(), 4);
+ EXPECT_EQ(CmpxchgPair16->getPointerOperand(), XVal);
+ EXPECT_EQ(CmpxchgPair16->getCompareOperand(), CmpxchgExpected14);
+ EXPECT_EQ(CmpxchgPair16->getNewValOperand(), CmpxchgDesired15);
+ }
}
TEST_F(OpenMPIRBuilderTest, CreateTeams) {
diff --git a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
index 32c7c501d03c3..733dda91134b3 100644
--- a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+++ b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
@@ -2699,7 +2699,10 @@ convertOmpAtomicRead(Operation &opInst, llvm::IRBuilderBase &builder,
llvm::OpenMPIRBuilder::AtomicOpValue V = {v, elementType, false, false};
llvm::OpenMPIRBuilder::AtomicOpValue X = {x, elementType, false, false};
- builder.restoreIP(ompBuilder->createAtomicRead(ompLoc, X, V, AO));
+ auto ContIP = ompBuilder->createAtomicRead(ompLoc, X, V, AO);
+ if (!ContIP)
+ return opInst.emitError(toString(ContIP.takeError()));
+ builder.restoreIP(*ContIP);
return success();
}
@@ -2713,14 +2716,19 @@ convertOmpAtomicWrite(Operation &opInst, llvm::IRBuilderBase &builder,
llvm::OpenMPIRBuilder *ompBuilder = moduleTranslation.getOpenMPBuilder();
- llvm::OpenMPIRBuilder::LocationDescription ompLoc(builder);
llvm::AtomicOrdering ao = convertAtomicOrdering(writeOp.getMemoryOrder());
llvm::Value *expr = moduleTranslation.lookupValue(writeOp.getExpr());
llvm::Value *dest = moduleTranslation.lookupValue(writeOp.getX());
llvm::Type *ty = moduleTranslation.convertType(writeOp.getExpr().getType());
llvm::OpenMPIRBuilder::AtomicOpValue x = {dest, ty, /*isSigned=*/false,
/*isVolatile=*/false};
- builder.restoreIP(ompBuilder->createAtomicWrite(ompLoc, x, expr, ao));
+ auto allocaIP = findAllocaInsertPoint(builder, moduleTranslation);
+
+ llvm::OpenMPIRBuilder::LocationDescription ompLoc(builder);
+ auto contIP = ompBuilder->createAtomicWrite(ompLoc, allocaIP, x, expr, ao);
+ if (!contIP)
+ opInst.emitError(toString(contIP.takeError()));
+ builder.restoreIP(*contIP);
return success();
}
diff --git a/mlir/test/Target/LLVMIR/openmp-llvm.mlir b/mlir/test/Target/LLVMIR/openmp-llvm.mlir
index f25ba4aa3c8dc..61ea0c888df3c 100644
--- a/mlir/test/Target/LLVMIR/openmp-llvm.mlir
+++ b/mlir/test/Target/LLVMIR/openmp-llvm.mlir
@@ -1346,23 +1346,24 @@ llvm.func @omp_ordered(%arg0 : i32, %arg1 : i32, %arg2 : i32, %arg3 : i64,
// CHECK-SAME: (ptr %[[ARG0:.*]], ptr %[[ARG1:.*]])
llvm.func @omp_atomic_read(%arg0 : !llvm.ptr, %arg1 : !llvm.ptr) -> () {
- // CHECK: %[[X1:.*]] = load atomic i32, ptr %[[ARG0]] monotonic, align 4
+ // CHECK: %[[X1:.*]] = load atomic i32, ptr %[[ARG0]] monotonic, align 1
// CHECK: store i32 %[[X1]], ptr %[[ARG1]], align 4
omp.atomic.read %arg1 = %arg0 : !llvm.ptr, !llvm.ptr, i32
- // CHECK: %[[X2:.*]] = load atomic i32, ptr %[[ARG0]] seq_cst, align 4
- // CHECK: call void @__kmpc_flush(ptr @{{.*}})
+ // CHECK: %[[X2:.*]] = load atomic i32, ptr %[[ARG0]] seq_cst, align 1
// CHECK: store i32 %[[X2]], ptr %[[ARG1]], align 4
+ // CHECK: call void @__kmpc_flush(ptr @{{.*}})
omp.atomic.read %arg1 = %arg0 memory_order(seq_cst) : !llvm.ptr, !llvm.ptr, i32
- // CHECK: %[[X3:.*]] = load atomic i32, ptr %[[ARG0]] acquire, align 4
- // CHECK: call void @__kmpc_flush(ptr @{{.*}})
+ // CHECK: %[[X3:.*]] = load atomic i32, ptr %[[ARG0]] acquire, align 1
// CHECK: store i32 %[[X3]], ptr %[[ARG1]], align 4
+ // CHECK: call void @__kmpc_flush(ptr @{{.*}})
omp.atomic.read %arg1 = %arg0 memory_order(acquire) : !llvm.ptr, !llvm.ptr, i32
- // CHECK: %[[X4:.*]] = load atomic i32, ptr %[[ARG0]] monotonic, align 4
+ // CHECK: %[[X4:.*]] = load atomic i32, ptr %[[ARG0]] monotonic, align 1
// CHECK: store i32 %[[X4]], ptr %[[ARG1]], align 4
omp.atomic.read %arg1 = %arg0 memory_order(relaxed) : !llvm.ptr, !llvm.ptr, i32
+
llvm.return
}
@@ -1394,46 +1395,34 @@ llvm.func @omp_atomic_read_implicit_cast () {
%16 = llvm.mul %10, %9 overflow<nsw> : i64
%17 = llvm.getelementptr %5[%15] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(f32, f32)>
-//CHECK: %[[ATOMIC_LOAD_TEMP:.*]] = alloca { float, float }, align 8
-//CHECK: call void @__atomic_load(i64 8, ptr %[[X_ELEMENT]], ptr %[[ATOMIC_LOAD_TEMP]], i32 0)
-//CHECK: %[[LOAD:.*]] = load { float, float }, ptr %[[ATOMIC_LOAD_TEMP]], align 8
-//CHECK: %[[EXT:.*]] = extractvalue { float, float } %[[LOAD]], 0
-//CHECK: store float %[[EXT]], ptr %[[Y]], align 4
+//CHECK: %[[ATOMIC_LOAD:.*]] = load atomic i64, ptr %[[X_ELEMENT]] monotonic, align 1
+//CHECK: store i64 %[[ATOMIC_LOAD:.*]], ptr %[[Y]], align 4
omp.atomic.read %3 = %17 : !llvm.ptr, !llvm.ptr, !llvm.struct<(f32, f32)>
-//CHECK: %[[ATOMIC_LOAD_TEMP:.*]] = load atomic i32, ptr %[[Z]] monotonic, align 4
-//CHECK: %[[CAST:.*]] = bitcast i32 %[[ATOMIC_LOAD_TEMP]] to float
-//CHECK: %[[LOAD:.*]] = fpext float %[[CAST]] to double
-//CHECK: store double %[[LOAD]], ptr %[[Y]], align 8
+//CHECK: %[[ATOMIC_LOAD:.*]] = load atomic float, ptr %[[Z]] monotonic, align 4
+//CHECK: store float %[[ATOMIC_LOAD]], ptr %[[Y]], align 4
omp.atomic.read %3 = %1 : !llvm.ptr, !llvm.ptr, f32
-//CHECK: %[[ATOMIC_LOAD_TEMP:.*]] = load atomic i32, ptr %[[W]] monotonic, align 4
-//CHECK: %[[LOAD:.*]] = sitofp i32 %[[ATOMIC_LOAD_TEMP]] to double
-//CHECK: store double %[[LOAD]], ptr %[[Y]], align 8
+//CHECK: %[[ATOMIC_LOAD:.*]] = load atomic i32, ptr %[[W]] monotonic, align 4
+//CHECK: store i32 %[[ATOMIC_LOAD]], ptr %[[Y]], align 4
omp.atomic.read %3 = %7 : !llvm.ptr, !llvm.ptr, i32
-//CHECK: %[[ATOMIC_LOAD_TEMP:.*]] = load atomic i64, ptr %[[Y]] monotonic, align 4
-//CHECK: %[[CAST:.*]] = bitcast i64 %[[ATOMIC_LOAD_TEMP]] to double
-//CHECK: %[[LOAD:.*]] = fptrunc double %[[CAST]] to float
-//CHECK: store float %[[LOAD]], ptr %[[Z]], align 4
+//CHECK: %[[ATOMIC_LOAD:.*]] = load atomic double, ptr %[[Y]] monotonic, align 8
+//CHECK: store double %[[ATOMIC_LOAD]], ptr %[[Z]], align 8
omp.atomic.read %1 = %3 : !llvm.ptr, !llvm.ptr, f64
-//CHECK: %[[ATOMIC_LOAD_TEMP:.*]] = load atomic i32, ptr %[[W]] monotonic, align 4
-//CHECK: %[[LOAD:.*]] = sitofp i32 %[[ATOMIC_LOAD_TEMP]] to float
-//CHECK: store float %[[LOAD]], ptr %[[Z]], align 4
+//CHECK: %[[ATOMIC_LOAD:.*]] = load atomic i32, ptr %[[W]] monotonic, align 4
+//CHECK: store i32 %[[ATOMIC_LOAD]], ptr %[[Z]], align 4
omp.atomic.read %1 = %7 : !llvm.ptr, !llvm.ptr, i32
-//CHECK: %[[ATOMIC_LOAD_TEMP:.*]] = load atomic i64, ptr %[[Y]] monotonic, align 4
-//CHECK: %[[CAST:.*]] = bitcast i64 %[[ATOMIC_LOAD_TEMP]] to double
-//CHECK: %[[LOAD:.*]] = fptosi double %[[CAST]] to i32
-//CHECK: store i32 %[[LOAD]], ptr %[[W]], align 4
+//CHECK: %[[ATOMIC_LOAD:.*]] = load atomic double, ptr %[[Y]] monotonic, align 8
+//CHECK: store double %[[ATOMIC_LOAD]], ptr %[[W]], align 8
omp.atomic.read %7 = %3 : !llvm.ptr, !llvm.ptr, f64
-//CHECK: %[[ATOMIC_LOAD_TEMP:.*]] = load atomic i32, ptr %[[Z]] monotonic, align 4
-//CHECK: %[[CAST:.*]] = bitcast i32 %[[ATOMIC_LOAD_TEMP]] to float
-//CHECK: %[[LOAD:.*]] = fptosi float %[[CAST]] to i32
-//CHECK: store i32 %[[LOAD]], ptr %[[W]], align 4
+//CHECK: %[[ATOMIC_LOAD:.*]] = load atomic float, ptr %[[Z]] monotonic, align 4
+//CHECK: store float %[[ATOMIC_LOAD]], ptr %[[W]], align 4
omp.atomic.read %7 = %1 : !llvm.ptr, !llvm.ptr, f32
+
llvm.return
}
@@ -1442,16 +1431,33 @@ llvm.func @omp_atomic_read_implicit_cast () {
// CHECK-LABEL: @omp_atomic_write
// CHECK-SAME: (ptr %[[x:.*]], i32 %[[expr:.*]])
llvm.func @omp_atomic_write(%x: !llvm.ptr, %expr: i32) -> () {
- // CHECK: store atomic i32 %[[expr]], ptr %[[x]] monotonic, align 4
+ // CHECK: %[[ATOMIC_TMP_ADDR_4:.*]] = alloca i32, align 4
+ // CHECK: %[[ATOMIC_TMP_ADDR_3:.*]] = alloca i32, align 4
+ // CHECK: %[[ATOMIC_TMP_ADDR_2:.*]] = alloca i32, align 4
+ // CHECK: %[[ATOMIC_TMP_ADDR_1:.*]] = alloca i32, align 4
+
+ // CHECK: store i32 %[[expr]], ptr %[[ATOMIC_TMP_ADDR_1]], align 4
+ // CHECK: %[[ATOMIC_TMP_VAL:.*]] = load i32, ptr %[[ATOMIC_TMP_ADDR_1]], align 4
+ // CHECK: store atomic i32 %[[ATOMIC_TMP_VAL]], ptr %[[x]] monotonic, align 1
omp.atomic.write %x = %expr : !llvm.ptr, i32
- // CHECK: store atomic i32 %[[expr]], ptr %[[x]] seq_cst, align 4
+
+ // CHECK: store i32 %[[expr]], ptr %[[ATOMIC_TMP_ADDR_2]], align 4
+ // CHECK: %[[ATOMIC_TMP_VAL:.*]] = load i32, ptr %[[ATOMIC_TMP_ADDR_2]], align 4
+ // CHECK: store atomic i32 %[[ATOMIC_TMP_VAL]], ptr %[[x]] seq_cst, align 1
// CHECK: call void @__kmpc_flush(ptr @{{.*}})
omp.atomic.write %x = %expr memory_order(seq_cst) : !llvm.ptr, i32
- // CHECK: store atomic i32 %[[expr]], ptr %[[x]] release, align 4
+
+ // CHECK: store i32 %[[expr]], ptr %[[ATOMIC_TMP_ADDR_3]], align 4
+ // CHECK: %[[ATOMIC_TMP_VAL:.*]] = load i32, ptr %[[ATOMIC_TMP_ADDR_3]], align 4
+ // CHECK: store atomic i32 %[[ATOMIC_TMP_VAL]], ptr %[[x]] release, align 1
// CHECK: call void @__kmpc_flush(ptr @{{.*}})
omp.atomic.write %x = %expr memory_order(release) : !llvm.ptr, i32
- // CHECK: store atomic i32 %[[expr]], ptr %[[x]] monotonic, align 4
+
+ // CHECK: store i32 %[[expr]], ptr %[[ATOMIC_TMP_ADDR_4]], align 4
+ // CHECK: %[[ATOMIC_TMP_VAL:.*]] = load i32, ptr %[[ATOMIC_TMP_ADDR_4]], align 4
+ // CHECK: store atomic i32 %[[ATOMIC_TMP_VAL]], ptr %[[x]] monotonic, align 1
omp.atomic.write %x = %expr memory_order(relaxed) : !llvm.ptr, i32
+
llvm.return
}
@@ -1462,10 +1468,13 @@ llvm.func @omp_atomic_write(%x: !llvm.ptr, %expr: i32) -> () {
// CHECK-LABEL: @omp_atomic_update
// CHECK-SAME: (ptr %[[x:.*]], i32 %[[expr:.*]], ptr %[[xbool:.*]], i1 %[[exprbool:.*]])
llvm.func @omp_atomic_update(%x:!llvm.ptr, %expr: i32, %xbool: !llvm.ptr, %exprbool: i1) {
- // CHECK: %[[t1:.*]] = mul i32 %[[x_old:.*]], %[[expr]]
- // CHECK: store i32 %[[t1]], ptr %[[x_new:.*]]
- // CHECK: %[[t2:.*]] = load i32, ptr %[[x_new]]
- // CHECK: cmpxchg ptr %[[x]], i32 %[[x_old]], i32 %[[t2]]
+
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[newval:.*]] = mul i32 %[[x_old:.*]], %[[expr]]
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
omp.atomic.update %x : !llvm.ptr {
^bb0(%xval: i32):
%newval = llvm.mul %xval, %expr : i32
@@ -1482,6 +1491,7 @@ llvm.func @omp_atomic_update(%x:!llvm.ptr, %expr: i32, %xbool: !llvm.ptr, %exprb
// -----
+//CHECK: %[[ATOMIC_EXPECTED_PTR:.*]] = alloca { float, float }, align 8
//CHECK: %[[X_NEW_VAL:.*]] = alloca { float, float }, align 8
//CHECK: {{.*}} = alloca { float, float }, i64 1, align 8
//CHECK: %[[ORIG_VAL:.*]] = alloca { float, float }, i64 1, align 8
@@ -1489,13 +1499,12 @@ llvm.func @omp_atomic_update(%x:!llvm.ptr, %expr: i32, %xbool: !llvm.ptr, %exprb
//CHECK: br label %entry
//CHECK: entry:
-//CHECK: %[[ATOMIC_TEMP_LOAD:.*]] = alloca { float, float }, align 8
-//CHECK: call void @__atomic_load(i64 8, ptr %[[ORIG_VAL]], ptr %[[ATOMIC_TEMP_LOAD]], i32 0)
-//CHECK: %[[PHI_NODE_ENTRY_1:.*]] = load { float, float }, ptr %[[ATOMIC_TEMP_LOAD]], align 8
-//CHECK: br label %.atomic.cont
+//CHECK: %[[ATOMIC_LOAD:.*]] = load atomic i64, ptr %[[ORIG_VAL]] monotonic, align 8
+//CHECK: store i64 %[[ATOMIC_LOAD:.*]], ptr %[[ATOMIC_EXPECTED_PTR]], align 4
+//CHECK: br label %entry.atomic.retry
-//CHECK: .atomic.cont
-//CHECK: %[[VAL_4:.*]] = phi { float, float } [ %[[PHI_NODE_ENTRY_1]], %entry ], [ %{{.*}}, %.atomic.cont ]
+//CHECK: entry.atomic.retry:
+//CHECK: %[[VAL_4:.*]] = load { float, float }, ptr %[[ATOMIC_EXPECTED_PTR:.*]], align 4
//CHECK: %[[VAL_5:.*]] = extractvalue { float, float } %[[VAL_4]], 0
//CHECK: %[[VAL_6:.*]] = extractvalue { float, float } %[[VAL_4]], 1
//CHECK: %[[VAL_7:.*]] = fadd contract float %[[VAL_5]], 1.000000e+00
@@ -1503,9 +1512,15 @@ llvm.func @omp_atomic_update(%x:!llvm.ptr, %expr: i32, %xbool: !llvm.ptr, %exprb
//CHECK: %[[VAL_9:.*]] = insertvalue { float, float } undef, float %[[VAL_7]], 0
//CHECK: %[[VAL_10:.*]] = insertvalue { float, float } %[[VAL_9]], float %[[VAL_8]], 1
//CHECK: store { float, float } %[[VAL_10]], ptr %[[X_NEW_VAL]], align 4
-//CHECK: %[[VAL_11:.*]] = call i1 @__atomic_compare_exchange(i64 8, ptr %[[ORIG_VAL]], ptr %[[ATOMIC_TEMP_LOAD]], ptr %[[X_NEW_VAL]], i32 2, i32 2)
-//CHECK: %[[VAL_12:.*]] = load { float, float }, ptr %[[ATOMIC_TEMP_LOAD]], align 4
-//CHECK: br i1 %[[VAL_11]], label %.atomic.exit, label %.atomic.cont
+//CHECK: %[[CMPXCHG_EXPECTED:.*]] = load i64, ptr %[[ATOMIC_EXPECTED_PTR]], align 4
+//CHECK: %[[CMPXCHG_DESIRED:.*]] = load i64, ptr %.atomic.desired.ptr, align 4
+//CHECK: %[[CMPXCHG_PAIR:.*]] = cmpxchg weak ptr %2, i64 %[[CMPXCHG_EXPECTED]], i64 %[[CMPXCHG_DESIRED]] monotonic monotonic, align 8
+//CHECK: %[[CMPXCHG_PREV:.*]] = extractvalue { i64, i1 } %[[CMPXCHG_PAIR]], 0
+//CHECK: store i64 %[[CMPXCHG_PREV]], ptr %[[ATOMIC_EXPECTED_PTR]], align 4
+//CHECK: %[[CMPXCHG_SUCCESS:.*]] = extractvalue { i64, i1 } %[[CMPXCHG_PAIR]], 1
+//CHECK: br i1 %[[CMPXCHG_SUCCESS]], label %entry.atomic.done, label %entry.atomic.retry
+
+//CHECK: entry.atomic.done:
llvm.func @_QPomp_atomic_update_complex() {
%0 = llvm.mlir.constant(1 : i64) : i64
@@ -1534,32 +1549,35 @@ llvm.func @_QPomp_atomic_update_complex() {
// -----
+//CHECK: %[[ATOMIC_EXPECTED_PTR:.*]] = alloca { float, float }, align 8
//CHECK: %[[X_NEW_VAL:.*]] = alloca { float, float }, align 8
//CHECK: %[[VAL_1:.*]] = alloca { float, float }, i64 1, align 8
//CHECK: %[[ORIG_VAL:.*]] = alloca { float, float }, i64 1, align 8
-//CHECK: store { float, float } { float 2.000000e+00, float 2.000000e+00 }, ptr %[[ORIG_VAL]], align 4
//CHECK: br label %entry
-//CHECK: entry: ; preds = %0
-//CHECK: %[[ATOMIC_TEMP_LOAD:.*]] = alloca { float, float }, align 8
-//CHECK: call void @__atomic_load(i64 8, ptr %[[ORIG_VAL]], ptr %[[ATOMIC_TEMP_LOAD]], i32 0)
-//CHECK: %[[PHI_NODE_ENTRY_1:.*]] = load { float, float }, ptr %[[ATOMIC_TEMP_LOAD]], align 8
-//CHECK: br label %.atomic.cont
+//CHECK: entry:
+//CHECK: %[[ATOMIC_LOAD:.*]] = load atomic i64, ptr %[[ORIG_VAL]] monotonic, align 8
+//CHECK: store i64 %[[ATOMIC_LOAD:.*]], ptr %[[ATOMIC_EXPECTED_PTR]], align 4
+//CHECK: br label %entry.atomic.retry
-//CHECK: .atomic.cont
-//CHECK: %[[VAL_4:.*]] = phi { float, float } [ %[[PHI_NODE_ENTRY_1]], %entry ], [ %{{.*}}, %.atomic.cont ]
+//CHECK: entry.atomic.retry:
+//CHECK: %[[VAL_4:.*]] = load { float, float }, ptr %[[ATOMIC_EXPECTED_PTR:.*]], align 4
//CHECK: %[[VAL_5:.*]] = extractvalue { float, float } %[[VAL_4]], 0
//CHECK: %[[VAL_6:.*]] = extractvalue { float, float } %[[VAL_4]], 1
//CHECK: %[[VAL_7:.*]] = fadd contract float %[[VAL_5]], 1.000000e+00
//CHECK: %[[VAL_8:.*]] = fadd contract float %[[VAL_6]], 1.000000e+00
//CHECK: %[[VAL_9:.*]] = insertvalue { float, float } undef, float %[[VAL_7]], 0
//CHECK: %[[VAL_10:.*]] = insertvalue { float, float } %[[VAL_9]], float %[[VAL_8]], 1
-//CHECK: store { float, float } %[[VAL_10]], ptr %[[X_NEW_VAL]], align 4
-//CHECK: %[[VAL_11:.*]] = call i1 @__atomic_compare_exchange(i64 8, ptr %[[ORIG_VAL]], ptr %[[ATOMIC_TEMP_LOAD]], ptr %[[X_NEW_VAL]], i32 2, i32 2)
-//CHECK: %[[VAL_12:.*]] = load { float, float }, ptr %[[ATOMIC_TEMP_LOAD]], align 4
-//CHECK: br i1 %[[VAL_11]], label %.atomic.exit, label %.atomic.cont
-//CHECK: .atomic.exit
-//CHECK: store { float, float } %[[VAL_10]], ptr %[[VAL_1]], align 4
+//CHECK: store { float, float } %[[VAL_10]], ptr %[[X_NEW_VAL]], align 4
+//CHECK: %[[CMPXCHG_EXPECTED:.*]] = load i64, ptr %[[ATOMIC_EXPECTED_PTR]], align 4
+//CHECK: %[[CMPXCHG_DESIRED:.*]] = load i64, ptr %.atomic.desired.ptr, align 4
+//CHECK: %[[CMPXCHG_PAIR:.*]] = cmpxchg weak ptr %2, i64 %[[CMPXCHG_EXPECTED]], i64 %[[CMPXCHG_DESIRED]] monotonic monotonic, align 8
+//CHECK: %[[CMPXCHG_PREV:.*]] = extractvalue { i64, i1 } %[[CMPXCHG_PAIR]], 0
+//CHECK: store i64 %[[CMPXCHG_PREV]], ptr %[[ATOMIC_EXPECTED_PTR]], align 4
+//CHECK: %[[CMPXCHG_SUCCESS:.*]] = extractvalue { i64, i1 } %[[CMPXCHG_PAIR]], 1
+//CHECK: br i1 %[[CMPXCHG_SUCCESS]], label %entry.atomic.done, label %entry.atomic.retry
+
+//CHECK: entry.atomic.done:
llvm.func @_QPomp_atomic_capture_complex() {
%0 = llvm.mlir.constant(1 : i64) : i64
@@ -1601,10 +1619,9 @@ llvm.func @omp_atomic_read_complex(){
// CHECK: %[[a:.*]] = alloca { float, float }, i64 1, align 8
// CHECK: %[[b:.*]] = alloca { float, float }, i64 1, align 8
-// CHECK: %[[ATOMIC_TEMP_LOAD:.*]] = alloca { float, float }, align 8
-// CHECK: call void @__atomic_load(i64 8, ptr %[[b]], ptr %[[ATOMIC_TEMP_LOAD]], i32 0)
-// CHECK: %[[LOADED_VAL:.*]] = load { float, float }, ptr %[[ATOMIC_TEMP_LOAD]], align 8
-// CHECK: store { float, float } %[[LOADED_VAL]], ptr %[[a]], align 4
+// CHECK: %[[LOADED_VAL:.*]] = load atomic i64, ptr %[[b]] monotonic, align 8
+
+// CHECK: store i64 %[[LOADED_VAL]], ptr %[[a]], align 4
// CHECK: ret void
// CHECK: }
@@ -1622,10 +1639,12 @@ llvm.func @omp_atomic_read_complex(){
// CHECK-LABEL: @omp_atomic_update_ordering
// CHECK-SAME: (ptr %[[x:.*]], i32 %[[expr:.*]])
llvm.func @omp_atomic_update_ordering(%x:!llvm.ptr, %expr: i32) {
- // CHECK: %[[t1:.*]] = shl i32 %[[expr]], %[[x_old:[^ ,]*]]
- // CHECK: store i32 %[[t1]], ptr %[[x_new:.*]]
- // CHECK: %[[t2:.*]] = load i32, ptr %[[x_new]]
- // CHECK: cmpxchg ptr %[[x]], i32 %[[x_old]], i32 %[[t2]]
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[newval:.*]] = shl i32 %[[expr]], %[[x_old:.*]]
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
omp.atomic.update %x : !llvm.ptr {
^bb0(%xval: i32):
%newval = llvm.shl %expr, %xval : i32
@@ -1640,10 +1659,12 @@ llvm.func @omp_atomic_update_ordering(%x:!llvm.ptr, %expr: i32) {
// CHECK-LABEL: @omp_atomic_update_ordering
// CHECK-SAME: (ptr %[[x:.*]], i32 %[[expr:.*]])
llvm.func @omp_atomic_update_ordering(%x:!llvm.ptr, %expr: i32) {
- // CHECK: %[[t1:.*]] = shl i32 %[[x_old:.*]], %[[expr]]
- // CHECK: store i32 %[[t1]], ptr %[[x_new:.*]]
- // CHECK: %[[t2:.*]] = load i32, ptr %[[x_new]]
- // CHECK: cmpxchg ptr %[[x]], i32 %[[x_old]], i32 %[[t2]] monotonic
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[newval:.*]] = shl i32 %[[x_old:.*]], %[[expr]]
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
omp.atomic.update %x : !llvm.ptr {
^bb0(%xval: i32):
%newval = llvm.shl %xval, %expr : i32
@@ -1658,19 +1679,25 @@ llvm.func @omp_atomic_update_ordering(%x:!llvm.ptr, %expr: i32) {
// CHECK-LABEL: @omp_atomic_update_intrinsic
// CHECK-SAME: (ptr %[[x:.*]], i32 %[[expr:.*]])
llvm.func @omp_atomic_update_intrinsic(%x:!llvm.ptr, %expr: i32) {
- // CHECK: %[[t1:.*]] = call i32 @llvm.smax.i32(i32 %[[x_old:.*]], i32 %[[expr]])
- // CHECK: store i32 %[[t1]], ptr %[[x_new:.*]]
- // CHECK: %[[t2:.*]] = load i32, ptr %[[x_new]]
- // CHECK: cmpxchg ptr %[[x]], i32 %[[x_old]], i32 %[[t2]]
+
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.smax.i32(i32 %[[x_old:.*]], i32 %[[expr]])
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
omp.atomic.update %x : !llvm.ptr {
^bb0(%xval: i32):
%newval = "llvm.intr.smax"(%xval, %expr) : (i32, i32) -> i32
omp.yield(%newval : i32)
}
- // CHECK: %[[t1:.*]] = call i32 @llvm.umax.i32(i32 %[[x_old:.*]], i32 %[[expr]])
- // CHECK: store i32 %[[t1]], ptr %[[x_new:.*]]
- // CHECK: %[[t2:.*]] = load i32, ptr %[[x_new]]
- // CHECK: cmpxchg ptr %[[x]], i32 %[[x_old]], i32 %[[t2]]
+
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.umax.i32(i32 %[[x_old:.*]], i32 %[[expr]])
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
omp.atomic.update %x : !llvm.ptr {
^bb0(%xval: i32):
%newval = "llvm.intr.umax"(%xval, %expr) : (i32, i32) -> i32
@@ -1682,12 +1709,34 @@ llvm.func @omp_atomic_update_intrinsic(%x:!llvm.ptr, %expr: i32) {
// -----
// CHECK-LABEL: @atomic_update_cmpxchg
-// CHECK-SAME: (ptr %[[X:.*]], ptr %[[EXPR:.*]]) {
-// CHECK: %[[AT_LOAD_VAL:.*]] = load atomic i32, ptr %[[X]] monotonic, align 4
-// CHECK: %[[LOAD_VAL_PHI:.*]] = phi i32 [ %[[AT_LOAD_VAL]], %entry ], [ %[[LOAD_VAL:.*]], %.atomic.cont ]
-// CHECK: %[[VAL_SUCCESS:.*]] = cmpxchg ptr %[[X]], i32 %[[LOAD_VAL_PHI]], i32 %{{.*}} monotonic monotonic, align 4
-// CHECK: %[[LOAD_VAL]] = extractvalue { i32, i1 } %[[VAL_SUCCESS]], 0
-// CHECK: br i1 %{{.*}}, label %.atomic.exit, label %.atomic.cont
+// CHECK-SAME: (ptr %[[X:.*]], ptr %[[EXPR:.*]]) {
+// CHECK-NEXT: %[[ATOMIC_EXPECTED_PTR:.*]] = alloca i32, align 4
+// CHECK-NEXT: %[[ATOMIC_DESIRED_PTR:.*]] = alloca i32, align 4
+// CHECK-NEXT: %[[EXPR_VAL:.*]] = load float, ptr %[[EXPR]], align 4
+// CHECK-NEXT: br label %entry
+// CHECK-EMPTY:
+// CHECK-NEXT: entry:
+// CHECK-NEXT: %[[ATOMIC_LOAD:.*]] = load atomic i32, ptr %[[X]] monotonic, align 1
+// CHECK-NEXT: store i32 %[[ATOMIC_LOAD]], ptr %[[ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: br label %entry.atomic.retry
+// CHECK-EMPTY:
+// CHECK-NEXT: entry.atomic.retry:
+// CHECK-NEXT: %[[ATOMIC_ORIG:.*]] = load i32, ptr %[[ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: %[[SITOFP:.*]] = sitofp i32 %[[ATOMIC_ORIG]] to float
+// CHECK-NEXT: %[[FADD:.*]] = fadd float %[[SITOFP]], %[[EXPR_VAL]]
+// CHECK-NEXT: %[[FPTOSI:.*]] = fptosi float %[[FADD]] to i32
+// CHECK-NEXT: store i32 %[[FPTOSI]], ptr %[[ATOMIC_DESIRED_PTR]], align 4
+// CHECK-NEXT: %[[CMPXCHG_EXPECTED:.*]] = load i32, ptr %[[ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: %[[CMPXCHG_DESIRED:.*]] = load i32, ptr %[[ATOMIC_DESIRED_PTR]], align 4
+// CHECK-NEXT: %[[CMPXCHG_PAIR:.*]] = cmpxchg weak ptr %[[X]], i32 %[[CMPXCHG_EXPECTED]], i32 %[[CMPXCHG_DESIRED]] monotonic monotonic, align 1
+// CHECK-NEXT: %[[CMPXCHG_PREV:.*]] = extractvalue { i32, i1 } %[[CMPXCHG_PAIR]], 0
+// CHECK-NEXT: store i32 %[[CMPXCHG_PREV]], ptr %[[ATOMIC_EXPECTED_PTR]], align 4
+// CHECK-NEXT: %[[CMPXCHG_SUCCESS:.*]] = extractvalue { i32, i1 } %[[CMPXCHG_PAIR]], 1
+// CHECK-NEXT: br i1 %[[CMPXCHG_SUCCESS]], label %entry.atomic.done, label %entry.atomic.retry
+// CHECK-EMPTY:
+// CHECK-NEXT: entry.atomic.done:
+// CHECK-NEXT: ret void
+// CHECK-NEXT: }
llvm.func @atomic_update_cmpxchg(%arg0: !llvm.ptr, %arg1: !llvm.ptr) {
%0 = llvm.load %arg1 : !llvm.ptr -> f32
@@ -1768,11 +1817,12 @@ llvm.func @omp_atomic_capture_prefix_update(
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = mul i32 %[[xval]], %[[expr]]
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr {
@@ -1783,11 +1833,12 @@ llvm.func @omp_atomic_capture_prefix_update(
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = sdiv i32 %[[xval]], %[[expr]]
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr {
@@ -1798,11 +1849,12 @@ llvm.func @omp_atomic_capture_prefix_update(
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = udiv i32 %[[xval]], %[[expr]]
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr {
@@ -1813,11 +1865,12 @@ llvm.func @omp_atomic_capture_prefix_update(
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = shl i32 %[[xval]], %[[expr]]
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr {
@@ -1828,11 +1881,12 @@ llvm.func @omp_atomic_capture_prefix_update(
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = lshr i32 %[[xval]], %[[expr]]
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr {
@@ -1843,11 +1897,12 @@ llvm.func @omp_atomic_capture_prefix_update(
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = ashr i32 %[[xval]], %[[expr]]
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr {
@@ -1858,11 +1913,12 @@ llvm.func @omp_atomic_capture_prefix_update(
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.smax.i32(i32 %[[xval]], i32 %[[expr]])
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr {
@@ -1873,11 +1929,12 @@ llvm.func @omp_atomic_capture_prefix_update(
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.smin.i32(i32 %[[xval]], i32 %[[expr]])
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr {
@@ -1888,11 +1945,12 @@ llvm.func @omp_atomic_capture_prefix_update(
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.umax.i32(i32 %[[xval]], i32 %[[expr]])
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr {
@@ -1903,11 +1961,12 @@ llvm.func @omp_atomic_capture_prefix_update(
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.umin.i32(i32 %[[xval]], i32 %[[expr]])
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[newval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.update %x : !llvm.ptr {
@@ -1918,11 +1977,12 @@ llvm.func @omp_atomic_capture_prefix_update(
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
}
- // CHECK: %[[xval:.*]] = phi i32
- // CHECK: %[[newval:.*]] = fadd float %{{.*}}, %[[exprf]]
- // CHECK: store float %[[newval]], ptr %{{.*}}
- // CHECK: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK: %{{.*}} = cmpxchg ptr %[[xf]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK: %[[xval:.*]] = load float, ptr %[[EXPECTED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[newval:.*]] = fadd float %{{.*}}, %[[exprf]]
+ // CHECK-NEXT: store float %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[xf]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store float %[[newval]], ptr %[[vf]]
omp.atomic.capture {
omp.atomic.update %xf : !llvm.ptr {
@@ -1933,11 +1993,12 @@ llvm.func @omp_atomic_capture_prefix_update(
omp.atomic.read %vf = %xf : !llvm.ptr, !llvm.ptr, f32
}
- // CHECK: %[[xval:.*]] = phi i32
- // CHECK: %[[newval:.*]] = fsub float %{{.*}}, %[[exprf]]
- // CHECK: store float %[[newval]], ptr %{{.*}}
- // CHECK: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK: %{{.*}} = cmpxchg ptr %[[xf]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK: %[[xval:.*]] = load float, ptr %[[EXPECTED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[newval:.*]] = fsub float %{{.*}}, %[[exprf]]
+ // CHECK-NEXT: store float %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[xf]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store float %[[newval]], ptr %[[vf]]
omp.atomic.capture {
omp.atomic.update %xf : !llvm.ptr {
@@ -2013,11 +2074,12 @@ llvm.func @omp_atomic_capture_postfix_update(
}
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = mul i32 %[[xval]], %[[expr]]
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
@@ -2028,11 +2090,12 @@ llvm.func @omp_atomic_capture_postfix_update(
}
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = sdiv i32 %[[xval]], %[[expr]]
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
@@ -2043,11 +2106,12 @@ llvm.func @omp_atomic_capture_postfix_update(
}
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = udiv i32 %[[xval]], %[[expr]]
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
@@ -2058,11 +2122,12 @@ llvm.func @omp_atomic_capture_postfix_update(
}
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = shl i32 %[[xval]], %[[expr]]
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
@@ -2073,11 +2138,12 @@ llvm.func @omp_atomic_capture_postfix_update(
}
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = lshr i32 %[[xval]], %[[expr]]
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
@@ -2088,11 +2154,12 @@ llvm.func @omp_atomic_capture_postfix_update(
}
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = ashr i32 %[[xval]], %[[expr]]
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
@@ -2103,11 +2170,12 @@ llvm.func @omp_atomic_capture_postfix_update(
}
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.smax.i32(i32 %[[xval]], i32 %[[expr]])
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
@@ -2118,11 +2186,12 @@ llvm.func @omp_atomic_capture_postfix_update(
}
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.smin.i32(i32 %[[xval]], i32 %[[expr]])
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
@@ -2133,11 +2202,12 @@ llvm.func @omp_atomic_capture_postfix_update(
}
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.umax.i32(i32 %[[xval]], i32 %[[expr]])
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
@@ -2148,11 +2218,12 @@ llvm.func @omp_atomic_capture_postfix_update(
}
}
- // CHECK: %[[xval:.*]] = phi i32
+ // CHECK: %[[xval:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR:.*]]
// CHECK-NEXT: %[[newval:.*]] = call i32 @llvm.umin.i32(i32 %[[xval]], i32 %[[expr]])
- // CHECK-NEXT: store i32 %[[newval]], ptr %{{.*}}
- // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK-NEXT: %{{.*}} = cmpxchg ptr %[[x]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
+ // CHECK-NEXT: store i32 %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[x]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
// CHECK: store i32 %[[xval]], ptr %[[v]]
omp.atomic.capture {
omp.atomic.read %v = %x : !llvm.ptr, !llvm.ptr, i32
@@ -2163,13 +2234,13 @@ llvm.func @omp_atomic_capture_postfix_update(
}
}
- // CHECK: %[[xval:.*]] = phi i32
- // CHECK: %[[xvalf:.*]] = bitcast i32 %[[xval]] to float
- // CHECK: %[[newval:.*]] = fadd float %{{.*}}, %[[exprf]]
- // CHECK: store float %[[newval]], ptr %{{.*}}
- // CHECK: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK: %{{.*}} = cmpxchg ptr %[[xf]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
- // CHECK: store float %[[xvalf]], ptr %[[vf]]
+ // CHECK: %[[xval:.*]] = load float, ptr %[[EXPECTED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[newval:.*]] = fadd float %{{.*}}, %[[exprf]]
+ // CHECK-NEXT: store float %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[xf]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
+ // CHECK: store float %[[xval]], ptr %[[vf]]
omp.atomic.capture {
omp.atomic.read %vf = %xf : !llvm.ptr, !llvm.ptr, f32
omp.atomic.update %xf : !llvm.ptr {
@@ -2179,13 +2250,13 @@ llvm.func @omp_atomic_capture_postfix_update(
}
}
- // CHECK: %[[xval:.*]] = phi i32
- // CHECK: %[[xvalf:.*]] = bitcast i32 %[[xval]] to float
- // CHECK: %[[newval:.*]] = fsub float %{{.*}}, %[[exprf]]
- // CHECK: store float %[[newval]], ptr %{{.*}}
- // CHECK: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK: %{{.*}} = cmpxchg ptr %[[xf]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
- // CHECK: store float %[[xvalf]], ptr %[[vf]]
+ // CHECK: %[[xval:.*]] = load float, ptr %[[EXPECTED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[newval:.*]] = fsub float %{{.*}}, %[[exprf]]
+ // CHECK-NEXT: store float %[[newval]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[xf]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
+ // CHECK: store float %[[xval]], ptr %[[vf]]
omp.atomic.capture {
omp.atomic.read %vf = %xf : !llvm.ptr, !llvm.ptr, f32
omp.atomic.update %xf : !llvm.ptr {
@@ -2199,6 +2270,7 @@ llvm.func @omp_atomic_capture_postfix_update(
}
// -----
+
// CHECK-LABEL: @omp_atomic_capture_misc
// CHECK-SAME: (ptr %[[x:.*]], ptr %[[v:.*]], i32 %[[expr:.*]], ptr %[[xf:.*]], ptr %[[vf:.*]], float %[[exprf:.*]])
llvm.func @omp_atomic_capture_misc(
@@ -2211,12 +2283,11 @@ llvm.func @omp_atomic_capture_misc(
omp.atomic.write %x = %expr : !llvm.ptr, i32
}
- // CHECK: %[[xval:.*]] = phi i32
- // CHECK: %[[xvalf:.*]] = bitcast i32 %[[xval]] to float
- // CHECK: store float %[[exprf]], ptr %{{.*}}
- // CHECK: %[[newval_:.*]] = load i32, ptr %{{.*}}
- // CHECK: %{{.*}} = cmpxchg ptr %[[xf]], i32 %[[xval]], i32 %[[newval_]] monotonic monotonic
- // CHECK: store float %[[xvalf]], ptr %[[vf]]
+ // CHECK: %[[xval:.*]] = load float, ptr %[[EXPECTED_TMP_ADDR:.*]]
+ // CHECK-NEXT: store float %[[exprf]], ptr %[[DESIRED_TMP_ADDR:.*]]
+ // CHECK-NEXT: %[[xval_:.*]] = load i32, ptr %[[EXPECTED_TMP_ADDR]]
+ // CHECK-NEXT: %[[newval_:.*]] = load i32, ptr %[[DESIRED_TMP_ADDR]]
+ // CHECK-NEXT: %{{.*}} = cmpxchg weak ptr %[[xf]], i32 %[[xval_]], i32 %[[newval_]] monotonic monotonic, align 1
omp.atomic.capture{
omp.atomic.read %vf = %xf : !llvm.ptr, !llvm.ptr, f32
omp.atomic.write %xf = %exprf : !llvm.ptr, f32
@@ -3005,7 +3076,7 @@ llvm.func @_QPomp_task_priority() {
// CHECK-LABEL: @omp_opaque_pointers
// CHECK-SAME: (ptr %[[ARG0:.*]], ptr %[[ARG1:.*]], i32 %[[EXPR:.*]])
llvm.func @omp_opaque_pointers(%arg0 : !llvm.ptr, %arg1: !llvm.ptr, %expr: i32) -> () {
- // CHECK: %[[X1:.*]] = load atomic i32, ptr %[[ARG0]] monotonic, align 4
+ // CHECK: %[[X1:.*]] = load atomic i32, ptr %[[ARG0]] monotonic, align 1
// CHECK: store i32 %[[X1]], ptr %[[ARG1]], align 4
omp.atomic.read %arg1 = %arg0 : !llvm.ptr, !llvm.ptr, i32
>From 74588b12d2c991145a998bd1b7c0affbec35a4f0 Mon Sep 17 00:00:00 2001
From: Michael Kruse <llvm-project at meinersbur.de>
Date: Mon, 3 Mar 2025 16:53:34 +0100
Subject: [PATCH 2/4] fix indention
---
.../Frontend/OpenMPIRBuilderTest.cpp | 92 +++++++++----------
1 file changed, 46 insertions(+), 46 deletions(-)
diff --git a/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp b/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
index 23f518fccd4b9..e509aa8e78e05 100644
--- a/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
+++ b/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
@@ -4179,7 +4179,7 @@ TEST_F(OpenMPIRBuilderTest, OMPAtomicUpdate) {
// %.atomic.load = load atomic i32, ptr %AtomicVar monotonic, align 4
// store i32 %.atomic.load, ptr %AtomicVar.atomic.expected.ptr, align 4
// br label %.atomic.retry
- //
+ //
// .atomic.retry: ; preds = %.atomic.retry, %1
// %AtomicVar.atomic.orig = load i32, ptr %AtomicVar.atomic.expected.ptr, align 4
// %2 = sub i32 1, %AtomicVar.atomic.orig
@@ -4191,7 +4191,7 @@ TEST_F(OpenMPIRBuilderTest, OMPAtomicUpdate) {
// store i32 %.cmpxchg.prev, ptr %AtomicVar.atomic.expected.ptr, align 4
// %.cmpxchg.success = extractvalue { i32, i1 } %.cmpxchg.pair, 1
// br i1 %.cmpxchg.success, label %.atomic.done, label %.atomic.retry
- //
+ //
// .atomic.done: ; preds = %.atomic.retry
// ret void
// clang-format on
@@ -4375,28 +4375,28 @@ TEST_F(OpenMPIRBuilderTest, OMPAtomicUpdateFloat) {
{
// clang-format off
- // %AtomicVar.atomic.expected.ptr = alloca float, align 4
- // %AtomicVar.atomic.desired.ptr = alloca float, align 4
- // %AtomicVar = alloca float, align 4
- // store float 0.000000e+00, ptr %AtomicVar, align 4
- // %.atomic.load = load atomic float, ptr %AtomicVar monotonic, align 4
- // store float %.atomic.load, ptr %AtomicVar.atomic.expected.ptr, align 4
- // br label %.atomic.retry
- //
- // .atomic.retry: ; preds = %.atomic.retry, %1
- // %AtomicVar.atomic.orig = load float, ptr %AtomicVar.atomic.expected.ptr, align 4
- // %2 = fsub float 1.000000e+00, %AtomicVar.atomic.orig
- // store float %2, ptr %AtomicVar.atomic.desired.ptr, align 4
- // %.cmpxchg.expected = load i32, ptr %AtomicVar.atomic.expected.ptr, align 4
- // %.cmpxchg.desired = load i32, ptr %AtomicVar.atomic.desired.ptr, align 4
- // %.cmpxchg.pair = cmpxchg weak ptr %AtomicVar, i32 %.cmpxchg.expected, i32 %.cmpxchg.desired monotonic monotonic, align 4
- // %.cmpxchg.prev = extractvalue { i32, i1 } %.cmpxchg.pair, 0
- // store i32 %.cmpxchg.prev, ptr %AtomicVar.atomic.expected.ptr, align 4
- // %.cmpxchg.success = extractvalue { i32, i1 } %.cmpxchg.pair, 1
- // br i1 %.cmpxchg.success, label %.atomic.done, label %.atomic.retry
- //
- // .atomic.done: ; preds = %.atomic.retry
- // ret void
+ // %AtomicVar.atomic.expected.ptr = alloca float, align 4
+ // %AtomicVar.atomic.desired.ptr = alloca float, align 4
+ // %AtomicVar = alloca float, align 4
+ // store float 0.000000e+00, ptr %AtomicVar, align 4
+ // %.atomic.load = load atomic float, ptr %AtomicVar monotonic, align 4
+ // store float %.atomic.load, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // br label %.atomic.retry
+ //
+ // .atomic.retry: ; preds = %.atomic.retry, %1
+ // %AtomicVar.atomic.orig = load float, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // %2 = fsub float 1.000000e+00, %AtomicVar.atomic.orig
+ // store float %2, ptr %AtomicVar.atomic.desired.ptr, align 4
+ // %.cmpxchg.expected = load i32, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // %.cmpxchg.desired = load i32, ptr %AtomicVar.atomic.desired.ptr, align 4
+ // %.cmpxchg.pair = cmpxchg weak ptr %AtomicVar, i32 %.cmpxchg.expected, i32 %.cmpxchg.desired monotonic monotonic, align 4
+ // %.cmpxchg.prev = extractvalue { i32, i1 } %.cmpxchg.pair, 0
+ // store i32 %.cmpxchg.prev, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // %.cmpxchg.success = extractvalue { i32, i1 } %.cmpxchg.pair, 1
+ // br i1 %.cmpxchg.success, label %.atomic.done, label %.atomic.retry
+ //
+ // .atomic.done: ; preds = %.atomic.retry
+ // ret void
// clang-format on
// Discover control flow graph
@@ -4576,28 +4576,28 @@ TEST_F(OpenMPIRBuilderTest, OMPAtomicUpdateIntr) {
{
// clang-format off
- // %AtomicVar.atomic.expected.ptr = alloca i32, align 4
- // %AtomicVar.atomic.desired.ptr = alloca i32, align 4
- // %AtomicVar = alloca i32, align 4
- // store i32 0, ptr %AtomicVar, align 4
- // %.atomic.load = load atomic i32, ptr %AtomicVar monotonic, align 4
- // store i32 %.atomic.load, ptr %AtomicVar.atomic.expected.ptr, align 4
- // br label %.atomic.retry
- //
- // .atomic.retry: ; preds = %.atomic.retry, %1
- // %AtomicVar.atomic.orig = load i32, ptr %AtomicVar.atomic.expected.ptr, align 4
- // %2 = sub i32 1, %AtomicVar.atomic.orig
- // store i32 %2, ptr %AtomicVar.atomic.desired.ptr, align 4
- // %.cmpxchg.expected = load i32, ptr %AtomicVar.atomic.expected.ptr, align 4
- // %.cmpxchg.desired = load i32, ptr %AtomicVar.atomic.desired.ptr, align 4
- // %.cmpxchg.pair = cmpxchg weak ptr %AtomicVar, i32 %.cmpxchg.expected, i32 %.cmpxchg.desired monotonic monotonic, align 4
- // %.cmpxchg.prev = extractvalue { i32, i1 } %.cmpxchg.pair, 0
- // store i32 %.cmpxchg.prev, ptr %AtomicVar.atomic.expected.ptr, align 4
- // %.cmpxchg.success = extractvalue { i32, i1 } %.cmpxchg.pair, 1
- // br i1 %.cmpxchg.success, label %.atomic.done, label %.atomic.retry
- //
- // .atomic.done: ; preds = %.atomic.retry
- // ret void
+ // %AtomicVar.atomic.expected.ptr = alloca i32, align 4
+ // %AtomicVar.atomic.desired.ptr = alloca i32, align 4
+ // %AtomicVar = alloca i32, align 4
+ // store i32 0, ptr %AtomicVar, align 4
+ // %.atomic.load = load atomic i32, ptr %AtomicVar monotonic, align 4
+ // store i32 %.atomic.load, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // br label %.atomic.retry
+ //
+ // .atomic.retry: ; preds = %.atomic.retry, %1
+ // %AtomicVar.atomic.orig = load i32, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // %2 = sub i32 1, %AtomicVar.atomic.orig
+ // store i32 %2, ptr %AtomicVar.atomic.desired.ptr, align 4
+ // %.cmpxchg.expected = load i32, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // %.cmpxchg.desired = load i32, ptr %AtomicVar.atomic.desired.ptr, align 4
+ // %.cmpxchg.pair = cmpxchg weak ptr %AtomicVar, i32 %.cmpxchg.expected, i32 %.cmpxchg.desired monotonic monotonic, align 4
+ // %.cmpxchg.prev = extractvalue { i32, i1 } %.cmpxchg.pair, 0
+ // store i32 %.cmpxchg.prev, ptr %AtomicVar.atomic.expected.ptr, align 4
+ // %.cmpxchg.success = extractvalue { i32, i1 } %.cmpxchg.pair, 1
+ // br i1 %.cmpxchg.success, label %.atomic.done, label %.atomic.retry
+ //
+ // .atomic.done: ; preds = %.atomic.retry
+ // ret void
// clang-format on
// Discover control flow graph
>From 849ec21162c63b91f20739e8c759dbb31592bce8 Mon Sep 17 00:00:00 2001
From: Michael Kruse <llvm-project at meinersbur.de>
Date: Fri, 7 Mar 2025 17:39:41 +0100
Subject: [PATCH 3/4] Undo unrealated change
---
flang/lib/Semantics/CMakeLists.txt | 65 ++++++++++--------------------
1 file changed, 22 insertions(+), 43 deletions(-)
diff --git a/flang/lib/Semantics/CMakeLists.txt b/flang/lib/Semantics/CMakeLists.txt
index c94c6a5a70183..00108dde49dbd 100644
--- a/flang/lib/Semantics/CMakeLists.txt
+++ b/flang/lib/Semantics/CMakeLists.txt
@@ -1,50 +1,10 @@
-add_flang_library(FortranSemantics PARTIAL_SOURCES_INTENDED
+add_flang_library(FortranSemantics
assignment.cpp
attr.cpp
canonicalize-acc.cpp
canonicalize-directives.cpp
canonicalize-do.cpp
canonicalize-omp.cpp
- compute-offsets.cpp
- data-to-inits.cpp
- definable.cpp
- expression.cpp
- mod-file.cpp
- openmp-modifiers.cpp
- pointer-assignment.cpp
- program-tree.cpp
- resolve-labels.cpp
- resolve-directives.cpp
- resolve-names-utils.cpp
- resolve-names.cpp
- rewrite-directives.cpp
- rewrite-parse-tree.cpp
- runtime-type-info.cpp
- scope.cpp
- semantics.cpp
- symbol.cpp
- tools.cpp
- type.cpp
- unparse-with-symbols.cpp
-
- DEPENDS
- acc_gen
- omp_gen
-
- LINK_LIBS
- FortranSupport
- FortranParser
- FortranEvaluate
-
- LINK_COMPONENTS
- Support
- FrontendOpenMP
- FrontendOpenACC
- TargetParser
-)
-
-
-add_flang_library(FortranSemanticsCheck PARTIAL_SOURCES_INTENDED
check-acc-structure.cpp
check-allocate.cpp
check-arithmeticif.cpp
@@ -66,6 +26,27 @@ add_flang_library(FortranSemanticsCheck PARTIAL_SOURCES_INTENDED
check-select-rank.cpp
check-select-type.cpp
check-stop.cpp
+ compute-offsets.cpp
+ data-to-inits.cpp
+ definable.cpp
+ expression.cpp
+ mod-file.cpp
+ openmp-modifiers.cpp
+ pointer-assignment.cpp
+ program-tree.cpp
+ resolve-labels.cpp
+ resolve-directives.cpp
+ resolve-names-utils.cpp
+ resolve-names.cpp
+ rewrite-directives.cpp
+ rewrite-parse-tree.cpp
+ runtime-type-info.cpp
+ scope.cpp
+ semantics.cpp
+ symbol.cpp
+ tools.cpp
+ type.cpp
+ unparse-with-symbols.cpp
DEPENDS
acc_gen
@@ -82,5 +63,3 @@ add_flang_library(FortranSemanticsCheck PARTIAL_SOURCES_INTENDED
FrontendOpenACC
TargetParser
)
-
-target_link_libraries(FortranSemantics PUBLIC FortranSemanticsCheck)
>From c5ce3bcc53a1434448a50147b8aec9f786b2e459 Mon Sep 17 00:00:00 2001
From: Michael Kruse <llvm-project at meinersbur.de>
Date: Tue, 11 Mar 2025 18:49:34 +0100
Subject: [PATCH 4/4] Remove disabled code
---
llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 83 -----------------------
1 file changed, 83 deletions(-)
diff --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
index 5851222922285..9eb908431078d 100644
--- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
@@ -8939,7 +8939,6 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createAtomicCompare(
bool IsInteger = E->getType()->isIntegerTy();
if (Op == OMPAtomicCompareOp::EQ) {
-#if 1
// TODO: Get TLI and TL from frontend
Triple T(Builder.GetInsertBlock()->getModule()->getTargetTriple());
TargetLibraryInfoImpl TLII(T);
@@ -9017,88 +9016,6 @@ OpenMPIRBuilder::InsertPointOrErrorTy OpenMPIRBuilder::createAtomicCompare(
: Builder.CreateZExt(SuccessOrFail, R.ElemTy);
Builder.CreateStore(ResultCast, R.Var, R.IsVolatile);
}
-
-#else
-
- // TODO: Use emitAtomicCompareExchangeBuiltin(...)
- AtomicCmpXchgInst *Result = nullptr;
- if (!IsInteger) {
- IntegerType *IntCastTy =
- IntegerType::get(M.getContext(), X.ElemTy->getScalarSizeInBits());
- Value *EBCast = Builder.CreateBitCast(E, IntCastTy);
- Value *DBCast = Builder.CreateBitCast(D, IntCastTy);
- Result = Builder.CreateAtomicCmpXchg(X.Var, EBCast, DBCast, MaybeAlign(),
- AO, Failure);
- } else {
- Result =
- Builder.CreateAtomicCmpXchg(X.Var, E, D, MaybeAlign(), AO, Failure);
- }
-
- if (V.Var) {
- Value *OldValue = Builder.CreateExtractValue(Result, /*Idxs=*/0);
- if (!IsInteger)
- OldValue = Builder.CreateBitCast(OldValue, X.ElemTy);
- assert(OldValue->getType() == V.ElemTy &&
- "OldValue and V must be of same type");
- if (IsPostfixUpdate) {
- Builder.CreateStore(OldValue, V.Var, V.IsVolatile);
- } else {
- Value *SuccessOrFail = Builder.CreateExtractValue(Result, /*Idxs=*/1);
- if (IsFailOnly) {
- // CurBB----
- // | |
- // v |
- // ContBB |
- // | |
- // v |
- // ExitBB <-
- //
- // where ContBB only contains the store of old value to 'v'.
- BasicBlock *CurBB = Builder.GetInsertBlock();
- Instruction *CurBBTI = CurBB->getTerminator();
- CurBBTI = CurBBTI ? CurBBTI : Builder.CreateUnreachable();
- BasicBlock *ExitBB = CurBB->splitBasicBlock(
- CurBBTI, X.Var->getName() + ".atomic.exit");
- BasicBlock *ContBB = CurBB->splitBasicBlock(
- CurBB->getTerminator(), X.Var->getName() + ".atomic.cont");
- ContBB->getTerminator()->eraseFromParent();
- CurBB->getTerminator()->eraseFromParent();
-
- Builder.CreateCondBr(SuccessOrFail, ExitBB, ContBB);
-
- Builder.SetInsertPoint(ContBB);
- Builder.CreateStore(OldValue, V.Var);
- Builder.CreateBr(ExitBB);
-
- if (UnreachableInst *ExitTI =
- dyn_cast<UnreachableInst>(ExitBB->getTerminator())) {
- CurBBTI->eraseFromParent();
- Builder.SetInsertPoint(ExitBB);
- } else {
- Builder.SetInsertPoint(ExitTI);
- }
- } else {
- Value *CapturedValue =
- Builder.CreateSelect(SuccessOrFail, E, OldValue);
- Builder.CreateStore(CapturedValue, V.Var, V.IsVolatile);
- }
- }
- }
-
- // The comparison result has to be stored.
- if (R.Var) {
- assert(R.Var->getType()->isPointerTy() &&
- "r.var must be of pointer type");
- assert(R.ElemTy->isIntegerTy() && "r must be of integral type");
-
- Value *SuccessFailureVal = Builder.CreateExtractValue(Result, /*Idxs=*/1);
- Value *ResultCast = R.IsSigned
- ? Builder.CreateSExt(SuccessFailureVal, R.ElemTy)
- : Builder.CreateZExt(SuccessFailureVal, R.ElemTy);
- Builder.CreateStore(ResultCast, R.Var, R.IsVolatile);
- }
-#endif
-
} else {
assert((Op == OMPAtomicCompareOp::MAX || Op == OMPAtomicCompareOp::MIN) &&
"Op should be either max or min at this point");
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