[libunwind] [libunwind][RISCV] Make asm statement volatile (PR #130286)

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``````````bash
git-clang-format --diff 308f933f75bcf92881c14e00e81d2d41a2893d7c c082d6c120b5eb090753413f14a571c9c8725640 --extensions hpp -- libunwind/src/Registers.hpp
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View the diff from clang-format here.
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``````````diff
diff --git a/libunwind/src/Registers.hpp b/libunwind/src/Registers.hpp
index 3b28874c9a..2c3bfb7e84 100644
--- a/libunwind/src/Registers.hpp
+++ b/libunwind/src/Registers.hpp
@@ -4126,7 +4126,7 @@ inline reg_t Registers_riscv::getRegister(int regNum) const {
     return _registers[regNum];
   if (regNum == UNW_RISCV_VLENB) {
     reg_t vlenb;
-    __asm__ volatile ("csrr %0, 0xC22" : "=r"(vlenb));
+    __asm__ volatile("csrr %0, 0xC22" : "=r"(vlenb));
     return vlenb;
   }
   _LIBUNWIND_ABORT("unsupported riscv register");

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https://github.com/llvm/llvm-project/pull/130286