[libunwind] [libunwind][RISCV] Make asm statement volatile (PR #130286)

[Gergely Futo via cfe-commits]

https://github.com/futog created https://github.com/llvm/llvm-project/pull/130286

Compiling with `O3`, the `early-machinelicm` pass hoisted the asm statement to a path that has been executed unconditionally during stack unwinding. On hardware without vector extension support, this resulted in reading a nonexistent register.

>From c082d6c120b5eb090753413f14a571c9c8725640 Mon Sep 17 00:00:00 2001
From: Gergely Futo <gergely.futo at hightec-rt.com>
Date: Thu, 10 Oct 2024 08:36:50 +0200
Subject: [PATCH] [libunwind][RISCV] Make asm statement volatile

Compiling with `O3`, the `early-machinelicm` pass hoisted the asm
statement to a path that has been executed unconditionally during
stack unwinding. On hardware without vector extension support, this
resulted in reading a nonexistent register.
---
 libunwind/src/Registers.hpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libunwind/src/Registers.hpp b/libunwind/src/Registers.hpp
index 452f46a0d56ea..3b28874c9ae32 100644
--- a/libunwind/src/Registers.hpp
+++ b/libunwind/src/Registers.hpp
@@ -4126,7 +4126,7 @@ inline reg_t Registers_riscv::getRegister(int regNum) const {
     return _registers[regNum];
   if (regNum == UNW_RISCV_VLENB) {
     reg_t vlenb;
-    __asm__("csrr %0, 0xC22" : "=r"(vlenb));
+    __asm__ volatile ("csrr %0, 0xC22" : "=r"(vlenb));
     return vlenb;
   }
   _LIBUNWIND_ABORT("unsupported riscv register");