[clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)

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git-clang-format --diff f7daa9d302a82f35c3b9ed4cede23ab808462b4f fcc75d7168040b41823768c585d2349a9ee88156 --extensions cpp,c -- clang/test/Driver/print-supported-extensions-riscv.c llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp llvm/lib/TargetParser/RISCVISAInfo.cpp llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
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diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index cef8fd1150..75599da547 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -742,10 +742,9 @@ Error RISCVISAInfo::checkDependency() {
   bool HasZvl = MinVLen != 0;
   bool HasZcmt = Exts.count("zcmt") != 0;
   static constexpr StringLiteral XqciExts[] = {
-      {"xqcia"},   {"xqciac"}, {"xqcibm"},  {"xqcicli"},
-      {"xqcicm"},  {"xqcics"}, {"xqcicsr"}, {"xqciint"},
-      {"xqcilia"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisim"},
-      {"xqcisls"}};
+      {"xqcia"},   {"xqciac"},  {"xqcibm"},  {"xqcicli"}, {"xqcicm"},
+      {"xqcics"},  {"xqcicsr"}, {"xqciint"}, {"xqcilia"}, {"xqcilo"},
+      {"xqcilsm"}, {"xqcisim"}, {"xqcisls"}};
   bool HasZcmp = Exts.count("zcmp") != 0;
   bool HasXqccmp = Exts.count("xqccmp") != 0;
 

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https://github.com/llvm/llvm-project/pull/128833