[clang] Reapply "[clang][HIP] Make some math not not work with AMDGCN SPIR-V #128360" (PR #129306)
LLVM Continuous Integration via cfe-commits
cfe-commits at lists.llvm.org
Fri Feb 28 16:17:13 PST 2025
llvm-ci wrote:
LLVM Buildbot has detected a new failure on builder `llvm-x86_64-debian-dylib` running on `gribozavr4` while building `clang` at step 7 "test-build-unified-tree-check-llvm".
Full details are available at: https://lab.llvm.org/buildbot/#/builders/60/builds/20773
<details>
<summary>Here is the relevant piece of the build log for the reference</summary>
```
Step 7 (test-build-unified-tree-check-llvm) failure: test (failure)
******************** TEST 'LLVM :: tools/llvm-exegesis/RISCV/rvv/reduction.test' FAILED ********************
Exit Code: 1
Command Output (stderr):
--
RUN: at line 1: /b/1/llvm-x86_64-debian-dylib/build/bin/llvm-exegesis -mtriple=riscv64 -mcpu=sifive-p670 -benchmark-phase=assemble-measured-code --mode=latency --opcode-name=PseudoVWREDSUMU_VS_M8_E32 --min-instructions=100 | /b/1/llvm-x86_64-debian-dylib/build/bin/FileCheck /b/1/llvm-x86_64-debian-dylib/llvm-project/llvm/test/tools/llvm-exegesis/RISCV/rvv/reduction.test
+ /b/1/llvm-x86_64-debian-dylib/build/bin/FileCheck /b/1/llvm-x86_64-debian-dylib/llvm-project/llvm/test/tools/llvm-exegesis/RISCV/rvv/reduction.test
+ /b/1/llvm-x86_64-debian-dylib/build/bin/llvm-exegesis -mtriple=riscv64 -mcpu=sifive-p670 -benchmark-phase=assemble-measured-code --mode=latency --opcode-name=PseudoVWREDSUMU_VS_M8_E32 --min-instructions=100
/b/1/llvm-x86_64-debian-dylib/llvm-project/llvm/test/tools/llvm-exegesis/RISCV/rvv/reduction.test:7:14: error: CHECK-NOT: excluded string found in input
# CHECK-NOT: V[[REG:[0-9]+]] V[[REG]] V{{[0-9]+}}M8 V[[REG]]
^
<stdin>:5:31: note: found here
- 'PseudoVWREDSUMU_VS_M8_E32 V7 V7 V0M8 V7 i_0xffffffffffffffff i_0x5 i_0x0'
^~~~~~~~~~~~~
<stdin>:5:32: note: captured var "REG"
- 'PseudoVWREDSUMU_VS_M8_E32 V7 V7 V0M8 V7 i_0xffffffffffffffff i_0x5 i_0x0'
^
Input file: <stdin>
Check file: /b/1/llvm-x86_64-debian-dylib/llvm-project/llvm/test/tools/llvm-exegesis/RISCV/rvv/reduction.test
-dump-input=help explains the following input dump.
Input was:
<<<<<<
1: ---
2: mode: latency
3: key:
4: instructions:
5: - 'PseudoVWREDSUMU_VS_M8_E32 V7 V7 V0M8 V7 i_0xffffffffffffffff i_0x5 i_0x0'
not:7'0 !~~~~~~~~~~~~ error: no match expected
not:7'1 ! captured var "REG"
6: config: 'vtype = {AVL: VLMAX, SEW: e32, Policy: tu/mu}'
7: register_initial_values:
8: - 'V7=0x0'
9: - 'V0M8=0x0'
10: cpu_name: sifive-p670
.
.
.
>>>>>>
--
********************
```
</details>
https://github.com/llvm/llvm-project/pull/129306
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