[clang] [X86][AVX10.2] Add comments for the avx10_2convertintrin.h file (PR #120766)
Mikołaj Piróg via cfe-commits
cfe-commits at lists.llvm.org
Thu Feb 27 05:51:45 PST 2025
https://github.com/mikolaj-pirog updated https://github.com/llvm/llvm-project/pull/120766
>From 18dfaec1d43fe38dc6b3fe754153426e5c974f0f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Miko=C5=82aj=20Pir=C3=B3g?= <mikolajpirog at gmail.com>
Date: Thu, 23 Jan 2025 23:27:17 +0100
Subject: [PATCH 01/23] rename
---
clang/lib/Headers/avx10_2convertintrin.h | 2943 +++++++++++++++++++++-
1 file changed, 2879 insertions(+), 64 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index c67a5b890f195..82d434c18df13 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -24,24 +24,157 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"), \
__min_vector_width__(256)))
+// clang-format off
+
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements to a 128-bit vector
+/// containing FP16 elements.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF i < 4
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 4])
+/// FI
+///
+/// ENDFOR
+///
+/// dst[MAX:127] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __A
+/// A 128-bit vector of [4 x float].
+/// \param __B
+/// A 128-bit vector of [4 x float].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Lower 4 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtx2ps_ph(__m128 __A,
__m128 __B) {
return (__m128h)__builtin_ia32_vcvt2ps2phx128_mask(
(__v4sf)__A, (__v4sf)__B, (__v8hf)_mm_setzero_ph(), (__mmask8)(-1));
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements to a 128-bit vector
+/// containing FP16 elements. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// IF i < 4
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 4])
+/// FI
+/// ELSE
+/// dst.fp16[i] := __W.fp16[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:127] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __W
+/// A 128-bit vector of [8 x fp16].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [4 x float].
+/// \param __B
+/// A 128-bit vector of [4 x float].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Lower elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
static __inline__ __m128h __DEFAULT_FN_ATTRS128
_mm_mask_cvtx2ps_ph(__m128h __W, __mmask8 __U, __m128 __A, __m128 __B) {
return (__m128h)__builtin_ia32_vcvt2ps2phx128_mask(
(__v4sf)__A, (__v4sf)__B, (__v8hf)__W, (__mmask8)__U);
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements to a 128-bit vector
+/// containing FP16 elements. Zeroing mask \a __U is used to determine if given
+/// element should be zeroed instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// IF i < 4
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 4])
+/// FI
+/// ELSE
+/// dst.fp16[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:127] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __U
+/// A 8-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [4 x float].
+/// \param __B
+/// A 128-bit vector of [4 x float].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Lower elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then zero is taken instead.
static __inline__ __m128h __DEFAULT_FN_ATTRS128
_mm_maskz_cvtx2ps_ph(__mmask8 __U, __m128 __A, __m128 __B) {
return (__m128h)__builtin_ia32_vcvt2ps2phx128_mask(
(__v4sf)__A, (__v4sf)__B, (__v8hf)_mm_setzero_ph(), (__mmask8)__U);
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements to a 256-bit vector
+/// containing FP16 elements.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF i < 8
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8])
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __A
+/// A 256-bit vector of [8 x float].
+/// \param __B
+/// A 256-bit vector of [8 x float].
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtx2ps_ph(__m256 __A,
__m256 __B) {
return (__m256h)__builtin_ia32_vcvt2ps2phx256_mask(
@@ -49,6 +182,44 @@ static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtx2ps_ph(__m256 __A,
_MM_FROUND_CUR_DIRECTION);
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements to a 256-bit vector
+/// containing FP16 elements. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// IF i < 8
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8])
+/// FI
+/// ELSE
+/// dst.fp16[i] := __W.fp16[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __W
+/// A 256-bit vector of [16 x fp16].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [8 x float].
+/// \param __B
+/// A 256-bit vector of [8 x float].
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
_mm256_mask_cvtx2ps_ph(__m256h __W, __mmask16 __U, __m256 __A, __m256 __B) {
return (__m256h)__builtin_ia32_vcvt2ps2phx256_mask(
@@ -56,6 +227,42 @@ _mm256_mask_cvtx2ps_ph(__m256h __W, __mmask16 __U, __m256 __A, __m256 __B) {
_MM_FROUND_CUR_DIRECTION);
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements to a 256-bit vector
+/// containing FP16 elements. Zeroing mask \a __U is used to determine if given
+/// element should be zeroed instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// IF i < 8
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8])
+/// FI
+/// ELSE
+/// dst.fp16[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __U
+/// A 16-bit zeroing mask.
+/// \param __A
+/// A 256-bit vector of [8 x float].
+/// \param __B
+/// A 256-bit vector of [8 x float].
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then zero is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
return (__m256h)__builtin_ia32_vcvt2ps2phx256_mask(
@@ -63,32 +270,239 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
_MM_FROUND_CUR_DIRECTION);
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements to a 256-bit vector
+/// containing FP16 elements. Rounding mode \a __R needs to be provided.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF i < 8
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8])
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __A
+/// A 256-bit vector of [8 x float].
+/// \param __B
+/// A 256-bit vector of [8 x float].
+/// \param __R
+/// Rounding mode. Valid inputs are: _MM_FROUND_CUR_DIRECTION or
+/// result of bitwise or of _MM_FROUND_NO_EXC with at most one of the following:
+/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF,
+/// _MM_FROUND_TO_ZERO.
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
#define _mm256_cvtx_round2ps_ph(A, B, R) \
((__m256h)__builtin_ia32_vcvt2ps2phx256_mask( \
(__v8sf)(A), (__v8sf)(B), (__v16hf)_mm256_undefined_ph(), \
(__mmask16)(-1), (const int)(R)))
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements to a 256-bit vector
+/// containing FP16 elements. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead. Rounding mode \a __R needs to
+/// be provided.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// IF i < 8
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8])
+/// FI
+/// ELSE
+/// dst.fp16[i] := __W.fp16[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __W
+/// A 256-bit vector of [16 x fp16].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [8 x float].
+/// \param __B
+/// A 256-bit vector of [8 x float].
+/// \param __R
+/// Rounding mode. Valid inputs are: _MM_FROUND_CUR_DIRECTION or
+/// result of bitwise or of _MM_FROUND_NO_EXC with at most one of the following:
+/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF,
+/// _MM_FROUND_TO_ZERO.
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
#define _mm256_mask_cvtx_round2ps_ph(W, U, A, B, R) \
((__m256h)__builtin_ia32_vcvt2ps2phx256_mask( \
(__v8sf)(A), (__v8sf)(B), (__v16hf)(W), (__mmask16)(U), (const int)(R)))
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements to a 256-bit vector
+/// containing FP16 elements. Zeroing mask \a __U is used to determine if given
+/// element should be zeroed instead. Rounding mode \a __R needs to be provided.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// IF i < 8
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8])
+/// FI
+/// ELSE
+/// dst.fp16[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __U
+/// A 16-bit zeroing mask.
+/// \param __A
+/// A 256-bit vector of [8 x float].
+/// \param __B
+/// A 256-bit vector of [8 x float].
+/// \param __R
+/// Rounding mode. Valid inputs are: _MM_FROUND_CUR_DIRECTION or
+/// result of bitwise or of _MM_FROUND_NO_EXC with at most one of the following:
+/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF,
+/// _MM_FROUND_TO_ZERO.
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then zero is taken instead.
#define _mm256_maskz_cvtx_round2ps_ph(U, A, B, R) \
((__m256h)__builtin_ia32_vcvt2ps2phx256_mask( \
(__v8sf)(A), (__v8sf)(B), (__v16hf)(_mm256_setzero_ph()), \
(__mmask16)(U), (const int)(R)))
-static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtbiasph_bf8(__m128i __A,
- __m128h __B) {
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// sum of elements from \a __A and \a __B; higher order elements are zeroed.
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvtbiasph_bf8(__m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := _W[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the sum of
+/// elements from \a __A and \a __B; higher order elements are zeroed. If
+/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtbiasph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
+///
+/// \param __U
+/// A 8-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the sum of
+/// elements from \a __A and \a __B; higher order elements are zeroed. If
+/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtbiasph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask(
@@ -96,6 +510,29 @@ _mm_maskz_cvtbiasph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
(__mmask8)__U);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x bf8]. Elements correspond to the
+/// sum of elements from \a __A and \a __B.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256_mask(
@@ -103,12 +540,78 @@ _mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) {
(__mmask16)-1);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := _W[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Elements correspond to the sum of
+/// elements from \a __A and \a __B. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_bf8(
__m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256_mask(
(__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
+///
+/// \param __U
+/// A 16-bit zeroing mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x bf8]. Elements correspond to the sum of
+/// elements from \a __A and \a __B. If corresponding mask bit is not set,
+/// then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtbiasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256_mask(
@@ -116,18 +619,108 @@ _mm256_maskz_cvtbiasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
(__mmask16)__U);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Results are saturated.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the
+/// sum of elements from \a __A and \a __B; higher order elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_cvtbiassph_bf8(__m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Results are saturated. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := _W[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the sum of
+/// elements from \a __A and \a __B; higher order elements are zeroed. If
+/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtbiassph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Results are saturated. Zeroing mask \a __U is used to determine if given
+/// element should be zeroed instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.
+///
+/// \param __U
+/// A 8-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the sum of
+/// elements from \a __A and \a __B; higher order elements are zeroed. If
+/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtbiassph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask(
@@ -135,6 +728,30 @@ _mm_maskz_cvtbiassph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
(__mmask8)__U);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Results are saturated.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x bf8]. Elements correspond to the
+/// sum of elements from \a __A and \a __B.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtbiassph_bf8(__m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_256_mask(
@@ -142,12 +759,78 @@ _mm256_cvtbiassph_bf8(__m256i __A, __m256h __B) {
(__mmask16)-1);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Results are saturated. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := _W[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Elements correspond to the sum of
+/// elements from \a __A and \a __B. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_bf8(
__m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_256_mask(
(__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Results are saturated. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.
+///
+/// \param __U
+/// A 16-bit zeroing mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x bf8]. Elements correspond to the sum of
+/// elements from \a __A and \a __B. If corresponding mask bit is not set,
+/// then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtbiassph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_256_mask(
@@ -155,18 +838,107 @@ _mm256_maskz_cvtbiassph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
(__mmask16)__U);
}
-static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtbiasph_hf8(__m128i __A,
- __m128h __B) {
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the
+/// sum of elements from \a __A and \a __B; higher order elements are zeroed.
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvtbiasph_hf8(__m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := _W[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the sum of
+/// elements from \a __A and \a __B; higher order elements are zeroed. If
+/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtbiasph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.
+///
+/// \param __U
+/// A 8-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the sum of
+/// elements from \a __A and \a __B; higher order elements are zeroed. If
+/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtbiasph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8_128_mask(
@@ -174,6 +946,29 @@ _mm_maskz_cvtbiasph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
(__mmask8)__U);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// dst.fp8[i] := add_fp16_int8_convert_to_hf8(__A.fp16[i], __B.int8[2 * i])
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x half].
+/// \param __B
+/// A 256-bit vector of [16 x i16].
+/// \returns
+/// A 128-bit vector of [16 x hf8]. Elements correspond to the
+/// sum of elements from \a __A and \a __B.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtbiasph_hf8(__m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8_256_mask(
@@ -181,12 +976,78 @@ _mm256_cvtbiasph_hf8(__m256i __A, __m256h __B) {
(__mmask16)-1);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := _W[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Elements correspond to the sum of
+/// elements from \a __A and \a __B. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_hf8(
__m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8_256_mask(
(__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := add_fp16_int8_convert_to_hf8(__A.fp16[i], __B.int8[2 * i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.
+///
+/// \param __U
+/// A 16-bit zeroing mask.
+/// \param __A
+/// A 256-bit vector of [16 x half].
+/// \param __B
+/// A 256-bit vector of [16 x i16].
+/// \returns
+/// A 128-bit vector of [16 x hf8]. Elements correspond to the sum of
+/// elements from \a __A and \a __B. If corresponding mask bit is not set,
+/// then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtbiasph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8_256_mask(
@@ -194,18 +1055,108 @@ _mm256_maskz_cvtbiasph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
(__mmask16)__U);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Results are saturated.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S`instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the
+/// sum of elements from \a __A and \a __B; higher order elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_cvtbiassph_hf8(__m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Results are saturated. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := _W[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the sum of
+/// elements from \a __A and \a __B; higher order elements are zeroed. If
+/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtbiassph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Results are saturated. Zeroing mask \a __U is used to determine if given
+/// element should be zeroed instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.
+///
+/// \param __U
+/// A 8-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the sum of
+/// elements from \a __A and \a __B; higher order elements are zeroed. If
+/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtbiassph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_128_mask(
@@ -213,6 +1164,30 @@ _mm_maskz_cvtbiassph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
(__mmask8)__U);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Results are saturated.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x hf8]. Elements correspond to the
+/// sum of elements from \a __A and \a __B.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtbiassph_hf8(__m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_256_mask(
@@ -220,12 +1195,78 @@ _mm256_cvtbiassph_hf8(__m256i __A, __m256h __B) {
(__mmask16)-1);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Results are saturated. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := _W[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Elements correspond to the sum of
+/// elements from \a __A and \a __B. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_hf8(
__m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_256_mask(
(__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Results are saturated. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.
+///
+/// \param __U
+/// A 16-bit zeroing mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x hf8]. Elements correspond to the sum of
+/// elements from \a __A and \a __B. If corresponding mask bit is not set,
+/// then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtbiassph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_256_mask(
@@ -233,17 +1274,119 @@ _mm256_maskz_cvtbiassph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
(__mmask16)__U);
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_bf8(__m128h __A,
- __m128h __B) {
- return (__m128i)__builtin_ia32_vcvt2ph2bf8_128((__v8hf)(__A), (__v8hf)(__B));
-}
-
+ __m128h __B) {
+ return (__m128i)__builtin_ia32_vcvt2ph2bf8_128((__v8hf)(__A),
+ (__v8hf)(__B));
+}
+
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ELSE
+/// dst.fp8 := __W.fp8[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvt2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_selectb_128(
(__mmask16)__U, (__v16qi)_mm_cvt2ph_bf8(__A, __B), (__v16qi)__W);
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction.
+///
+/// \param __U
+/// A 16-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// zero is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvt2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_selectb_128(
@@ -251,18 +1394,119 @@ _mm_maskz_cvt2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
(__v16qi)(__m128i)_mm_setzero_si128());
}
-static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_cvt2ph_bf8(__m256h __A,
- __m256h __B) {
- return (__m256i)__builtin_ia32_vcvt2ph2bf8_256((__v16hf)(__A),
- (__v16hf)(__B));
-}
-
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
-_mm256_mask_cvt2ph_bf8(__m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {
+_mm256_cvt2ph_bf8(__m256h __A, __m256h __B) {
+ return (__m256i)__builtin_ia32_vcvt2ph2bf8_256((__v16hf)(__A),
+ (__v16hf)(__B));
+}
+
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF __U[i]
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// ELSE
+/// dst.fp8[i] := __W.fp8[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction.
+///
+/// \param __W
+/// A 256-bit vector of [32 x fp8].
+/// \param __U
+/// A 32-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
+static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_bf8(
+ __m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_selectb_256(
(__mmask16)__U, (__v32qi)_mm256_cvt2ph_bf8(__A, __B), (__v32qi)__W);
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be zeroed
+/// instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF __U[i]
+/// dst.fp8[i] := 0
+/// ELSE
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction.
+///
+/// \param __U
+/// A 32-bit zeroing mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// zero is taken instead.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvt2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_selectb_256(
@@ -270,17 +1514,120 @@ _mm256_maskz_cvt2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {
(__v32qi)(__m256i)_mm256_setzero_si256());
}
-static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvts2ph_bf8(__m128h __A,
- __m128h __B) {
- return (__m128i)__builtin_ia32_vcvt2ph2bf8s_128((__v8hf)(__A), (__v8hf)(__B));
-}
-
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
+/// Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvts2ph_bf8(__m128h __A, __m128h __B) {
+ return (__m128i)__builtin_ia32_vcvt2ph2bf8s_128((__v8hf)(__A),
+ (__v8hf)(__B));
+}
+
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead. Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ELSE
+/// dst.fp8 := __W.fp8[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvts2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_selectb_128(
(__mmask16)__U, (__v16qi)_mm_cvts2ph_bf8(__A, __B), (__v16qi)__W);
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead. Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF __U[i]
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction.
+///
+/// \param __U
+/// A 16-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// zero is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvts2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_selectb_128(
@@ -288,18 +1635,120 @@ _mm_maskz_cvts2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
(__v16qi)(__m128i)_mm_setzero_si128());
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
+/// Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_cvts2ph_bf8(__m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_vcvt2ph2bf8s_256((__v16hf)(__A),
- (__v16hf)(__B));
-}
-
-static __inline__ __m256i __DEFAULT_FN_ATTRS256
-_mm256_mask_cvts2ph_bf8(__m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {
+ (__v16hf)(__B));
+}
+
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead. Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF __U[i]
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// ELSE
+/// dst.fp8[i] := __W.fp8[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction.
+///
+/// \param __W
+/// A 256-bit vector of [32 x fp8].
+/// \param __U
+/// A 32-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
+static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_bf8(
+ __m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_selectb_256(
(__mmask16)__U, (__v32qi)_mm256_cvts2ph_bf8(__A, __B), (__v32qi)__W);
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be zeroed
+/// instead. Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF __U[i]
+/// dst.fp8[i] := 0
+/// ELSE
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction.
+///
+/// \param __U
+/// A 32-bit zeroing mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// zero is taken instead.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvts2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_selectb_256(
@@ -307,17 +1756,119 @@ _mm256_maskz_cvts2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {
(__v32qi)(__m256i)_mm256_setzero_si256());
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_hf8(__m128h __A,
- __m128h __B) {
- return (__m128i)__builtin_ia32_vcvt2ph2hf8_128((__v8hf)(__A), (__v8hf)(__B));
-}
-
+ __m128h __B) {
+ return (__m128i)__builtin_ia32_vcvt2ph2hf8_128((__v8hf)(__A),
+ (__v8hf)(__B));
+}
+
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF __U[i]
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ELSE
+/// dst.fp8 := __W.fp8[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvt2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_selectb_128(
(__mmask16)__U, (__v16qi)_mm_cvt2ph_hf8(__A, __B), (__v16qi)__W);
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF __U[i]
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction.
+///
+/// \param __U
+/// A 16-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// zero is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvt2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_selectb_128(
@@ -325,18 +1876,119 @@ _mm_maskz_cvt2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
(__v16qi)(__m128i)_mm_setzero_si128());
}
-static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_cvt2ph_hf8(__m256h __A,
- __m256h __B) {
- return (__m256i)__builtin_ia32_vcvt2ph2hf8_256((__v16hf)(__A),
- (__v16hf)(__B));
-}
-
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
-_mm256_mask_cvt2ph_hf8(__m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {
+_mm256_cvt2ph_hf8(__m256h __A, __m256h __B) {
+ return (__m256i)__builtin_ia32_vcvt2ph2hf8_256((__v16hf)(__A),
+ (__v16hf)(__B));
+}
+
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF __U[i]
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// ELSE
+/// dst.fp8[i] := __W.fp8[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction.
+///
+/// \param __W
+/// A 256-bit vector of [32 x fp8].
+/// \param __U
+/// A 32-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
+static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_hf8(
+ __m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_selectb_256(
(__mmask16)__U, (__v32qi)_mm256_cvt2ph_hf8(__A, __B), (__v32qi)__W);
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be zeroed
+/// instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF __U[i]
+/// dst.fp8[i] := 0
+/// ELSE
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction.
+///
+/// \param __U
+/// A 32-bit zeroing mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// zero is taken instead.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvt2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_selectb_256(
@@ -344,17 +1996,120 @@ _mm256_maskz_cvt2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
(__v32qi)(__m256i)_mm256_setzero_si256());
}
-static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvts2ph_hf8(__m128h __A,
- __m128h __B) {
- return (__m128i)__builtin_ia32_vcvt2ph2hf8s_128((__v8hf)(__A), (__v8hf)(__B));
-}
-
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
+/// Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_cvts2ph_hf8(__m128h __A, __m128h __B) {
+ return (__m128i)__builtin_ia32_vcvt2ph2hf8s_128((__v8hf)(__A),
+ (__v8hf)(__B));
+}
+
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead. Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF __U[i]
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ELSE
+/// dst.fp8 := __W.fp8[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvts2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_selectb_128(
(__mmask16)__U, (__v16qi)_mm_cvts2ph_hf8(__A, __B), (__v16qi)__W);
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead. Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF __U[i]
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction.
+///
+/// \param __U
+/// A 16-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// zero is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvts2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_selectb_128(
@@ -362,18 +2117,120 @@ _mm_maskz_cvts2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
(__v16qi)(__m128i)_mm_setzero_si128());
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
+/// Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_cvts2ph_hf8(__m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_vcvt2ph2hf8s_256((__v16hf)(__A),
- (__v16hf)(__B));
-}
-
-static __inline__ __m256i __DEFAULT_FN_ATTRS256
-_mm256_mask_cvts2ph_hf8(__m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {
+ (__v16hf)(__B));
+}
+
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead. Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF __U[i]
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// ELSE
+/// dst.fp8[i] := __W.fp8[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction.
+///
+/// \param __W
+/// A 256-bit vector of [32 x fp8].
+/// \param __U
+/// A 32-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
+static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_hf8(
+ __m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_selectb_256(
(__mmask16)__U, (__v32qi)_mm256_cvts2ph_hf8(__A, __B), (__v32qi)__W);
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be zeroed
+/// instead. Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF __U[i]
+/// dst.fp8[i] := 0
+/// ELSE
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction.
+///
+/// \param __U
+/// A 32-bit zeroing mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// zero is taken instead.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvts2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_selectb_256(
@@ -381,208 +2238,1166 @@ _mm256_maskz_cvts2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
(__v32qi)(__m256i)_mm256_setzero_si256());
}
+/// Convert 128-bit vector \a __A, containing packed FP8 E4M3 floating-point
+/// elements to a 128-bit vector containing FP16 elements. The conversion is exact.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+///
+/// \param __A
+/// A 128-bit vector of [16 x fp8].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvthf8(__m128i __A) {
return (__m128h)__builtin_ia32_vcvthf8_2ph128_mask(
(__v16qi)__A, (__v8hf)(__m128h)_mm_undefined_ph(), (__mmask8)-1);
}
-static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_mask_cvthf8(__m128h __W,
- __mmask8 __U,
- __m128i __A) {
+/// Convert 128-bit vector \a __A, containing packed FP8 E4M3 floating-point
+/// elements to a 128-bit vector containing FP16 elements. The conversion is
+/// exact. Merging mask \a __U is used to determine if given element should be
+/// taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp16[i] := convert_fp8_to_fp16(__A.fp8[i])
+/// ELSE
+/// dst.fp16[i] := __W.fp16[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+///
+/// \param __W
+/// A 128-bit vector of [8 x fp16].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [16 x fp8].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
+static __inline__ __m128h __DEFAULT_FN_ATTRS128
+_mm_mask_cvthf8(__m128h __W, __mmask8 __U, __m128i __A) {
return (__m128h)__builtin_ia32_vcvthf8_2ph128_mask(
(__v16qi)__A, (__v8hf)(__m128h)__W, (__mmask8)__U);
}
-static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_maskz_cvthf8(__mmask8 __U,
- __m128i __A) {
+/// Convert 128-bit vector \a __A, containing packed FP8 E4M3 floating-point
+/// elements to a 128-bit vector containing FP16 elements. The conversion is
+/// exact. Zeroing mask \a __U is used to determine if given element should be
+/// zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// ELSE
+/// dst.fp16[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+///
+/// \param __U
+/// A 8-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [16 x fp8].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// zero is taken instead.
+static __inline__ __m128h __DEFAULT_FN_ATTRS128
+_mm_maskz_cvthf8(__mmask8 __U, __m128i __A) {
return (__m128h)__builtin_ia32_vcvthf8_2ph128_mask(
(__v16qi)__A, (__v8hf)(__m128h)_mm_setzero_ph(), (__mmask8)__U);
}
-static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvthf8(__m128i __A) {
+/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point
+/// elements to a 256-bit vector containing FP16 elements. The conversion is exact.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+///
+/// \param __A
+/// A 256-bit vector of [32 x fp8].
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A.
+static __inline__ __m256h __DEFAULT_FN_ATTRS256
+_mm256_cvthf8(__m128i __A) {
return (__m256h)__builtin_ia32_vcvthf8_2ph256_mask(
(__v16qi)__A, (__v16hf)(__m256h)_mm256_undefined_ph(), (__mmask16)-1);
}
+/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point
+/// elements to a 256-bit vector containing FP16 elements. The conversion is
+/// exact. Merging mask \a __U is used to determine if given element should be
+/// taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp16[i] := convert_fp8_to_fp16(__A.fp8[i])
+/// ELSE
+/// dst.fp16[i] := __W.fp16[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+///
+/// \param __W
+/// A 256-bit vector of [16 x fp16].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [32 x fp8].
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
_mm256_mask_cvthf8(__m256h __W, __mmask16 __U, __m128i __A) {
return (__m256h)__builtin_ia32_vcvthf8_2ph256_mask(
(__v16qi)__A, (__v16hf)(__m256h)__W, (__mmask16)__U);
}
+/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point
+/// elements to a 256-bit vector containing FP16 elements. The conversion is
+/// exact. Zeroing mask \a __U is used to determine if given element should be
+/// zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// ELSE
+/// dst.fp16[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:256] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+///
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [32 x fp8].
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// zero is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
_mm256_maskz_cvthf8(__mmask16 __U, __m128i __A) {
return (__m256h)__builtin_ia32_vcvthf8_2ph256_mask(
(__v16qi)__A, (__v16hf)(__m256h)_mm256_setzero_ph(), (__mmask16)__U);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the (converted)
+/// elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_bf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2bf8_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Merging mask \a __U is used to determine if
+/// given element should be taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8 := __W.fp8[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+///
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed. If
+/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2bf8_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Zeroing mask \a __U is used to determine if
+/// given element should be zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := 0
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction.
+///
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+///
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed. If
+/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtph_bf8(__mmask8 __U, __m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2bf8_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
}
-static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_cvtph_bf8(__m256h __A) {
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the (converted)
+/// elements from \a __A.
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_cvtph_bf8(__m256h __A) {
return (__m128i)__builtin_ia32_vcvtph2bf8_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Merging mask \a __U is
+/// used to determine if given element should be taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8 := __W.fp8[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If
+/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
return (__m128i)__builtin_ia32_vcvtph2bf8_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Zeroing mask \a __U is
+/// used to determine if given element should be zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction.
+///
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then element is zeroed instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtph_bf8(__mmask16 __U, __m256h __A) {
return (__m128i)__builtin_ia32_vcvtph2bf8_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Results are saturated.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the (converted)
+/// elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_bf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2bf8s_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Results are saturated. Merging mask \a __U is
+/// used to determine if given element should be taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8 := __W.fp8[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed. If
+/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtsph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2bf8s_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Results are saturated. Zeroing mask \a __U is
+/// used to determine if given element should be zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction.
+///
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed. If
+/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtsph_bf8(__mmask8 __U, __m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2bf8s_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
}
-static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_cvtsph_bf8(__m256h __A) {
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the (converted)
+/// elements from \a __A.
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_cvtsph_bf8(__m256h __A) {
return (__m128i)__builtin_ia32_vcvtph2bf8s_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8 := __W.fp8[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If
+/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtsph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
return (__m128i)__builtin_ia32_vcvtph2bf8s_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction.
+///
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then element is zeroed instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtsph_bf8(__mmask16 __U, __m256h __A) {
return (__m128i)__builtin_ia32_vcvtph2bf8s_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the (converted)
+/// elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_hf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2hf8_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Merging mask \a __U is used to determine if
+/// given element should be taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8 := __W.fp8[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+///
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed. If
+/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtph_hf8(__m128i __W, __mmask8 __U, __m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2hf8_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Zeroing mask \a __U is used to determine if
+/// given element should be zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction.
+///
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+///
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed. If
+/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtph_hf8(__mmask8 __U, __m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2hf8_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
}
-static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_cvtph_hf8(__m256h __A) {
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the (converted)
+/// elements from \a __A.
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_cvtph_hf8(__m256h __A) {
return (__m128i)__builtin_ia32_vcvtph2hf8_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Merging mask \a __U is
+/// used to determine if given element should be taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8 := __W.fp8[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If
+/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {
return (__m128i)__builtin_ia32_vcvtph2hf8_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Zeroing mask \a __U is
+/// used to determine if given element should be zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction.
+///
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then element is zeroed instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtph_hf8(__mmask16 __U, __m256h __A) {
return (__m128i)__builtin_ia32_vcvtph2hf8_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Results are saturated.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the (converted)
+/// elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_hf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2hf8s_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Results are saturated. Merging mask \a __U is
+/// used to determine if given element should be taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8 := __W.fp8[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed. If
+/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtsph_hf8(__m128i __W, __mmask8 __U, __m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2hf8s_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Results are saturated. Zeroing mask \a __U is
+/// used to determine if given element should be zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction.
+///
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed. If
+/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtsph_hf8(__mmask8 __U, __m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2hf8s_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
}
-static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_cvtsph_hf8(__m256h __A) {
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the (converted)
+/// elements from \a __A.
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_cvtsph_hf8(__m256h __A) {
return (__m128i)__builtin_ia32_vcvtph2hf8s_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8 := __W.fp8[i]
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If
+/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtsph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {
return (__m128i)__builtin_ia32_vcvtph2hf8s_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[MAX:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction.
+///
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then element is zeroed instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtsph_hf8(__mmask16 __U, __m256h __A) {
return (__m128i)__builtin_ia32_vcvtph2hf8s_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
}
+/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point
+/// elements to a 128-bit vector containing FP16 elements. The conversion is exact.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic does not correspond to a single instruction.
+///
+/// \param __A
+/// A 128-bit vector of [16 x fp8].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtbf8_ph(__m128i __A) {
return _mm_castsi128_ph(_mm_slli_epi16(_mm_cvtepi8_epi16(__A), 8));
}
+/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point
+/// elements to a 128-bit vector containing FP16 elements. The conversion is
+/// exact. Merging mask \a __U is used to determine if given element should be
+/// taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// ELSE
+/// dst.fp16[i] := __W.fp16[i]
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic does not correspond to a single instruction.
+///
+/// \param __W
+/// A 128-bit vector of [8 x fp16].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [16 x fp8].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
static __inline__ __m128h __DEFAULT_FN_ATTRS128
-_mm_mask_cvtbf8_ph(__m128h __S, __mmask8 __U, __m128i __A) {
+_mm_mask_cvtbf8_ph(__m128h __W, __mmask8 __U, __m128i __A) {
return _mm_castsi128_ph(
- _mm_mask_slli_epi16((__m128i)__S, __U, _mm_cvtepi8_epi16(__A), 8));
-}
-
+ _mm_mask_slli_epi16((__m128i)__W, __U, _mm_cvtepi8_epi16(__A), 8));
+}
+
+/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point
+/// elements to a 128-bit vector containing FP16 elements. The conversion is
+/// exact. Zeroing mask \a __U is used to determine if given element should be
+/// zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// ELSE
+/// dst.fp16[i] := 0
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic does not correspond to a single instruction.
+///
+/// \param __U
+/// A 8-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [16 x fp8].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// zero is taken instead.
static __inline__ __m128h __DEFAULT_FN_ATTRS128
_mm_maskz_cvtbf8_ph(__mmask8 __U, __m128i __A) {
return _mm_castsi128_ph(_mm_slli_epi16(_mm_maskz_cvtepi8_epi16(__U, __A), 8));
}
+/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point
+/// elements to a 256-bit vector containing FP16 elements. The conversion is exact.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic does not correspond to a single instruction.
+///
+/// \param __A
+/// A 256-bit vector of [32 x fp8].
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtbf8_ph(__m128i __A) {
return _mm256_castsi256_ph(_mm256_slli_epi16(_mm256_cvtepi8_epi16(__A), 8));
}
+/// Convert 256-bit vector \a __A, containing packed FP8 E5M2 floating-point
+/// elements to a 256-bit vector containing FP16 elements. The conversion is
+/// exact. Merging mask \a __U is used to determine if given element should be
+/// taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// ELSE
+/// dst.fp16[i] := __W.fp16[i]
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic does not correspond to a single instruction.
+///
+/// \param __W
+/// A 256-bit vector of [16 x fp16].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [32 x fp8].
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// element from \a __W is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
-_mm256_mask_cvtbf8_ph(__m256h __S, __mmask16 __U, __m128i __A) {
+_mm256_mask_cvtbf8_ph(__m256h __W, __mmask16 __U, __m128i __A) {
return _mm256_castsi256_ph(
- _mm256_mask_slli_epi16((__m256i)__S, __U, _mm256_cvtepi8_epi16(__A), 8));
-}
-
+ _mm256_mask_slli_epi16((__m256i)__W, __U, _mm256_cvtepi8_epi16(__A), 8));
+}
+
+/// Convert 256-bit vector \a __A, containing packed FP8 E5M2 floating-point
+/// elements to a 256-bit vector containing FP16 elements. The conversion is
+/// exact. Zeroing mask \a __U is used to determine if given element should be
+/// zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// ELSE
+/// dst.fp16[i] := 0
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic does not correspond to a single instruction.
+///
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [32 x fp8].
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// zero is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtbf8_ph(__mmask16 __U, __m128i __A) {
return _mm256_castsi256_ph(
_mm256_slli_epi16(_mm256_maskz_cvtepi8_epi16(__U, __A), 8));
}
+// clang-format on
+
#undef __DEFAULT_FN_ATTRS128
#undef __DEFAULT_FN_ATTRS256
>From 66f4f5e6c96a00f0d1a0cc1a362d7479f4cc44d3 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Wed, 29 Jan 2025 13:56:47 +0100
Subject: [PATCH 02/23] Replace all fp8 -> bf8/hf8
---
clang/lib/Headers/avx10_2convertintrin.h | 498 +++++++++++------------
1 file changed, 249 insertions(+), 249 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 82d434c18df13..52cd08d6d2d59 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -408,7 +408,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -423,7 +423,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// \param __B
/// A 128-bit vector of [8 x int16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the
/// sum of elements from \a __A and \a __B; higher order elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_cvtbiasph_bf8(__m128i __A, __m128h __B) {
@@ -440,9 +440,9 @@ _mm_cvtbiasph_bf8(__m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
/// ELSE
-/// dst.fp8[i] := _W[i]
+/// dst.bf8[i] := _W[i]
/// FI
/// ENDFOR
///
@@ -454,7 +454,7 @@ _mm_cvtbiasph_bf8(__m128i __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x bf8].
/// \param __U
/// A 8-bit merging mask.
/// \param __A
@@ -462,7 +462,7 @@ _mm_cvtbiasph_bf8(__m128i __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x int16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the sum of
+/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the sum of
/// elements from \a __A and \a __B; higher order elements are zeroed. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -480,9 +480,9 @@ _mm_mask_cvtbiasph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.bf8[i] := 0
/// FI
/// ENDFOR
///
@@ -516,7 +516,7 @@ _mm_maskz_cvtbiasph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -549,9 +549,9 @@ _mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
/// ELSE
-/// dst.fp8[i] := _W[i]
+/// dst.bf8[i] := _W[i]
/// FI
/// ENDFOR
///
@@ -563,7 +563,7 @@ _mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x bf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
@@ -571,7 +571,7 @@ _mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) {
/// \param __B
/// A 256-bit vector of [16 x int16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Elements correspond to the sum of
+/// A 128-bit vector of [16 x bf8]. Elements correspond to the sum of
/// elements from \a __A and \a __B. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_bf8(
@@ -589,9 +589,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_bf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.bf8[i] := 0
/// FI
/// ENDFOR
///
@@ -626,7 +626,7 @@ _mm256_maskz_cvtbiasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -658,9 +658,9 @@ _mm_cvtbiassph_bf8(__m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
/// ELSE
-/// dst.fp8[i] := _W[i]
+/// dst.bf8[i] := _W[i]
/// FI
/// ENDFOR
///
@@ -672,7 +672,7 @@ _mm_cvtbiassph_bf8(__m128i __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x bf8].
/// \param __U
/// A 8-bit merging mask.
/// \param __A
@@ -680,7 +680,7 @@ _mm_cvtbiassph_bf8(__m128i __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x int16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the sum of
+/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the sum of
/// elements from \a __A and \a __B; higher order elements are zeroed. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -698,9 +698,9 @@ _mm_mask_cvtbiassph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.bf8[i] := 0
/// FI
/// ENDFOR
///
@@ -735,7 +735,7 @@ _mm_maskz_cvtbiassph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -768,9 +768,9 @@ _mm256_cvtbiassph_bf8(__m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
/// ELSE
-/// dst.fp8[i] := _W[i]
+/// dst.bf8[i] := _W[i]
/// FI
/// ENDFOR
///
@@ -782,7 +782,7 @@ _mm256_cvtbiassph_bf8(__m256i __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x bf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
@@ -790,7 +790,7 @@ _mm256_cvtbiassph_bf8(__m256i __A, __m256h __B) {
/// \param __B
/// A 256-bit vector of [16 x int16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Elements correspond to the sum of
+/// A 128-bit vector of [16 x bf8]. Elements correspond to the sum of
/// elements from \a __A and \a __B. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_bf8(
@@ -808,9 +808,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_bf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.bf8[i] := 0
/// FI
/// ENDFOR
///
@@ -844,7 +844,7 @@ _mm256_maskz_cvtbiassph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -876,9 +876,9 @@ _mm_cvtbiasph_hf8(__m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
/// ELSE
-/// dst.fp8[i] := _W[i]
+/// dst.hf8[i] := _W[i]
/// FI
/// ENDFOR
///
@@ -890,7 +890,7 @@ _mm_cvtbiasph_hf8(__m128i __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x hf8].
/// \param __U
/// A 8-bit merging mask.
/// \param __A
@@ -898,7 +898,7 @@ _mm_cvtbiasph_hf8(__m128i __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x int16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the sum of
+/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the sum of
/// elements from \a __A and \a __B; higher order elements are zeroed. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -916,9 +916,9 @@ _mm_mask_cvtbiasph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.hf8[i] := 0
/// FI
/// ENDFOR
///
@@ -952,7 +952,7 @@ _mm_maskz_cvtbiasph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.fp8[i] := add_fp16_int8_convert_to_hf8(__A.fp16[i], __B.int8[2 * i])
+/// dst.hf8[i] := add_fp16_int8_convert_to_hf8(__A.fp16[i], __B.int8[2 * i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -985,9 +985,9 @@ _mm256_cvtbiasph_hf8(__m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
/// ELSE
-/// dst.fp8[i] := _W[i]
+/// dst.hf8[i] := _W[i]
/// FI
/// ENDFOR
///
@@ -999,7 +999,7 @@ _mm256_cvtbiasph_hf8(__m256i __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x hf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
@@ -1007,7 +1007,7 @@ _mm256_cvtbiasph_hf8(__m256i __A, __m256h __B) {
/// \param __B
/// A 256-bit vector of [16 x int16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Elements correspond to the sum of
+/// A 128-bit vector of [16 x hf8]. Elements correspond to the sum of
/// elements from \a __A and \a __B. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_hf8(
@@ -1025,9 +1025,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_hf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := add_fp16_int8_convert_to_hf8(__A.fp16[i], __B.int8[2 * i])
+/// dst.hf8[i] := add_fp16_int8_convert_to_hf8(__A.fp16[i], __B.int8[2 * i])
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.hf8[i] := 0
/// FI
/// ENDFOR
///
@@ -1062,7 +1062,7 @@ _mm256_maskz_cvtbiasph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -1094,9 +1094,9 @@ _mm_cvtbiassph_hf8(__m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
/// ELSE
-/// dst.fp8[i] := _W[i]
+/// dst.hf8[i] := _W[i]
/// FI
/// ENDFOR
///
@@ -1108,7 +1108,7 @@ _mm_cvtbiassph_hf8(__m128i __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x hf8].
/// \param __U
/// A 8-bit merging mask.
/// \param __A
@@ -1116,7 +1116,7 @@ _mm_cvtbiassph_hf8(__m128i __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x int16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the sum of
+/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the sum of
/// elements from \a __A and \a __B; higher order elements are zeroed. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -1134,9 +1134,9 @@ _mm_mask_cvtbiassph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.hf8[i] := 0
/// FI
/// ENDFOR
///
@@ -1171,7 +1171,7 @@ _mm_maskz_cvtbiassph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -1204,9 +1204,9 @@ _mm256_cvtbiassph_hf8(__m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
/// ELSE
-/// dst.fp8[i] := _W[i]
+/// dst.hf8[i] := _W[i]
/// FI
/// ENDFOR
///
@@ -1218,7 +1218,7 @@ _mm256_cvtbiassph_hf8(__m256i __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x hf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
@@ -1226,7 +1226,7 @@ _mm256_cvtbiassph_hf8(__m256i __A, __m256h __B) {
/// \param __B
/// A 256-bit vector of [16 x int16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Elements correspond to the sum of
+/// A 128-bit vector of [16 x hf8]. Elements correspond to the sum of
/// elements from \a __A and \a __B. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_hf8(
@@ -1244,9 +1244,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_hf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.hf8[i] := 0
/// FI
/// ENDFOR
///
@@ -1280,9 +1280,9 @@ _mm256_maskz_cvtbiassph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF i < 8
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 8])
/// FI
/// ENDFOR
///
@@ -1298,7 +1298,7 @@ _mm256_maskz_cvtbiassph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_bf8(__m128h __A,
@@ -1316,12 +1316,12 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_bf8(__m128h __A,
/// FOR i := 0 to 15
/// IF __U[i]
/// IF i < 8
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 8])
/// FI
/// ELSE
-/// dst.fp8 := __W.fp8[i]
+/// dst.bf8 := __W.bf8[i]
/// FI
/// ENDFOR
///
@@ -1333,7 +1333,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_bf8(__m128h __A,
/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x bf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
@@ -1341,7 +1341,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_bf8(__m128h __A,
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
@@ -1360,12 +1360,12 @@ _mm_mask_cvt2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// FOR i := 0 to 15
/// IF __U[i]
/// IF i < 8
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 8])
/// FI
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.bf8[i] := 0
/// FI
/// ENDFOR
///
@@ -1383,7 +1383,7 @@ _mm_mask_cvt2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// zero is taken instead.
@@ -1400,9 +1400,9 @@ _mm_maskz_cvt2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// \code{.operation]
/// FOR i := 0 to 32
/// IF i < 16
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 16])
/// FI
/// ENDFOR
///
@@ -1418,7 +1418,7 @@ _mm_maskz_cvt2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
@@ -1436,12 +1436,12 @@ _mm256_cvt2ph_bf8(__m256h __A, __m256h __B) {
/// FOR i := 0 to 32
/// IF __U[i]
/// IF i < 16
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 16])
/// FI
/// ELSE
-/// dst.fp8[i] := __W.fp8[i]
+/// dst.bf8[i] := __W.bf8[i]
/// FI
/// ENDFOR
///
@@ -1453,7 +1453,7 @@ _mm256_cvt2ph_bf8(__m256h __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction.
///
/// \param __W
-/// A 256-bit vector of [32 x fp8].
+/// A 256-bit vector of [32 x bf8].
/// \param __U
/// A 32-bit merging mask.
/// \param __A
@@ -1461,7 +1461,7 @@ _mm256_cvt2ph_bf8(__m256h __A, __m256h __B) {
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
@@ -1479,12 +1479,12 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_bf8(
/// \code{.operation]
/// FOR i := 0 to 32
/// IF __U[i]
-/// dst.fp8[i] := 0
+/// dst.bf8[i] := 0
/// ELSE
/// IF i < 16
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 16])
/// FI
/// FI
/// ENDFOR
@@ -1503,7 +1503,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_bf8(
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// zero is taken instead.
@@ -1521,9 +1521,9 @@ _mm256_maskz_cvt2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF i < 8
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 8])
/// FI
/// ENDFOR
///
@@ -1539,7 +1539,7 @@ _mm256_maskz_cvt2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -1557,12 +1557,12 @@ _mm_cvts2ph_bf8(__m128h __A, __m128h __B) {
/// FOR i := 0 to 15
/// IF __U[i]
/// IF i < 8
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 8])
/// FI
/// ELSE
-/// dst.fp8 := __W.fp8[i]
+/// dst.bf8 := __W.bf8[i]
/// FI
/// ENDFOR
///
@@ -1574,7 +1574,7 @@ _mm_cvts2ph_bf8(__m128h __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x bf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
@@ -1582,7 +1582,7 @@ _mm_cvts2ph_bf8(__m128h __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
@@ -1601,12 +1601,12 @@ _mm_mask_cvts2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// FOR i := 0 to 16
/// IF __U[i]
/// IF i < 8
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 8])
/// FI
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.bf8[i] := 0
/// FI
/// ENDFOR
///
@@ -1624,7 +1624,7 @@ _mm_mask_cvts2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// zero is taken instead.
@@ -1642,9 +1642,9 @@ _mm_maskz_cvts2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// \code{.operation]
/// FOR i := 0 to 32
/// IF i < 16
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 16])
/// FI
/// ENDFOR
///
@@ -1660,7 +1660,7 @@ _mm_maskz_cvts2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
@@ -1678,12 +1678,12 @@ _mm256_cvts2ph_bf8(__m256h __A, __m256h __B) {
/// FOR i := 0 to 32
/// IF __U[i]
/// IF i < 16
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 16])
/// FI
/// ELSE
-/// dst.fp8[i] := __W.fp8[i]
+/// dst.bf8[i] := __W.bf8[i]
/// FI
/// ENDFOR
///
@@ -1695,7 +1695,7 @@ _mm256_cvts2ph_bf8(__m256h __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction.
///
/// \param __W
-/// A 256-bit vector of [32 x fp8].
+/// A 256-bit vector of [32 x bf8].
/// \param __U
/// A 32-bit merging mask.
/// \param __A
@@ -1703,7 +1703,7 @@ _mm256_cvts2ph_bf8(__m256h __A, __m256h __B) {
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
@@ -1721,12 +1721,12 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_bf8(
/// \code{.operation]
/// FOR i := 0 to 32
/// IF __U[i]
-/// dst.fp8[i] := 0
+/// dst.bf8[i] := 0
/// ELSE
/// IF i < 16
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 16])
/// FI
/// FI
/// ENDFOR
@@ -1745,7 +1745,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_bf8(
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// zero is taken instead.
@@ -1762,9 +1762,9 @@ _mm256_maskz_cvts2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// \code{.operation]
/// FOR i := 0 to 16
/// IF i < 8
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 8])
/// FI
/// ENDFOR
///
@@ -1780,7 +1780,7 @@ _mm256_maskz_cvts2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_hf8(__m128h __A,
@@ -1798,12 +1798,12 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_hf8(__m128h __A,
/// FOR i := 0 to 16
/// IF __U[i]
/// IF i < 8
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 8])
/// FI
/// ELSE
-/// dst.fp8 := __W.fp8[i]
+/// dst.hf8 := __W.hf8[i]
/// FI
/// ENDFOR
///
@@ -1815,7 +1815,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_hf8(__m128h __A,
/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x hf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
@@ -1823,7 +1823,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_hf8(__m128h __A,
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
@@ -1842,12 +1842,12 @@ _mm_mask_cvt2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// FOR i := 0 to 16
/// IF __U[i]
/// IF i < 8
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 8])
/// FI
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.hf8[i] := 0
/// FI
/// ENDFOR
///
@@ -1865,7 +1865,7 @@ _mm_mask_cvt2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// zero is taken instead.
@@ -1882,9 +1882,9 @@ _mm_maskz_cvt2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// \code{.operation]
/// FOR i := 0 to 32
/// IF i < 16
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 16])
/// FI
/// ENDFOR
///
@@ -1900,7 +1900,7 @@ _mm_maskz_cvt2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
@@ -1918,12 +1918,12 @@ _mm256_cvt2ph_hf8(__m256h __A, __m256h __B) {
/// FOR i := 0 to 32
/// IF __U[i]
/// IF i < 16
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 16])
/// FI
/// ELSE
-/// dst.fp8[i] := __W.fp8[i]
+/// dst.hf8[i] := __W.hf8[i]
/// FI
/// ENDFOR
///
@@ -1935,7 +1935,7 @@ _mm256_cvt2ph_hf8(__m256h __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction.
///
/// \param __W
-/// A 256-bit vector of [32 x fp8].
+/// A 256-bit vector of [32 x hf8].
/// \param __U
/// A 32-bit merging mask.
/// \param __A
@@ -1943,7 +1943,7 @@ _mm256_cvt2ph_hf8(__m256h __A, __m256h __B) {
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
@@ -1961,12 +1961,12 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_hf8(
/// \code{.operation]
/// FOR i := 0 to 32
/// IF __U[i]
-/// dst.fp8[i] := 0
+/// dst.hf8[i] := 0
/// ELSE
/// IF i < 16
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 16])
/// FI
/// FI
/// ENDFOR
@@ -1985,7 +1985,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_hf8(
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// zero is taken instead.
@@ -2003,9 +2003,9 @@ _mm256_maskz_cvt2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// \code{.operation]
/// FOR i := 0 to 16
/// IF i < 8
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 8])
/// FI
/// ENDFOR
///
@@ -2021,7 +2021,7 @@ _mm256_maskz_cvt2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -2039,12 +2039,12 @@ _mm_cvts2ph_hf8(__m128h __A, __m128h __B) {
/// FOR i := 0 to 16
/// IF __U[i]
/// IF i < 8
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 8])
/// FI
/// ELSE
-/// dst.fp8 := __W.fp8[i]
+/// dst.hf8 := __W.hf8[i]
/// FI
/// ENDFOR
///
@@ -2056,7 +2056,7 @@ _mm_cvts2ph_hf8(__m128h __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x hf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
@@ -2064,7 +2064,7 @@ _mm_cvts2ph_hf8(__m128h __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
@@ -2083,12 +2083,12 @@ _mm_mask_cvts2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// FOR i := 0 to 16
/// IF __U[i]
/// IF i < 8
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 8])
/// FI
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.hf8[i] := 0
/// FI
/// ENDFOR
///
@@ -2106,7 +2106,7 @@ _mm_mask_cvts2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// zero is taken instead.
@@ -2124,9 +2124,9 @@ _mm_maskz_cvts2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// \code{.operation]
/// FOR i := 0 to 32
/// IF i < 16
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 16])
/// FI
/// ENDFOR
///
@@ -2142,7 +2142,7 @@ _mm_maskz_cvts2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
@@ -2160,12 +2160,12 @@ _mm256_cvts2ph_hf8(__m256h __A, __m256h __B) {
/// FOR i := 0 to 32
/// IF __U[i]
/// IF i < 16
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 16])
/// FI
/// ELSE
-/// dst.fp8[i] := __W.fp8[i]
+/// dst.hf8[i] := __W.hf8[i]
/// FI
/// ENDFOR
///
@@ -2177,7 +2177,7 @@ _mm256_cvts2ph_hf8(__m256h __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction.
///
/// \param __W
-/// A 256-bit vector of [32 x fp8].
+/// A 256-bit vector of [32 x hf8].
/// \param __U
/// A 32-bit merging mask.
/// \param __A
@@ -2185,7 +2185,7 @@ _mm256_cvts2ph_hf8(__m256h __A, __m256h __B) {
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
@@ -2203,12 +2203,12 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_hf8(
/// \code{.operation]
/// FOR i := 0 to 32
/// IF __U[i]
-/// dst.fp8[i] := 0
+/// dst.hf8[i] := 0
/// ELSE
/// IF i < 16
-/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 16])
/// FI
/// FI
/// ENDFOR
@@ -2227,7 +2227,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_hf8(
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// zero is taken instead.
@@ -2243,7 +2243,7 @@ _mm256_maskz_cvts2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
///
/// \code{.operation]
/// FOR i := 0 to 7
-/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// dst.fp16[i] := convert_hf8_to_fp16(__B.hf8[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -2254,7 +2254,7 @@ _mm256_maskz_cvts2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
///
/// \param __A
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x hf8].
/// \returns
/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A.
@@ -2271,7 +2271,7 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvthf8(__m128i __A) {
/// \code{.operation]
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp16[i] := convert_fp8_to_fp16(__A.fp8[i])
+/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i])
/// ELSE
/// dst.fp16[i] := __W.fp16[i]
/// FI
@@ -2289,7 +2289,7 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvthf8(__m128i __A) {
/// \param __U
/// A 8-bit merging mask.
/// \param __A
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x hf8].
/// \returns
/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
@@ -2308,7 +2308,7 @@ _mm_mask_cvthf8(__m128h __W, __mmask8 __U, __m128i __A) {
/// \code{.operation]
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// dst.fp16[i] := convert_hf8_to_fp16(__B.hf8[i])
/// ELSE
/// dst.fp16[i] := 0
/// FI
@@ -2324,7 +2324,7 @@ _mm_mask_cvthf8(__m128h __W, __mmask8 __U, __m128i __A) {
/// \param __U
/// A 8-bit zeroing mask.
/// \param __A
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x hf8].
/// \returns
/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
@@ -2340,7 +2340,7 @@ _mm_maskz_cvthf8(__mmask8 __U, __m128i __A) {
///
/// \code{.operation]
/// FOR i := 0 to 15
-/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// dst.fp16[i] := convert_hf8_to_fp16(__B.hf8[i])
/// ENDFOR
///
/// dst[MAX:256] := 0
@@ -2351,7 +2351,7 @@ _mm_maskz_cvthf8(__mmask8 __U, __m128i __A) {
/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
///
/// \param __A
-/// A 256-bit vector of [32 x fp8].
+/// A 256-bit vector of [32 x hf8].
/// \returns
/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A.
@@ -2369,7 +2369,7 @@ _mm256_cvthf8(__m128i __A) {
/// \code{.operation]
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp16[i] := convert_fp8_to_fp16(__A.fp8[i])
+/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i])
/// ELSE
/// dst.fp16[i] := __W.fp16[i]
/// FI
@@ -2387,7 +2387,7 @@ _mm256_cvthf8(__m128i __A) {
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [32 x fp8].
+/// A 256-bit vector of [32 x hf8].
/// \returns
/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
@@ -2406,7 +2406,7 @@ _mm256_mask_cvthf8(__m256h __W, __mmask16 __U, __m128i __A) {
/// \code{.operation]
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// dst.fp16[i] := convert_hf8_to_fp16(__B.hf8[i])
/// ELSE
/// dst.fp16[i] := 0
/// FI
@@ -2422,7 +2422,7 @@ _mm256_mask_cvthf8(__m256h __W, __mmask16 __U, __m128i __A) {
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [32 x fp8].
+/// A 256-bit vector of [32 x hf8].
/// \returns
/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
@@ -2439,7 +2439,7 @@ _mm256_maskz_cvthf8(__mmask16 __U, __m128i __A) {
///
/// \code{.operation]
/// FOR i := 0 to 7
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -2452,7 +2452,7 @@ _mm256_maskz_cvthf8(__mmask16 __U, __m128i __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the (converted)
+/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the (converted)
/// elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_bf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2bf8_128_mask(
@@ -2467,9 +2467,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_bf8(__m128h __A) {
/// \code{.operation]
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
/// ELSE
-/// dst.fp8 := __W.fp8[i]
+/// dst.bf8 := __W.bf8[i]
/// FI
/// ENDFOR
///
@@ -2481,14 +2481,14 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_bf8(__m128h __A) {
/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x bf8].
/// \param __U
/// A 8-bit merging mask.
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
///
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -2505,9 +2505,9 @@ _mm_mask_cvtph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// \code{.operation]
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := 0
+/// dst.bf8[i] := 0
/// ELSE
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
/// FI
/// ENDFOR
///
@@ -2524,7 +2524,7 @@ _mm_mask_cvtph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// A 128-bit vector of [8 x fp16].
/// \returns
///
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -2538,7 +2538,7 @@ _mm_maskz_cvtph_bf8(__mmask8 __U, __m128h __A) {
///
/// \code{.operation]
/// FOR i := 0 to 15
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -2551,7 +2551,7 @@ _mm_maskz_cvtph_bf8(__mmask8 __U, __m128h __A) {
/// \param __A
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the (converted)
+/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the (converted)
/// elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtph_bf8(__m256h __A) {
@@ -2566,9 +2566,9 @@ _mm256_cvtph_bf8(__m256h __A) {
/// \code{.operation]
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
/// ELSE
-/// dst.fp8 := __W.fp8[i]
+/// dst.bf8 := __W.bf8[i]
/// FI
/// ENDFOR
///
@@ -2580,13 +2580,13 @@ _mm256_cvtph_bf8(__m256h __A) {
/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x bf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
/// A 256-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the
/// (converted) elements from \a __A. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
@@ -2602,9 +2602,9 @@ _mm256_mask_cvtph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// \code{.operation]
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.bf8[i] := 0
/// FI
/// ENDFOR
///
@@ -2620,7 +2620,7 @@ _mm256_mask_cvtph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// \param __A
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// then element is zeroed instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
@@ -2635,7 +2635,7 @@ _mm256_maskz_cvtph_bf8(__mmask16 __U, __m256h __A) {
///
/// \code{.operation]
/// FOR i := 0 to 7
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -2648,7 +2648,7 @@ _mm256_maskz_cvtph_bf8(__mmask16 __U, __m256h __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the (converted)
+/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the (converted)
/// elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_bf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2bf8s_128_mask(
@@ -2663,9 +2663,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_bf8(__m128h __A) {
/// \code{.operation]
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
/// ELSE
-/// dst.fp8 := __W.fp8[i]
+/// dst.bf8 := __W.bf8[i]
/// FI
/// ENDFOR
///
@@ -2677,13 +2677,13 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_bf8(__m128h __A) {
/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x bf8].
/// \param __U
/// A 8-bit merging mask.
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -2700,9 +2700,9 @@ _mm_mask_cvtsph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// \code{.operation]
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.bf8[i] := 0
/// FI
/// ENDFOR
///
@@ -2718,7 +2718,7 @@ _mm_mask_cvtsph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -2732,7 +2732,7 @@ _mm_maskz_cvtsph_bf8(__mmask8 __U, __m128h __A) {
///
/// \code{.operation]
/// FOR i := 0 to 15
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -2745,7 +2745,7 @@ _mm_maskz_cvtsph_bf8(__mmask8 __U, __m128h __A) {
/// \param __A
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the (converted)
+/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the (converted)
/// elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtsph_bf8(__m256h __A) {
@@ -2761,9 +2761,9 @@ _mm256_cvtsph_bf8(__m256h __A) {
/// \code{.operation]
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
/// ELSE
-/// dst.fp8 := __W.fp8[i]
+/// dst.bf8 := __W.bf8[i]
/// FI
/// ENDFOR
///
@@ -2775,13 +2775,13 @@ _mm256_cvtsph_bf8(__m256h __A) {
/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x bf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
/// A 256-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the
/// (converted) elements from \a __A. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
@@ -2798,9 +2798,9 @@ _mm256_mask_cvtsph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// \code{.operation]
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.bf8[i] := 0
/// FI
/// ENDFOR
///
@@ -2816,7 +2816,7 @@ _mm256_mask_cvtsph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// \param __A
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// then element is zeroed instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
@@ -2831,7 +2831,7 @@ _mm256_maskz_cvtsph_bf8(__mmask16 __U, __m256h __A) {
///
/// \code{.operation]
/// FOR i := 0 to 7
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -2844,7 +2844,7 @@ _mm256_maskz_cvtsph_bf8(__mmask16 __U, __m256h __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the (converted)
+/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the (converted)
/// elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_hf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2hf8_128_mask(
@@ -2859,9 +2859,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_hf8(__m128h __A) {
/// \code{.operation]
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
/// ELSE
-/// dst.fp8 := __W.fp8[i]
+/// dst.hf8 := __W.hf8[i]
/// FI
/// ENDFOR
///
@@ -2873,14 +2873,14 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_hf8(__m128h __A) {
/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x hf8].
/// \param __U
/// A 8-bit merging mask.
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
///
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -2897,9 +2897,9 @@ _mm_mask_cvtph_hf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// \code{.operation]
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.hf8[i] := 0
/// FI
/// ENDFOR
///
@@ -2916,7 +2916,7 @@ _mm_mask_cvtph_hf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// A 128-bit vector of [8 x fp16].
/// \returns
///
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -2930,7 +2930,7 @@ _mm_maskz_cvtph_hf8(__mmask8 __U, __m128h __A) {
///
/// \code{.operation]
/// FOR i := 0 to 15
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -2943,7 +2943,7 @@ _mm_maskz_cvtph_hf8(__mmask8 __U, __m128h __A) {
/// \param __A
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the (converted)
+/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the (converted)
/// elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtph_hf8(__m256h __A) {
@@ -2958,9 +2958,9 @@ _mm256_cvtph_hf8(__m256h __A) {
/// \code{.operation]
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
/// ELSE
-/// dst.fp8 := __W.fp8[i]
+/// dst.hf8 := __W.hf8[i]
/// FI
/// ENDFOR
///
@@ -2972,13 +2972,13 @@ _mm256_cvtph_hf8(__m256h __A) {
/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x hf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
/// A 256-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the
/// (converted) elements from \a __A. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
@@ -2994,9 +2994,9 @@ _mm256_mask_cvtph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// \code{.operation]
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.hf8[i] := 0
/// FI
/// ENDFOR
///
@@ -3012,7 +3012,7 @@ _mm256_mask_cvtph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// \param __A
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// then element is zeroed instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
@@ -3027,7 +3027,7 @@ _mm256_maskz_cvtph_hf8(__mmask16 __U, __m256h __A) {
///
/// \code{.operation]
/// FOR i := 0 to 7
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -3040,7 +3040,7 @@ _mm256_maskz_cvtph_hf8(__mmask16 __U, __m256h __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the (converted)
+/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the (converted)
/// elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_hf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2hf8s_128_mask(
@@ -3055,9 +3055,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_hf8(__m128h __A) {
/// \code{.operation]
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
/// ELSE
-/// dst.fp8 := __W.fp8[i]
+/// dst.hf8 := __W.hf8[i]
/// FI
/// ENDFOR
///
@@ -3069,13 +3069,13 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_hf8(__m128h __A) {
/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x hf8].
/// \param __U
/// A 8-bit merging mask.
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -3092,9 +3092,9 @@ _mm_mask_cvtsph_hf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// \code{.operation]
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.hf8[i] := 0
/// FI
/// ENDFOR
///
@@ -3110,7 +3110,7 @@ _mm_mask_cvtsph_hf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -3124,7 +3124,7 @@ _mm_maskz_cvtsph_hf8(__mmask8 __U, __m128h __A) {
///
/// \code{.operation]
/// FOR i := 0 to 15
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -3137,7 +3137,7 @@ _mm_maskz_cvtsph_hf8(__mmask8 __U, __m128h __A) {
/// \param __A
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the (converted)
+/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the (converted)
/// elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtsph_hf8(__m256h __A) {
@@ -3153,9 +3153,9 @@ _mm256_cvtsph_hf8(__m256h __A) {
/// \code{.operation]
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
/// ELSE
-/// dst.fp8 := __W.fp8[i]
+/// dst.hf8 := __W.hf8[i]
/// FI
/// ENDFOR
///
@@ -3167,13 +3167,13 @@ _mm256_cvtsph_hf8(__m256h __A) {
/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x hf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
/// A 256-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the
/// (converted) elements from \a __A. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
@@ -3190,9 +3190,9 @@ _mm256_mask_cvtsph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// \code{.operation]
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
/// ELSE
-/// dst.fp8[i] := 0
+/// dst.hf8[i] := 0
/// FI
/// ENDFOR
///
@@ -3208,7 +3208,7 @@ _mm256_mask_cvtsph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// \param __A
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// then element is zeroed instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
@@ -3222,7 +3222,7 @@ _mm256_maskz_cvtsph_hf8(__mmask16 __U, __m256h __A) {
///
/// \code{.operation]
/// FOR i := 0 to 7
-/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// dst.fp16[i] := convert_bf8_to_fp16(__B.bf8[i])
/// ENDFOR
/// \endcode
///
@@ -3231,7 +3231,7 @@ _mm256_maskz_cvtsph_hf8(__mmask16 __U, __m256h __A) {
/// This intrinsic does not correspond to a single instruction.
///
/// \param __A
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x bf8].
/// \returns
/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A.
@@ -3247,7 +3247,7 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtbf8_ph(__m128i __A) {
/// \code{.operation]
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// dst.fp16[i] := convert_bf8_to_fp16(__B.bf8[i])
/// ELSE
/// dst.fp16[i] := __W.fp16[i]
/// FI
@@ -3263,7 +3263,7 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtbf8_ph(__m128i __A) {
/// \param __U
/// A 8-bit merging mask.
/// \param __A
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x bf8].
/// \returns
/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
@@ -3282,7 +3282,7 @@ _mm_mask_cvtbf8_ph(__m128h __W, __mmask8 __U, __m128i __A) {
/// \code{.operation]
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// dst.fp16[i] := convert_bf8_to_fp16(__B.bf8[i])
/// ELSE
/// dst.fp16[i] := 0
/// FI
@@ -3296,7 +3296,7 @@ _mm_mask_cvtbf8_ph(__m128h __W, __mmask8 __U, __m128i __A) {
/// \param __U
/// A 8-bit zeroing mask.
/// \param __A
-/// A 128-bit vector of [16 x fp8].
+/// A 128-bit vector of [16 x bf8].
/// \returns
/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
@@ -3311,7 +3311,7 @@ _mm_maskz_cvtbf8_ph(__mmask8 __U, __m128i __A) {
///
/// \code{.operation]
/// FOR i := 0 to 15
-/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// dst.fp16[i] := convert_bf8_to_fp16(__B.bf8[i])
/// ENDFOR
/// \endcode
///
@@ -3320,7 +3320,7 @@ _mm_maskz_cvtbf8_ph(__mmask8 __U, __m128i __A) {
/// This intrinsic does not correspond to a single instruction.
///
/// \param __A
-/// A 256-bit vector of [32 x fp8].
+/// A 256-bit vector of [32 x bf8].
/// \returns
/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A.
@@ -3336,7 +3336,7 @@ static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtbf8_ph(__m128i __A) {
/// \code{.operation]
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// dst.fp16[i] := convert_bf8_to_fp16(__B.bf8[i])
/// ELSE
/// dst.fp16[i] := __W.fp16[i]
/// FI
@@ -3352,7 +3352,7 @@ static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtbf8_ph(__m128i __A) {
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [32 x fp8].
+/// A 256-bit vector of [32 x bf8].
/// \returns
/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
@@ -3371,7 +3371,7 @@ _mm256_mask_cvtbf8_ph(__m256h __W, __mmask16 __U, __m128i __A) {
/// \code{.operation]
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// dst.fp16[i] := convert_bf8_to_fp16(__B.bf8[i])
/// ELSE
/// dst.fp16[i] := 0
/// FI
@@ -3385,7 +3385,7 @@ _mm256_mask_cvtbf8_ph(__m256h __W, __mmask16 __U, __m128i __A) {
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [32 x fp8].
+/// A 256-bit vector of [32 x bf8].
/// \returns
/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
>From 0560ea527fcc22a218e2e9dc3bde5e3e428c4f63 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Wed, 29 Jan 2025 14:36:36 +0100
Subject: [PATCH 03/23] 2i -> 2 * i
---
clang/lib/Headers/avx10_2convertintrin.h | 44 ++++++++++++------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 52cd08d6d2d59..63cf2f4f01683 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -408,7 +408,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -440,7 +440,7 @@ _mm_cvtbiasph_bf8(__m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ELSE
/// dst.bf8[i] := _W[i]
/// FI
@@ -480,7 +480,7 @@ _mm_mask_cvtbiasph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ELSE
/// dst.bf8[i] := 0
/// FI
@@ -516,7 +516,7 @@ _mm_maskz_cvtbiasph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -549,7 +549,7 @@ _mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ELSE
/// dst.bf8[i] := _W[i]
/// FI
@@ -589,7 +589,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_bf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ELSE
/// dst.bf8[i] := 0
/// FI
@@ -626,7 +626,7 @@ _mm256_maskz_cvtbiasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -658,7 +658,7 @@ _mm_cvtbiassph_bf8(__m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ELSE
/// dst.bf8[i] := _W[i]
/// FI
@@ -698,7 +698,7 @@ _mm_mask_cvtbiassph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ELSE
/// dst.bf8[i] := 0
/// FI
@@ -735,7 +735,7 @@ _mm_maskz_cvtbiassph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -768,7 +768,7 @@ _mm256_cvtbiassph_bf8(__m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ELSE
/// dst.bf8[i] := _W[i]
/// FI
@@ -808,7 +808,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_bf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ELSE
/// dst.bf8[i] := 0
/// FI
@@ -844,7 +844,7 @@ _mm256_maskz_cvtbiassph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -876,7 +876,7 @@ _mm_cvtbiasph_hf8(__m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ELSE
/// dst.hf8[i] := _W[i]
/// FI
@@ -916,7 +916,7 @@ _mm_mask_cvtbiasph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ELSE
/// dst.hf8[i] := 0
/// FI
@@ -985,7 +985,7 @@ _mm256_cvtbiasph_hf8(__m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ELSE
/// dst.hf8[i] := _W[i]
/// FI
@@ -1062,7 +1062,7 @@ _mm256_maskz_cvtbiasph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -1094,7 +1094,7 @@ _mm_cvtbiassph_hf8(__m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ELSE
/// dst.hf8[i] := _W[i]
/// FI
@@ -1134,7 +1134,7 @@ _mm_mask_cvtbiassph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ELSE
/// dst.hf8[i] := 0
/// FI
@@ -1171,7 +1171,7 @@ _mm_maskz_cvtbiassph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -1204,7 +1204,7 @@ _mm256_cvtbiassph_hf8(__m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ELSE
/// dst.hf8[i] := _W[i]
/// FI
@@ -1244,7 +1244,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_hf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
/// ELSE
/// dst.hf8[i] := 0
/// FI
>From 8ebd5cc5ab0ff37a2843fff1801db20c70275c98 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Mon, 3 Feb 2025 18:12:29 +0100
Subject: [PATCH 04/23] Fix wrong instr order
---
clang/lib/Headers/avx10_2convertintrin.h | 136 +++++++++++------------
1 file changed, 68 insertions(+), 68 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 63cf2f4f01683..d2a16b416bb2a 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -408,7 +408,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -419,9 +419,9 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
///
/// \param __A
-/// A 128-bit vector of [8 x fp16].
-/// \param __B
/// A 128-bit vector of [8 x int16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
/// \returns
/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the
/// sum of elements from \a __A and \a __B; higher order elements are zeroed.
@@ -440,7 +440,7 @@ _mm_cvtbiasph_bf8(__m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := _W[i]
/// FI
@@ -458,9 +458,9 @@ _mm_cvtbiasph_bf8(__m128i __A, __m128h __B) {
/// \param __U
/// A 8-bit merging mask.
/// \param __A
-/// A 128-bit vector of [8 x fp16].
-/// \param __B
/// A 128-bit vector of [8 x int16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
/// \returns
/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the sum of
/// elements from \a __A and \a __B; higher order elements are zeroed. If
@@ -480,7 +480,7 @@ _mm_mask_cvtbiasph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := 0
/// FI
@@ -496,9 +496,9 @@ _mm_mask_cvtbiasph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \param __U
/// A 8-bit zeroing mask.
/// \param __A
-/// A 128-bit vector of [8 x fp16].
-/// \param __B
/// A 128-bit vector of [8 x int16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
/// \returns
/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the sum of
/// elements from \a __A and \a __B; higher order elements are zeroed. If
@@ -516,7 +516,7 @@ _mm_maskz_cvtbiasph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -527,9 +527,9 @@ _mm_maskz_cvtbiasph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
///
/// \param __A
-/// A 256-bit vector of [16 x fp16].
-/// \param __B
/// A 256-bit vector of [16 x int16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
/// \returns
/// A 128-bit vector of [16 x bf8]. Elements correspond to the
/// sum of elements from \a __A and \a __B.
@@ -549,7 +549,7 @@ _mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := _W[i]
/// FI
@@ -567,9 +567,9 @@ _mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) {
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
-/// \param __B
/// A 256-bit vector of [16 x int16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
/// \returns
/// A 128-bit vector of [16 x bf8]. Elements correspond to the sum of
/// elements from \a __A and \a __B. If corresponding mask bit is not set, then
@@ -589,7 +589,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_bf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := 0
/// FI
@@ -605,9 +605,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_bf8(
/// \param __U
/// A 16-bit zeroing mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
-/// \param __B
/// A 256-bit vector of [16 x int16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
/// \returns
/// A 128-bit vector of [16 x bf8]. Elements correspond to the sum of
/// elements from \a __A and \a __B. If corresponding mask bit is not set,
@@ -626,7 +626,7 @@ _mm256_maskz_cvtbiasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -637,9 +637,9 @@ _mm256_maskz_cvtbiasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
///
/// \param __A
-/// A 128-bit vector of [8 x fp16].
-/// \param __B
/// A 128-bit vector of [8 x int16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
/// \returns
/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the
/// sum of elements from \a __A and \a __B; higher order elements are zeroed.
@@ -658,7 +658,7 @@ _mm_cvtbiassph_bf8(__m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := _W[i]
/// FI
@@ -676,9 +676,9 @@ _mm_cvtbiassph_bf8(__m128i __A, __m128h __B) {
/// \param __U
/// A 8-bit merging mask.
/// \param __A
-/// A 128-bit vector of [8 x fp16].
-/// \param __B
/// A 128-bit vector of [8 x int16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
/// \returns
/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the sum of
/// elements from \a __A and \a __B; higher order elements are zeroed. If
@@ -698,7 +698,7 @@ _mm_mask_cvtbiassph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := 0
/// FI
@@ -714,9 +714,9 @@ _mm_mask_cvtbiassph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \param __U
/// A 8-bit zeroing mask.
/// \param __A
-/// A 128-bit vector of [8 x fp16].
-/// \param __B
/// A 128-bit vector of [8 x int16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
/// \returns
/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the sum of
/// elements from \a __A and \a __B; higher order elements are zeroed. If
@@ -735,7 +735,7 @@ _mm_maskz_cvtbiassph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -746,9 +746,9 @@ _mm_maskz_cvtbiassph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.
///
/// \param __A
-/// A 256-bit vector of [16 x fp16].
-/// \param __B
/// A 256-bit vector of [16 x int16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
/// \returns
/// A 128-bit vector of [16 x bf8]. Elements correspond to the
/// sum of elements from \a __A and \a __B.
@@ -768,7 +768,7 @@ _mm256_cvtbiassph_bf8(__m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := _W[i]
/// FI
@@ -786,9 +786,9 @@ _mm256_cvtbiassph_bf8(__m256i __A, __m256h __B) {
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
-/// \param __B
/// A 256-bit vector of [16 x int16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
/// \returns
/// A 128-bit vector of [16 x bf8]. Elements correspond to the sum of
/// elements from \a __A and \a __B. If corresponding mask bit is not set, then
@@ -808,7 +808,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_bf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := 0
/// FI
@@ -824,9 +824,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_bf8(
/// \param __U
/// A 16-bit zeroing mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
-/// \param __B
/// A 256-bit vector of [16 x int16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
/// \returns
/// A 128-bit vector of [16 x bf8]. Elements correspond to the sum of
/// elements from \a __A and \a __B. If corresponding mask bit is not set,
@@ -844,7 +844,7 @@ _mm256_maskz_cvtbiassph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -855,9 +855,9 @@ _mm256_maskz_cvtbiassph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.
///
/// \param __A
-/// A 128-bit vector of [8 x fp16].
-/// \param __B
/// A 128-bit vector of [8 x int16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
/// \returns
/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the
/// sum of elements from \a __A and \a __B; higher order elements are zeroed.
@@ -876,7 +876,7 @@ _mm_cvtbiasph_hf8(__m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := _W[i]
/// FI
@@ -894,9 +894,9 @@ _mm_cvtbiasph_hf8(__m128i __A, __m128h __B) {
/// \param __U
/// A 8-bit merging mask.
/// \param __A
-/// A 128-bit vector of [8 x fp16].
-/// \param __B
/// A 128-bit vector of [8 x int16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
/// \returns
/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the sum of
/// elements from \a __A and \a __B; higher order elements are zeroed. If
@@ -916,7 +916,7 @@ _mm_mask_cvtbiasph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := 0
/// FI
@@ -932,9 +932,9 @@ _mm_mask_cvtbiasph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \param __U
/// A 8-bit zeroing mask.
/// \param __A
-/// A 128-bit vector of [8 x fp16].
-/// \param __B
/// A 128-bit vector of [8 x int16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
/// \returns
/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the sum of
/// elements from \a __A and \a __B; higher order elements are zeroed. If
@@ -952,7 +952,7 @@ _mm_maskz_cvtbiasph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.hf8[i] := add_fp16_int8_convert_to_hf8(__A.fp16[i], __B.int8[2 * i])
+/// dst.hf8[i] := add_fp16_int8_convert_to_hf8(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -985,7 +985,7 @@ _mm256_cvtbiasph_hf8(__m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := _W[i]
/// FI
@@ -1003,9 +1003,9 @@ _mm256_cvtbiasph_hf8(__m256i __A, __m256h __B) {
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
-/// \param __B
/// A 256-bit vector of [16 x int16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
/// \returns
/// A 128-bit vector of [16 x hf8]. Elements correspond to the sum of
/// elements from \a __A and \a __B. If corresponding mask bit is not set, then
@@ -1025,7 +1025,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_hf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.hf8[i] := add_fp16_int8_convert_to_hf8(__A.fp16[i], __B.int8[2 * i])
+/// dst.hf8[i] := add_fp16_int8_convert_to_hf8(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := 0
/// FI
@@ -1062,7 +1062,7 @@ _mm256_maskz_cvtbiasph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -1073,9 +1073,9 @@ _mm256_maskz_cvtbiasph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S`instruction.
///
/// \param __A
-/// A 128-bit vector of [8 x fp16].
-/// \param __B
/// A 128-bit vector of [8 x int16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
/// \returns
/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the
/// sum of elements from \a __A and \a __B; higher order elements are zeroed.
@@ -1094,7 +1094,7 @@ _mm_cvtbiassph_hf8(__m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := _W[i]
/// FI
@@ -1112,9 +1112,9 @@ _mm_cvtbiassph_hf8(__m128i __A, __m128h __B) {
/// \param __U
/// A 8-bit merging mask.
/// \param __A
-/// A 128-bit vector of [8 x fp16].
-/// \param __B
/// A 128-bit vector of [8 x int16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
/// \returns
/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the sum of
/// elements from \a __A and \a __B; higher order elements are zeroed. If
@@ -1134,7 +1134,7 @@ _mm_mask_cvtbiassph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := 0
/// FI
@@ -1150,9 +1150,9 @@ _mm_mask_cvtbiassph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \param __U
/// A 8-bit zeroing mask.
/// \param __A
-/// A 128-bit vector of [8 x fp16].
-/// \param __B
/// A 128-bit vector of [8 x int16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
/// \returns
/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the sum of
/// elements from \a __A and \a __B; higher order elements are zeroed. If
@@ -1171,7 +1171,7 @@ _mm_maskz_cvtbiassph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -1182,9 +1182,9 @@ _mm_maskz_cvtbiassph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.
///
/// \param __A
-/// A 256-bit vector of [16 x fp16].
-/// \param __B
/// A 256-bit vector of [16 x int16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
/// \returns
/// A 128-bit vector of [16 x hf8]. Elements correspond to the
/// sum of elements from \a __A and \a __B.
@@ -1204,7 +1204,7 @@ _mm256_cvtbiassph_hf8(__m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := _W[i]
/// FI
@@ -1222,9 +1222,9 @@ _mm256_cvtbiassph_hf8(__m256i __A, __m256h __B) {
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
-/// \param __B
/// A 256-bit vector of [16 x int16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
/// \returns
/// A 128-bit vector of [16 x hf8]. Elements correspond to the sum of
/// elements from \a __A and \a __B. If corresponding mask bit is not set, then
@@ -1244,7 +1244,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_hf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.fp16[i], __B.int8[2 * i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := 0
/// FI
@@ -1260,9 +1260,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_hf8(
/// \param __U
/// A 16-bit zeroing mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
-/// \param __B
/// A 256-bit vector of [16 x int16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
/// \returns
/// A 128-bit vector of [16 x hf8]. Elements correspond to the sum of
/// elements from \a __A and \a __B. If corresponding mask bit is not set,
>From 758dd4c07c6adea9f6e87cf5a2f458ed20bd2eec Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Tue, 4 Feb 2025 05:15:43 -0800
Subject: [PATCH 05/23] Fix wrong brackets
---
clang/lib/Headers/avx10_2convertintrin.h | 112 +++++++++++------------
1 file changed, 56 insertions(+), 56 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index d2a16b416bb2a..587aa4b2737b3 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -1312,7 +1312,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_bf8(__m128h __A,
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// IF i < 8
@@ -1397,7 +1397,7 @@ _mm_maskz_cvt2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF i < 16
/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
@@ -1432,7 +1432,7 @@ _mm256_cvt2ph_bf8(__m256h __A, __m256h __B) {
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF __U[i]
/// IF i < 16
@@ -1476,7 +1476,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_bf8(
/// Merging mask \a __U is used to determine if given element should be zeroed
/// instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF __U[i]
/// dst.bf8[i] := 0
@@ -1597,7 +1597,7 @@ _mm_mask_cvts2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// Zeroing mask \a __U is used to determine if given element should be zeroed
/// instead. Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 16
/// IF __U[i]
/// IF i < 8
@@ -1639,7 +1639,7 @@ _mm_maskz_cvts2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
/// Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF i < 16
/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
@@ -1674,7 +1674,7 @@ _mm256_cvts2ph_bf8(__m256h __A, __m256h __B) {
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead. Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF __U[i]
/// IF i < 16
@@ -1718,7 +1718,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_bf8(
/// Merging mask \a __U is used to determine if given element should be zeroed
/// instead. Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF __U[i]
/// dst.bf8[i] := 0
@@ -1759,7 +1759,7 @@ _mm256_maskz_cvts2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 16
/// IF i < 8
/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
@@ -1794,7 +1794,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_hf8(__m128h __A,
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 16
/// IF __U[i]
/// IF i < 8
@@ -1838,7 +1838,7 @@ _mm_mask_cvt2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// Zeroing mask \a __U is used to determine if given element should be zeroed
/// instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 16
/// IF __U[i]
/// IF i < 8
@@ -1879,7 +1879,7 @@ _mm_maskz_cvt2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF i < 16
/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
@@ -1914,7 +1914,7 @@ _mm256_cvt2ph_hf8(__m256h __A, __m256h __B) {
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF __U[i]
/// IF i < 16
@@ -1958,7 +1958,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_hf8(
/// Merging mask \a __U is used to determine if given element should be zeroed
/// instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF __U[i]
/// dst.hf8[i] := 0
@@ -2000,7 +2000,7 @@ _mm256_maskz_cvt2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
/// Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 16
/// IF i < 8
/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
@@ -2035,7 +2035,7 @@ _mm_cvts2ph_hf8(__m128h __A, __m128h __B) {
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead. Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 16
/// IF __U[i]
/// IF i < 8
@@ -2079,7 +2079,7 @@ _mm_mask_cvts2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// Zeroing mask \a __U is used to determine if given element should be zeroed
/// instead. Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 16
/// IF __U[i]
/// IF i < 8
@@ -2121,7 +2121,7 @@ _mm_maskz_cvts2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
/// Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF i < 16
/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
@@ -2156,7 +2156,7 @@ _mm256_cvts2ph_hf8(__m256h __A, __m256h __B) {
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead. Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF __U[i]
/// IF i < 16
@@ -2200,7 +2200,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_hf8(
/// Merging mask \a __U is used to determine if given element should be zeroed
/// instead. Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF __U[i]
/// dst.hf8[i] := 0
@@ -2241,7 +2241,7 @@ _mm256_maskz_cvts2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// Convert 128-bit vector \a __A, containing packed FP8 E4M3 floating-point
/// elements to a 128-bit vector containing FP16 elements. The conversion is exact.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// dst.fp16[i] := convert_hf8_to_fp16(__B.hf8[i])
/// ENDFOR
@@ -2268,7 +2268,7 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvthf8(__m128i __A) {
/// exact. Merging mask \a __U is used to determine if given element should be
/// taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i])
@@ -2305,7 +2305,7 @@ _mm_mask_cvthf8(__m128h __W, __mmask8 __U, __m128i __A) {
/// exact. Zeroing mask \a __U is used to determine if given element should be
/// zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.fp16[i] := convert_hf8_to_fp16(__B.hf8[i])
@@ -2338,7 +2338,7 @@ _mm_maskz_cvthf8(__mmask8 __U, __m128i __A) {
/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point
/// elements to a 256-bit vector containing FP16 elements. The conversion is exact.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// dst.fp16[i] := convert_hf8_to_fp16(__B.hf8[i])
/// ENDFOR
@@ -2366,7 +2366,7 @@ _mm256_cvthf8(__m128i __A) {
/// exact. Merging mask \a __U is used to determine if given element should be
/// taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i])
@@ -2403,7 +2403,7 @@ _mm256_mask_cvthf8(__m256h __W, __mmask16 __U, __m128i __A) {
/// exact. Zeroing mask \a __U is used to determine if given element should be
/// zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp16[i] := convert_hf8_to_fp16(__B.hf8[i])
@@ -2437,7 +2437,7 @@ _mm256_maskz_cvthf8(__mmask16 __U, __m128i __A) {
/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
/// resulting vector are zeroed.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
/// ENDFOR
@@ -2464,7 +2464,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_bf8(__m128h __A) {
/// resulting vector are zeroed. Merging mask \a __U is used to determine if
/// given element should be taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
@@ -2502,7 +2502,7 @@ _mm_mask_cvtph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// resulting vector are zeroed. Zeroing mask \a __U is used to determine if
/// given element should be zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.bf8[i] := 0
@@ -2536,7 +2536,7 @@ _mm_maskz_cvtph_bf8(__mmask8 __U, __m128h __A) {
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
/// to a 128-bit vector containing E5M2 FP8 elements.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
/// ENDFOR
@@ -2563,7 +2563,7 @@ _mm256_cvtph_bf8(__m256h __A) {
/// to a 128-bit vector containing E5M2 FP8 elements. Merging mask \a __U is
/// used to determine if given element should be taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
@@ -2599,7 +2599,7 @@ _mm256_mask_cvtph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// to a 128-bit vector containing E5M2 FP8 elements. Zeroing mask \a __U is
/// used to determine if given element should be zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
@@ -2633,7 +2633,7 @@ _mm256_maskz_cvtph_bf8(__mmask16 __U, __m256h __A) {
/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
/// resulting vector are zeroed. Results are saturated.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
/// ENDFOR
@@ -2660,7 +2660,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_bf8(__m128h __A) {
/// resulting vector are zeroed. Results are saturated. Merging mask \a __U is
/// used to determine if given element should be taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
@@ -2697,7 +2697,7 @@ _mm_mask_cvtsph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// resulting vector are zeroed. Results are saturated. Zeroing mask \a __U is
/// used to determine if given element should be zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
@@ -2730,7 +2730,7 @@ _mm_maskz_cvtsph_bf8(__mmask8 __U, __m128h __A) {
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
/// ENDFOR
@@ -2758,7 +2758,7 @@ _mm256_cvtsph_bf8(__m256h __A) {
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
@@ -2795,7 +2795,7 @@ _mm256_mask_cvtsph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// Zeroing mask \a __U is used to determine if given element should be zeroed
/// instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
@@ -2829,7 +2829,7 @@ _mm256_maskz_cvtsph_bf8(__mmask16 __U, __m256h __A) {
/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
/// resulting vector are zeroed.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
/// ENDFOR
@@ -2856,7 +2856,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_hf8(__m128h __A) {
/// resulting vector are zeroed. Merging mask \a __U is used to determine if
/// given element should be taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
@@ -2894,7 +2894,7 @@ _mm_mask_cvtph_hf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// resulting vector are zeroed. Zeroing mask \a __U is used to determine if
/// given element should be zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
@@ -2928,7 +2928,7 @@ _mm_maskz_cvtph_hf8(__mmask8 __U, __m128h __A) {
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
/// to a 128-bit vector containing E4M3 FP8 elements.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
/// ENDFOR
@@ -2955,7 +2955,7 @@ _mm256_cvtph_hf8(__m256h __A) {
/// to a 128-bit vector containing E4M3 FP8 elements. Merging mask \a __U is
/// used to determine if given element should be taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
@@ -2991,7 +2991,7 @@ _mm256_mask_cvtph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// to a 128-bit vector containing E4M3 FP8 elements. Zeroing mask \a __U is
/// used to determine if given element should be zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
@@ -3025,7 +3025,7 @@ _mm256_maskz_cvtph_hf8(__mmask16 __U, __m256h __A) {
/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
/// resulting vector are zeroed. Results are saturated.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
/// ENDFOR
@@ -3052,7 +3052,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_hf8(__m128h __A) {
/// resulting vector are zeroed. Results are saturated. Merging mask \a __U is
/// used to determine if given element should be taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
@@ -3089,7 +3089,7 @@ _mm_mask_cvtsph_hf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// resulting vector are zeroed. Results are saturated. Zeroing mask \a __U is
/// used to determine if given element should be zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
@@ -3122,7 +3122,7 @@ _mm_maskz_cvtsph_hf8(__mmask8 __U, __m128h __A) {
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
/// ENDFOR
@@ -3150,7 +3150,7 @@ _mm256_cvtsph_hf8(__m256h __A) {
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
@@ -3187,7 +3187,7 @@ _mm256_mask_cvtsph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// Zeroing mask \a __U is used to determine if given element should be zeroed
/// instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
@@ -3220,7 +3220,7 @@ _mm256_maskz_cvtsph_hf8(__mmask16 __U, __m256h __A) {
/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point
/// elements to a 128-bit vector containing FP16 elements. The conversion is exact.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// dst.fp16[i] := convert_bf8_to_fp16(__B.bf8[i])
/// ENDFOR
@@ -3244,7 +3244,7 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtbf8_ph(__m128i __A) {
/// exact. Merging mask \a __U is used to determine if given element should be
/// taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.fp16[i] := convert_bf8_to_fp16(__B.bf8[i])
@@ -3279,7 +3279,7 @@ _mm_mask_cvtbf8_ph(__m128h __W, __mmask8 __U, __m128i __A) {
/// exact. Zeroing mask \a __U is used to determine if given element should be
/// zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.fp16[i] := convert_bf8_to_fp16(__B.bf8[i])
@@ -3309,7 +3309,7 @@ _mm_maskz_cvtbf8_ph(__mmask8 __U, __m128i __A) {
/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point
/// elements to a 256-bit vector containing FP16 elements. The conversion is exact.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// dst.fp16[i] := convert_bf8_to_fp16(__B.bf8[i])
/// ENDFOR
@@ -3333,7 +3333,7 @@ static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtbf8_ph(__m128i __A) {
/// exact. Merging mask \a __U is used to determine if given element should be
/// taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp16[i] := convert_bf8_to_fp16(__B.bf8[i])
@@ -3368,7 +3368,7 @@ _mm256_mask_cvtbf8_ph(__m256h __W, __mmask16 __U, __m128i __A) {
/// exact. Zeroing mask \a __U is used to determine if given element should be
/// zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp16[i] := convert_bf8_to_fp16(__B.bf8[i])
>From 74c4a2d52605f1dfe1ea50692aa281015f5c2408 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Wed, 5 Feb 2025 04:49:14 -0800
Subject: [PATCH 06/23] Fix wrong loop bounds
---
clang/lib/Headers/avx10_2convertintrin.h | 38 ++++++++++++------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 587aa4b2737b3..a9261908241e8 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -1398,7 +1398,7 @@ _mm_maskz_cvt2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF i < 16
/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
/// ELSE
@@ -1433,7 +1433,7 @@ _mm256_cvt2ph_bf8(__m256h __A, __m256h __B) {
/// from \a __W instead.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF __U[i]
/// IF i < 16
/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
@@ -1477,7 +1477,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_bf8(
/// instead.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF __U[i]
/// dst.bf8[i] := 0
/// ELSE
@@ -1598,7 +1598,7 @@ _mm_mask_cvts2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// instead. Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 16
+/// FOR i := 0 to 15
/// IF __U[i]
/// IF i < 8
/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
@@ -1640,7 +1640,7 @@ _mm_maskz_cvts2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF i < 16
/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
/// ELSE
@@ -1675,7 +1675,7 @@ _mm256_cvts2ph_bf8(__m256h __A, __m256h __B) {
/// from \a __W instead. Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF __U[i]
/// IF i < 16
/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
@@ -1719,7 +1719,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_bf8(
/// instead. Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF __U[i]
/// dst.bf8[i] := 0
/// ELSE
@@ -1760,7 +1760,7 @@ _mm256_maskz_cvts2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
///
/// \code{.operation}
-/// FOR i := 0 to 16
+/// FOR i := 0 to 15
/// IF i < 8
/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
/// ELSE
@@ -1795,7 +1795,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_hf8(__m128h __A,
/// from \a __W instead.
///
/// \code{.operation}
-/// FOR i := 0 to 16
+/// FOR i := 0 to 15
/// IF __U[i]
/// IF i < 8
/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
@@ -1839,7 +1839,7 @@ _mm_mask_cvt2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// instead.
///
/// \code{.operation}
-/// FOR i := 0 to 16
+/// FOR i := 0 to 15
/// IF __U[i]
/// IF i < 8
/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
@@ -1880,7 +1880,7 @@ _mm_maskz_cvt2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF i < 16
/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
/// ELSE
@@ -1915,7 +1915,7 @@ _mm256_cvt2ph_hf8(__m256h __A, __m256h __B) {
/// from \a __W instead.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF __U[i]
/// IF i < 16
/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
@@ -1959,7 +1959,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_hf8(
/// instead.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF __U[i]
/// dst.hf8[i] := 0
/// ELSE
@@ -2001,7 +2001,7 @@ _mm256_maskz_cvt2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 16
+/// FOR i := 0 to 15
/// IF i < 8
/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
/// ELSE
@@ -2036,7 +2036,7 @@ _mm_cvts2ph_hf8(__m128h __A, __m128h __B) {
/// from \a __W instead. Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 16
+/// FOR i := 0 to 15
/// IF __U[i]
/// IF i < 8
/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
@@ -2080,7 +2080,7 @@ _mm_mask_cvts2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// instead. Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 16
+/// FOR i := 0 to 15
/// IF __U[i]
/// IF i < 8
/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
@@ -2122,7 +2122,7 @@ _mm_maskz_cvts2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF i < 16
/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
/// ELSE
@@ -2157,7 +2157,7 @@ _mm256_cvts2ph_hf8(__m256h __A, __m256h __B) {
/// from \a __W instead. Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF __U[i]
/// IF i < 16
/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
@@ -2201,7 +2201,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_hf8(
/// instead. Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF __U[i]
/// dst.hf8[i] := 0
/// ELSE
>From f42a5885ccc7a53acb0e466454ddbc4482c1e40d Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Wed, 5 Feb 2025 05:15:34 -0800
Subject: [PATCH 07/23] Rename wrong var
---
clang/lib/Headers/avx10_2convertintrin.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index a9261908241e8..cc2cd1b3e2b62 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -3222,7 +3222,7 @@ _mm256_maskz_cvtsph_hf8(__mmask16 __U, __m256h __A) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.fp16[i] := convert_bf8_to_fp16(__B.bf8[i])
+/// dst.fp16[i] := convert_bf8_to_fp16(__A.bf8[i])
/// ENDFOR
/// \endcode
///
@@ -3247,7 +3247,7 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtbf8_ph(__m128i __A) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp16[i] := convert_bf8_to_fp16(__B.bf8[i])
+/// dst.fp16[i] := convert_bf8_to_fp16(__A.bf8[i])
/// ELSE
/// dst.fp16[i] := __W.fp16[i]
/// FI
@@ -3282,7 +3282,7 @@ _mm_mask_cvtbf8_ph(__m128h __W, __mmask8 __U, __m128i __A) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp16[i] := convert_bf8_to_fp16(__B.bf8[i])
+/// dst.fp16[i] := convert_bf8_to_fp16(__A.bf8[i])
/// ELSE
/// dst.fp16[i] := 0
/// FI
@@ -3311,7 +3311,7 @@ _mm_maskz_cvtbf8_ph(__mmask8 __U, __m128i __A) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.fp16[i] := convert_bf8_to_fp16(__B.bf8[i])
+/// dst.fp16[i] := convert_bf8_to_fp16(__A.bf8[i])
/// ENDFOR
/// \endcode
///
@@ -3336,7 +3336,7 @@ static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtbf8_ph(__m128i __A) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp16[i] := convert_bf8_to_fp16(__B.bf8[i])
+/// dst.fp16[i] := convert_bf8_to_fp16(__A.bf8[i])
/// ELSE
/// dst.fp16[i] := __W.fp16[i]
/// FI
@@ -3371,7 +3371,7 @@ _mm256_mask_cvtbf8_ph(__m256h __W, __mmask16 __U, __m128i __A) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp16[i] := convert_bf8_to_fp16(__B.bf8[i])
+/// dst.fp16[i] := convert_bf8_to_fp16(__A.bf8[i])
/// ELSE
/// dst.fp16[i] := 0
/// FI
>From 9b4569db3caaeac5b44758813d344f1f95de0451 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Mon, 10 Feb 2025 02:22:36 -0800
Subject: [PATCH 08/23] Add saturate info
---
clang/lib/Headers/avx10_2convertintrin.h | 72 ++++++++++++------------
1 file changed, 36 insertions(+), 36 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index cc2cd1b3e2b62..bcaa188fbec22 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -626,7 +626,7 @@ _mm256_maskz_cvtbiasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -658,7 +658,7 @@ _mm_cvtbiassph_bf8(__m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := _W[i]
/// FI
@@ -698,7 +698,7 @@ _mm_mask_cvtbiassph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := 0
/// FI
@@ -735,7 +735,7 @@ _mm_maskz_cvtbiassph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -768,7 +768,7 @@ _mm256_cvtbiassph_bf8(__m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := _W[i]
/// FI
@@ -808,7 +808,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_bf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := 0
/// FI
@@ -1062,7 +1062,7 @@ _mm256_maskz_cvtbiasph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -1094,7 +1094,7 @@ _mm_cvtbiassph_hf8(__m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := _W[i]
/// FI
@@ -1134,7 +1134,7 @@ _mm_mask_cvtbiassph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := 0
/// FI
@@ -1171,7 +1171,7 @@ _mm_maskz_cvtbiassph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -1204,7 +1204,7 @@ _mm256_cvtbiassph_hf8(__m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := _W[i]
/// FI
@@ -1244,7 +1244,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_hf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := 0
/// FI
@@ -1521,9 +1521,9 @@ _mm256_maskz_cvt2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF i < 8
-/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i])
/// ELSE
-/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 8])
+/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 8])
/// FI
/// ENDFOR
///
@@ -1557,9 +1557,9 @@ _mm_cvts2ph_bf8(__m128h __A, __m128h __B) {
/// FOR i := 0 to 15
/// IF __U[i]
/// IF i < 8
-/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i])
/// ELSE
-/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 8])
+/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 8])
/// FI
/// ELSE
/// dst.bf8 := __W.bf8[i]
@@ -1601,9 +1601,9 @@ _mm_mask_cvts2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// FOR i := 0 to 15
/// IF __U[i]
/// IF i < 8
-/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i])
/// ELSE
-/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 8])
+/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 8])
/// FI
/// ELSE
/// dst.bf8[i] := 0
@@ -1642,9 +1642,9 @@ _mm_maskz_cvts2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 31
/// IF i < 16
-/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i])
/// ELSE
-/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 16])
+/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 16])
/// FI
/// ENDFOR
///
@@ -1678,9 +1678,9 @@ _mm256_cvts2ph_bf8(__m256h __A, __m256h __B) {
/// FOR i := 0 to 31
/// IF __U[i]
/// IF i < 16
-/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i])
/// ELSE
-/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 16])
+/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 16])
/// FI
/// ELSE
/// dst.bf8[i] := __W.bf8[i]
@@ -1724,9 +1724,9 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_bf8(
/// dst.bf8[i] := 0
/// ELSE
/// IF i < 16
-/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i])
/// ELSE
-/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 16])
+/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 16])
/// FI
/// FI
/// ENDFOR
@@ -2635,7 +2635,7 @@ _mm256_maskz_cvtph_bf8(__mmask16 __U, __m256h __A) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -2663,7 +2663,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_bf8(__m128h __A) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i])
/// ELSE
/// dst.bf8 := __W.bf8[i]
/// FI
@@ -2700,7 +2700,7 @@ _mm_mask_cvtsph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i])
/// ELSE
/// dst.bf8[i] := 0
/// FI
@@ -2732,7 +2732,7 @@ _mm_maskz_cvtsph_bf8(__mmask8 __U, __m128h __A) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -2761,7 +2761,7 @@ _mm256_cvtsph_bf8(__m256h __A) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i])
/// ELSE
/// dst.bf8 := __W.bf8[i]
/// FI
@@ -2798,7 +2798,7 @@ _mm256_mask_cvtsph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i])
/// ELSE
/// dst.bf8[i] := 0
/// FI
@@ -3027,7 +3027,7 @@ _mm256_maskz_cvtph_hf8(__mmask16 __U, __m256h __A) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -3055,7 +3055,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_hf8(__m128h __A) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i])
/// ELSE
/// dst.hf8 := __W.hf8[i]
/// FI
@@ -3092,7 +3092,7 @@ _mm_mask_cvtsph_hf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i])
/// ELSE
/// dst.hf8[i] := 0
/// FI
@@ -3124,7 +3124,7 @@ _mm_maskz_cvtsph_hf8(__mmask8 __U, __m128h __A) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -3153,7 +3153,7 @@ _mm256_cvtsph_hf8(__m256h __A) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i])
/// ELSE
/// dst.hf8 := __W.hf8[i]
/// FI
@@ -3190,7 +3190,7 @@ _mm256_mask_cvtsph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i])
/// ELSE
/// dst.hf8[i] := 0
/// FI
>From 1313a90ded0fd1a88931e78e4acb63daba16e649 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Mon, 17 Feb 2025 09:17:21 -0800
Subject: [PATCH 09/23] Rename define vars
---
clang/lib/Headers/avx10_2convertintrin.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index ff87fd4150a75..948629b877ac4 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -303,10 +303,10 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
-#define _mm256_cvtx_round2ps_ph(A, B, R) \
+#define _mm256_cvtx_round2ps_ph(__A, __B, __R) \
((__m256h)__builtin_ia32_vcvt2ps2phx256_mask( \
- (__v8sf)(A), (__v8sf)(B), (__v16hf)_mm256_undefined_ph(), \
- (__mmask16)(-1), (const int)(R)))
+ (__v8sf)(__A), (__v8sf)(__B), (__v16hf)_mm256_undefined_ph(), \
+ (__mmask16)(-1), (const int)(__R)))
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
/// single-precision (32-bit) floating-point elements to a 256-bit vector
@@ -352,9 +352,9 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
-#define _mm256_mask_cvtx_round2ps_ph(W, U, A, B, R) \
+#define _mm256_mask_cvtx_round2ps_ph(__W, __U, __A, __B, __R) \
((__m256h)__builtin_ia32_vcvt2ps2phx256_mask( \
- (__v8sf)(A), (__v8sf)(B), (__v16hf)(W), (__mmask16)(U), (const int)(R)))
+ (__v8sf)(__A), (__v8sf)(__B), (__v16hf)(__W), (__mmask16)(__U), (const int)(__R)))
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
/// single-precision (32-bit) floating-point elements to a 256-bit vector
@@ -397,10 +397,10 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// then zero is taken instead.
-#define _mm256_maskz_cvtx_round2ps_ph(U, A, B, R) \
+#define _mm256_maskz_cvtx_round2ps_ph(__U, __A, __B, __R) \
((__m256h)__builtin_ia32_vcvt2ps2phx256_mask( \
- (__v8sf)(A), (__v8sf)(B), (__v16hf)(_mm256_setzero_ph()), \
- (__mmask16)(U), (const int)(R)))
+ (__v8sf)(__A), (__v8sf)(__B), (__v16hf)(_mm256_setzero_ph()), \
+ (__mmask16)(__U), (const int)(__R)))
/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements and 8-bit integers stored in the lower half of
>From 3befbd86a2941eedd16205a00374d2fe515b1a1a Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Wed, 19 Feb 2025 05:19:34 -0800
Subject: [PATCH 10/23] Typo fix
---
clang/lib/Headers/avx10_2convertintrin.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 948629b877ac4..5dd3e58849aa9 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -2243,7 +2243,7 @@ _mm256_maskz_cvts2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.fp16[i] := convert_hf8_to_fp16(__B.hf8[i])
+/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -2308,7 +2308,7 @@ _mm_mask_cvthf8_ph(__m128h __W, __mmask8 __U, __m128i __A) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp16[i] := convert_hf8_to_fp16(__B.hf8[i])
+/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i])
/// ELSE
/// dst.fp16[i] := 0
/// FI
@@ -2340,7 +2340,7 @@ _mm_maskz_cvthf8_ph(__mmask8 __U, __m128i __A) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.fp16[i] := convert_hf8_to_fp16(__B.hf8[i])
+/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i])
/// ENDFOR
///
/// dst[MAX:256] := 0
@@ -2405,7 +2405,7 @@ _mm256_mask_cvthf8_ph(__m256h __W, __mmask16 __U, __m128i __A) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp16[i] := convert_hf8_to_fp16(__B.hf8[i])
+/// dst.fp16[i] := convert_hf8_to_fp16(__A.hf8[i])
/// ELSE
/// dst.fp16[i] := 0
/// FI
>From dac8d913f7f6070618405ccf181440135187a3a2 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Fri, 21 Feb 2025 05:15:59 -0800
Subject: [PATCH 11/23] Add missing saturate
---
clang/lib/Headers/avx10_2convertintrin.h | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 5dd3e58849aa9..9d869138a32fd 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -2003,9 +2003,9 @@ _mm256_maskz_cvt2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF i < 8
-/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i])
/// ELSE
-/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 8])
+/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 8])
/// FI
/// ENDFOR
///
@@ -2039,9 +2039,9 @@ _mm_cvts2ph_hf8(__m128h __A, __m128h __B) {
/// FOR i := 0 to 15
/// IF __U[i]
/// IF i < 8
-/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i])
/// ELSE
-/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 8])
+/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 8])
/// FI
/// ELSE
/// dst.hf8 := __W.hf8[i]
@@ -2083,9 +2083,9 @@ _mm_mask_cvts2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// FOR i := 0 to 15
/// IF __U[i]
/// IF i < 8
-/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i])
/// ELSE
-/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 8])
+/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 8])
/// FI
/// ELSE
/// dst.hf8[i] := 0
@@ -2124,9 +2124,9 @@ _mm_maskz_cvts2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 31
/// IF i < 16
-/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i])
/// ELSE
-/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 16])
+/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 16])
/// FI
/// ENDFOR
///
@@ -2160,9 +2160,9 @@ _mm256_cvts2ph_hf8(__m256h __A, __m256h __B) {
/// FOR i := 0 to 31
/// IF __U[i]
/// IF i < 16
-/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i])
/// ELSE
-/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 16])
+/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 16])
/// FI
/// ELSE
/// dst.hf8[i] := __W.hf8[i]
@@ -2206,9 +2206,9 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_hf8(
/// dst.hf8[i] := 0
/// ELSE
/// IF i < 16
-/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i])
/// ELSE
-/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 16])
+/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 16])
/// FI
/// FI
/// ENDFOR
>From 59560a31f2687ab78a7b1e213747419082230194 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Fri, 21 Feb 2025 05:30:45 -0800
Subject: [PATCH 12/23] Fix _W -> __W
---
clang/lib/Headers/avx10_2convertintrin.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 9d869138a32fd..3e912dd89ac4c 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -442,7 +442,7 @@ _mm_cvtbiasph_bf8(__m128i __A, __m128h __B) {
/// IF __U[i]
/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
-/// dst.bf8[i] := _W[i]
+/// dst.bf8[i] := __W[i]
/// FI
/// ENDFOR
///
@@ -551,7 +551,7 @@ _mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) {
/// IF __U[i]
/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
-/// dst.bf8[i] := _W[i]
+/// dst.bf8[i] := __W[i]
/// FI
/// ENDFOR
///
@@ -660,7 +660,7 @@ _mm_cvtbiassph_bf8(__m128i __A, __m128h __B) {
/// IF __U[i]
/// dst.bf8[i] := add_convert_fp16_to_bf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
-/// dst.bf8[i] := _W[i]
+/// dst.bf8[i] := __W[i]
/// FI
/// ENDFOR
///
@@ -770,7 +770,7 @@ _mm256_cvtbiassph_bf8(__m256i __A, __m256h __B) {
/// IF __U[i]
/// dst.bf8[i] := add_convert_fp16_to_bf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
-/// dst.bf8[i] := _W[i]
+/// dst.bf8[i] := __W[i]
/// FI
/// ENDFOR
///
@@ -878,7 +878,7 @@ _mm_cvtbiasph_hf8(__m128i __A, __m128h __B) {
/// IF __U[i]
/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
-/// dst.hf8[i] := _W[i]
+/// dst.hf8[i] := __W[i]
/// FI
/// ENDFOR
///
@@ -987,7 +987,7 @@ _mm256_cvtbiasph_hf8(__m256i __A, __m256h __B) {
/// IF __U[i]
/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
-/// dst.hf8[i] := _W[i]
+/// dst.hf8[i] := __W[i]
/// FI
/// ENDFOR
///
@@ -1096,7 +1096,7 @@ _mm_cvtbiassph_hf8(__m128i __A, __m128h __B) {
/// IF __U[i]
/// dst.hf8[i] := add_convert_fp16_to_hf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
-/// dst.hf8[i] := _W[i]
+/// dst.hf8[i] := __W[i]
/// FI
/// ENDFOR
///
@@ -1206,7 +1206,7 @@ _mm256_cvtbiassph_hf8(__m256i __A, __m256h __B) {
/// IF __U[i]
/// dst.hf8[i] := add_convert_fp16_to_hf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
-/// dst.hf8[i] := _W[i]
+/// dst.hf8[i] := __W[i]
/// FI
/// ENDFOR
///
>From a22a2ada07cee6aedd59378086e8cabc903875a5 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Mon, 24 Feb 2025 10:48:34 -0800
Subject: [PATCH 13/23] Fix _W -> __W
---
clang/lib/Headers/avx10_2convertintrin.h | 28 ++++++++++++------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 3e912dd89ac4c..433244b5cf81a 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -442,7 +442,7 @@ _mm_cvtbiasph_bf8(__m128i __A, __m128h __B) {
/// IF __U[i]
/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
-/// dst.bf8[i] := __W[i]
+/// dst.bf8[i] := __W.bf8[i]
/// FI
/// ENDFOR
///
@@ -551,7 +551,7 @@ _mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) {
/// IF __U[i]
/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
-/// dst.bf8[i] := __W[i]
+/// dst.bf8[i] := __W.bf8[i]
/// FI
/// ENDFOR
///
@@ -660,7 +660,7 @@ _mm_cvtbiassph_bf8(__m128i __A, __m128h __B) {
/// IF __U[i]
/// dst.bf8[i] := add_convert_fp16_to_bf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
-/// dst.bf8[i] := __W[i]
+/// dst.bf8[i] := __W.bf8[i]
/// FI
/// ENDFOR
///
@@ -770,7 +770,7 @@ _mm256_cvtbiassph_bf8(__m256i __A, __m256h __B) {
/// IF __U[i]
/// dst.bf8[i] := add_convert_fp16_to_bf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
-/// dst.bf8[i] := __W[i]
+/// dst.bf8[i] := __W.bf8[i]
/// FI
/// ENDFOR
///
@@ -878,7 +878,7 @@ _mm_cvtbiasph_hf8(__m128i __A, __m128h __B) {
/// IF __U[i]
/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
-/// dst.hf8[i] := __W[i]
+/// dst.hf8[i] := __W.hf8[i]
/// FI
/// ENDFOR
///
@@ -987,7 +987,7 @@ _mm256_cvtbiasph_hf8(__m256i __A, __m256h __B) {
/// IF __U[i]
/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
-/// dst.hf8[i] := __W[i]
+/// dst.hf8[i] := __W.hf8[i]
/// FI
/// ENDFOR
///
@@ -1096,7 +1096,7 @@ _mm_cvtbiassph_hf8(__m128i __A, __m128h __B) {
/// IF __U[i]
/// dst.hf8[i] := add_convert_fp16_to_hf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
-/// dst.hf8[i] := __W[i]
+/// dst.hf8[i] := __W.hf8[i]
/// FI
/// ENDFOR
///
@@ -1206,7 +1206,7 @@ _mm256_cvtbiassph_hf8(__m256i __A, __m256h __B) {
/// IF __U[i]
/// dst.hf8[i] := add_convert_fp16_to_hf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
-/// dst.hf8[i] := __W[i]
+/// dst.hf8[i] := __W.hf8[i]
/// FI
/// ENDFOR
///
@@ -1321,7 +1321,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_bf8(__m128h __A,
/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 8])
/// FI
/// ELSE
-/// dst.bf8 := __W.bf8[i]
+/// dst.bf8[i] := __W.bf8[i]
/// FI
/// ENDFOR
///
@@ -1562,7 +1562,7 @@ _mm_cvts2ph_bf8(__m128h __A, __m128h __B) {
/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 8])
/// FI
/// ELSE
-/// dst.bf8 := __W.bf8[i]
+/// dst.bf8[i] := __W.bf8[i]
/// FI
/// ENDFOR
///
@@ -2468,7 +2468,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_bf8(__m128h __A) {
/// IF __U[i]
/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
/// ELSE
-/// dst.bf8 := __W.bf8[i]
+/// dst.bf8[i] := __W.bf8[i]
/// FI
/// ENDFOR
///
@@ -2567,7 +2567,7 @@ _mm256_cvtph_bf8(__m256h __A) {
/// IF __U[i]
/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
/// ELSE
-/// dst.bf8 := __W.bf8[i]
+/// dst.bf8[i] := __W.bf8[i]
/// FI
/// ENDFOR
///
@@ -2664,7 +2664,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_bf8(__m128h __A) {
/// IF __U[i]
/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i])
/// ELSE
-/// dst.bf8 := __W.bf8[i]
+/// dst.bf8[i] := __W.bf8[i]
/// FI
/// ENDFOR
///
@@ -2762,7 +2762,7 @@ _mm256_cvtsph_bf8(__m256h __A) {
/// IF __U[i]
/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i])
/// ELSE
-/// dst.bf8 := __W.bf8[i]
+/// dst.bf8[i] := __W.bf8[i]
/// FI
/// ENDFOR
///
>From 6cac19682284c7b58ce6dbe77cfb71639eceb006 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Mon, 24 Feb 2025 11:10:52 -0800
Subject: [PATCH 14/23] Fix hf8 without subscript
---
clang/lib/Headers/avx10_2convertintrin.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 433244b5cf81a..9f817bbd0b182 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -1803,7 +1803,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_hf8(__m128h __A,
/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 8])
/// FI
/// ELSE
-/// dst.hf8 := __W.hf8[i]
+/// dst.hf8[i] := __W.hf8[i]
/// FI
/// ENDFOR
///
@@ -2044,7 +2044,7 @@ _mm_cvts2ph_hf8(__m128h __A, __m128h __B) {
/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 8])
/// FI
/// ELSE
-/// dst.hf8 := __W.hf8[i]
+/// dst.hf8[i] := __W.hf8[i]
/// FI
/// ENDFOR
///
@@ -2860,7 +2860,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_hf8(__m128h __A) {
/// IF __U[i]
/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
/// ELSE
-/// dst.hf8 := __W.hf8[i]
+/// dst.hf8[i] := __W.hf8[i]
/// FI
/// ENDFOR
///
@@ -2959,7 +2959,7 @@ _mm256_cvtph_hf8(__m256h __A) {
/// IF __U[i]
/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i])
/// ELSE
-/// dst.hf8 := __W.hf8[i]
+/// dst.hf8[i] := __W.hf8[i]
/// FI
/// ENDFOR
///
@@ -3056,7 +3056,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_hf8(__m128h __A) {
/// IF __U[i]
/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i])
/// ELSE
-/// dst.hf8 := __W.hf8[i]
+/// dst.hf8[i] := __W.hf8[i]
/// FI
/// ENDFOR
///
@@ -3154,7 +3154,7 @@ _mm256_cvtsph_hf8(__m256h __A) {
/// IF __U[i]
/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i])
/// ELSE
-/// dst.hf8 := __W.hf8[i]
+/// dst.hf8[i] := __W.hf8[i]
/// FI
/// ENDFOR
///
>From 7ce0d46399c98fe09393081db82d4408598e8c48 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Tue, 25 Feb 2025 03:33:52 -0800
Subject: [PATCH 15/23] Fix wrong maskz
---
clang/lib/Headers/avx10_2convertintrin.h | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 9f817bbd0b182..2138e1dfd83f7 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -1479,13 +1479,13 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_bf8(
/// \code{.operation}
/// FOR i := 0 to 31
/// IF __U[i]
-/// dst.bf8[i] := 0
-/// ELSE
/// IF i < 16
/// dst.bf8[i] := convert_fp16_to_bf8(__B.fp16[i])
/// ELSE
/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i - 16])
/// FI
+/// ELSE
+/// dst.bf8[i] := 0
/// FI
/// ENDFOR
///
@@ -1721,13 +1721,13 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_bf8(
/// \code{.operation}
/// FOR i := 0 to 31
/// IF __U[i]
-/// dst.bf8[i] := 0
-/// ELSE
/// IF i < 16
/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__B.fp16[i])
/// ELSE
/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i - 16])
/// FI
+/// ELSE
+/// dst.bf8[i] := 0
/// FI
/// ENDFOR
///
@@ -1961,13 +1961,13 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_hf8(
/// \code{.operation}
/// FOR i := 0 to 31
/// IF __U[i]
-/// dst.hf8[i] := 0
-/// ELSE
/// IF i < 16
/// dst.hf8[i] := convert_fp16_to_hf8(__B.fp16[i])
/// ELSE
/// dst.hf8[i] := convert_fp16_to_hf8(__A.fp16[i - 16])
/// FI
+/// ELSE
+/// dst.hf8[i] := 0
/// FI
/// ENDFOR
///
@@ -2203,13 +2203,13 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_hf8(
/// \code{.operation}
/// FOR i := 0 to 31
/// IF __U[i]
-/// dst.hf8[i] := 0
-/// ELSE
/// IF i < 16
/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__B.fp16[i])
/// ELSE
/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i - 16])
/// FI
+/// ELSE
+/// dst.hf8[i] := 0
/// FI
/// ENDFOR
///
@@ -2504,9 +2504,9 @@ _mm_mask_cvtph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.bf8[i] := 0
-/// ELSE
/// dst.bf8[i] := convert_fp16_to_bf8(__A.fp16[i])
+/// ELSE
+/// dst.bf8[i] := 0
/// FI
/// ENDFOR
///
>From 04f6f5add75439f3d8f933ceaddc40d4f2536623 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Tue, 25 Feb 2025 04:21:52 -0800
Subject: [PATCH 16/23] Fix wrong zeroing
---
clang/lib/Headers/avx10_2convertintrin.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 2138e1dfd83f7..2d7580c5d9d58 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -2607,7 +2607,7 @@ _mm256_mask_cvtph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// FI
/// ENDFOR
///
-/// dst[MAX:64] := 0
+/// dst[MAX:128] := 0
/// \endcode
///
/// \headerfile <immintrin.h>
>From 408c07064401730d883df11dad40106f5ffb09a5 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Tue, 25 Feb 2025 04:36:47 -0800
Subject: [PATCH 17/23] Fix wrong zeroing
---
clang/lib/Headers/avx10_2convertintrin.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 2d7580c5d9d58..012ef647dbd26 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -2803,7 +2803,7 @@ _mm256_mask_cvtsph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// FI
/// ENDFOR
///
-/// dst[MAX:64] := 0
+/// dst[MAX:128] := 0
/// \endcode
///
/// \headerfile <immintrin.h>
>From e955673f75c086f453734a0cec90f23d5f206972 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Tue, 25 Feb 2025 10:16:31 -0800
Subject: [PATCH 18/23] Fix wrong zeroing
---
clang/lib/Headers/avx10_2convertintrin.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 012ef647dbd26..76bb7541b43dc 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -2999,7 +2999,7 @@ _mm256_mask_cvtph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// FI
/// ENDFOR
///
-/// dst[MAX:64] := 0
+/// dst[MAX:128] := 0
/// \endcode
///
/// \headerfile <immintrin.h>
@@ -3195,7 +3195,7 @@ _mm256_mask_cvtsph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// FI
/// ENDFOR
///
-/// dst[MAX:64] := 0
+/// dst[MAX:128] := 0
/// \endcode
///
/// \headerfile <immintrin.h>
>From 22d4bafb153fea507212a63ac977fc0ab200055b Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Tue, 25 Feb 2025 10:27:01 -0800
Subject: [PATCH 19/23] Fix one-off
---
clang/lib/Headers/avx10_2convertintrin.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 76bb7541b43dc..edb0cf3bd2d5a 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -40,7 +40,7 @@
///
/// ENDFOR
///
-/// dst[MAX:127] := 0
+/// dst[MAX:128] := 0
/// \endcode
///
/// \headerfile <immintrin.h>
@@ -79,7 +79,7 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtx2ps_ph(__m128 __A,
/// FI
/// ENDFOR
///
-/// dst[MAX:127] := 0
+/// dst[MAX:128] := 0
/// \endcode
///
/// \headerfile <immintrin.h>
@@ -123,7 +123,7 @@ _mm_mask_cvtx2ps_ph(__m128h __W, __mmask8 __U, __m128 __A, __m128 __B) {
/// FI
/// ENDFOR
///
-/// dst[MAX:127] := 0
+/// dst[MAX:128] := 0
/// \endcode
///
/// \headerfile <immintrin.h>
>From 11c0a12df907fa40ef60dea5cc647b18046af7d0 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Wed, 26 Feb 2025 02:54:36 -0800
Subject: [PATCH 20/23] Further work
---
clang/lib/Headers/avx10_2convertintrin.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index edb0cf3bd2d5a..bcc0c363a0e71 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -408,7 +408,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int9[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -952,7 +952,7 @@ _mm_maskz_cvtbiasph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.hf8[i] := add_fp16_int8_convert_to_hf8(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -1025,7 +1025,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_hf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.hf8[i] := add_fp16_int8_convert_to_hf8(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := 0
/// FI
>From 5c151a3733ca9fed4b52ae0f774ee937d656199e Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Wed, 26 Feb 2025 05:23:10 -0800
Subject: [PATCH 21/23] Further work
---
clang/lib/Headers/avx10_2convertintrin.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index bcc0c363a0e71..9e3ec0b3e5aff 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -408,7 +408,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int9[2 * i], __B.fp16[i])
+/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:64] := 0
>From cd7372eb373fbae3c9215eb646889de8be57bff9 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Wed, 26 Feb 2025 10:59:23 -0800
Subject: [PATCH 22/23] Further work
---
clang/lib/Headers/avx10_2convertintrin.h | 48 ++++++++++++------------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 9e3ec0b3e5aff..383c3d6c1960c 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -408,7 +408,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_with_bias(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -440,7 +440,7 @@ _mm_cvtbiasph_bf8(__m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_with_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := __W.bf8[i]
/// FI
@@ -480,7 +480,7 @@ _mm_mask_cvtbiasph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_with_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := 0
/// FI
@@ -516,7 +516,7 @@ _mm_maskz_cvtbiasph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_with_bias(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -549,7 +549,7 @@ _mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_with_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := __W.bf8[i]
/// FI
@@ -589,7 +589,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_bf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_with_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := 0
/// FI
@@ -626,7 +626,7 @@ _mm256_maskz_cvtbiasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -658,7 +658,7 @@ _mm_cvtbiassph_bf8(__m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := __W.bf8[i]
/// FI
@@ -698,7 +698,7 @@ _mm_mask_cvtbiassph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := 0
/// FI
@@ -735,7 +735,7 @@ _mm_maskz_cvtbiassph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -768,7 +768,7 @@ _mm256_cvtbiassph_bf8(__m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := __W.bf8[i]
/// FI
@@ -808,7 +808,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_bf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.bf8[i] := add_convert_fp16_to_bf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
+/// dst.bf8[i] := convert_fp16_to_bf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.bf8[i] := 0
/// FI
@@ -844,7 +844,7 @@ _mm256_maskz_cvtbiassph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_with_bias(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -876,7 +876,7 @@ _mm_cvtbiasph_hf8(__m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_with_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := __W.hf8[i]
/// FI
@@ -916,7 +916,7 @@ _mm_mask_cvtbiasph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_with_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := 0
/// FI
@@ -952,7 +952,7 @@ _mm_maskz_cvtbiasph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_with_bias(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -985,7 +985,7 @@ _mm256_cvtbiasph_hf8(__m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_with_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := __W.hf8[i]
/// FI
@@ -1025,7 +1025,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_hf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_with_bias(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := 0
/// FI
@@ -1062,7 +1062,7 @@ _mm256_maskz_cvtbiasph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:64] := 0
@@ -1094,7 +1094,7 @@ _mm_cvtbiassph_hf8(__m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := __W.hf8[i]
/// FI
@@ -1134,7 +1134,7 @@ _mm_mask_cvtbiassph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := 0
/// FI
@@ -1171,7 +1171,7 @@ _mm_maskz_cvtbiassph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ENDFOR
///
/// dst[MAX:128] := 0
@@ -1204,7 +1204,7 @@ _mm256_cvtbiassph_hf8(__m256i __A, __m256h __B) {
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := __W.hf8[i]
/// FI
@@ -1244,7 +1244,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_hf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.hf8[i] := add_convert_fp16_to_hf8_bias_saturate(__A.int8[2 * i], __B.fp16[i])
+/// dst.hf8[i] := convert_fp16_to_hf8_with_bias_saturate(__A.int8[2 * i], __B.fp16[i])
/// ELSE
/// dst.hf8[i] := 0
/// FI
>From a8c6c206e894301264e9b3294e3c2da1c25103f2 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Thu, 27 Feb 2025 05:51:20 -0800
Subject: [PATCH 23/23] Rewrite bias description
---
clang/lib/Headers/avx10_2convertintrin.h | 1032 +++++++++++-----------
1 file changed, 512 insertions(+), 520 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 383c3d6c1960c..d3cb89b46adb8 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -62,9 +62,9 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtx2ps_ph(__m128 __A,
}
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed
-/// single-precision (32-bit) floating-point elements to a 128-bit vector
-/// containing FP16 elements. Merging mask \a __U is used to determine if given
-/// element should be taken from \a __W instead.
+/// single-precision (32-bit) floating-point elements to a 128-bit vector
+/// containing FP16 elements. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -106,9 +106,9 @@ _mm_mask_cvtx2ps_ph(__m128h __W, __mmask8 __U, __m128 __A, __m128 __B) {
}
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed
-/// single-precision (32-bit) floating-point elements to a 128-bit vector
-/// containing FP16 elements. Zeroing mask \a __U is used to determine if given
-/// element should be zeroed instead.
+/// single-precision (32-bit) floating-point elements to a 128-bit vector
+/// containing FP16 elements. Zeroing mask \a __U is used to determine if given
+/// element should be zeroed instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -148,9 +148,9 @@ _mm_maskz_cvtx2ps_ph(__mmask8 __U, __m128 __A, __m128 __B) {
}
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
-/// single-precision (32-bit) floating-point elements to a 256-bit vector
-/// containing FP16 elements.
-///
+/// single-precision (32-bit) floating-point elements to a 256-bit vector
+/// containing FP16 elements.
+///
/// \code{.operation}
/// FOR i := 0 to 15
/// IF i < 8
@@ -172,7 +172,7 @@ _mm_maskz_cvtx2ps_ph(__mmask8 __U, __m128 __A, __m128 __B) {
/// \param __B
/// A 256-bit vector of [8 x float].
/// \returns
-/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
+/// A 256-bit vector of [6 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtx2ps_ph(__m256 __A,
@@ -183,9 +183,9 @@ static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtx2ps_ph(__m256 __A,
}
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
-/// single-precision (32-bit) floating-point elements to a 256-bit vector
-/// containing FP16 elements. Merging mask \a __U is used to determine if given
-/// element should be taken from \a __W instead.
+/// single-precision (32-bit) floating-point elements to a 256-bit vector
+/// containing FP16 elements. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -208,7 +208,7 @@ static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtx2ps_ph(__m256 __A,
/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
///
/// \param __W
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
@@ -216,7 +216,7 @@ static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtx2ps_ph(__m256 __A,
/// \param __B
/// A 256-bit vector of [8 x float].
/// \returns
-/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
+/// A 256-bit vector of [6 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
@@ -228,9 +228,9 @@ _mm256_mask_cvtx2ps_ph(__m256h __W, __mmask16 __U, __m256 __A, __m256 __B) {
}
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
-/// single-precision (32-bit) floating-point elements to a 256-bit vector
-/// containing FP16 elements. Zeroing mask \a __U is used to determine if given
-/// element should be zeroed instead.
+/// single-precision (32-bit) floating-point elements to a 256-bit vector
+/// containing FP16 elements. Zeroing mask \a __U is used to determine if given
+/// element should be zeroed instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -259,7 +259,7 @@ _mm256_mask_cvtx2ps_ph(__m256h __W, __mmask16 __U, __m256 __A, __m256 __B) {
/// \param __B
/// A 256-bit vector of [8 x float].
/// \returns
-/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
+/// A 256-bit vector of [6 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// then zero is taken instead.
@@ -271,9 +271,9 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
}
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
-/// single-precision (32-bit) floating-point elements to a 256-bit vector
-/// containing FP16 elements. Rounding mode \a __R needs to be provided.
-///
+/// single-precision (32-bit) floating-point elements to a 256-bit vector
+/// containing FP16 elements. Rounding mode \a __R needs to be provided.
+///
/// \code{.operation}
/// FOR i := 0 to 15
/// IF i < 8
@@ -300,7 +300,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF,
/// _MM_FROUND_TO_ZERO.
/// \returns
-/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
+/// A 256-bit vector of [6 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
#define _mm256_cvtx_round2ps_ph(__A, __B, __R) \
@@ -309,10 +309,10 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
(__mmask16)(-1), (const int)(__R)))
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
-/// single-precision (32-bit) floating-point elements to a 256-bit vector
-/// containing FP16 elements. Merging mask \a __U is used to determine if given
-/// element should be taken from \a __W instead. Rounding mode \a __R needs to
-/// be provided.
+/// single-precision (32-bit) floating-point elements to a 256-bit vector
+/// containing FP16 elements. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead. Rounding mode \a __R needs to
+/// be provided.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -335,7 +335,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
///
/// \param __W
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
@@ -348,7 +348,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF,
/// _MM_FROUND_TO_ZERO.
/// \returns
-/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
+/// A 256-bit vector of [6 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
@@ -357,9 +357,9 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
(__v8sf)(__A), (__v8sf)(__B), (__v16hf)(__W), (__mmask16)(__U), (const int)(__R)))
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
-/// single-precision (32-bit) floating-point elements to a 256-bit vector
-/// containing FP16 elements. Zeroing mask \a __U is used to determine if given
-/// element should be zeroed instead. Rounding mode \a __R needs to be provided.
+/// single-precision (32-bit) floating-point elements to a 256-bit vector
+/// containing FP16 elements. Zeroing mask \a __U is used to determine if given
+/// element should be zeroed instead. Rounding mode \a __R needs to be provided.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -393,7 +393,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF,
/// _MM_FROUND_TO_ZERO.
/// \returns
-/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
+/// A 256-bit vector of [6 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// then zero is taken instead.
@@ -402,9 +402,9 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
(__v8sf)(__A), (__v8sf)(__B), (__v16hf)(_mm256_setzero_ph()), \
(__mmask16)(__U), (const int)(__R)))
-/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -421,21 +421,21 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// \param __A
/// A 128-bit vector of [8 x int16].
/// \param __B
-/// A 128-bit vector of [8 x fp16].
+/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the
-/// sum of elements from \a __A and \a __B; higher order elements are zeroed.
+/// A 128-bit vector of [6 x bf8]. Lower elements correspond to the
+/// converted elements from \a __B using biases from \a __A; higher order
+/// elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_cvtbiasph_bf8(__m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
}
-/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
-/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead.
+/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Merging mask \a __U is used to determine if
+/// given element should be taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -454,28 +454,28 @@ _mm_cvtbiasph_bf8(__m128i __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x bf8].
+/// A 128-bit vector of [6 x bf8].
/// \param __U
/// A 8-bit merging mask.
/// \param __A
/// A 128-bit vector of [8 x int16].
/// \param __B
-/// A 128-bit vector of [8 x fp16].
+/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the sum of
-/// elements from \a __A and \a __B; higher order elements are zeroed. If
-/// corresponding mask bit is not set, then element from \a __W is taken instead.
+/// A 128-bit vector of [6 x bf8]. Lower elements correspond to the
+/// converted elements from \a __B, using biases from \a __A; higher order
+/// elements are zeroed. If corresponding mask bit is not set, then element
+/// from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtbiasph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
-/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
-/// Zeroing mask \a __U is used to determine if given element should be zeroed
-/// instead.
+/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Zeroing mask \a __U is used to determine if
+/// given element should be zeroed instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -498,11 +498,12 @@ _mm_mask_cvtbiasph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \param __A
/// A 128-bit vector of [8 x int16].
/// \param __B
-/// A 128-bit vector of [8 x fp16].
+/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the sum of
-/// elements from \a __A and \a __B; higher order elements are zeroed. If
-/// corresponding mask bit is not set, then element is zeroed.
+/// A 128-bit vector of [6 x bf8]. Lower elements correspond to the
+/// converted elements from \a __B, using biases from \a __A; higher order
+/// elements are zeroed. If corresponding mask bit is not set, then element
+/// is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtbiasph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask(
@@ -510,9 +511,9 @@ _mm_maskz_cvtbiasph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
(__mmask8)__U);
}
-/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -527,12 +528,12 @@ _mm_maskz_cvtbiasph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
///
/// \param __A
-/// A 256-bit vector of [16 x int16].
+/// A 256-bit vector of [6 x int16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Elements correspond to the
-/// sum of elements from \a __A and \a __B.
+/// A 128-bit vector of [6 x bf8]. Elements correspond to the
+/// converted elements from \a __B using biases from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256_mask(
@@ -540,11 +541,10 @@ _mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) {
(__mmask16)-1);
}
-/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
-/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead.
+/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Merging mask \a __U is used to determine if
+/// given element should be taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -563,28 +563,27 @@ _mm256_cvtbiasph_bf8(__m256i __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x bf8].
+/// A 128-bit vector of [6 x bf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [16 x int16].
+/// A 256-bit vector of [6 x int16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Elements correspond to the sum of
-/// elements from \a __A and \a __B. If corresponding mask bit is not set, then
-/// element from \a __W is taken instead.
+/// A 128-bit vector of [6 x bf8]. Elements correspond to the converted
+/// elements from \a __B, using biases from \a __A. If corresponding mask bit
+/// is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_bf8(
__m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256_mask(
(__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
-/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
-/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead.
+/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Zeroing mask \a __U is used to determine if
+/// given element should be zeroed instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -605,13 +604,13 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_bf8(
/// \param __U
/// A 16-bit zeroing mask.
/// \param __A
-/// A 256-bit vector of [16 x int16].
+/// A 256-bit vector of [6 x int16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Elements correspond to the sum of
-/// elements from \a __A and \a __B. If corresponding mask bit is not set,
-/// then element is zeroed.
+/// A 128-bit vector of [6 x bf8]. Elements correspond to the converted
+/// elements from \a __B, using biases from \a __A. If corresponding mask bit
+/// is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtbiasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256_mask(
@@ -619,10 +618,9 @@ _mm256_maskz_cvtbiasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
(__mmask16)__U);
}
-/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
-/// Results are saturated.
+/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Results are saturated.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -639,21 +637,21 @@ _mm256_maskz_cvtbiasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
/// \param __A
/// A 128-bit vector of [8 x int16].
/// \param __B
-/// A 128-bit vector of [8 x fp16].
+/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the
-/// sum of elements from \a __A and \a __B; higher order elements are zeroed.
+/// A 128-bit vector of [6 x bf8]. Lower elements correspond to the
+/// converted elements from \a __B using biases from \a __A; higher order
+/// elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_cvtbiassph_bf8(__m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
}
-/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
-/// Results are saturated. Merging mask \a __U is used to determine if given
-/// element should be taken from \a __W instead.
+/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Results are saturated. Merging mask \a __U
+/// is used to determine if given element should be taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -672,28 +670,27 @@ _mm_cvtbiassph_bf8(__m128i __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x bf8].
+/// A 128-bit vector of [6 x bf8].
/// \param __U
/// A 8-bit merging mask.
/// \param __A
/// A 128-bit vector of [8 x int16].
/// \param __B
-/// A 128-bit vector of [8 x fp16].
+/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the sum of
-/// elements from \a __A and \a __B; higher order elements are zeroed. If
-/// corresponding mask bit is not set, then element from \a __W is taken instead.
-static __inline__ __m128i __DEFAULT_FN_ATTRS128
-_mm_mask_cvtbiassph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
- return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask(
- (__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
-}
+/// A 128-bit vector of [6 x bf8]. Lower elements correspond to the
+/// converted elements from \a __B, using biases from \a __A; higher order
+/// elements are zeroed. If corresponding mask bit is not set, then element
+/// from \a __W is taken instead.
+static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_mask_cvtbiassph_bf8(__m128i
+ __W, __mmask8 __U, __m128i __A, __m128h __B) { return
+ (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask( (__v16qi)__A,
+ (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U); }
-/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
-/// Results are saturated. Zeroing mask \a __U is used to determine if given
-/// element should be zeroed instead.
+/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Results are saturated. Zeroing mask \a __U
+/// is used to determine if given element should be zeroed instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -716,11 +713,12 @@ _mm_mask_cvtbiassph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \param __A
/// A 128-bit vector of [8 x int16].
/// \param __B
-/// A 128-bit vector of [8 x fp16].
+/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the sum of
-/// elements from \a __A and \a __B; higher order elements are zeroed. If
-/// corresponding mask bit is not set, then element is zeroed.
+/// A 128-bit vector of [6 x bf8]. Lower elements correspond to the
+/// converted elements from \a __B, using biases from \a __A; higher order
+/// elements are zeroed. If corresponding mask bit is not set, then element
+/// is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtbiassph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask(
@@ -728,10 +726,10 @@ _mm_maskz_cvtbiassph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
(__mmask8)__U);
}
-/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
-/// Results are saturated.
+
+/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Results are saturated.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -746,12 +744,12 @@ _mm_maskz_cvtbiassph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.
///
/// \param __A
-/// A 256-bit vector of [16 x int16].
+/// A 256-bit vector of [6 x int16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Elements correspond to the
-/// sum of elements from \a __A and \a __B.
+/// A 128-bit vector of [6 x bf8]. Elements correspond to the
+/// converted elements from \a __B using biases from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtbiassph_bf8(__m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_256_mask(
@@ -759,11 +757,10 @@ _mm256_cvtbiassph_bf8(__m256i __A, __m256h __B) {
(__mmask16)-1);
}
-/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
-/// Results are saturated. Merging mask \a __U is used to determine if given
-/// element should be taken from \a __W instead.
+/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Results are saturated. Merging mask \a __U
+/// is used to determine if given element should be taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -782,28 +779,27 @@ _mm256_cvtbiassph_bf8(__m256i __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x bf8].
+/// A 128-bit vector of [6 x bf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [16 x int16].
+/// A 256-bit vector of [6 x int16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Elements correspond to the sum of
-/// elements from \a __A and \a __B. If corresponding mask bit is not set, then
-/// element from \a __W is taken instead.
+/// A 128-bit vector of [6 x bf8]. Elements correspond to the converted
+/// elements from \a __B, using biases from \a __A. If corresponding mask bit
+/// is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_bf8(
__m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_256_mask(
(__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
-/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
-/// Results are saturated. Merging mask \a __U is used to determine if given
-/// element should be taken from \a __W instead.
+/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E5M2 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Results are saturated. Merging mask \a __U
+/// is used to determine if given element should be taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -824,13 +820,13 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_bf8(
/// \param __U
/// A 16-bit zeroing mask.
/// \param __A
-/// A 256-bit vector of [16 x int16].
+/// A 256-bit vector of [6 x int16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Elements correspond to the sum of
-/// elements from \a __A and \a __B. If corresponding mask bit is not set,
-/// then element is zeroed.
+/// A 128-bit vector of [6 x bf8]. Elements correspond to the converted
+/// elements from \a __B, using biases from \a __A. If corresponding mask bit
+/// is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtbiassph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_256_mask(
@@ -838,9 +834,9 @@ _mm256_maskz_cvtbiassph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
(__mmask16)__U);
}
-/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -857,21 +853,21 @@ _mm256_maskz_cvtbiassph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
/// \param __A
/// A 128-bit vector of [8 x int16].
/// \param __B
-/// A 128-bit vector of [8 x fp16].
+/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the
-/// sum of elements from \a __A and \a __B; higher order elements are zeroed.
+/// A 128-bit vector of [6 x hf8]. Lower elements correspond to the
+/// converted elements from \a __B using biases from \a __A; higher order
+/// elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_cvtbiasph_hf8(__m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
}
-/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
-/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead.
+/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Merging mask \a __U is used to determine if
+/// given element should be taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -890,28 +886,28 @@ _mm_cvtbiasph_hf8(__m128i __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x hf8].
+/// A 128-bit vector of [6 x hf8].
/// \param __U
/// A 8-bit merging mask.
/// \param __A
/// A 128-bit vector of [8 x int16].
/// \param __B
-/// A 128-bit vector of [8 x fp16].
+/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the sum of
-/// elements from \a __A and \a __B; higher order elements are zeroed. If
-/// corresponding mask bit is not set, then element from \a __W is taken instead.
+/// A 128-bit vector of [6 x hf8]. Lower elements correspond to the
+/// converted elements from \a __B, using biases from \a __A; higher order
+/// elements are zeroed. If corresponding mask bit is not set, then element
+/// from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtbiasph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
-/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
-/// Zeroing mask \a __U is used to determine if given element should be zeroed
-/// instead.
+/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Zeroing mask \a __U is used to determine if
+/// given element should be zeroed instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -934,11 +930,12 @@ _mm_mask_cvtbiasph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \param __A
/// A 128-bit vector of [8 x int16].
/// \param __B
-/// A 128-bit vector of [8 x fp16].
+/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the sum of
-/// elements from \a __A and \a __B; higher order elements are zeroed. If
-/// corresponding mask bit is not set, then element is zeroed.
+/// A 128-bit vector of [6 x hf8]. Lower elements correspond to the
+/// converted elements from \a __B, using biases from \a __A; higher order
+/// elements are zeroed. If corresponding mask bit is not set, then element
+/// is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtbiasph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8_128_mask(
@@ -946,9 +943,9 @@ _mm_maskz_cvtbiasph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
(__mmask8)__U);
}
-/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -963,12 +960,12 @@ _mm_maskz_cvtbiasph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.
///
/// \param __A
-/// A 256-bit vector of [16 x half].
+/// A 256-bit vector of [6 x half].
/// \param __B
-/// A 256-bit vector of [16 x i16].
+/// A 256-bit vector of [6 x i16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Elements correspond to the
-/// sum of elements from \a __A and \a __B.
+/// A 128-bit vector of [6 x hf8]. Elements correspond to the
+/// converted elements from \a __B using biases from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtbiasph_hf8(__m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8_256_mask(
@@ -976,11 +973,10 @@ _mm256_cvtbiasph_hf8(__m256i __A, __m256h __B) {
(__mmask16)-1);
}
-/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
-/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead.
+/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Merging mask \a __U is used to determine if
+/// given element should be taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -999,28 +995,27 @@ _mm256_cvtbiasph_hf8(__m256i __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x hf8].
+/// A 128-bit vector of [6 x hf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [16 x int16].
+/// A 256-bit vector of [6 x int16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Elements correspond to the sum of
-/// elements from \a __A and \a __B. If corresponding mask bit is not set, then
-/// element from \a __W is taken instead.
+/// A 128-bit vector of [6 x hf8]. Elements correspond to the converted
+/// elements from \a __B, using biases from \a __A. If corresponding mask bit
+/// is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_hf8(
__m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8_256_mask(
(__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
-/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3
-/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead.
+/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Merging mask \a __U is used to determine if
+/// given element should be taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -1041,13 +1036,13 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_hf8(
/// \param __U
/// A 16-bit zeroing mask.
/// \param __A
-/// A 256-bit vector of [16 x half].
+/// A 256-bit vector of [6 x half].
/// \param __B
-/// A 256-bit vector of [16 x i16].
+/// A 256-bit vector of [6 x i16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Elements correspond to the sum of
-/// elements from \a __A and \a __B. If corresponding mask bit is not set,
-/// then element is zeroed.
+/// A 128-bit vector of [6 x hf8]. Elements correspond to the converted
+/// elements from \a __B, using biases from \a __A. If corresponding mask bit
+/// is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtbiasph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8_256_mask(
@@ -1055,10 +1050,9 @@ _mm256_maskz_cvtbiasph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
(__mmask16)__U);
}
-/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
-/// Results are saturated.
+/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Results are saturated.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -1075,21 +1069,21 @@ _mm256_maskz_cvtbiasph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
/// \param __A
/// A 128-bit vector of [8 x int16].
/// \param __B
-/// A 128-bit vector of [8 x fp16].
+/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the
-/// sum of elements from \a __A and \a __B; higher order elements are zeroed.
+/// A 128-bit vector of [6 x hf8]. Lower elements correspond to the
+/// converted elements from \a __B using biases from \a __A; higher order
+/// elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_cvtbiassph_hf8(__m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
}
-/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
-/// Results are saturated. Merging mask \a __U is used to determine if given
-/// element should be taken from \a __W instead.
+/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Results are saturated. Merging mask \a __U
+/// is used to determine if given element should be taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -1108,28 +1102,28 @@ _mm_cvtbiassph_hf8(__m128i __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x hf8].
+/// A 128-bit vector of [6 x hf8].
/// \param __U
/// A 8-bit merging mask.
/// \param __A
/// A 128-bit vector of [8 x int16].
/// \param __B
-/// A 128-bit vector of [8 x fp16].
+/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the sum of
-/// elements from \a __A and \a __B; higher order elements are zeroed. If
-/// corresponding mask bit is not set, then element from \a __W is taken instead.
+/// A 128-bit vector of [6 x hf8]. Lower elements correspond to the
+/// converted elements from \a __B, using biases from \a __A; higher order
+/// elements are zeroed. If corresponding mask bit is not set, then element
+/// from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtbiassph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
-/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
-/// Results are saturated. Zeroing mask \a __U is used to determine if given
-/// element should be zeroed instead.
+/// Convert 128-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Results are saturated. Zeroing mask \a __U
+/// is used to determine if given element should be zeroed instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -1152,11 +1146,12 @@ _mm_mask_cvtbiassph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \param __A
/// A 128-bit vector of [8 x int16].
/// \param __B
-/// A 128-bit vector of [8 x fp16].
+/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the sum of
-/// elements from \a __A and \a __B; higher order elements are zeroed. If
-/// corresponding mask bit is not set, then element is zeroed.
+/// A 128-bit vector of [6 x hf8]. Lower elements correspond to the
+/// converted elements from \a __B, using biases from \a __A; higher order
+/// elements are zeroed. If corresponding mask bit is not set, then element
+/// is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtbiassph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_128_mask(
@@ -1164,10 +1159,9 @@ _mm_maskz_cvtbiassph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
(__mmask8)__U);
}
-/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
-/// Results are saturated.
+/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Results are saturated.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -1182,12 +1176,12 @@ _mm_maskz_cvtbiassph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.
///
/// \param __A
-/// A 256-bit vector of [16 x int16].
+/// A 256-bit vector of [6 x int16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Elements correspond to the
-/// sum of elements from \a __A and \a __B.
+/// A 128-bit vector of [6 x hf8]. Elements correspond to the
+/// converted elements from \a __B using biases from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtbiassph_hf8(__m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_256_mask(
@@ -1195,11 +1189,10 @@ _mm256_cvtbiassph_hf8(__m256i __A, __m256h __B) {
(__mmask16)-1);
}
-/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
-/// Results are saturated. Merging mask \a __U is used to determine if given
-/// element should be taken from \a __W instead.
+/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Results are saturated. Merging mask \a __U
+/// is used to determine if given element should be taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -1218,28 +1211,27 @@ _mm256_cvtbiassph_hf8(__m256i __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x hf8].
+/// A 128-bit vector of [6 x hf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [16 x int16].
+/// A 256-bit vector of [6 x int16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Elements correspond to the sum of
-/// elements from \a __A and \a __B. If corresponding mask bit is not set, then
-/// element from \a __W is taken instead.
+/// A 128-bit vector of [6 x hf8]. Elements correspond to the converted
+/// elements from \a __B, using biases from \a __A. If corresponding mask bit
+/// is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_hf8(
__m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_256_mask(
(__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
-/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
-/// Results are saturated. Merging mask \a __U is used to determine if given
-/// element should be taken from \a __W instead.
+/// Convert 256-bit vector \a __B containing packed FP16 floating-point elements
+/// to FP8 E4M3 numbers, using conversion biases stored in lower 8 bits of each
+/// 16-bit integer stored in \a __B. Results are saturated. Merging mask \a __U
+/// is used to determine if given element should be taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -1260,13 +1252,13 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_hf8(
/// \param __U
/// A 16-bit zeroing mask.
/// \param __A
-/// A 256-bit vector of [16 x int16].
+/// A 256-bit vector of [6 x int16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Elements correspond to the sum of
-/// elements from \a __A and \a __B. If corresponding mask bit is not set,
-/// then element is zeroed.
+/// A 128-bit vector of [6 x hf8]. Elements correspond to the converted
+/// elements from \a __B, using biases from \a __A. If corresponding mask bit
+/// is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtbiassph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_256_mask(
@@ -1275,7 +1267,7 @@ _mm256_maskz_cvtbiassph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
}
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
+/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -1298,7 +1290,7 @@ _mm256_maskz_cvtbiassph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [6 x bf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_bf8(__m128h __A,
@@ -1308,9 +1300,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_bf8(__m128h __A,
}
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
-/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead.
+/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -1333,7 +1325,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_bf8(__m128h __A,
/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x bf8].
+/// A 128-bit vector of [6 x bf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
@@ -1341,7 +1333,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_bf8(__m128h __A,
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [6 x bf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
@@ -1352,9 +1344,9 @@ _mm_mask_cvt2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
}
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
-/// Zeroing mask \a __U is used to determine if given element should be zeroed
-/// instead.
+/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -1383,7 +1375,7 @@ _mm_mask_cvt2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [6 x bf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// zero is taken instead.
@@ -1395,7 +1387,7 @@ _mm_maskz_cvt2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
}
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
+/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
///
/// \code{.operation}
/// FOR i := 0 to 31
@@ -1414,11 +1406,11 @@ _mm_maskz_cvt2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction.
///
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [2 x bf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
@@ -1428,9 +1420,9 @@ _mm256_cvt2ph_bf8(__m256h __A, __m256h __B) {
}
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
-/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead.
+/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 31
@@ -1453,15 +1445,15 @@ _mm256_cvt2ph_bf8(__m256h __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVT2PH2BF8 instruction.
///
/// \param __W
-/// A 256-bit vector of [32 x bf8].
+/// A 256-bit vector of [2 x bf8].
/// \param __U
/// A 32-bit merging mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [2 x bf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
@@ -1472,9 +1464,9 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_bf8(
}
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
-/// Merging mask \a __U is used to determine if given element should be zeroed
-/// instead.
+/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be zeroed
+/// instead.
///
/// \code{.operation}
/// FOR i := 0 to 31
@@ -1499,11 +1491,11 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_bf8(
/// \param __U
/// A 32-bit zeroing mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [2 x bf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// zero is taken instead.
@@ -1515,8 +1507,8 @@ _mm256_maskz_cvt2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {
}
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
-/// Resulting elements are saturated in case of overflow.
+/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
+/// Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -1539,7 +1531,7 @@ _mm256_maskz_cvt2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [6 x bf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -1549,9 +1541,9 @@ _mm_cvts2ph_bf8(__m128h __A, __m128h __B) {
}
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
-/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead. Resulting elements are saturated in case of overflow.
+/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead. Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -1574,7 +1566,7 @@ _mm_cvts2ph_bf8(__m128h __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x bf8].
+/// A 128-bit vector of [6 x bf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
@@ -1582,7 +1574,7 @@ _mm_cvts2ph_bf8(__m128h __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [6 x bf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
@@ -1593,9 +1585,9 @@ _mm_mask_cvts2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
}
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
-/// Zeroing mask \a __U is used to determine if given element should be zeroed
-/// instead. Resulting elements are saturated in case of overflow.
+/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead. Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -1624,7 +1616,7 @@ _mm_mask_cvts2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [6 x bf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// zero is taken instead.
@@ -1636,8 +1628,8 @@ _mm_maskz_cvts2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
}
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
-/// Resulting elements are saturated in case of overflow.
+/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
+/// Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
/// FOR i := 0 to 31
@@ -1656,11 +1648,11 @@ _mm_maskz_cvts2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction.
///
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [2 x bf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
@@ -1670,9 +1662,9 @@ _mm256_cvts2ph_bf8(__m256h __A, __m256h __B) {
}
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
-/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead. Resulting elements are saturated in case of overflow.
+/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead. Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
/// FOR i := 0 to 31
@@ -1695,15 +1687,15 @@ _mm256_cvts2ph_bf8(__m256h __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVT2PH2BF8S instruction.
///
/// \param __W
-/// A 256-bit vector of [32 x bf8].
+/// A 256-bit vector of [2 x bf8].
/// \param __U
/// A 32-bit merging mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [2 x bf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
@@ -1714,9 +1706,9 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_bf8(
}
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
-/// Merging mask \a __U is used to determine if given element should be zeroed
-/// instead. Resulting elements are saturated in case of overflow.
+/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be zeroed
+/// instead. Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
/// FOR i := 0 to 31
@@ -1741,11 +1733,11 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_bf8(
/// \param __U
/// A 32-bit zeroing mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 256-bit vector of [32 x bf8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [2 x bf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// zero is taken instead.
@@ -1757,7 +1749,7 @@ _mm256_maskz_cvts2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {
}
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
+/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -1780,7 +1772,7 @@ _mm256_maskz_cvts2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [6 x hf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_hf8(__m128h __A,
@@ -1790,9 +1782,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_hf8(__m128h __A,
}
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
-/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead.
+/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -1815,7 +1807,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_hf8(__m128h __A,
/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x hf8].
+/// A 128-bit vector of [6 x hf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
@@ -1823,7 +1815,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvt2ph_hf8(__m128h __A,
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [6 x hf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
@@ -1834,9 +1826,9 @@ _mm_mask_cvt2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
}
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
-/// Zeroing mask \a __U is used to determine if given element should be zeroed
-/// instead.
+/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -1865,7 +1857,7 @@ _mm_mask_cvt2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [6 x hf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// zero is taken instead.
@@ -1877,7 +1869,7 @@ _mm_maskz_cvt2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
}
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
+/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
///
/// \code{.operation}
/// FOR i := 0 to 31
@@ -1896,11 +1888,11 @@ _mm_maskz_cvt2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction.
///
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [2 x hf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
@@ -1910,9 +1902,9 @@ _mm256_cvt2ph_hf8(__m256h __A, __m256h __B) {
}
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
-/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead.
+/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 31
@@ -1935,15 +1927,15 @@ _mm256_cvt2ph_hf8(__m256h __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVT2PH2HF8 instruction.
///
/// \param __W
-/// A 256-bit vector of [32 x hf8].
+/// A 256-bit vector of [2 x hf8].
/// \param __U
/// A 32-bit merging mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [2 x hf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
@@ -1954,9 +1946,9 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_hf8(
}
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
-/// Merging mask \a __U is used to determine if given element should be zeroed
-/// instead.
+/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be zeroed
+/// instead.
///
/// \code{.operation}
/// FOR i := 0 to 31
@@ -1981,11 +1973,11 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvt2ph_hf8(
/// \param __U
/// A 32-bit zeroing mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [2 x hf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// zero is taken instead.
@@ -1997,8 +1989,8 @@ _mm256_maskz_cvt2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
}
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
-/// Resulting elements are saturated in case of overflow.
+/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
+/// Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -2021,7 +2013,7 @@ _mm256_maskz_cvt2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [6 x hf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -2031,9 +2023,9 @@ _mm_cvts2ph_hf8(__m128h __A, __m128h __B) {
}
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
-/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead. Resulting elements are saturated in case of overflow.
+/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead. Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -2056,7 +2048,7 @@ _mm_cvts2ph_hf8(__m128h __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x hf8].
+/// A 128-bit vector of [6 x hf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
@@ -2064,7 +2056,7 @@ _mm_cvts2ph_hf8(__m128h __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [6 x hf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
@@ -2075,9 +2067,9 @@ _mm_mask_cvts2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
}
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
-/// Zeroing mask \a __U is used to determine if given element should be zeroed
-/// instead. Resulting elements are saturated in case of overflow.
+/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead. Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -2106,7 +2098,7 @@ _mm_mask_cvts2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [6 x hf8]. Lower 8 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// zero is taken instead.
@@ -2118,8 +2110,8 @@ _mm_maskz_cvts2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
}
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
-/// Resulting elements are saturated in case of overflow.
+/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
+/// Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
/// FOR i := 0 to 31
@@ -2138,11 +2130,11 @@ _mm_maskz_cvts2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction.
///
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [2 x hf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
@@ -2152,9 +2144,9 @@ _mm256_cvts2ph_hf8(__m256h __A, __m256h __B) {
}
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
-/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead. Resulting elements are saturated in case of overflow.
+/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead. Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
/// FOR i := 0 to 31
@@ -2177,15 +2169,15 @@ _mm256_cvts2ph_hf8(__m256h __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVT2PH2HF8S instruction.
///
/// \param __W
-/// A 256-bit vector of [32 x hf8].
+/// A 256-bit vector of [2 x hf8].
/// \param __U
/// A 32-bit merging mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [2 x hf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
@@ -2196,9 +2188,9 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_hf8(
}
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
-/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
-/// Merging mask \a __U is used to determine if given element should be zeroed
-/// instead. Resulting elements are saturated in case of overflow.
+/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be zeroed
+/// instead. Resulting elements are saturated in case of overflow.
///
/// \code{.operation}
/// FOR i := 0 to 31
@@ -2223,11 +2215,11 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts2ph_hf8(
/// \param __U
/// A 32-bit zeroing mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \param __B
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 256-bit vector of [32 x hf8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [2 x hf8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// zero is taken instead.
@@ -2239,7 +2231,7 @@ _mm256_maskz_cvts2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
}
/// Convert 128-bit vector \a __A, containing packed FP8 E4M3 floating-point
-/// elements to a 128-bit vector containing FP16 elements. The conversion is exact.
+/// elements to a 128-bit vector containing FP16 elements. The conversion is exact.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -2254,7 +2246,7 @@ _mm256_maskz_cvts2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
///
/// \param __A
-/// A 128-bit vector of [16 x hf8].
+/// A 128-bit vector of [6 x hf8].
/// \returns
/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A.
@@ -2264,9 +2256,9 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvthf8_ph(__m128i __A) {
}
/// Convert 128-bit vector \a __A, containing packed FP8 E4M3 floating-point
-/// elements to a 128-bit vector containing FP16 elements. The conversion is
-/// exact. Merging mask \a __U is used to determine if given element should be
-/// taken from \a __W instead.
+/// elements to a 128-bit vector containing FP16 elements. The conversion is
+/// exact. Merging mask \a __U is used to determine if given element should be
+/// taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -2289,7 +2281,7 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvthf8_ph(__m128i __A) {
/// \param __U
/// A 8-bit merging mask.
/// \param __A
-/// A 128-bit vector of [16 x hf8].
+/// A 128-bit vector of [6 x hf8].
/// \returns
/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
@@ -2301,9 +2293,9 @@ _mm_mask_cvthf8_ph(__m128h __W, __mmask8 __U, __m128i __A) {
}
/// Convert 128-bit vector \a __A, containing packed FP8 E4M3 floating-point
-/// elements to a 128-bit vector containing FP16 elements. The conversion is
-/// exact. Zeroing mask \a __U is used to determine if given element should be
-/// zeroed instead.
+/// elements to a 128-bit vector containing FP16 elements. The conversion is
+/// exact. Zeroing mask \a __U is used to determine if given element should be
+/// zeroed instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -2324,7 +2316,7 @@ _mm_mask_cvthf8_ph(__m128h __W, __mmask8 __U, __m128i __A) {
/// \param __U
/// A 8-bit zeroing mask.
/// \param __A
-/// A 128-bit vector of [16 x hf8].
+/// A 128-bit vector of [6 x hf8].
/// \returns
/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
@@ -2336,7 +2328,7 @@ _mm_maskz_cvthf8_ph(__mmask8 __U, __m128i __A) {
}
/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point
-/// elements to a 256-bit vector containing FP16 elements. The conversion is exact.
+/// elements to a 256-bit vector containing FP16 elements. The conversion is exact.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -2351,9 +2343,9 @@ _mm_maskz_cvthf8_ph(__mmask8 __U, __m128i __A) {
/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
///
/// \param __A
-/// A 256-bit vector of [32 x hf8].
+/// A 256-bit vector of [2 x hf8].
/// \returns
-/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
+/// A 256-bit vector of [6 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvthf8_ph(__m128i __A) {
return (__m256h)__builtin_ia32_vcvthf8_2ph256_mask(
@@ -2361,9 +2353,9 @@ static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvthf8_ph(__m128i __A) {
}
/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point
-/// elements to a 256-bit vector containing FP16 elements. The conversion is
-/// exact. Merging mask \a __U is used to determine if given element should be
-/// taken from \a __W instead.
+/// elements to a 256-bit vector containing FP16 elements. The conversion is
+/// exact. Merging mask \a __U is used to determine if given element should be
+/// taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -2382,13 +2374,13 @@ static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvthf8_ph(__m128i __A) {
/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
///
/// \param __W
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [32 x hf8].
+/// A 256-bit vector of [2 x hf8].
/// \returns
-/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
+/// A 256-bit vector of [6 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
@@ -2398,9 +2390,9 @@ _mm256_mask_cvthf8_ph(__m256h __W, __mmask16 __U, __m128i __A) {
}
/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point
-/// elements to a 256-bit vector containing FP16 elements. The conversion is
-/// exact. Zeroing mask \a __U is used to determine if given element should be
-/// zeroed instead.
+/// elements to a 256-bit vector containing FP16 elements. The conversion is
+/// exact. Zeroing mask \a __U is used to determine if given element should be
+/// zeroed instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -2421,9 +2413,9 @@ _mm256_mask_cvthf8_ph(__m256h __W, __mmask16 __U, __m128i __A) {
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [32 x hf8].
+/// A 256-bit vector of [2 x hf8].
/// \returns
-/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
+/// A 256-bit vector of [6 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// zero is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
@@ -2433,8 +2425,8 @@ _mm256_maskz_cvthf8_ph(__mmask16 __U, __m128i __A) {
}
/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
-/// resulting vector are zeroed.
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -2451,7 +2443,7 @@ _mm256_maskz_cvthf8_ph(__mmask16 __U, __m128i __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the (converted)
+/// A 128-bit vector of [6 x bf8]. Lower elements correspond to the (converted)
/// elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_bf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2bf8_128_mask(
@@ -2459,9 +2451,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_bf8(__m128h __A) {
}
/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
-/// resulting vector are zeroed. Merging mask \a __U is used to determine if
-/// given element should be taken from \a __W instead.
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Merging mask \a __U is used to determine if
+/// given element should be taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -2480,14 +2472,14 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_bf8(__m128h __A) {
/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x bf8].
+/// A 128-bit vector of [6 x bf8].
/// \param __U
/// A 8-bit merging mask.
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
///
-/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the
+/// A 128-bit vector of [6 x bf8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -2497,9 +2489,9 @@ _mm_mask_cvtph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {
}
/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
-/// resulting vector are zeroed. Zeroing mask \a __U is used to determine if
-/// given element should be zeroed instead.
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Zeroing mask \a __U is used to determine if
+/// given element should be zeroed instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -2523,7 +2515,7 @@ _mm_mask_cvtph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// A 128-bit vector of [8 x fp16].
/// \returns
///
-/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the
+/// A 128-bit vector of [6 x bf8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -2533,7 +2525,7 @@ _mm_maskz_cvtph_bf8(__mmask8 __U, __m128h __A) {
}
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E5M2 FP8 elements.
+/// to a 128-bit vector containing E5M2 FP8 elements.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -2548,9 +2540,9 @@ _mm_maskz_cvtph_bf8(__mmask8 __U, __m128h __A) {
/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction.
///
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the (converted)
+/// A 128-bit vector of [6 x bf8]. Resulting elements correspond to the (converted)
/// elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtph_bf8(__m256h __A) {
@@ -2559,9 +2551,9 @@ _mm256_cvtph_bf8(__m256h __A) {
}
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E5M2 FP8 elements. Merging mask \a __U is
-/// used to determine if given element should be taken from \a __W instead.
-///
+/// to a 128-bit vector containing E5M2 FP8 elements. Merging mask \a __U is
+/// used to determine if given element should be taken from \a __W instead.
+///
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
@@ -2579,13 +2571,13 @@ _mm256_cvtph_bf8(__m256h __A) {
/// This intrinsic corresponds to the \c VCVTPH2BF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x bf8].
+/// A 128-bit vector of [6 x bf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
/// A 256-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the
+/// A 128-bit vector of [6 x bf8]. Resulting elements correspond to the
/// (converted) elements from \a __A. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
@@ -2595,9 +2587,9 @@ _mm256_mask_cvtph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
}
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E5M2 FP8 elements. Zeroing mask \a __U is
-/// used to determine if given element should be zeroed instead.
-///
+/// to a 128-bit vector containing E5M2 FP8 elements. Zeroing mask \a __U is
+/// used to determine if given element should be zeroed instead.
+///
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
@@ -2617,9 +2609,9 @@ _mm256_mask_cvtph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the
+/// A 128-bit vector of [6 x bf8]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// then element is zeroed instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
@@ -2629,9 +2621,9 @@ _mm256_maskz_cvtph_bf8(__mmask16 __U, __m256h __A) {
}
/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
-/// resulting vector are zeroed. Results are saturated.
-///
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Results are saturated.
+///
/// \code{.operation}
/// FOR i := 0 to 7
/// dst.bf8[i] := convert_fp16_to_bf8_saturate(__A.fp16[i])
@@ -2647,7 +2639,7 @@ _mm256_maskz_cvtph_bf8(__mmask16 __U, __m256h __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the (converted)
+/// A 128-bit vector of [6 x bf8]. Lower elements correspond to the (converted)
/// elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_bf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2bf8s_128_mask(
@@ -2655,9 +2647,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_bf8(__m128h __A) {
}
/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
-/// resulting vector are zeroed. Results are saturated. Merging mask \a __U is
-/// used to determine if given element should be taken from \a __W instead.
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Results are saturated. Merging mask \a __U is
+/// used to determine if given element should be taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -2676,13 +2668,13 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_bf8(__m128h __A) {
/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x bf8].
+/// A 128-bit vector of [6 x bf8].
/// \param __U
/// A 8-bit merging mask.
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the
+/// A 128-bit vector of [6 x bf8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -2692,9 +2684,9 @@ _mm_mask_cvtsph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {
}
/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
-/// resulting vector are zeroed. Results are saturated. Zeroing mask \a __U is
-/// used to determine if given element should be zeroed instead.
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Results are saturated. Zeroing mask \a __U is
+/// used to determine if given element should be zeroed instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -2717,7 +2709,7 @@ _mm_mask_cvtsph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Lower elements correspond to the
+/// A 128-bit vector of [6 x bf8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -2727,7 +2719,7 @@ _mm_maskz_cvtsph_bf8(__mmask8 __U, __m128h __A) {
}
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated.
+/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -2742,9 +2734,9 @@ _mm_maskz_cvtsph_bf8(__mmask8 __U, __m128h __A) {
/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction.
///
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the (converted)
+/// A 128-bit vector of [6 x bf8]. Resulting elements correspond to the (converted)
/// elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtsph_bf8(__m256h __A) {
@@ -2753,9 +2745,9 @@ _mm256_cvtsph_bf8(__m256h __A) {
}
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated.
-/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead.
+/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -2774,13 +2766,13 @@ _mm256_cvtsph_bf8(__m256h __A) {
/// This intrinsic corresponds to the \c VCVTPH2BF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x bf8].
+/// A 128-bit vector of [6 x bf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
/// A 256-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the
+/// A 128-bit vector of [6 x bf8]. Resulting elements correspond to the
/// (converted) elements from \a __A. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
@@ -2790,9 +2782,9 @@ _mm256_mask_cvtsph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
}
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated.
-/// Zeroing mask \a __U is used to determine if given element should be zeroed
-/// instead.
+/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -2813,9 +2805,9 @@ _mm256_mask_cvtsph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 128-bit vector of [16 x bf8]. Resulting elements correspond to the
+/// A 128-bit vector of [6 x bf8]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// then element is zeroed instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
@@ -2825,8 +2817,8 @@ _mm256_maskz_cvtsph_bf8(__mmask16 __U, __m256h __A) {
}
/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
-/// resulting vector are zeroed.
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -2843,7 +2835,7 @@ _mm256_maskz_cvtsph_bf8(__mmask16 __U, __m256h __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the (converted)
+/// A 128-bit vector of [6 x hf8]. Lower elements correspond to the (converted)
/// elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_hf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2hf8_128_mask(
@@ -2851,9 +2843,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_hf8(__m128h __A) {
}
/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
-/// resulting vector are zeroed. Merging mask \a __U is used to determine if
-/// given element should be taken from \a __W instead.
+/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Merging mask \a __U is used to determine if
+/// given element should be taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -2872,14 +2864,14 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_hf8(__m128h __A) {
/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x hf8].
+/// A 128-bit vector of [6 x hf8].
/// \param __U
/// A 8-bit merging mask.
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
///
-/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the
+/// A 128-bit vector of [6 x hf8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -2889,9 +2881,9 @@ _mm_mask_cvtph_hf8(__m128i __W, __mmask8 __U, __m128h __A) {
}
/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
-/// resulting vector are zeroed. Zeroing mask \a __U is used to determine if
-/// given element should be zeroed instead.
+/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Zeroing mask \a __U is used to determine if
+/// given element should be zeroed instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -2915,7 +2907,7 @@ _mm_mask_cvtph_hf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// A 128-bit vector of [8 x fp16].
/// \returns
///
-/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the
+/// A 128-bit vector of [6 x hf8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -2925,7 +2917,7 @@ _mm_maskz_cvtph_hf8(__mmask8 __U, __m128h __A) {
}
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E4M3 FP8 elements.
+/// to a 128-bit vector containing E4M3 FP8 elements.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -2940,9 +2932,9 @@ _mm_maskz_cvtph_hf8(__mmask8 __U, __m128h __A) {
/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction.
///
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the (converted)
+/// A 128-bit vector of [6 x hf8]. Resulting elements correspond to the (converted)
/// elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtph_hf8(__m256h __A) {
@@ -2951,9 +2943,9 @@ _mm256_cvtph_hf8(__m256h __A) {
}
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E4M3 FP8 elements. Merging mask \a __U is
-/// used to determine if given element should be taken from \a __W instead.
-///
+/// to a 128-bit vector containing E4M3 FP8 elements. Merging mask \a __U is
+/// used to determine if given element should be taken from \a __W instead.
+///
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
@@ -2971,13 +2963,13 @@ _mm256_cvtph_hf8(__m256h __A) {
/// This intrinsic corresponds to the \c VCVTPH2HF8 instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x hf8].
+/// A 128-bit vector of [6 x hf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
/// A 256-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the
+/// A 128-bit vector of [6 x hf8]. Resulting elements correspond to the
/// (converted) elements from \a __A. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
@@ -2987,9 +2979,9 @@ _mm256_mask_cvtph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {
}
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E4M3 FP8 elements. Zeroing mask \a __U is
-/// used to determine if given element should be zeroed instead.
-///
+/// to a 128-bit vector containing E4M3 FP8 elements. Zeroing mask \a __U is
+/// used to determine if given element should be zeroed instead.
+///
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
@@ -3009,9 +3001,9 @@ _mm256_mask_cvtph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the
+/// A 128-bit vector of [6 x hf8]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// then element is zeroed instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
@@ -3021,9 +3013,9 @@ _mm256_maskz_cvtph_hf8(__mmask16 __U, __m256h __A) {
}
/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
-/// resulting vector are zeroed. Results are saturated.
-///
+/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Results are saturated.
+///
/// \code{.operation}
/// FOR i := 0 to 7
/// dst.hf8[i] := convert_fp16_to_hf8_saturate(__A.fp16[i])
@@ -3039,7 +3031,7 @@ _mm256_maskz_cvtph_hf8(__mmask16 __U, __m256h __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the (converted)
+/// A 128-bit vector of [6 x hf8]. Lower elements correspond to the (converted)
/// elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_hf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtph2hf8s_128_mask(
@@ -3047,9 +3039,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_hf8(__m128h __A) {
}
/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
-/// resulting vector are zeroed. Results are saturated. Merging mask \a __U is
-/// used to determine if given element should be taken from \a __W instead.
+/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Results are saturated. Merging mask \a __U is
+/// used to determine if given element should be taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -3068,13 +3060,13 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_hf8(__m128h __A) {
/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x hf8].
+/// A 128-bit vector of [6 x hf8].
/// \param __U
/// A 8-bit merging mask.
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the
+/// A 128-bit vector of [6 x hf8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -3084,9 +3076,9 @@ _mm_mask_cvtsph_hf8(__m128i __W, __mmask8 __U, __m128h __A) {
}
/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
-/// resulting vector are zeroed. Results are saturated. Zeroing mask \a __U is
-/// used to determine if given element should be zeroed instead.
+/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Results are saturated. Zeroing mask \a __U is
+/// used to determine if given element should be zeroed instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -3109,7 +3101,7 @@ _mm_mask_cvtsph_hf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Lower elements correspond to the
+/// A 128-bit vector of [6 x hf8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -3119,7 +3111,7 @@ _mm_maskz_cvtsph_hf8(__mmask8 __U, __m128h __A) {
}
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated.
+/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -3134,9 +3126,9 @@ _mm_maskz_cvtsph_hf8(__mmask8 __U, __m128h __A) {
/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction.
///
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the (converted)
+/// A 128-bit vector of [6 x hf8]. Resulting elements correspond to the (converted)
/// elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtsph_hf8(__m256h __A) {
@@ -3145,9 +3137,9 @@ _mm256_cvtsph_hf8(__m256h __A) {
}
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated.
-/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead.
+/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -3166,13 +3158,13 @@ _mm256_cvtsph_hf8(__m256h __A) {
/// This intrinsic corresponds to the \c VCVTPH2HF8S instruction.
///
/// \param __W
-/// A 128-bit vector of [16 x hf8].
+/// A 128-bit vector of [6 x hf8].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
/// A 256-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the
+/// A 128-bit vector of [6 x hf8]. Resulting elements correspond to the
/// (converted) elements from \a __A. If
/// corresponding mask bit is not set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
@@ -3182,9 +3174,9 @@ _mm256_mask_cvtsph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {
}
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
-/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated.
-/// Zeroing mask \a __U is used to determine if given element should be zeroed
-/// instead.
+/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -3205,9 +3197,9 @@ _mm256_mask_cvtsph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \returns
-/// A 128-bit vector of [16 x hf8]. Resulting elements correspond to the
+/// A 128-bit vector of [6 x hf8]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// then element is zeroed instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
@@ -3217,7 +3209,7 @@ _mm256_maskz_cvtsph_hf8(__mmask16 __U, __m256h __A) {
}
/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point
-/// elements to a 128-bit vector containing FP16 elements. The conversion is exact.
+/// elements to a 128-bit vector containing FP16 elements. The conversion is exact.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -3230,7 +3222,7 @@ _mm256_maskz_cvtsph_hf8(__mmask16 __U, __m256h __A) {
/// This intrinsic does not correspond to a single instruction.
///
/// \param __A
-/// A 128-bit vector of [16 x bf8].
+/// A 128-bit vector of [6 x bf8].
/// \returns
/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A.
@@ -3239,9 +3231,9 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtbf8_ph(__m128i __A) {
}
/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point
-/// elements to a 128-bit vector containing FP16 elements. The conversion is
-/// exact. Merging mask \a __U is used to determine if given element should be
-/// taken from \a __W instead.
+/// elements to a 128-bit vector containing FP16 elements. The conversion is
+/// exact. Merging mask \a __U is used to determine if given element should be
+/// taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -3262,7 +3254,7 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtbf8_ph(__m128i __A) {
/// \param __U
/// A 8-bit merging mask.
/// \param __A
-/// A 128-bit vector of [16 x bf8].
+/// A 128-bit vector of [6 x bf8].
/// \returns
/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
@@ -3274,9 +3266,9 @@ _mm_mask_cvtbf8_ph(__m128h __W, __mmask8 __U, __m128i __A) {
}
/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point
-/// elements to a 128-bit vector containing FP16 elements. The conversion is
-/// exact. Zeroing mask \a __U is used to determine if given element should be
-/// zeroed instead.
+/// elements to a 128-bit vector containing FP16 elements. The conversion is
+/// exact. Zeroing mask \a __U is used to determine if given element should be
+/// zeroed instead.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -3295,7 +3287,7 @@ _mm_mask_cvtbf8_ph(__m128h __W, __mmask8 __U, __m128i __A) {
/// \param __U
/// A 8-bit zeroing mask.
/// \param __A
-/// A 128-bit vector of [16 x bf8].
+/// A 128-bit vector of [6 x bf8].
/// \returns
/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
@@ -3306,7 +3298,7 @@ _mm_maskz_cvtbf8_ph(__mmask8 __U, __m128i __A) {
}
/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point
-/// elements to a 256-bit vector containing FP16 elements. The conversion is exact.
+/// elements to a 256-bit vector containing FP16 elements. The conversion is exact.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -3319,18 +3311,18 @@ _mm_maskz_cvtbf8_ph(__mmask8 __U, __m128i __A) {
/// This intrinsic does not correspond to a single instruction.
///
/// \param __A
-/// A 256-bit vector of [32 x bf8].
+/// A 256-bit vector of [2 x bf8].
/// \returns
-/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
+/// A 256-bit vector of [6 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtbf8_ph(__m128i __A) {
return _mm256_castsi256_ph(_mm256_slli_epi16(_mm256_cvtepi8_epi16(__A), 8));
}
/// Convert 256-bit vector \a __A, containing packed FP8 E5M2 floating-point
-/// elements to a 256-bit vector containing FP16 elements. The conversion is
-/// exact. Merging mask \a __U is used to determine if given element should be
-/// taken from \a __W instead.
+/// elements to a 256-bit vector containing FP16 elements. The conversion is
+/// exact. Merging mask \a __U is used to determine if given element should be
+/// taken from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -3347,13 +3339,13 @@ static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtbf8_ph(__m128i __A) {
/// This intrinsic does not correspond to a single instruction.
///
/// \param __W
-/// A 256-bit vector of [16 x fp16].
+/// A 256-bit vector of [6 x fp16].
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [32 x bf8].
+/// A 256-bit vector of [2 x bf8].
/// \returns
-/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
+/// A 256-bit vector of [6 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// element from \a __W is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
@@ -3363,9 +3355,9 @@ _mm256_mask_cvtbf8_ph(__m256h __W, __mmask16 __U, __m128i __A) {
}
/// Convert 256-bit vector \a __A, containing packed FP8 E5M2 floating-point
-/// elements to a 256-bit vector containing FP16 elements. The conversion is
-/// exact. Zeroing mask \a __U is used to determine if given element should be
-/// zeroed instead.
+/// elements to a 256-bit vector containing FP16 elements. The conversion is
+/// exact. Zeroing mask \a __U is used to determine if given element should be
+/// zeroed instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -3384,9 +3376,9 @@ _mm256_mask_cvtbf8_ph(__m256h __W, __mmask16 __U, __m128i __A) {
/// \param __U
/// A 16-bit merging mask.
/// \param __A
-/// A 256-bit vector of [32 x bf8].
+/// A 256-bit vector of [2 x bf8].
/// \returns
-/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
+/// A 256-bit vector of [6 x fp16]. Resulting elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// zero is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
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