[clang] [llvm] [AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (PR #127837)

[Paul Walker via cfe-commits]

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@@ -2993,6 +2993,22 @@ let Predicates = [HasSVE_or_SME] in {
   defm : unpred_loadstore_bitcast<nxv2i64>;
   defm : unpred_loadstore_bitcast<nxv2f64>;
 
+  // Allow using LDR/STR to avoid the predicate dependence.
+  let Predicates = [IsLE, AllowMisalignedMemAccesses] in
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paulwalker-arm wrote:

```suggestion
  let Predicates = [HasSVE_or_SME, IsLE, AllowMisalignedMemAccesses] in
```
This is not critical because in theory we shouldn't get this far if scalable vectors are not available but this is normally what we do when overriding `Predicate`.

https://github.com/llvm/llvm-project/pull/127837