[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)

[Craig Topper via cfe-commits]

topperc wrote:

> Even for these rare cases, the user can achieve the same effect if they put `vl/vtype` into clobbered registers explicitly.

They can, but will they? clobbers are a relatively uncommon feature I suspect many people don't know about it.

I think maybe we need documentation of how to use RVV with inline assembly. I've seen a lot of things that aren't technically correct, but usually work.

For example, one statement per instruction with hand allocated vector registers and no clobbers. The vector register aren't technically alive between the statements as far as the compiler is concerned.

https://github.com/llvm/llvm-project/pull/128636