[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)

[Min-Yih Hsu via cfe-commits]

mshockwave wrote:

I think what @wangpc-pp advocated here (please correct me if I'm wrong) was that user should be responsible annotating these registers as clobbered so that we have more freedom on scheduling when the inline assembly is not using any vector instructions. While other approaches -- regardless of marking them as clobber or implicit-def these two registers in RISCVInsertVSETVLI -- are taking a more conservative path to ensure correctness.

It's a shame that we're not able to analyze the instructions within inline assembly to make a better decision. Personally I think we should prioritize correctness, therefore I'm more incline to the latter approaches. I do agree that we probably should only do it when vector instructions are present, as pointed out by one of the review comments by @wangpc-pp.

https://github.com/llvm/llvm-project/pull/128636