[clang] 538b898 - [RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (#124706)
via cfe-commits
cfe-commits at lists.llvm.org
Mon Feb 24 08:04:37 PST 2025
Author: quic_hchandel
Date: 2025-02-24T08:04:29-08:00
New Revision: 538b898a836ac6efc3b0ec12cf27b511608d2e64
URL: https://github.com/llvm/llvm-project/commit/538b898a836ac6efc3b0ec12cf27b511608d2e64
DIFF: https://github.com/llvm/llvm-project/commit/538b898a836ac6efc3b0ec12cf27b511608d2e64.diff
LOG: [RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (#124706)
This extension adds eight 48 bit large arithmetic instructions.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
Added:
llvm/test/MC/RISCV/xqcilia-invalid.s
llvm/test/MC/RISCV/xqcilia-valid.s
Modified:
clang/test/Driver/print-supported-extensions-riscv.c
llvm/docs/RISCVUsage.rst
llvm/docs/ReleaseNotes.md
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
llvm/lib/TargetParser/RISCVISAInfo.cpp
llvm/test/CodeGen/RISCV/attributes.ll
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Removed:
################################################################################
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 9c089bed99e9a..fcd820464e2d1 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -200,6 +200,7 @@
// CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension)
// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension)
// CHECK-NEXT: xqciint 0.2 'Xqciint' (Qualcomm uC Interrupts Extension)
+// CHECK-NEXT: xqcilia 0.2 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 09fb59f94e84d..3c59216a40976 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -450,6 +450,9 @@ The current vendor extensions supported are:
``experimental-Xqciint``
LLVM implements `version 0.2 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
+``experimental-Xqcilia``
+ LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
+
``experimental-Xqcilo``
LLVM implements `version 0.2 of the Qualcomm uC Large Offset Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 9203e22a9c886..2a617901a1146 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -107,6 +107,9 @@ Changes to the PowerPC Backend
Changes to the RISC-V Backend
-----------------------------
+* Adds experimental assembler support for the Qualcomm uC 'Xqcilia` (Large Immediate Arithmetic)
+ extension.
+
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 6d4466b7abf53..650ad48e50de0 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1056,6 +1056,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
isInt<26>(fixImmediateForRV32(Imm, isRV64Imm()));
}
+ bool isSImm32() const {
+ int64_t Imm;
+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+ if (!isImm())
+ return false;
+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+ return IsConstantImm && isInt<32>(fixImmediateForRV32(Imm, isRV64Imm())) &&
+ VK == RISCVMCExpr::VK_RISCV_None;
+ }
+
/// getStartLoc - Gets location of the first token of this operand
SMLoc getStartLoc() const override { return StartLoc; }
/// getEndLoc - Gets location of the last token of this operand
@@ -1665,6 +1675,10 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidSImm26:
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 25),
(1 << 25) - 1);
+ case Match_InvalidSImm32:
+ return generateImmOutOfRangeError(Operands, ErrorInfo,
+ std::numeric_limits<int32_t>::min(),
+ std::numeric_limits<uint32_t>::max());
case Match_InvalidRnumArg: {
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 10);
}
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 53208b43faabc..8c07d87680d65 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -767,6 +767,8 @@ DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size,
for (size_t i = Size; i-- != 0;) {
Insn += (static_cast<uint64_t>(Bytes[i]) << 8 * i);
}
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcilia, DecoderTableXqcilia48,
+ "Qualcomm uC Large Immediate Arithmetic 48bit");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcilo, DecoderTableXqcilo48,
"Qualcomm uC Large Offset Load Store 48bit");
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 2e5b03c2eba5a..80ff18d914dca 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -327,6 +327,7 @@ enum OperandType : unsigned {
OPERAND_SIMM12,
OPERAND_SIMM12_LSB00000,
OPERAND_SIMM26,
+ OPERAND_SIMM32,
OPERAND_CLUI_IMM,
OPERAND_VTYPEI10,
OPERAND_VTYPEI11,
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 26d46afe68923..1a93371a4d92f 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1358,6 +1358,14 @@ def HasVendorXqciint
AssemblerPredicate<(all_of FeatureVendorXqciint),
"'Xqciint' (Qualcomm uC Interrupts Extension)">;
+def FeatureVendorXqcilia
+ : RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Immediate Arithmetic Extension",
+ [FeatureStdExtZca]>;
+def HasVendorXqcilia
+ : Predicate<"Subtarget->hasVendorXqcilia()">,
+ AssemblerPredicate<(all_of FeatureVendorXqcilia),
+ "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)">;
+
def FeatureVendorXqcilo
: RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Offset Load Store Extension",
[FeatureStdExtZca]>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 1f042b0f47e96..3a8039fce1f49 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -34,6 +34,21 @@ def uimm11 : RISCVUImmLeafOp<11>;
def simm26 : RISCVSImmLeafOp<26>;
+// 32-bit Immediate, used by RV32 Instructions in 32-bit operations, so no
+// sign-/zero-extension. This is represented internally as a signed 32-bit value.
+def simm32 : RISCVOp<XLenVT> {
+ let ParserMatchClass = SImmAsmOperand<32, "">;
+ let EncoderMethod = "getImmOpValue";
+ let DecoderMethod = "decodeSImmOperand<32>";
+ let OperandType = "OPERAND_SIMM32";
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return isInt<32>(Imm);
+ return false;
+ }];
+}
+
//===----------------------------------------------------------------------===//
// Instruction Formats
//===----------------------------------------------------------------------===//
@@ -245,6 +260,25 @@ class QCIRVInstESStore<bits<3> funct3, bits<2> funct2, string opcodestr>
(ins GPRMem:$rs2, GPR:$rs1, simm26:$imm),
opcodestr, "$rs2, ${imm}(${rs1})">;
+class QCIRVInstEAI<bits<3> funct3, bits<1> funct1, string opcodestr>
+ : RVInst48<(outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, simm32:$imm),
+ opcodestr, "$rd, $imm", [], InstFormatOther> {
+ bits<5> rd;
+ bits<32> imm;
+
+ let Constraints = "$rd = $rd_wb";
+ let Inst{47-16} = imm{31-0};
+ let Inst{15} = funct1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = 0b0011111;
+}
+
+class QCIRVInstEI<bits<3> funct3, bits<2> funct2, string opcodestr>
+ : QCIRVInstEIBase<funct3, funct2, (outs GPRNoX0:$rd),
+ (ins GPRNoX0:$rs1, simm26:$imm), opcodestr,
+ "$rd, $rs1, $imm">;
+
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
@@ -435,6 +469,20 @@ let Predicates = [HasVendorXqcilo, IsRV32], DecoderNamespace = "Xqcilo" in {
def QC_E_SW : QCIRVInstESStore<0b110, 0b11, "qc.e.sw">;
} // Predicates = [HasVendorXqcilo, IsRV32], DecoderNamespace = "Xqcilo"
+let Predicates = [HasVendorXqcilia, IsRV32], DecoderNamespace = "Xqcilia" in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+ def QC_E_XORAI : QCIRVInstEAI<0b001, 0b0, "qc.e.xorai">;
+ def QC_E_ORAI : QCIRVInstEAI<0b001, 0b1, "qc.e.orai" >;
+ def QC_E_ADDAI : QCIRVInstEAI<0b010, 0b0, "qc.e.addai">;
+ def QC_E_ANDAI : QCIRVInstEAI<0b010, 0b1, "qc.e.andai">;
+
+ def QC_E_XORI : QCIRVInstEI<0b011, 0b00, "qc.e.xori">;
+ def QC_E_ORI : QCIRVInstEI<0b011, 0b01, "qc.e.ori" >;
+ def QC_E_ADDI : QCIRVInstEI<0b011, 0b10, "qc.e.addi">;
+ def QC_E_ANDI : QCIRVInstEI<0b011, 0b11, "qc.e.andi">;
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+} // Predicates = [HasVendorXqcilia, IsRV32], DecoderNamespace = "Xqcilia"
+
//===----------------------------------------------------------------------===//
// Aliases
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index c78d60fd86b3f..132c47ca631b6 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -742,8 +742,9 @@ Error RISCVISAInfo::checkDependency() {
bool HasZvl = MinVLen != 0;
bool HasZcmt = Exts.count("zcmt") != 0;
static constexpr StringLiteral XqciExts[] = {
- {"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"}, {"xqcics"},
- {"xqcicsr"}, {"xqciint"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
+ {"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"},
+ {"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqcilia"},
+ {"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
if (HasI && HasE)
return getIncompatibleError("i", "e");
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index b9d5bf0a7227c..daab7b236879f 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -88,6 +88,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics %s -o - | FileCheck --check-prefix=RV32XQCICS %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciint %s -o - | FileCheck --check-prefix=RV32XQCIINT %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilia %s -o - | FileCheck --check-prefix=RV32XQCILIA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilo %s -o - | FileCheck --check-prefix=RV32XQCILO %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilsm %s -o - | FileCheck --check-prefix=RV32XQCILSM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s
@@ -404,6 +405,7 @@
; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2"
; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2"
; RV32XQCIINT: .attribute 5, "rv32i2p1_zca1p0_xqciint0p2"
+; RV32XQCILIA: .attribute 5, "rv32i2p1_zca1p0_xqcilia0p2"
; RV32XQCILO: .attribute 5, "rv32i2p1_zca1p0_xqcilo0p2"
; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2"
; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2"
diff --git a/llvm/test/MC/RISCV/xqcilia-invalid.s b/llvm/test/MC/RISCV/xqcilia-invalid.s
new file mode 100644
index 0000000000000..50b56bc0db41d
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqcilia-invalid.s
@@ -0,0 +1,117 @@
+# Xqcilia - Qualcomm uC Large Immediate Arithmetic extension
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcilia < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS,CHECK-IMM %s
+# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcilia < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS,CHECK-EXT %s
+
+# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction
+qc.e.addai 9, 33554432
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.addai x9
+
+# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
+qc.e.addai x9, 20485546494
+
+# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
+qc.e.addai x9, 33554432
+
+
+# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
+qc.e.addi x10, 9, 554432
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.addi x10, x9
+
+# CHECK-IMM: :[[@LINE+1]]:20: error: immediate must be an integer in the range [-33554432, 33554431]
+qc.e.addi x10, x9, 335544312
+
+# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
+qc.e.addi x10, x9, 554432
+
+
+# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction
+qc.e.andai 9, 33554432
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.andai x9
+
+# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
+qc.e.andai x9, 20494437494
+
+# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
+qc.e.andai x9, 33554432
+
+
+# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
+qc.e.andi x10, 9, 554432
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.andi x10, x9
+
+# CHECK-IMM: :[[@LINE+1]]:20: error: immediate must be an integer in the range [-33554432, 33554431]
+qc.e.andi x10, x9, 335544312
+
+# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
+qc.e.andi x10, x9, 554432
+
+
+# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction
+qc.e.orai 9, 33554432
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.orai x9
+
+# CHECK-IMM: :[[@LINE+1]]:15: error: immediate must be an integer in the range [-2147483648, 4294967295]
+qc.e.orai x9, 20494437494
+
+# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
+qc.e.orai x9, 33554432
+
+
+# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction
+qc.e.ori x10, 9, 554432
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.ori x10, x9
+
+# CHECK-IMM: :[[@LINE+1]]:19: error: immediate must be an integer in the range [-33554432, 33554431]
+qc.e.ori x10, x9, 335544312
+
+# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
+qc.e.ori x10, x9, 554432
+
+
+
+# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction
+qc.e.xorai 9, 33554432
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.xorai x9
+
+# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
+qc.e.xorai x9, 20494437494
+
+# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
+qc.e.xorai x9, 33554432
+
+
+# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction
+qc.e.xori x10, 9, 554432
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.xori x10, x9
+
+# CHECK-IMM: :[[@LINE+1]]:20: error: immediate must be an integer in the range [-33554432, 33554431]
+qc.e.xori x10, x9, 335544312
+
+# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
+qc.e.xori x10, x9, 554432
diff --git a/llvm/test/MC/RISCV/xqcilia-valid.s b/llvm/test/MC/RISCV/xqcilia-valid.s
new file mode 100644
index 0000000000000..49727d5d36239
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqcilia-valid.s
@@ -0,0 +1,82 @@
+# Xqcilia - Qualcomm uC Large Immediate Arithmetic extension
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilia -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilia < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xqcilia -M no-aliases --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilia -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilia < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xqcilia --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: qc.e.addai s1, -1
+# CHECK-ENC: encoding: [0x9f,0x24,0xff,0xff,0xff,0xff]
+qc.e.addai x9, 4294967295
+
+# CHECK-INST: qc.e.addai s1, -2147483648
+# CHECK-ENC: encoding: [0x9f,0x24,0x00,0x00,0x00,0x80]
+qc.e.addai x9, -2147483648
+
+
+# CHECK-INST: qc.e.addi a0, s1, -33554432
+# CHECK-ENC: encoding: [0x1f,0xb5,0x04,0x80,0x00,0x80]
+qc.e.addi x10, x9, -33554432
+
+# CHECK-INST: qc.e.addi a0, s1, 33554431
+# CHECK-ENC: encoding: [0x1f,0xb5,0xf4,0xbf,0xff,0x7f]
+qc.e.addi x10, x9, 33554431
+
+
+# CHECK-INST: qc.e.andai s1, -1
+# CHECK-ENC: encoding: [0x9f,0xa4,0xff,0xff,0xff,0xff]
+qc.e.andai x9, 4294967295
+
+# CHECK-INST: qc.e.andai s1, -2147483648
+# CHECK-ENC: encoding: [0x9f,0xa4,0x00,0x00,0x00,0x80]
+qc.e.andai x9, -2147483648
+
+
+# CHECK-INST: qc.e.andi a0, s1, -33554432
+# CHECK-ENC: encoding: [0x1f,0xb5,0x04,0xc0,0x00,0x80]
+qc.e.andi x10, x9, -33554432
+
+# CHECK-INST: qc.e.andi a0, s1, 33554431
+# CHECK-ENC: encoding: [0x1f,0xb5,0xf4,0xff,0xff,0x7f]
+qc.e.andi x10, x9, 33554431
+
+
+# CHECK-INST: qc.e.orai s1, -1
+# CHECK-ENC: encoding: [0x9f,0x94,0xff,0xff,0xff,0xff]
+qc.e.orai x9, 4294967295
+
+# CHECK-INST: qc.e.orai s1, -2147483648
+# CHECK-ENC: encoding: [0x9f,0x94,0x00,0x00,0x00,0x80]
+qc.e.orai x9, -2147483648
+
+
+# CHECK-INST: qc.e.ori a0, s1, -33554432
+# CHECK-ENC: encoding: [0x1f,0xb5,0x04,0x40,0x00,0x80]
+qc.e.ori x10, x9, -33554432
+
+# CHECK-INST: qc.e.ori a0, s1, 33554431
+# CHECK-ENC: encoding: [0x1f,0xb5,0xf4,0x7f,0xff,0x7f]
+qc.e.ori x10, x9, 33554431
+
+
+# CHECK-INST: qc.e.xorai s1, -1
+# CHECK-ENC: encoding: [0x9f,0x14,0xff,0xff,0xff,0xff]
+qc.e.xorai x9, 4294967295
+
+# CHECK-INST: qc.e.xorai s1, -2147483648
+# CHECK-ENC: encoding: [0x9f,0x14,0x00,0x00,0x00,0x80]
+qc.e.xorai x9, -2147483648
+
+
+# CHECK-INST: qc.e.xori a0, s1, -33554432
+# CHECK-ENC: encoding: [0x1f,0xb5,0x04,0x00,0x00,0x80]
+qc.e.xori x10, x9, -33554432
+
+# CHECK-INST: qc.e.xori a0, s1, 33554431
+# CHECK-ENC: encoding: [0x1f,0xb5,0xf4,0x3f,0xff,0x7f]
+qc.e.xori x10, x9, 33554431
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 549a411381040..f734b4e25551b 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -657,7 +657,7 @@ TEST(ParseArchString, RejectsConflictingExtensions) {
{"rv64i_xqcisls0p2", "rv64i_xqcia0p2", "rv64i_xqciac0p3",
"rv64i_xqcicsr0p2", "rv64i_xqcilsm0p2", "rv64i_xqcicm0p2",
"rv64i_xqcics0p2", "rv64i_xqcicli0p2", "rv64i_xqciint0p2",
- "rv64i_xqcilo0p2"}) {
+ "rv64i_xqcilo0p2", "rv64i_xqcilia0p2"}) {
EXPECT_THAT(
toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
::testing::EndsWith(" is only supported for 'rv32'"));
@@ -1126,6 +1126,7 @@ Experimental extensions
xqcics 0.2
xqcicsr 0.2
xqciint 0.2
+ xqcilia 0.2
xqcilo 0.2
xqcilsm 0.2
xqcisls 0.2
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