[clang] aef63c5 - [RISCV] Assembler support for XRivosVizip (#127694)
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Fri Feb 21 15:44:37 PST 2025
Author: Philip Reames
Date: 2025-02-21T15:44:33-08:00
New Revision: aef63c506be7ba791d0e0befc48f7837638a233a
URL: https://github.com/llvm/llvm-project/commit/aef63c506be7ba791d0e0befc48f7837638a233a
DIFF: https://github.com/llvm/llvm-project/commit/aef63c506be7ba791d0e0befc48f7837638a233a.diff
LOG: [RISCV] Assembler support for XRivosVizip (#127694)
This implements assembler support for the XRivosVizip custom/vendor
extension from Rivos Inc. which is defined in:
https://github.com/rivosinc/rivos-custom-extensions (See
src/xrivosvizip.adoc)
Codegen support will follow in a separate change.
Added:
llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
llvm/test/MC/RISCV/xrivosvizip-invalid.s
llvm/test/MC/RISCV/xrivosvizip-valid.s
Modified:
clang/test/Driver/print-supported-extensions-riscv.c
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Removed:
################################################################################
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 49c5bfca2716f..9c089bed99e9a 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -203,6 +203,7 @@
// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
+// CHECK-NEXT: xrivosvizip 0.1 'XRivosVizip' (Rivos Vector Register Zips)
// CHECK-EMPTY:
// CHECK-NEXT: Supported Profiles
// CHECK-NEXT: rva20s64
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 8515ec266289b..53208b43faabc 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -711,6 +711,9 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
"Qualcomm uC Conditional Move");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqciint, DecoderTableXqciint32,
"Qualcomm uC Interrupts");
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXRivosVizip, DecoderTableXRivos32,
+ "Rivos");
+
TRY_TO_DECODE(true, DecoderTable32, "RISCV32");
return MCDisassembler::Fail;
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 30595119e37bf..26d46afe68923 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1366,6 +1366,15 @@ def HasVendorXqcilo
AssemblerPredicate<(all_of FeatureVendorXqcilo),
"'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)">;
+// Rivos Extension(s)
+
+def FeatureVendorXRivosVizip
+ : RISCVExperimentalExtension<0, 1, "Rivos Vector Register Zips">;
+def HasVendorXRivosVizip
+ : Predicate<"Subtarget->hasVendorXRivosVizip()">,
+ AssemblerPredicate<(all_of FeatureVendorXRivosVizip),
+ "'XRivosVizip' (Rivos Vector Register Zips)">;
+
//===----------------------------------------------------------------------===//
// LLVM specific features and extensions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index fde7dc89dd693..a962e64581797 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2148,6 +2148,7 @@ include "RISCVInstrInfoXCV.td"
include "RISCVInstrInfoXwch.td"
include "RISCVInstrInfoXqci.td"
include "RISCVInstrInfoXMips.td"
+include "RISCVInstrInfoXRivos.td"
//===----------------------------------------------------------------------===//
// Global ISel
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
new file mode 100644
index 0000000000000..873fa150755ba
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
@@ -0,0 +1,27 @@
+//===-- RISCVInstrInfoXRivos.td ----------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the vendor extensions defined by Rivos Inc.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// XRivosVizip
+//===----------------------------------------------------------------------===//
+
+
+let Predicates = [HasVendorXRivosVizip], DecoderNamespace = "XRivos",
+ Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather,
+ Inst<6-0> = OPC_CUSTOM_2.Value in {
+defm RV_VZIPEVEN_V : VALU_IV_V<"rv.vzipeven", 0b001100>;
+defm RV_VZIPODD_V : VALU_IV_V<"rv.vzipodd", 0b011100>;
+defm RV_VZIP2A_V : VALU_IV_V<"rv.vzip2a", 0b000100>;
+defm RV_VZIP2B_V : VALU_IV_V<"rv.vzip2b", 0b010100>;
+defm RV_VUNZIP2A_V : VALU_IV_V<"rv.vunzip2a", 0b001000>;
+defm RV_VUNZIP2B_V : VALU_IV_V<"rv.vunzip2b", 0b011000>;
+}
diff --git a/llvm/test/MC/RISCV/xrivosvizip-invalid.s b/llvm/test/MC/RISCV/xrivosvizip-invalid.s
new file mode 100644
index 0000000000000..5a36c7757849c
--- /dev/null
+++ b/llvm/test/MC/RISCV/xrivosvizip-invalid.s
@@ -0,0 +1,10 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-xrivosvizip < %s 2>&1 | \
+# RUN: FileCheck %s
+
+# Disallowed source/dest overlap cases
+# CHECK: error: the destination vector register group cannot overlap the source vector register group
+rv.vzipeven.vv v2, v2, v3
+# CHECK: error: the destination vector register group cannot overlap the source vector register group
+rv.vzipeven.vv v3, v2, v3
+# CHECK: error: the destination vector register group cannot overlap the mask register
+rv.vzipeven.vv v0, v2, v3, v0.t
diff --git a/llvm/test/MC/RISCV/xrivosvizip-valid.s b/llvm/test/MC/RISCV/xrivosvizip-valid.s
new file mode 100644
index 0000000000000..1447e0a950a2c
--- /dev/null
+++ b/llvm/test/MC/RISCV/xrivosvizip-valid.s
@@ -0,0 +1,59 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xrivosvizip -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-xrivosvizip < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xrivosvizip -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-xrivosvizip -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-xrivosvizip < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xrivosvizip -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: rv.vzipeven.vv v1, v2, v3
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x32]
+rv.vzipeven.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vzipeven.vv v1, v2, v3, v0.t
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x30]
+rv.vzipeven.vv v1, v2, v3, v0.t
+# CHECK-ASM-AND-OBJ: rv.vzipodd.vv v1, v2, v3
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x72]
+rv.vzipodd.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vzipodd.vv v1, v2, v3, v0.t
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x70]
+rv.vzipodd.vv v1, v2, v3, v0.t
+
+# CHECK-ASM-AND-OBJ: rv.vzip2a.vv v1, v2, v3
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x12]
+rv.vzip2a.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vzip2a.vv v1, v2, v3, v0.t
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x10]
+rv.vzip2a.vv v1, v2, v3, v0.t
+# CHECK-ASM-AND-OBJ: rv.vzip2b.vv v1, v2, v3
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x52]
+rv.vzip2b.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vzip2b.vv v1, v2, v3, v0.t
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x50]
+rv.vzip2b.vv v1, v2, v3, v0.t
+
+# CHECK-ASM-AND-OBJ: rv.vunzip2a.vv v1, v2, v3
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x22]
+rv.vunzip2a.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vunzip2a.vv v1, v2, v3, v0.t
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x20]
+rv.vunzip2a.vv v1, v2, v3, v0.t
+# CHECK-ASM-AND-OBJ: rv.vunzip2b.vv v1, v2, v3
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x62]
+rv.vunzip2b.vv v1, v2, v3
+# CHECK-ASM-AND-OBJ: rv.vunzip2b.vv v1, v2, v3, v0.t
+# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x60]
+rv.vunzip2b.vv v1, v2, v3, v0.t
+
+# Overlap between source registers *is* allowed
+
+# CHECK-ASM-AND-OBJ: rv.vzipeven.vv v1, v2, v2
+# CHECK-ASM: encoding: [0xdb,0x00,0x21,0x32]
+rv.vzipeven.vv v1, v2, v2
+
+# CHECK-ASM-AND-OBJ: rv.vzipeven.vv v1, v2, v0, v0.t
+# CHECK-ASM: encoding: [0xdb,0x00,0x20,0x30]
+rv.vzipeven.vv v1, v2, v0, v0.t
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 563f587d9d1c0..549a411381040 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1129,6 +1129,7 @@ Experimental extensions
xqcilo 0.2
xqcilsm 0.2
xqcisls 0.2
+ xrivosvizip 0.1
Supported Profiles
rva20s64
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