[clang] [llvm] [AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (PR #127837)

[Benjamin Maxwell via cfe-commits]

MacDue wrote:

I think with the `AllowMisalignedMemAccesses` check (preventing this applying when `+strict-align` is set) this _probably_ okay. The `LDR ZPR` notes:

> The load is performed as contiguous byte accesses, with no endian conversion and no guarantee of single-copy atomicity larger than a byte. However, if alignment is checked, then the base register must be aligned to 16 bytes.

http://developer.arm.com/documentation/ddi0602/2024-12/SVE-Instructions/LDR--vector---Load-vector-register-

Alignment checking is enabled by `SCTLR_EL1.A`, which is disabled by default:

https://developer.arm.com/documentation/ddi0488/h/system-control/aarch64-register-descriptions/system-control-register--el1

https://github.com/llvm/llvm-project/pull/127837