[clang] [llvm] [AArch64][SVE] Lower unpredicated loads/stores as LDR/STR. (PR #127837)

[Ricardo Jesus via cfe-commits]

rj-jesus wrote:

Hi @paulwalker-arm, I think the alignment requirements of LD1 and LDR are indeed different, but this only matters if `AlignmentEnforced()` is enabled, right? I thought `AlignmentEnforced` wasn't generally a concern, otherwise even the current lowering we have for `vld1q_u8(uint8_t const *ptr)`, for example, seems too permissive (https://godbolt.org/z/coYefno3j):
```cpp
#include <arm_neon.h>

uint8x16_t foo(uint8_t *ptr) {
  return vld1q_u8(ptr);
}
```
Currently gets lowered to:
```llvm
define <16 x i8> @foo(ptr %0) {
  %2 = load <16 x i8>, ptr %0, align 1
  ret <16 x i8> %2
}
```
Which finally lowers to:
```gas
foo:
        ldr     q0, [x0]
        ret
```
`ptr` isn't necessarily aligned to 16 (in the IR, it's only guaranteed to be aligned to 1), but, unless I'm missing something in the docs, LDR.Q also seems to expect an alignment of 16 if `AlignmentEnforced` is enabled, and will fault if not.

Am I missing anything?

Also, even if we can't indeed lower LD1/ST1 to LDR/STR generally, do you think it would be worth trying to do it in some other more restricted way (for example only for SP, which I believe should be aligned to 16), or should we drop the idea entirely?

https://github.com/llvm/llvm-project/pull/127837