[libclc] [libclc] Suppress data-layout warnings during linking (PR #127532)

Mon Feb 17 10:16:50 PST 2025

https://github.com/frasercrmck created https://github.com/llvm/llvm-project/pull/127532

libclc uses llvm-link to link together all of the individually built libclc builtins files into one module. Some of these builtins files are compiled from source by clang whilst others are converted from LLVM IR directly to bytecode.

When llvm-link links a 'source' module into a 'destination' module, it warns if the two modules have differing data layouts.

The LLVM IR files libclc links either have no data layout (shared submodule files) or an explicit data layout in the case of certain amdgcn/r600 files.

The warnings are very noisy and largely inconsequential. We can suppress them exploiting a specific behaviours exhibited by llvm-link. When the destination module has no data layout, it is given the source module's data layout. Thus, if we link together all IR files first, followed by the clang-compiled modules, 99% of the warnings are suppressed as they arose from linking an empty data layout into a non-empty one.

The remaining warnings come from the amdgcn and r600 targets. Some of these were because the data layouts were out of date compared with what clang currently produced, so those were updated. However, even by grouping the IR files together, it may still link explicit ones with empty ones depending on the order the IR files are processed.

>From d9588e35df36015a91e0c71aa15c66ff2947251a Mon Sep 17 00:00:00 2001
From: Fraser Cormack <fraser at codeplay.com>
Date: Mon, 17 Feb 2025 18:04:08 +0000
Subject: [PATCH] [libclc] Suppress data-layout warnings during linking

libclc uses llvm-link to link together all of the individually built
libclc builtins files into one module. Some of these builtins files are
compiled from source by clang whilst others are converted from LLVM IR
directly to bytecode.

When llvm-link links a 'source' module into a 'destination' module, it
warns if the two modules have differing data layouts.

The LLVM IR files libclc links either have no data layout (shared
submodule files) or an explicit data layout in the case of certain
amdgcn/r600 files.

The warnings are very noisy and largely inconsequential. We can suppress
them exploiting a specific behaviours exhibited by llvm-link. When the
destination module has no data layout, it is given the source module's
data layout. Thus, if we link together all IR files first, followed by
the clang-compiled modules, 99% of the warnings are suppressed as they
arose from linking an empty data layout into a non-empty one.

The remaining warnings come from the amdgcn and r600 targets. Some of
these were because the data layouts were out of date compared with what
clang currently produced, so those were updated. However, even by
grouping the IR files together, it may still link explicit ones with
empty ones depending on the order the IR files are processed.
---
 .../minmax_helpers.ll                         |  6 +-----
 libclc/cmake/modules/AddLibclc.cmake          | 19 +++++++++++++++++--
 .../lib/image/get_image_attributes_impl.ll    |  2 +-
 libclc/r600/lib/image/read_image_impl.ll      |  2 +-
 libclc/r600/lib/image/write_image_impl.ll     |  2 +-
 5 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/libclc/amdgcn/lib/cl_khr_int64_extended_atomics/minmax_helpers.ll b/libclc/amdgcn/lib/cl_khr_int64_extended_atomics/minmax_helpers.ll
index 98f1f54718a1f..5300f7718a591 100644
--- a/libclc/amdgcn/lib/cl_khr_int64_extended_atomics/minmax_helpers.ll
+++ b/libclc/amdgcn/lib/cl_khr_int64_extended_atomics/minmax_helpers.ll
@@ -1,8 +1,4 @@
-#if __clang_major__ >= 7
-target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
-#else
-target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
-#endif
+target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
 
 define i64 @__clc__sync_fetch_and_min_global_8(i64 addrspace(1)* nocapture %ptr, i64 %value) nounwind alwaysinline {
 entry:
diff --git a/libclc/cmake/modules/AddLibclc.cmake b/libclc/cmake/modules/AddLibclc.cmake
index 5347b0822477b..b90d15d3185d0 100644
--- a/libclc/cmake/modules/AddLibclc.cmake
+++ b/libclc/cmake/modules/AddLibclc.cmake
@@ -225,7 +225,8 @@ function(add_libclc_builtin_set)
     message( FATAL_ERROR "Must provide ARCH, ARCH_SUFFIX, and TRIPLE" )
   endif()
 
-  set( bytecode_files "" )
+  set( bytecode_files )
+  set( bytecode_ir_files )
   foreach( file IN LISTS ARG_GEN_FILES ARG_LIB_FILES )
     # We need to take each file and produce an absolute input file, as well
     # as a unique architecture-specific output file. We deal with a mix of
@@ -263,9 +264,23 @@ function(add_libclc_builtin_set)
         "${ARG_COMPILE_FLAGS}" -I${CMAKE_CURRENT_SOURCE_DIR}/${file_dir}
       DEPENDENCIES ${input_file_dep}
     )
-    list( APPEND bytecode_files ${output_file} )
+
+    # Collect all files originating in LLVM IR separately
+    get_filename_component( file_ext ${file} EXT )
+    if( ${file_ext} STREQUAL ".ll" )
+      list( APPEND bytecode_ir_files ${output_file} )
+    else()
+      list( APPEND bytecode_files ${output_file} )
+    endif()
   endforeach()
 
+  # Prepend all LLVM IR files to the list so they are linked into the final
+  # bytecode modules first. This helps to suppress unnecessary warnings
+  # regarding different data layouts while linking. Any LLVM IR files without a
+  # data layout will (silently) be given the first data layout the linking
+  # process comes across.
+  list( PREPEND bytecode_files ${bytecode_ir_files} )
+
   set( builtins_comp_lib_tgt builtins.comp.${ARG_ARCH_SUFFIX} )
   add_custom_target( ${builtins_comp_lib_tgt}
     DEPENDS ${bytecode_files}
diff --git a/libclc/r600/lib/image/get_image_attributes_impl.ll b/libclc/r600/lib/image/get_image_attributes_impl.ll
index f867ab6603591..b64022c702d6e 100644
--- a/libclc/r600/lib/image/get_image_attributes_impl.ll
+++ b/libclc/r600/lib/image/get_image_attributes_impl.ll
@@ -1,4 +1,4 @@
-target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
 
 %opencl.image2d_t = type opaque
 %opencl.image3d_t = type opaque
diff --git a/libclc/r600/lib/image/read_image_impl.ll b/libclc/r600/lib/image/read_image_impl.ll
index ca2e465b4b5b8..ee76cde30d096 100644
--- a/libclc/r600/lib/image/read_image_impl.ll
+++ b/libclc/r600/lib/image/read_image_impl.ll
@@ -1,4 +1,4 @@
-target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
 
 %opencl.image2d_t = type opaque
 
diff --git a/libclc/r600/lib/image/write_image_impl.ll b/libclc/r600/lib/image/write_image_impl.ll
index 03595ba1db737..4b02e8a681188 100644
--- a/libclc/r600/lib/image/write_image_impl.ll
+++ b/libclc/r600/lib/image/write_image_impl.ll
@@ -1,4 +1,4 @@
-target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
 
 %opencl.image2d_t = type opaque
 %opencl.image3d_t = type opaque

