[clang] [llvm] [AArch64][SelectionDAG] Add CodeGen support for scalar FEAT_CPA (PR #105669)

[Rodolfo Wottrich via cfe-commits]

================
@@ -401,7 +401,7 @@ def tblockaddress: SDNode<"ISD::TargetBlockAddress",  SDTPtrLeaf, [],
 
 def add        : SDNode<"ISD::ADD"       , SDTIntBinOp   ,
                         [SDNPCommutative, SDNPAssociative]>;
-def ptradd     : SDNode<"ISD::ADD"       , SDTPtrAddOp, []>;
+def ptradd     : SDNode<"ISD::PTRADD"    , SDTPtrAddOp, []>;
----------------
rgwott wrote:

This should not be a problem because PTRADD falls back to ADD in any target that does not opt in to shouldPreservedPtrArith().

https://github.com/llvm/llvm-project/pull/105669