[clang] [llvm] [HLSL] [DXIL] Implement the `AddUint64` HLSL function and the `UAddc` DXIL op (PR #125319)
Farzon Lotfi via cfe-commits
cfe-commits at lists.llvm.org
Wed Feb 5 13:51:40 PST 2025
================
@@ -12553,6 +12553,8 @@ def err_std_initializer_list_malformed : Error<
"%0 layout not recognized. Must be a non-polymorphic class type with no bases and two fields: a 'const E *' and either another 'const E *' or a 'std::size_t'">;
// HLSL Diagnostics
+def err_hlsl_adduint64_invalid_arguments: Error<
----------------
farzonl wrote:
Few things I think there is already an error for the scalar when expecting a vector case so we should just use that one.
Second this title is too specific to the adduint64 case. we should allow this to be more configurable.
I also don't think this should be hlsl specific. You weren't off base to use `err_vector_incorrect_num_elements`. It is correct that the number of elements is wrong but it would be better is if we could specify something like `Invalid element count of 3 when expecting even element counts in the range of 2 to 4`. That way we could make 2 and 4 configurable via min max args. Also be nice to make the type configurable too.
https://github.com/llvm/llvm-project/pull/125319
More information about the cfe-commits
mailing list