[clang] [AArch64][Clang] Update untyped sme intrinsics with fp8 variants (PR #124543)

[via cfe-commits]

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@@ -856,18 +926,18 @@ void test_svwrite_za64_s64_vg1x2(uint32_t base, svint64x2_t val) __arm_streaming
   SVE_ACLE_FUNC(svwrite_za64,_s64,_vg1x2,)(base, val);
 }
 
-// CHECK-LABEL: @test_svwrite_za8_s8_vg1x4(
+// CHECK-LABEL: @test_svwrite_za8_mf8_vg1x4(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    tail call void @llvm.aarch64.sme.write.vg1x4.nxv16i8(i32 [[BASE:%.*]], <vscale x 16 x i8> [[VAL_COERCE0:%.*]], <vscale x 16 x i8> [[VAL_COERCE1:%.*]], <vscale x 16 x i8> [[VAL_COERCE2:%.*]], <vscale x 16 x i8> [[VAL_COERCE3:%.*]])
 // CHECK-NEXT:    ret void
 //
-// CPP-CHECK-LABEL: @_Z25test_svwrite_za8_s8_vg1x4j10svint8x4_t(
+// CPP-CHECK-LABEL: @_Z26test_svwrite_za8_mf8_vg1x4j13svmfloat8x4_t(
 // CPP-CHECK-NEXT:  entry:
 // CPP-CHECK-NEXT:    tail call void @llvm.aarch64.sme.write.vg1x4.nxv16i8(i32 [[BASE:%.*]], <vscale x 16 x i8> [[VAL_COERCE0:%.*]], <vscale x 16 x i8> [[VAL_COERCE1:%.*]], <vscale x 16 x i8> [[VAL_COERCE2:%.*]], <vscale x 16 x i8> [[VAL_COERCE3:%.*]])
 // CPP-CHECK-NEXT:    ret void
 //
-void test_svwrite_za8_s8_vg1x4(uint32_t base, svint8x4_t val) __arm_streaming __arm_inout("za") {
-  SVE_ACLE_FUNC(svwrite_za8,_s8,_vg1x4,)(base, val);
+void test_svwrite_za8_mf8_vg1x4(uint32_t base, svmfloat8x4_t val) __arm_streaming __arm_inout("za") {
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CarolineConcatto wrote:

It looks you replaced  test_svwrite_za8_s8_vg1x4 by test_svwrite_za8_mf8_vg1x4, but we should still have both.

https://github.com/llvm/llvm-project/pull/124543