[clang] [Clang][Arch] Disable mve.fp when explicit -mfpu option (PR #123028)

via cfe-commits cfe-commits at lists.llvm.org
Wed Jan 15 01:20:25 PST 2025


llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang-driver

@llvm/pr-subscribers-clang

Author: None (flopop01)

<details>
<summary>Changes</summary>

-mfpu=fpv5-d16 or -mfpu=fpv5-sp-d16 disables the scalar half-precision floating-point operations feature. Therefore, because the M-profile Vector Extension (MVE) floating-point feature requires the scalar half-precision floating-point operations, this option also disables the MVE floating-point feature, -mve.fp

---
Full diff: https://github.com/llvm/llvm-project/pull/123028.diff


1 Files Affected:

- (modified) clang/lib/Driver/ToolChains/Arch/ARM.cpp (+9) 


``````````diff
diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
index b8181ce6dc012a..cec2c4f24d676d 100644
--- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -748,6 +748,15 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver &D,
       Features.push_back("-crc");
   }
 
+  // Invalid value of the __ARM_FEATURE_MVE macro when an explicit -mfpu= option
+  // disables MVE-FP -mfpu=fpv5-d16 or -mfpu=fpv5-sp-d16 disables the scalar
+  // half-precision floating-point operations feature. Therefore, because the
+  // M-profile Vector Extension (MVE) floating-point feature requires the scalar
+  // half-precision floating-point operations, this option also disables the MVE
+  // floating-point feature: -mve.fp
+  if (FPUKind == llvm::ARM::FK_FPV5_D16 || FPUKind == llvm::ARM::FK_FPV5_SP_D16)
+    Features.push_back("-mve.fp");
+
   // For Arch >= ARMv8.0 && A or R profile:  crypto = sha2 + aes
   // Rather than replace within the feature vector, determine whether each
   // algorithm is enabled and append this to the end of the vector.

``````````

</details>


https://github.com/llvm/llvm-project/pull/123028


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