[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Djordje Todorovic via cfe-commits]

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@@ -2710,6 +2713,45 @@ MachineInstr *RISCVInstrInfo::emitLdStWithAddr(MachineInstr &MemI,
       .setMemRefs(MemI.memoperands())
       .setMIFlags(MemI.getFlags());
 }
+bool RISCVInstrInfo::isPairableLdStInstOpc(unsigned Opc) {
+  switch (Opc) {
+  default:
+    return false;
+  case RISCV::SH:
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djtodoro wrote:

That is true. I have added a TODO marker for it in https://github.com/llvm/llvm-project/pull/121394.

https://github.com/llvm/llvm-project/pull/117865