[clang] [X86][AVX10.2] Add comments for the avx10_2convertintrin.h file (PR #120766)
Mikołaj Piróg via cfe-commits
cfe-commits at lists.llvm.org
Fri Dec 20 09:01:28 PST 2024
https://github.com/mikolaj-pirog updated https://github.com/llvm/llvm-project/pull/120766
>From 0c107c06255cc2c8c2ae1abd1825d547b70db33a Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Fri, 13 Dec 2024 15:40:14 +0100
Subject: [PATCH 1/7] mend
---
clang/lib/Headers/avx10_2convertintrin.h | 304 +++++++++++++++++++++++
1 file changed, 304 insertions(+)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 134adb2850c8de..62b71ce87dd382 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -24,24 +24,146 @@
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"), \
__min_vector_width__(256)))
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements to a 128-bit vector
+/// containing FP16 elements.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF i < 4
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 4])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __A
+/// A 128-bit vector of [4 x float].
+/// \param __B
+/// A 128-bit vector of [4 x float].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Lower 4 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtx2ps_ph(__m128 __A,
__m128 __B) {
return (__m128h)__builtin_ia32_vcvt2ps2phx128_mask(
(__v4sf)__A, (__v4sf)__B, (__v8hf)_mm_setzero_ph(), (__mmask8)(-1));
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements to a 128-bit vector
+/// containing FP16 elements. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF mask[i]
+/// dst.fp16[i] := __W[i]
+/// ELSE
+/// IF i < 4
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 4])
+/// FI
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __W
+/// A 128-bit vector of [8 x fp16].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [4 x float].
+/// \param __B
+/// A 128-bit vector of [4 x float].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Lower 4 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
static __inline__ __m128h __DEFAULT_FN_ATTRS128
_mm_mask_cvtx2ps_ph(__m128h __W, __mmask8 __U, __m128 __A, __m128 __B) {
return (__m128h)__builtin_ia32_vcvt2ps2phx128_mask(
(__v4sf)__A, (__v4sf)__B, (__v8hf)__W, (__mmask8)__U);
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements to a 128-bit vector
+/// containing FP16 elements. Zeroing mask \a __U is used to determine if given
+/// element should be zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF mask[i]
+/// dst.fp16[i] := 0
+/// ELSE
+/// IF i < 4
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 4])
+/// FI
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [4 x float].
+/// \param __B
+/// A 128-bit vector of [4 x float].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Lower 4 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is set, then
+/// zero is taken instead.
static __inline__ __m128h __DEFAULT_FN_ATTRS128
_mm_maskz_cvtx2ps_ph(__mmask8 __U, __m128 __A, __m128 __B) {
return (__m128h)__builtin_ia32_vcvt2ps2phx128_mask(
(__v4sf)__A, (__v4sf)__B, (__v8hf)_mm_setzero_ph(), (__mmask8)__U);
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements to a 256-bit vector
+/// containing FP16 elements.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF i < 8
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __A
+/// A 256-bit vector of [8 x float].
+/// \param __B
+/// A 256-bit vector of [8 x float].
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtx2ps_ph(__m256 __A,
__m256 __B) {
return (__m256h)__builtin_ia32_vcvt2ps2phx256_mask(
@@ -49,6 +171,42 @@ static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtx2ps_ph(__m256 __A,
_MM_FROUND_CUR_DIRECTION);
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements to a 256-bit vector
+/// containing FP16 elements. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF mask[i]
+/// dst.fp16[i] := __W[i]
+/// ELSE
+/// IF i < 8
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8])
+/// FI
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __W
+/// A 256-bit vector of [16 x fp16].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [8 x float].
+/// \param __B
+/// A 256-bit vector of [8 x float].
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Lower 4 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
_mm256_mask_cvtx2ps_ph(__m256h __W, __mmask16 __U, __m256 __A, __m256 __B) {
return (__m256h)__builtin_ia32_vcvt2ps2phx256_mask(
@@ -56,6 +214,40 @@ _mm256_mask_cvtx2ps_ph(__m256h __W, __mmask16 __U, __m256 __A, __m256 __B) {
_MM_FROUND_CUR_DIRECTION);
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements to a 256-bit vector
+/// containing FP16 elements. Zeroing mask \a __U is used to determine if given
+/// element should be zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF mask[i]
+/// dst.fp16[i] := 0
+/// ELSE
+/// IF i < 8
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8])
+/// FI
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [8 x float].
+/// \param __B
+/// A 256-bit vector of [8 x float].
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Lower 4 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is set, then
+/// zero is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
return (__m256h)__builtin_ia32_vcvt2ps2phx256_mask(
@@ -63,15 +255,127 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
_MM_FROUND_CUR_DIRECTION);
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements to a 256-bit vector
+/// containing FP16 elements. Rounding mode \a __R needs to be provided.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF i < 8
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __A
+/// A 256-bit vector of [8 x float].
+/// \param __B
+/// A 256-bit vector of [8 x float].
+/// \param __R
+/// Rounding mode. Valid inputs are: _MM_FROUND_CUR_DIRECTION or
+/// result bitwise or of _MM_FROUND_NO_EXC with at most one of the following:
+/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF,
+/// _MM_FROUND_TO_ZERO.
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
#define _mm256_cvtx_round2ps_ph(A, B, R) \
((__m256h)__builtin_ia32_vcvt2ps2phx256_mask( \
(__v8sf)(A), (__v8sf)(B), (__v16hf)_mm256_undefined_ph(), \
(__mmask16)(-1), (const int)(R)))
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements to a 256-bit vector
+/// containing FP16 elements. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead. Rounding mode \a __R needs to
+/// be provided.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF mask[i]
+/// dst.fp16[i] := __W[i]
+/// ELSE
+/// IF i < 8
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8])
+/// FI
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __W
+/// A 256-bit vector of [16 x fp16].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [8 x float].
+/// \param __B
+/// A 256-bit vector of [8 x float].
+/// \param __R
+/// Rounding mode. Valid inputs are: _MM_FROUND_CUR_DIRECTION or
+/// result bitwise or of _MM_FROUND_NO_EXC with at most one of the following:
+/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF,
+/// _MM_FROUND_TO_ZERO.
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Lower 4 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
#define _mm256_mask_cvtx_round2ps_ph(W, U, A, B, R) \
((__m256h)__builtin_ia32_vcvt2ps2phx256_mask( \
(__v8sf)(A), (__v8sf)(B), (__v16hf)(W), (__mmask16)(U), (const int)(R)))
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements to a 256-bit vector
+/// containing FP16 elements. Zeroing mask \a __U is used to determine if given
+/// element should be zeroed instead. Rounding mode \a __R needs to be provided.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF mask[i]
+/// dst.fp16[i] := 0
+/// ELSE
+/// IF i < 8
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8])
+/// FI
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [8 x float].
+/// \param __B
+/// A 256-bit vector of [8 x float].
+/// \param __R
+/// Rounding mode. Valid inputs are: _MM_FROUND_CUR_DIRECTION or
+/// result bitwise or of _MM_FROUND_NO_EXC with at most one of the following:
+/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF,
+/// _MM_FROUND_TO_ZERO.
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Lower 4 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is set, then
+/// zero is taken instead.
#define _mm256_maskz_cvtx_round2ps_ph(U, A, B, R) \
((__m256h)__builtin_ia32_vcvt2ps2phx256_mask( \
(__v8sf)(A), (__v8sf)(B), (__v16hf)(_mm256_setzero_ph()), \
>From 5a7f69432e56429aa325e6e99b6614582a866277 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Tue, 17 Dec 2024 15:52:08 +0100
Subject: [PATCH 2/7] further work
---
clang/lib/Headers/avx10_2convertintrin.h | 226 +++++++++++++++++++++--
1 file changed, 209 insertions(+), 17 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 62b71ce87dd382..28e028e906bb66 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -106,13 +106,13 @@ _mm_mask_cvtx2ps_ph(__m128h __W, __mmask8 __U, __m128 __A, __m128 __B) {
/// \code{.operation]
/// FOR i := 0 to 7
/// IF mask[i]
-/// dst.fp16[i] := 0
-/// ELSE
/// IF i < 4
/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
/// ELSE
/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 4])
/// FI
+/// ELSE
+/// dst.fp16[i] := 0
/// FI
/// ENDFOR
/// \endcode
@@ -130,8 +130,8 @@ _mm_mask_cvtx2ps_ph(__m128h __W, __mmask8 __U, __m128 __A, __m128 __B) {
/// \returns
/// A 128-bit vector of [8 x fp16]. Lower 4 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
-/// (converted) elements from \a __A. If corresponding mask bit is set, then
-/// zero is taken instead.
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then zero is taken instead.
static __inline__ __m128h __DEFAULT_FN_ATTRS128
_mm_maskz_cvtx2ps_ph(__mmask8 __U, __m128 __A, __m128 __B) {
return (__m128h)__builtin_ia32_vcvt2ps2phx128_mask(
@@ -222,13 +222,13 @@ _mm256_mask_cvtx2ps_ph(__m256h __W, __mmask16 __U, __m256 __A, __m256 __B) {
/// \code{.operation]
/// FOR i := 0 to 15
/// IF mask[i]
-/// dst.fp16[i] := 0
-/// ELSE
/// IF i < 8
/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
/// ELSE
/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8])
/// FI
+/// ELSE
+/// dst.fp16[i] := 0
/// FI
/// ENDFOR
/// \endcode
@@ -238,7 +238,7 @@ _mm256_mask_cvtx2ps_ph(__m256h __W, __mmask16 __U, __m256 __A, __m256 __B) {
/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
///
/// \param __U
-/// A 8-bit merging mask.
+/// A 8-bit zeroing mask.
/// \param __A
/// A 256-bit vector of [8 x float].
/// \param __B
@@ -246,8 +246,8 @@ _mm256_mask_cvtx2ps_ph(__m256h __W, __mmask16 __U, __m256 __A, __m256 __B) {
/// \returns
/// A 256-bit vector of [16 x fp16]. Lower 4 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
-/// (converted) elements from \a __A. If corresponding mask bit is set, then
-/// zero is taken instead.
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then zero is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
return (__m256h)__builtin_ia32_vcvt2ps2phx256_mask(
@@ -279,7 +279,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// A 256-bit vector of [8 x float].
/// \param __R
/// Rounding mode. Valid inputs are: _MM_FROUND_CUR_DIRECTION or
-/// result bitwise or of _MM_FROUND_NO_EXC with at most one of the following:
+/// result of bitwise or of _MM_FROUND_NO_EXC with at most one of the following:
/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF,
/// _MM_FROUND_TO_ZERO.
/// \returns
@@ -325,7 +325,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// A 256-bit vector of [8 x float].
/// \param __R
/// Rounding mode. Valid inputs are: _MM_FROUND_CUR_DIRECTION or
-/// result bitwise or of _MM_FROUND_NO_EXC with at most one of the following:
+/// result of bitwise or of _MM_FROUND_NO_EXC with at most one of the following:
/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF,
/// _MM_FROUND_TO_ZERO.
/// \returns
@@ -345,13 +345,13 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// \code{.operation]
/// FOR i := 0 to 15
/// IF mask[i]
-/// dst.fp16[i] := 0
-/// ELSE
/// IF i < 8
/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
/// ELSE
/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 8])
/// FI
+/// ELSE
+/// dst.fp16[i] := 0
/// FI
/// ENDFOR
/// \endcode
@@ -361,21 +361,21 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
///
/// \param __U
-/// A 8-bit merging mask.
+/// A 8-bit zeroing mask.
/// \param __A
/// A 256-bit vector of [8 x float].
/// \param __B
/// A 256-bit vector of [8 x float].
/// \param __R
/// Rounding mode. Valid inputs are: _MM_FROUND_CUR_DIRECTION or
-/// result bitwise or of _MM_FROUND_NO_EXC with at most one of the following:
+/// result of bitwise or of _MM_FROUND_NO_EXC with at most one of the following:
/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF,
/// _MM_FROUND_TO_ZERO.
/// \returns
/// A 256-bit vector of [16 x fp16]. Lower 4 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
-/// (converted) elements from \a __A. If corresponding mask bit is set, then
-/// zero is taken instead.
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then zero is taken instead.
#define _mm256_maskz_cvtx_round2ps_ph(U, A, B, R) \
((__m256h)__builtin_ia32_vcvt2ps2phx256_mask( \
(__v8sf)(A), (__v8sf)(B), (__v16hf)(_mm256_setzero_ph()), \
@@ -537,18 +537,114 @@ _mm256_maskz_cvtbiassph_phf8(__mmask16 __U, __m256i __A, __m256h __B) {
(__mmask16)__U);
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed
+/// FP16 floating-point elements to a 128-bit vector
+/// containing E5M2 FP8 elements.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtne2ph_pbf8(__m128h __A,
__m128h __B) {
return (__m128i)__builtin_ia32_vcvtne2ph2bf8_128((__v8hf)(__A),
(__v8hf)(__B));
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF __U[i]
+/// dst.fp8[i] := __W[i]
+/// ELSE
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtne2ph_pbf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_selectb_128(
(__mmask16)__U, (__v16qi)_mm_cvtne2ph_pbf8(__A, __B), (__v16qi)__W);
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF __U[i]
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __U
+/// A 16-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// zero is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtne2ph_pbf8(__mmask16 __U, __m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_selectb_128(
@@ -556,18 +652,114 @@ _mm_maskz_cvtne2ph_pbf8(__mmask16 __U, __m128h __A, __m128h __B) {
(__v16qi)(__m128i)_mm_setzero_si128());
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
+/// FP16 floating-point elements to a 256-bit vector
+/// containing E5M2 FP8 elements.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_cvtne2ph_pbf8(__m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_vcvtne2ph2bf8_256((__v16hf)(__A),
(__v16hf)(__B));
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF __U[i]
+/// dst.fp8[i] := __W.fp8[i]
+/// ELSE
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __W
+/// A 256-bit vector of [32 x fp8].
+/// \param __U
+/// A 32-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtne2ph_pbf8(
__m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_selectb_256(
(__mmask16)__U, (__v32qi)_mm256_cvtne2ph_pbf8(__A, __B), (__v32qi)__W);
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be zeroed
+/// instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF __U[i]
+/// dst.fp8[i] := 0
+/// ELSE
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __U
+/// A 32-bit zeroing mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then element from \a __W is taken instead.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtne2ph_pbf8(__mmask32 __U, __m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_selectb_256(
>From f895546ee95495ae6464582510f1e79b30e60948 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Thu, 19 Dec 2024 20:10:03 +0100
Subject: [PATCH 3/7] further work
---
clang/lib/Headers/avx10_2convertintrin.h | 1586 +++++++++++++++++++++-
1 file changed, 1562 insertions(+), 24 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 28e028e906bb66..15c7d9b66f520f 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -381,6 +381,32 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
(__v8sf)(A), (__v8sf)(B), (__v16hf)(_mm256_setzero_ph()), \
(__mmask16)(U), (const int)(R)))
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed
+/// single-precision (32-bit) floating-point elements and 16-bit integers
+/// respectively.
+
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF i < 4
+/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
+/// ELSE
+/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 4])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __A
+/// A 128-bit vector of [4 x float].
+/// \param __B
+/// A 128-bit vector of [4 x float].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Lower 4 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_cvtbiasph_pbf8(__m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask(
@@ -537,9 +563,8 @@ _mm256_maskz_cvtbiassph_phf8(__mmask16 __U, __m256i __A, __m256h __B) {
(__mmask16)__U);
}
-/// Convert two 128-bit vectors, \a __A and \a __B, containing packed
-/// FP16 floating-point elements to a 128-bit vector
-/// containing E5M2 FP8 elements.
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
///
/// \code{.operation]
/// FOR i := 0 to 16
@@ -575,7 +600,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtne2ph_pbf8(__m128h __A,
/// from \a __W instead.
///
/// \code{.operation]
-/// FOR i := 0 to 16
+/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp8[i] := __W[i]
/// ELSE
@@ -652,9 +677,8 @@ _mm_maskz_cvtne2ph_pbf8(__mmask16 __U, __m128h __A, __m128h __B) {
(__v16qi)(__m128i)_mm_setzero_si128());
}
-/// Convert two 256-bit vectors, \a __A and \a __B, containing packed
-/// FP16 floating-point elements to a 256-bit vector
-/// containing E5M2 FP8 elements.
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
///
/// \code{.operation]
/// FOR i := 0 to 32
@@ -759,7 +783,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtne2ph_pbf8(
/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
-/// then element from \a __W is taken instead.
+/// zero is taken instead.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtne2ph_pbf8(__mmask32 __U, __m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_selectb_256(
@@ -767,18 +791,114 @@ _mm256_maskz_cvtne2ph_pbf8(__mmask32 __U, __m256h __A, __m256h __B) {
(__v32qi)(__m256i)_mm256_setzero_si256());
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
+/// Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_cvtnes2ph_pbf8(__m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtne2ph2bf8s_128((__v8hf)(__A),
(__v8hf)(__B));
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead. Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF __U[i]
+/// dst.fp8[i] := __W[i]
+/// ELSE
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtnes2ph_pbf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_selectb_128(
(__mmask16)__U, (__v16qi)_mm_cvtnes2ph_pbf8(__A, __B), (__v16qi)__W);
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead. Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF __U[i]
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __U
+/// A 16-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// zero is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtnes2ph_pbf8(__mmask16 __U, __m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_selectb_128(
@@ -786,18 +906,114 @@ _mm_maskz_cvtnes2ph_pbf8(__mmask16 __U, __m128h __A, __m128h __B) {
(__v16qi)(__m128i)_mm_setzero_si128());
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
+/// Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_cvtnes2ph_pbf8(__m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_vcvtne2ph2bf8s_256((__v16hf)(__A),
(__v16hf)(__B));
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead. Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF __U[i]
+/// dst.fp8[i] := __W.fp8[i]
+/// ELSE
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __W
+/// A 256-bit vector of [32 x fp8].
+/// \param __U
+/// A 32-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtnes2ph_pbf8(
__m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_selectb_256(
(__mmask16)__U, (__v32qi)_mm256_cvtnes2ph_pbf8(__A, __B), (__v32qi)__W);
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be zeroed
+/// instead. Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF __U[i]
+/// dst.fp8[i] := 0
+/// ELSE
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __U
+/// A 32-bit zeroing mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// zero is taken instead.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtnes2ph_pbf8(__mmask32 __U, __m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_selectb_256(
@@ -805,37 +1021,227 @@ _mm256_maskz_cvtnes2ph_pbf8(__mmask32 __U, __m256h __A, __m256h __B) {
(__v32qi)(__m256i)_mm256_setzero_si256());
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2HF8 instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtne2ph_phf8(__m128h __A,
__m128h __B) {
return (__m128i)__builtin_ia32_vcvtne2ph2hf8_128((__v8hf)(__A),
(__v8hf)(__B));
}
-static __inline__ __m128i __DEFAULT_FN_ATTRS128
-_mm_mask_cvtne2ph_phf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
- return (__m128i)__builtin_ia32_selectb_128(
- (__mmask16)__U, (__v16qi)_mm_cvtne2ph_phf8(__A, __B), (__v16qi)__W);
-}
-
-static __inline__ __m128i __DEFAULT_FN_ATTRS128
-_mm_maskz_cvtne2ph_phf8(__mmask16 __U, __m128h __A, __m128h __B) {
- return (__m128i)__builtin_ia32_selectb_128(
- (__mmask16)__U, (__v16qi)_mm_cvtne2ph_phf8(__A, __B),
- (__v16qi)(__m128i)_mm_setzero_si128());
-}
-
-static __inline__ __m256i __DEFAULT_FN_ATTRS256
-_mm256_cvtne2ph_phf8(__m256h __A, __m256h __B) {
- return (__m256i)__builtin_ia32_vcvtne2ph2hf8_256((__v16hf)(__A),
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF __U[i]
+/// dst.fp8[i] := __W[i]
+/// ELSE
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2HF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_mask_cvtne2ph_phf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
+ return (__m128i)__builtin_ia32_selectb_128(
+ (__mmask16)__U, (__v16qi)_mm_cvtne2ph_phf8(__A, __B), (__v16qi)__W);
+}
+
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF __U[i]
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2HF8 instruction.
+///
+/// \param __U
+/// A 16-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// zero is taken instead.
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_maskz_cvtne2ph_phf8(__mmask16 __U, __m128h __A, __m128h __B) {
+ return (__m128i)__builtin_ia32_selectb_128(
+ (__mmask16)__U, (__v16qi)_mm_cvtne2ph_phf8(__A, __B),
+ (__v16qi)(__m128i)_mm_setzero_si128());
+}
+
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2HF8 instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_cvtne2ph_phf8(__m256h __A, __m256h __B) {
+ return (__m256i)__builtin_ia32_vcvtne2ph2hf8_256((__v16hf)(__A),
(__v16hf)(__B));
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF __U[i]
+/// dst.fp8[i] := __W.fp8[i]
+/// ELSE
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2HF8 instruction.
+///
+/// \param __W
+/// A 256-bit vector of [32 x fp8].
+/// \param __U
+/// A 32-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtne2ph_phf8(
__m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_selectb_256(
(__mmask16)__U, (__v32qi)_mm256_cvtne2ph_phf8(__A, __B), (__v32qi)__W);
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be zeroed
+/// instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF __U[i]
+/// dst.fp8[i] := 0
+/// ELSE
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __U
+/// A 32-bit zeroing mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// zero is taken instead.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtne2ph_phf8(__mmask32 __U, __m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_selectb_256(
@@ -843,18 +1249,114 @@ _mm256_maskz_cvtne2ph_phf8(__mmask32 __U, __m256h __A, __m256h __B) {
(__v32qi)(__m256i)_mm256_setzero_si256());
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
+/// Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_cvtnes2ph_phf8(__m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtne2ph2hf8s_128((__v8hf)(__A),
(__v8hf)(__B));
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead. Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF __U[i]
+/// dst.fp8[i] := __W[i]
+/// ELSE
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtnes2ph_phf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_selectb_128(
(__mmask16)__U, (__v16qi)_mm_cvtnes2ph_phf8(__A, __B), (__v16qi)__W);
}
+/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead. Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 16
+/// IF __U[i]
+/// IF i < 8
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 8])
+/// FI
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __U
+/// A 16-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// zero is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtnes2ph_phf8(__mmask16 __U, __m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_selectb_128(
@@ -862,18 +1364,114 @@ _mm_maskz_cvtnes2ph_phf8(__mmask16 __U, __m128h __A, __m128h __B) {
(__v16qi)(__m128i)_mm_setzero_si128());
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
+/// Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_cvtnes2ph_phf8(__m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_vcvtne2ph2hf8s_256((__v16hf)(__A),
(__v16hf)(__B));
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead. Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF __U[i]
+/// dst.fp8[i] := __W.fp8[i]
+/// ELSE
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __W
+/// A 256-bit vector of [32 x fp8].
+/// \param __U
+/// A 32-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtnes2ph_phf8(
__m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_selectb_256(
(__mmask16)__U, (__v32qi)_mm256_cvtnes2ph_phf8(__A, __B), (__v32qi)__W);
}
+/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
+/// Merging mask \a __U is used to determine if given element should be zeroed
+/// instead. Resulting elements are saturated in case of overflow.
+///
+/// \code{.operation]
+/// FOR i := 0 to 32
+/// IF __U[i]
+/// dst.fp8[i] := 0
+/// ELSE
+/// IF i < 16
+/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
+/// FI
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __U
+/// A 32-bit zeroing mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// (converted) elements from \a __B; higher order elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// zero is taken instead.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtnes2ph_phf8(__mmask32 __U, __m256h __A, __m256h __B) {
return (__m256i)__builtin_ia32_selectb_256(
@@ -881,206 +1479,1146 @@ _mm256_maskz_cvtnes2ph_phf8(__mmask32 __U, __m256h __A, __m256h __B) {
(__v32qi)(__m256i)_mm256_setzero_si256());
}
+/// Convert 128-bit vector \a __A, containing packed FP8 E4M3 floating-point
+/// elements to a 128-bit vector containing FP16 elements. The conversion is exact.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+///
+/// \param __A
+/// A 128-bit vector of [16 x fp8].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtnehf8_ph(__m128i __A) {
return (__m128h)__builtin_ia32_vcvthf8_2ph128_mask(
(__v16qi)__A, (__v8hf)(__m128h)_mm_undefined_ph(), (__mmask8)-1);
}
+/// Convert 128-bit vector \a __A, containing packed FP8 E4M3 floating-point
+/// elements to a 128-bit vector containing FP16 elements. The conversion is
+/// exact. Merging mask \a __U is used to determine if given element should be
+/// taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp16[i] := __W[i]
+/// ELSE
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+///
+/// \param __W
+/// A 128-bit vector of [8 x fp16].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [16 x fp8].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
static __inline__ __m128h __DEFAULT_FN_ATTRS128
_mm_mask_cvtnehf8_ph(__m128h __W, __mmask8 __U, __m128i __A) {
return (__m128h)__builtin_ia32_vcvthf8_2ph128_mask(
(__v16qi)__A, (__v8hf)(__m128h)__W, (__mmask8)__U);
}
+/// Convert 128-bit vector \a __A, containing packed FP8 E4M3 floating-point
+/// elements to a 128-bit vector containing FP16 elements. The conversion is
+/// exact. Zeroing mask \a __U is used to determine if given element should be
+/// zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// ELSE
+/// dst.fp16[i] := 0
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+///
+/// \param __U
+/// A 8-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [16 x fp8].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// zero is taken instead.
static __inline__ __m128h __DEFAULT_FN_ATTRS128
_mm_maskz_cvtnehf8_ph(__mmask8 __U, __m128i __A) {
return (__m128h)__builtin_ia32_vcvthf8_2ph128_mask(
(__v16qi)__A, (__v8hf)(__m128h)_mm_setzero_ph(), (__mmask8)__U);
}
+/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point
+/// elements to a 256-bit vector containing FP16 elements. The conversion is exact.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+///
+/// \param __A
+/// A 256-bit vector of [32 x fp8].
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
_mm256_cvtnehf8_ph(__m128i __A) {
return (__m256h)__builtin_ia32_vcvthf8_2ph256_mask(
(__v16qi)__A, (__v16hf)(__m256h)_mm256_undefined_ph(), (__mmask16)-1);
}
+/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point
+/// elements to a 256-bit vector containing FP16 elements. The conversion is
+/// exact. Merging mask \a __U is used to determine if given element should be
+/// taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp16[i] := __W[i]
+/// ELSE
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+///
+/// \param __W
+/// A 256-bit vector of [16 x fp16].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [32 x fp8].
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
_mm256_mask_cvtnehf8_ph(__m256h __W, __mmask16 __U, __m128i __A) {
return (__m256h)__builtin_ia32_vcvthf8_2ph256_mask(
(__v16qi)__A, (__v16hf)(__m256h)__W, (__mmask16)__U);
}
+/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point
+/// elements to a 256-bit vector containing FP16 elements. The conversion is
+/// exact. Zeroing mask \a __U is used to determine if given element should be
+/// zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// ELSE
+/// dst.fp16[i] := 0
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+///
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [32 x fp8].
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// zero is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtnehf8_ph(__mmask16 __U, __m128i __A) {
return (__m256h)__builtin_ia32_vcvthf8_2ph256_mask(
(__v16qi)__A, (__v16hf)(__m256h)_mm256_setzero_ph(), (__mmask16)__U);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the (converted)
+/// elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtneph_pbf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtneph2bf8_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Merging mask \a __U is used to determine if
+/// given element should be taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := __W[i]
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+///
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed. If
+/// corresponding mask bit is set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtneph_pbf8(__m128i __W, __mmask8 __U, __m128h __A) {
return (__m128i)__builtin_ia32_vcvtneph2bf8_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Zeroing mask \a __U is used to determine if
+/// given element should be zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+///
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed. If
+/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtneph_pbf8(__mmask8 __U, __m128h __A) {
return (__m128i)__builtin_ia32_vcvtneph2bf8_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ENDFOR
+///
+/// dst[255:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the (converted)
+/// elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtneph_pbf8(__m256h __A) {
return (__m128i)__builtin_ia32_vcvtneph2bf8_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Merging mask \a __U is
+/// used to determine if given element should be taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := __W[i]
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// FI
+/// ENDFOR
+///
+/// dst[255:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If
+/// corresponding mask bit is set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtneph_pbf8(__m128i __W, __mmask16 __U, __m256h __A) {
return (__m128i)__builtin_ia32_vcvtneph2bf8_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Zeroing mask \a __U is
+/// used to determine if given element should be zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then element is zeroed instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtneph_pbf8(__mmask16 __U, __m256h __A) {
return (__m128i)__builtin_ia32_vcvtneph2bf8_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Results are saturated.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the (converted)
+/// elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtnesph_pbf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtneph2bf8s_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Results are saturated. Merging mask \a __U is
+/// used to determine if given element should be taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := __W[i]
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed. If
+/// corresponding mask bit is set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtnesph_pbf8(__m128i __W, __mmask8 __U, __m128h __A) {
return (__m128i)__builtin_ia32_vcvtneph2bf8s_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Results are saturated. Zeroing mask \a __U is
+/// used to determine if given element should be zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed. If
+/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtnesph_pbf8(__mmask8 __U, __m128h __A) {
return (__m128i)__builtin_ia32_vcvtneph2bf8s_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ENDFOR
+///
+/// dst[255:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the (converted)
+/// elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtnesph_pbf8(__m256h __A) {
return (__m128i)__builtin_ia32_vcvtneph2bf8s_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := __W[i]
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// FI
+/// ENDFOR
+///
+/// dst[255:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If
+/// corresponding mask bit is set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtnesph_pbf8(__m128i __W, __mmask16 __U, __m256h __A) {
return (__m128i)__builtin_ia32_vcvtneph2bf8s_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then element is zeroed instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtnesph_pbf8(__mmask16 __U, __m256h __A) {
return (__m128i)__builtin_ia32_vcvtneph2bf8s_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
+/// resulting vector are zeroed.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the (converted)
+/// elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtneph_phf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtneph2hf8_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Merging mask \a __U is used to determine if
+/// given element should be taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := __W[i]
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+///
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed. If
+/// corresponding mask bit is set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtneph_phf8(__m128i __W, __mmask8 __U, __m128h __A) {
return (__m128i)__builtin_ia32_vcvtneph2hf8_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Zeroing mask \a __U is used to determine if
+/// given element should be zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+///
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed. If
+/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtneph_phf8(__mmask8 __U, __m128h __A) {
return (__m128i)__builtin_ia32_vcvtneph2hf8_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ENDFOR
+///
+/// dst[255:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the (converted)
+/// elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtneph_phf8(__m256h __A) {
return (__m128i)__builtin_ia32_vcvtneph2hf8_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Merging mask \a __U is
+/// used to determine if given element should be taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := __W[i]
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// FI
+/// ENDFOR
+///
+/// dst[255:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If
+/// corresponding mask bit is set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtneph_phf8(__m128i __W, __mmask16 __U, __m256h __A) {
return (__m128i)__builtin_ia32_vcvtneph2hf8_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Zeroing mask \a __U is
+/// used to determine if given element should be zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then element is zeroed instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtneph_phf8(__mmask16 __U, __m256h __A) {
return (__m128i)__builtin_ia32_vcvtneph2hf8_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Results are saturated.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the (converted)
+/// elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtnesph_phf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtneph2hf8s_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Results are saturated. Merging mask \a __U is
+/// used to determine if given element should be taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := __W[i]
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed. If
+/// corresponding mask bit is set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtnesph_phf8(__m128i __W, __mmask8 __U, __m128h __A) {
return (__m128i)__builtin_ia32_vcvtneph2hf8s_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
+/// Convert 128-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
+/// resulting vector are zeroed. Results are saturated. Zeroing mask \a __U is
+/// used to determine if given element should be zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed. If
+/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtnesph_phf8(__mmask8 __U, __m128h __A) {
return (__m128i)__builtin_ia32_vcvtneph2hf8s_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ENDFOR
+///
+/// dst[255:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the (converted)
+/// elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtnesph_phf8(__m256h __A) {
return (__m128i)__builtin_ia32_vcvtneph2hf8s_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := __W[i]
+/// ELSE
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// FI
+/// ENDFOR
+///
+/// dst[255:128] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [8 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If
+/// corresponding mask bit is set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_mask_cvtnesph_phf8(__m128i __W, __mmask16 __U, __m256h __A) {
return (__m128i)__builtin_ia32_vcvtneph2hf8s_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
+/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
+/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+///
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then element is zeroed instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtnesph_phf8(__mmask16 __U, __m256h __A) {
return (__m128i)__builtin_ia32_vcvtneph2hf8s_256_mask(
(__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
}
+/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point
+/// elements to a 128-bit vector containing FP16 elements. The conversion is exact.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+///
+/// \param __A
+/// A 128-bit vector of [16 x fp8].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtpbf8_ph(__m128i __A) {
return _mm_castsi128_ph(_mm_slli_epi16(_mm_cvtepi8_epi16(__A), 8));
}
+/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point
+/// elements to a 128-bit vector containing FP16 elements. The conversion is
+/// exact. Merging mask \a __U is used to determine if given element should be
+/// taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp16[i] := __W[i]
+/// ELSE
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+///
+/// \param __W
+/// A 128-bit vector of [8 x fp16].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [16 x fp8].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
static __inline__ __m128h __DEFAULT_FN_ATTRS128
_mm_mask_cvtpbf8_ph(__m128h __S, __mmask8 __U, __m128i __A) {
return _mm_castsi128_ph(
_mm_mask_slli_epi16((__m128i)__S, __U, _mm_cvtepi8_epi16(__A), 8));
}
+/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point
+/// elements to a 128-bit vector containing FP16 elements. The conversion is
+/// exact. Zeroing mask \a __U is used to determine if given element should be
+/// zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// ELSE
+/// dst.fp16[i] := 0
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+///
+/// \param __U
+/// A 8-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [16 x fp8].
+/// \returns
+/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// zero is taken instead.
static __inline__ __m128h __DEFAULT_FN_ATTRS128
_mm_maskz_cvtpbf8_ph(__mmask8 __U, __m128i __A) {
return _mm_castsi128_ph(_mm_slli_epi16(_mm_maskz_cvtepi8_epi16(__U, __A), 8));
}
+/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point
+/// elements to a 256-bit vector containing FP16 elements. The conversion is exact.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+///
+/// \param __A
+/// A 256-bit vector of [32 x fp8].
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtpbf8_ph(__m128i __A) {
return _mm256_castsi256_ph(_mm256_slli_epi16(_mm256_cvtepi8_epi16(__A), 8));
}
+/// Convert 256-bit vector \a __A, containing packed FP8 E5M2 floating-point
+/// elements to a 256-bit vector containing FP16 elements. The conversion is
+/// exact. Merging mask \a __U is used to determine if given element should be
+/// taken from \a __W instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp16[i] := __W[i]
+/// ELSE
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+///
+/// \param __W
+/// A 256-bit vector of [16 x fp16].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [32 x fp8].
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
_mm256_mask_cvtpbf8_ph(__m256h __S, __mmask8 __U, __m128i __A) {
return _mm256_castsi256_ph(
_mm256_mask_slli_epi16((__m256i)__S, __U, _mm256_cvtepi8_epi16(__A), 8));
}
+/// Convert 256-bit vector \a __A, containing packed FP8 E5M2 floating-point
+/// elements to a 256-bit vector containing FP16 elements. The conversion is
+/// exact. Zeroing mask \a __U is used to determine if given element should be
+/// zeroed instead.
+///
+/// \code{.operation]
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// ELSE
+/// dst.fp16[i] := 0
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+///
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [32 x fp8].
+/// \returns
+/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
+/// (converted) elements from \a __A. If corresponding mask bit is not set, then
+/// zero is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtpbf8_ph(__mmask8 __U, __m128i __A) {
return _mm256_castsi256_ph(
>From 99ff5fe6607836cc0b39d4794fd7d932398e7bd6 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Fri, 20 Dec 2024 14:44:14 +0100
Subject: [PATCH 4/7] further work
---
clang/lib/Headers/avx10_2convertintrin.h | 837 ++++++++++++++++++++---
1 file changed, 751 insertions(+), 86 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 15c7d9b66f520f..341dc9cfd6aae3 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -28,7 +28,7 @@
/// single-precision (32-bit) floating-point elements to a 128-bit vector
/// containing FP16 elements.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF i < 4
/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
@@ -61,7 +61,7 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtx2ps_ph(__m128 __A,
/// containing FP16 elements. Merging mask \a __U is used to determine if given
/// element should be taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF mask[i]
/// dst.fp16[i] := __W[i]
@@ -103,7 +103,7 @@ _mm_mask_cvtx2ps_ph(__m128h __W, __mmask8 __U, __m128 __A, __m128 __B) {
/// containing FP16 elements. Zeroing mask \a __U is used to determine if given
/// element should be zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF mask[i]
/// IF i < 4
@@ -142,7 +142,7 @@ _mm_maskz_cvtx2ps_ph(__mmask8 __U, __m128 __A, __m128 __B) {
/// single-precision (32-bit) floating-point elements to a 256-bit vector
/// containing FP16 elements.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF i < 8
/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
@@ -176,7 +176,7 @@ static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtx2ps_ph(__m256 __A,
/// containing FP16 elements. Merging mask \a __U is used to determine if given
/// element should be taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF mask[i]
/// dst.fp16[i] := __W[i]
@@ -219,7 +219,7 @@ _mm256_mask_cvtx2ps_ph(__m256h __W, __mmask16 __U, __m256 __A, __m256 __B) {
/// containing FP16 elements. Zeroing mask \a __U is used to determine if given
/// element should be zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF mask[i]
/// IF i < 8
@@ -259,7 +259,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// single-precision (32-bit) floating-point elements to a 256-bit vector
/// containing FP16 elements. Rounding mode \a __R needs to be provided.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF i < 8
/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
@@ -297,7 +297,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// element should be taken from \a __W instead. Rounding mode \a __R needs to
/// be provided.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF mask[i]
/// dst.fp16[i] := __W[i]
@@ -342,7 +342,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// containing FP16 elements. Zeroing mask \a __U is used to determine if given
/// element should be zeroed instead. Rounding mode \a __R needs to be provided.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF mask[i]
/// IF i < 8
@@ -381,18 +381,16 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
(__v8sf)(A), (__v8sf)(B), (__v16hf)(_mm256_setzero_ph()), \
(__mmask16)(U), (const int)(R)))
-/// Add two 128-bit vectors, \a __A and \a __B, containing packed
-/// single-precision (32-bit) floating-point elements and 16-bit integers
-/// respectively.
-
-/// \code{.operation]
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+///
+/// \code{.operation}
/// FOR i := 0 to 7
-/// IF i < 4
-/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
-/// ELSE
-/// dst.fp16[i] := convert_fp32_to_fp16(__A.fp32[i - 4])
-/// FI
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
/// ENDFOR
+///
+/// dst[127:64] := 0
/// \endcode
///
/// \headerfile <immintrin.h>
@@ -400,25 +398,90 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
///
/// \param __A
-/// A 128-bit vector of [4 x float].
+/// A 128-bit vector of [8 x fp16].
/// \param __B
-/// A 128-bit vector of [4 x float].
+/// A 128-bit vector of [8 x int16].
/// \returns
-/// A 128-bit vector of [8 x fp16]. Lower 4 elements correspond to the
-/// (converted) elements from \a __B; higher order elements correspond to the
-/// (converted) elements from \a __A.
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// sum of elements from \a __A and \a __B; higher order elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_cvtbiasph_pbf8(__m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := _W[i]
+/// ELSE
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the sum of
+/// elements from \a __A and \a __B; higher order elements are zeroed. If
+/// corresponding mask bit is set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtbiasph_pbf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __U
+/// A 8-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the sum of
+/// elements from \a __A and \a __B; higher order elements are zeroed. If
+/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtbiasph_pbf8(__mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask(
@@ -426,6 +489,27 @@ _mm_maskz_cvtbiasph_pbf8(__mmask8 __U, __m128i __A, __m128h __B) {
(__mmask8)__U);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Elements correspond to the
+/// sum of elements from \a __A and \a __B.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtbiasph_pbf8(__m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256_mask(
@@ -433,12 +517,74 @@ _mm256_cvtbiasph_pbf8(__m256i __A, __m256h __B) {
(__mmask16)-1);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := _W[i]
+/// ELSE
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Elements correspond to the sum of
+/// elements from \a __A and \a __B. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_pbf8(
__m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256_mask(
(__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __U
+/// A 16-bit zeroing mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Elements correspond to the sum of
+/// elements from \a __A and \a __B. If corresponding mask bit is not set,
+/// then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtbiasph_pbf8(__mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8_256_mask(
@@ -446,18 +592,108 @@ _mm256_maskz_cvtbiasph_pbf8(__mmask16 __U, __m256i __A, __m256h __B) {
(__mmask16)__U);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Results are saturated.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// sum of elements from \a __A and \a __B; higher order elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_cvtbiassph_pbf8(__m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Results are saturated. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := _W[i]
+/// ELSE
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the sum of
+/// elements from \a __A and \a __B; higher order elements are zeroed. If
+/// corresponding mask bit is set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtbiassph_pbf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Results are saturated. Zeroing mask \a __U is used to determine if given
+/// element should be zeroed instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __U
+/// A 8-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the sum of
+/// elements from \a __A and \a __B; higher order elements are zeroed. If
+/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtbiassph_pbf8(__mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask(
@@ -465,6 +701,28 @@ _mm_maskz_cvtbiassph_pbf8(__mmask8 __U, __m128i __A, __m128h __B) {
(__mmask8)__U);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Results are saturated.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Elements correspond to the
+/// sum of elements from \a __A and \a __B.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtbiassph_pbf8(__m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_256_mask(
@@ -472,12 +730,74 @@ _mm256_cvtbiassph_pbf8(__m256i __A, __m256h __B) {
(__mmask16)-1);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Results are saturated. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := _W[i]
+/// ELSE
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Elements correspond to the sum of
+/// elements from \a __A and \a __B. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_pbf8(
__m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_256_mask(
(__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E5M2.
+/// Results are saturated. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __U
+/// A 16-bit zeroing mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Elements correspond to the sum of
+/// elements from \a __A and \a __B. If corresponding mask bit is not set,
+/// then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtbiassph_pbf8(__mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_256_mask(
@@ -485,18 +805,107 @@ _mm256_maskz_cvtbiassph_pbf8(__mmask16 __U, __m256i __A, __m256h __B) {
(__mmask16)__U);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// sum of elements from \a __A and \a __B; higher order elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_cvtbiasph_phf8(__m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := _W[i]
+/// ELSE
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the sum of
+/// elements from \a __A and \a __B; higher order elements are zeroed. If
+/// corresponding mask bit is set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtbiasph_phf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Zeroing mask \a __U is used to determine if given element should be zeroed
+/// instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __U
+/// A 8-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the sum of
+/// elements from \a __A and \a __B; higher order elements are zeroed. If
+/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtbiasph_phf8(__mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8_128_mask(
@@ -504,6 +913,27 @@ _mm_maskz_cvtbiasph_phf8(__mmask8 __U, __m128i __A, __m128h __B) {
(__mmask8)__U);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Elements correspond to the
+/// sum of elements from \a __A and \a __B.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtbiasph_phf8(__m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8_256_mask(
@@ -511,12 +941,74 @@ _mm256_cvtbiasph_phf8(__m256i __A, __m256h __B) {
(__mmask16)-1);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := _W[i]
+/// ELSE
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Elements correspond to the sum of
+/// elements from \a __A and \a __B. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_phf8(
__m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8_256_mask(
(__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3
+/// Merging mask \a __U is used to determine if given element should be taken
+/// from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __U
+/// A 16-bit zeroing mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Elements correspond to the sum of
+/// elements from \a __A and \a __B. If corresponding mask bit is not set,
+/// then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtbiasph_phf8(__mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8_256_mask(
@@ -524,18 +1016,108 @@ _mm256_maskz_cvtbiasph_phf8(__mmask16 __U, __m256i __A, __m256h __B) {
(__mmask16)__U);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Results are saturated.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// sum of elements from \a __A and \a __B; higher order elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_cvtbiassph_phf8(__m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Results are saturated. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := _W[i]
+/// ELSE
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 8-bit merging mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the sum of
+/// elements from \a __A and \a __B; higher order elements are zeroed. If
+/// corresponding mask bit is set, then element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_cvtbiassph_phf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_128_mask(
(__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
}
+/// Add two 128-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Results are saturated. Zeroing mask \a __U is used to determine if given
+/// element should be zeroed instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 7
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+///
+/// dst[127:64] := 0
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __U
+/// A 8-bit zeroing mask.
+/// \param __A
+/// A 128-bit vector of [8 x fp16].
+/// \param __B
+/// A 128-bit vector of [8 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the sum of
+/// elements from \a __A and \a __B; higher order elements are zeroed. If
+/// corresponding mask bit is not set, then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtbiassph_phf8(__mmask8 __U, __m128i __A, __m128h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_128_mask(
@@ -543,6 +1125,28 @@ _mm_maskz_cvtbiassph_phf8(__mmask8 __U, __m128i __A, __m128h __B) {
(__mmask8)__U);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Results are saturated.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Elements correspond to the
+/// sum of elements from \a __A and \a __B.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtbiassph_phf8(__m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_256_mask(
@@ -550,12 +1154,74 @@ _mm256_cvtbiassph_phf8(__m256i __A, __m256h __B) {
(__mmask16)-1);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Results are saturated. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := _W[i]
+/// ELSE
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __W
+/// A 128-bit vector of [16 x fp8].
+/// \param __U
+/// A 16-bit merging mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Elements correspond to the sum of
+/// elements from \a __A and \a __B. If corresponding mask bit is set, then
+/// element from \a __W is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_phf8(
__m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_256_mask(
(__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
}
+/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
+/// floating-point elements and 8-bit integers stored in the lower half of
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3.
+/// Results are saturated. Merging mask \a __U is used to determine if given
+/// element should be taken from \a __W instead.
+///
+/// \code{.operation}
+/// FOR i := 0 to 15
+/// IF __U[i]
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
+/// ELSE
+/// dst.fp8[i] := 0
+/// FI
+/// ENDFOR
+/// \endcode
+///
+/// \headerfile <immintrin.h>
+///
+/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+///
+/// \param __U
+/// A 16-bit zeroing mask.
+/// \param __A
+/// A 256-bit vector of [16 x fp16].
+/// \param __B
+/// A 256-bit vector of [16 x int16].
+/// \returns
+/// A 128-bit vector of [16 x fp8]. Elements correspond to the sum of
+/// elements from \a __A and \a __B. If corresponding mask bit is not set,
+/// then element is zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtbiassph_phf8(__mmask16 __U, __m256i __A, __m256h __B) {
return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_256_mask(
@@ -566,7 +1232,7 @@ _mm256_maskz_cvtbiassph_phf8(__mmask16 __U, __m256i __A, __m256h __B) {
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 16
/// IF i < 8
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
@@ -599,7 +1265,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtne2ph_pbf8(__m128h __A,
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp8[i] := __W[i]
@@ -641,7 +1307,7 @@ _mm_mask_cvtne2ph_pbf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// Zeroing mask \a __U is used to determine if given element should be zeroed
/// instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 16
/// IF __U[i]
/// IF i < 8
@@ -680,7 +1346,7 @@ _mm_maskz_cvtne2ph_pbf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
@@ -713,7 +1379,7 @@ _mm256_cvtne2ph_pbf8(__m256h __A, __m256h __B) {
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF __U[i]
/// dst.fp8[i] := __W.fp8[i]
@@ -755,7 +1421,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtne2ph_pbf8(
/// Merging mask \a __U is used to determine if given element should be zeroed
/// instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF __U[i]
/// dst.fp8[i] := 0
@@ -795,7 +1461,7 @@ _mm256_maskz_cvtne2ph_pbf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
/// Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 16
/// IF i < 8
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
@@ -828,7 +1494,7 @@ _mm_cvtnes2ph_pbf8(__m128h __A, __m128h __B) {
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead. Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 16
/// IF __U[i]
/// dst.fp8[i] := __W[i]
@@ -870,7 +1536,7 @@ _mm_mask_cvtnes2ph_pbf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// Zeroing mask \a __U is used to determine if given element should be zeroed
/// instead. Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 16
/// IF __U[i]
/// IF i < 8
@@ -910,7 +1576,7 @@ _mm_maskz_cvtnes2ph_pbf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
/// Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
@@ -943,7 +1609,7 @@ _mm256_cvtnes2ph_pbf8(__m256h __A, __m256h __B) {
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead. Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF __U[i]
/// dst.fp8[i] := __W.fp8[i]
@@ -985,7 +1651,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtnes2ph_pbf8(
/// Merging mask \a __U is used to determine if given element should be zeroed
/// instead. Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF __U[i]
/// dst.fp8[i] := 0
@@ -1024,7 +1690,7 @@ _mm256_maskz_cvtnes2ph_pbf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 16
/// IF i < 8
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
@@ -1057,7 +1723,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtne2ph_phf8(__m128h __A,
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 16
/// IF __U[i]
/// dst.fp8[i] := __W[i]
@@ -1099,7 +1765,7 @@ _mm_mask_cvtne2ph_phf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// Zeroing mask \a __U is used to determine if given element should be zeroed
/// instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 16
/// IF __U[i]
/// IF i < 8
@@ -1138,7 +1804,7 @@ _mm_maskz_cvtne2ph_phf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
@@ -1171,7 +1837,7 @@ _mm256_cvtne2ph_phf8(__m256h __A, __m256h __B) {
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF __U[i]
/// dst.fp8[i] := __W.fp8[i]
@@ -1213,7 +1879,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtne2ph_phf8(
/// Merging mask \a __U is used to determine if given element should be zeroed
/// instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF __U[i]
/// dst.fp8[i] := 0
@@ -1253,7 +1919,7 @@ _mm256_maskz_cvtne2ph_phf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
/// Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 16
/// IF i < 8
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
@@ -1286,7 +1952,7 @@ _mm_cvtnes2ph_phf8(__m128h __A, __m128h __B) {
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead. Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 16
/// IF __U[i]
/// dst.fp8[i] := __W[i]
@@ -1328,7 +1994,7 @@ _mm_mask_cvtnes2ph_phf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// Zeroing mask \a __U is used to determine if given element should be zeroed
/// instead. Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 16
/// IF __U[i]
/// IF i < 8
@@ -1368,7 +2034,7 @@ _mm_maskz_cvtnes2ph_phf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
/// Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
@@ -1401,7 +2067,7 @@ _mm256_cvtnes2ph_phf8(__m256h __A, __m256h __B) {
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead. Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF __U[i]
/// dst.fp8[i] := __W.fp8[i]
@@ -1443,7 +2109,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtnes2ph_phf8(
/// Merging mask \a __U is used to determine if given element should be zeroed
/// instead. Resulting elements are saturated in case of overflow.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 32
/// IF __U[i]
/// dst.fp8[i] := 0
@@ -1482,7 +2148,7 @@ _mm256_maskz_cvtnes2ph_phf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// Convert 128-bit vector \a __A, containing packed FP8 E4M3 floating-point
/// elements to a 128-bit vector containing FP16 elements. The conversion is exact.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
/// ENDFOR
@@ -1507,7 +2173,7 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtnehf8_ph(__m128i __A) {
/// exact. Merging mask \a __U is used to determine if given element should be
/// taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.fp16[i] := __W[i]
@@ -1542,7 +2208,7 @@ _mm_mask_cvtnehf8_ph(__m128h __W, __mmask8 __U, __m128i __A) {
/// exact. Zeroing mask \a __U is used to determine if given element should be
/// zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
@@ -1573,7 +2239,7 @@ _mm_maskz_cvtnehf8_ph(__mmask8 __U, __m128i __A) {
/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point
/// elements to a 256-bit vector containing FP16 elements. The conversion is exact.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
/// ENDFOR
@@ -1599,7 +2265,7 @@ _mm256_cvtnehf8_ph(__m128i __A) {
/// exact. Merging mask \a __U is used to determine if given element should be
/// taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp16[i] := __W[i]
@@ -1634,7 +2300,7 @@ _mm256_mask_cvtnehf8_ph(__m256h __W, __mmask16 __U, __m128i __A) {
/// exact. Zeroing mask \a __U is used to determine if given element should be
/// zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
@@ -1666,7 +2332,7 @@ _mm256_maskz_cvtnehf8_ph(__mmask16 __U, __m128i __A) {
/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
/// resulting vector are zeroed.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
/// ENDFOR
@@ -1693,7 +2359,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtneph_pbf8(__m128h __A) {
/// resulting vector are zeroed. Merging mask \a __U is used to determine if
/// given element should be taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.fp8[i] := __W[i]
@@ -1731,7 +2397,7 @@ _mm_mask_cvtneph_pbf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// resulting vector are zeroed. Zeroing mask \a __U is used to determine if
/// given element should be zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
@@ -1752,7 +2418,6 @@ _mm_mask_cvtneph_pbf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-///
/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is not set, then element is zeroed.
@@ -1765,7 +2430,7 @@ _mm_maskz_cvtneph_pbf8(__mmask8 __U, __m128h __A) {
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
/// to a 128-bit vector containing E5M2 FP8 elements.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
/// ENDFOR
@@ -1792,7 +2457,7 @@ _mm256_cvtneph_pbf8(__m256h __A) {
/// to a 128-bit vector containing E5M2 FP8 elements. Merging mask \a __U is
/// used to determine if given element should be taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp8[i] := __W[i]
@@ -1828,7 +2493,7 @@ _mm256_mask_cvtneph_pbf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// to a 128-bit vector containing E5M2 FP8 elements. Zeroing mask \a __U is
/// used to determine if given element should be zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
@@ -1862,7 +2527,7 @@ _mm256_maskz_cvtneph_pbf8(__mmask16 __U, __m256h __A) {
/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
/// resulting vector are zeroed. Results are saturated.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
/// ENDFOR
@@ -1889,7 +2554,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtnesph_pbf8(__m128h __A) {
/// resulting vector are zeroed. Results are saturated. Merging mask \a __U is
/// used to determine if given element should be taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.fp8[i] := __W[i]
@@ -1926,7 +2591,7 @@ _mm_mask_cvtnesph_pbf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// resulting vector are zeroed. Results are saturated. Zeroing mask \a __U is
/// used to determine if given element should be zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
@@ -1943,7 +2608,7 @@ _mm_mask_cvtnesph_pbf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
///
/// \param __U
-/// A 8-bit merging mask.
+/// A 8-bit zeroing mask.
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
@@ -1959,7 +2624,7 @@ _mm_maskz_cvtnesph_pbf8(__mmask8 __U, __m128h __A) {
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
/// to a 128-bit vector containing E5M2 FP8 elements. Results are saturated.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
/// ENDFOR
@@ -1987,7 +2652,7 @@ _mm256_cvtnesph_pbf8(__m256h __A) {
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp8[i] := __W[i]
@@ -2024,7 +2689,7 @@ _mm256_mask_cvtnesph_pbf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// Zeroing mask \a __U is used to determine if given element should be zeroed
/// instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
@@ -2058,7 +2723,7 @@ _mm256_maskz_cvtnesph_pbf8(__mmask16 __U, __m256h __A) {
/// to a 128-bit vector containing E5M2 FP8 elements. Upper elements of
/// resulting vector are zeroed.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
/// ENDFOR
@@ -2085,7 +2750,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtneph_phf8(__m128h __A) {
/// resulting vector are zeroed. Merging mask \a __U is used to determine if
/// given element should be taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.fp8[i] := __W[i]
@@ -2123,7 +2788,7 @@ _mm_mask_cvtneph_phf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// resulting vector are zeroed. Zeroing mask \a __U is used to determine if
/// given element should be zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
@@ -2157,7 +2822,7 @@ _mm_maskz_cvtneph_phf8(__mmask8 __U, __m128h __A) {
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
/// to a 128-bit vector containing E4M3 FP8 elements.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
/// ENDFOR
@@ -2184,7 +2849,7 @@ _mm256_cvtneph_phf8(__m256h __A) {
/// to a 128-bit vector containing E4M3 FP8 elements. Merging mask \a __U is
/// used to determine if given element should be taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp8[i] := __W[i]
@@ -2220,7 +2885,7 @@ _mm256_mask_cvtneph_phf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// to a 128-bit vector containing E4M3 FP8 elements. Zeroing mask \a __U is
/// used to determine if given element should be zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
@@ -2254,7 +2919,7 @@ _mm256_maskz_cvtneph_phf8(__mmask16 __U, __m256h __A) {
/// to a 128-bit vector containing E4M3 FP8 elements. Upper elements of
/// resulting vector are zeroed. Results are saturated.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
/// ENDFOR
@@ -2281,7 +2946,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtnesph_phf8(__m128h __A) {
/// resulting vector are zeroed. Results are saturated. Merging mask \a __U is
/// used to determine if given element should be taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.fp8[i] := __W[i]
@@ -2318,7 +2983,7 @@ _mm_mask_cvtnesph_phf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// resulting vector are zeroed. Results are saturated. Zeroing mask \a __U is
/// used to determine if given element should be zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
@@ -2351,7 +3016,7 @@ _mm_maskz_cvtnesph_phf8(__mmask8 __U, __m128h __A) {
/// Convert 256-bit vector \a __A containing packed FP16 floating-point elements
/// to a 128-bit vector containing E4M3 FP8 elements. Results are saturated.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
/// ENDFOR
@@ -2379,7 +3044,7 @@ _mm256_cvtnesph_phf8(__m256h __A) {
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp8[i] := __W[i]
@@ -2416,7 +3081,7 @@ _mm256_mask_cvtnesph_phf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// Zeroing mask \a __U is used to determine if given element should be zeroed
/// instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
@@ -2449,7 +3114,7 @@ _mm256_maskz_cvtnesph_phf8(__mmask16 __U, __m256h __A) {
/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point
/// elements to a 128-bit vector containing FP16 elements. The conversion is exact.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
/// ENDFOR
@@ -2473,7 +3138,7 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtpbf8_ph(__m128i __A) {
/// exact. Merging mask \a __U is used to determine if given element should be
/// taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.fp16[i] := __W[i]
@@ -2508,7 +3173,7 @@ _mm_mask_cvtpbf8_ph(__m128h __S, __mmask8 __U, __m128i __A) {
/// exact. Zeroing mask \a __U is used to determine if given element should be
/// zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
@@ -2538,7 +3203,7 @@ _mm_maskz_cvtpbf8_ph(__mmask8 __U, __m128i __A) {
/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point
/// elements to a 256-bit vector containing FP16 elements. The conversion is exact.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
/// ENDFOR
@@ -2562,7 +3227,7 @@ static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtpbf8_ph(__m128i __A) {
/// exact. Merging mask \a __U is used to determine if given element should be
/// taken from \a __W instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp16[i] := __W[i]
@@ -2597,7 +3262,7 @@ _mm256_mask_cvtpbf8_ph(__m256h __S, __mmask8 __U, __m128i __A) {
/// exact. Zeroing mask \a __U is used to determine if given element should be
/// zeroed instead.
///
-/// \code{.operation]
+/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
>From b069337d461da42883093aedeb00c019131d3559 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Fri, 20 Dec 2024 17:17:17 +0100
Subject: [PATCH 5/7] Add all comments
---
clang/lib/Headers/avx10_2convertintrin.h | 281 +++++++++++------------
1 file changed, 139 insertions(+), 142 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 341dc9cfd6aae3..52a64a5309763d 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -47,7 +47,7 @@
/// \param __B
/// A 128-bit vector of [4 x float].
/// \returns
-/// A 128-bit vector of [8 x fp16]. Lower 4 elements correspond to the
+/// A 128-bit vector of [8 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtx2ps_ph(__m128 __A,
@@ -88,7 +88,7 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtx2ps_ph(__m128 __A,
/// \param __B
/// A 128-bit vector of [4 x float].
/// \returns
-/// A 128-bit vector of [8 x fp16]. Lower 4 elements correspond to the
+/// A 128-bit vector of [8 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is set, then
/// element from \a __W is taken instead.
@@ -122,13 +122,13 @@ _mm_mask_cvtx2ps_ph(__m128h __W, __mmask8 __U, __m128 __A, __m128 __B) {
/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
///
/// \param __U
-/// A 8-bit merging mask.
+/// A 8-bit zeroing mask.
/// \param __A
/// A 128-bit vector of [4 x float].
/// \param __B
/// A 128-bit vector of [4 x float].
/// \returns
-/// A 128-bit vector of [8 x fp16]. Lower 4 elements correspond to the
+/// A 128-bit vector of [8 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// then zero is taken instead.
@@ -161,7 +161,7 @@ _mm_maskz_cvtx2ps_ph(__mmask8 __U, __m128 __A, __m128 __B) {
/// \param __B
/// A 256-bit vector of [8 x float].
/// \returns
-/// A 256-bit vector of [16 x fp16]. Lower 8 elements correspond to the
+/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtx2ps_ph(__m256 __A,
@@ -197,13 +197,13 @@ static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtx2ps_ph(__m256 __A,
/// \param __W
/// A 256-bit vector of [16 x fp16].
/// \param __U
-/// A 8-bit merging mask.
+/// A 16-bit merging mask.
/// \param __A
/// A 256-bit vector of [8 x float].
/// \param __B
/// A 256-bit vector of [8 x float].
/// \returns
-/// A 256-bit vector of [16 x fp16]. Lower 4 elements correspond to the
+/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is set, then
/// element from \a __W is taken instead.
@@ -238,13 +238,13 @@ _mm256_mask_cvtx2ps_ph(__m256h __W, __mmask16 __U, __m256 __A, __m256 __B) {
/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
///
/// \param __U
-/// A 8-bit zeroing mask.
+/// A 16-bit zeroing mask.
/// \param __A
/// A 256-bit vector of [8 x float].
/// \param __B
/// A 256-bit vector of [8 x float].
/// \returns
-/// A 256-bit vector of [16 x fp16]. Lower 4 elements correspond to the
+/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// then zero is taken instead.
@@ -283,7 +283,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF,
/// _MM_FROUND_TO_ZERO.
/// \returns
-/// A 256-bit vector of [16 x fp16]. Lower 8 elements correspond to the
+/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
#define _mm256_cvtx_round2ps_ph(A, B, R) \
@@ -318,7 +318,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// \param __W
/// A 256-bit vector of [16 x fp16].
/// \param __U
-/// A 8-bit merging mask.
+/// A 16-bit merging mask.
/// \param __A
/// A 256-bit vector of [8 x float].
/// \param __B
@@ -329,7 +329,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF,
/// _MM_FROUND_TO_ZERO.
/// \returns
-/// A 256-bit vector of [16 x fp16]. Lower 4 elements correspond to the
+/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is set, then
/// element from \a __W is taken instead.
@@ -361,7 +361,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
///
/// \param __U
-/// A 8-bit zeroing mask.
+/// A 16-bit zeroing mask.
/// \param __A
/// A 256-bit vector of [8 x float].
/// \param __B
@@ -372,7 +372,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF,
/// _MM_FROUND_TO_ZERO.
/// \returns
-/// A 256-bit vector of [16 x fp16]. Lower 4 elements correspond to the
+/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// then zero is taken instead.
@@ -395,7 +395,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
///
/// \param __A
/// A 128-bit vector of [8 x fp16].
@@ -430,7 +430,7 @@ _mm_cvtbiasph_pbf8(__m128i __A, __m128h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
///
/// \param __W
/// A 128-bit vector of [16 x fp8].
@@ -470,7 +470,7 @@ _mm_mask_cvtbiasph_pbf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
///
/// \param __U
/// A 8-bit zeroing mask.
@@ -501,7 +501,7 @@ _mm_maskz_cvtbiasph_pbf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
///
/// \param __A
/// A 256-bit vector of [16 x fp16].
@@ -535,7 +535,7 @@ _mm256_cvtbiasph_pbf8(__m256i __A, __m256h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
///
/// \param __W
/// A 128-bit vector of [16 x fp8].
@@ -573,7 +573,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_pbf8(
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
///
/// \param __U
/// A 16-bit zeroing mask.
@@ -607,7 +607,7 @@ _mm256_maskz_cvtbiasph_pbf8(__mmask16 __U, __m256i __A, __m256h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8 instruction.
///
/// \param __A
/// A 128-bit vector of [8 x fp16].
@@ -642,7 +642,7 @@ _mm_cvtbiassph_pbf8(__m128i __A, __m128h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.
///
/// \param __W
/// A 128-bit vector of [16 x fp8].
@@ -682,7 +682,7 @@ _mm_mask_cvtbiassph_pbf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.
///
/// \param __U
/// A 8-bit zeroing mask.
@@ -714,7 +714,7 @@ _mm_maskz_cvtbiassph_pbf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.
///
/// \param __A
/// A 256-bit vector of [16 x fp16].
@@ -748,7 +748,7 @@ _mm256_cvtbiassph_pbf8(__m256i __A, __m256h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.
///
/// \param __W
/// A 128-bit vector of [16 x fp8].
@@ -786,7 +786,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_pbf8(
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2BF8S instruction.
///
/// \param __U
/// A 16-bit zeroing mask.
@@ -819,7 +819,7 @@ _mm256_maskz_cvtbiassph_pbf8(__mmask16 __U, __m256i __A, __m256h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.
///
/// \param __A
/// A 128-bit vector of [8 x fp16].
@@ -854,7 +854,7 @@ _mm_cvtbiasph_phf8(__m128i __A, __m128h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.
///
/// \param __W
/// A 128-bit vector of [16 x fp8].
@@ -894,7 +894,7 @@ _mm_mask_cvtbiasph_phf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.
///
/// \param __U
/// A 8-bit zeroing mask.
@@ -925,7 +925,7 @@ _mm_maskz_cvtbiasph_phf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.
///
/// \param __A
/// A 256-bit vector of [16 x fp16].
@@ -959,7 +959,7 @@ _mm256_cvtbiasph_phf8(__m256i __A, __m256h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.
///
/// \param __W
/// A 128-bit vector of [16 x fp8].
@@ -997,7 +997,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_phf8(
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8 instruction.
///
/// \param __U
/// A 16-bit zeroing mask.
@@ -1031,7 +1031,7 @@ _mm256_maskz_cvtbiasph_phf8(__mmask16 __U, __m256i __A, __m256h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S`instruction.
///
/// \param __A
/// A 128-bit vector of [8 x fp16].
@@ -1066,7 +1066,7 @@ _mm_cvtbiassph_phf8(__m128i __A, __m128h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.
///
/// \param __W
/// A 128-bit vector of [16 x fp8].
@@ -1106,7 +1106,7 @@ _mm_mask_cvtbiassph_phf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.
///
/// \param __U
/// A 8-bit zeroing mask.
@@ -1138,7 +1138,7 @@ _mm_maskz_cvtbiassph_phf8(__mmask8 __U, __m128i __A, __m128h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.
///
/// \param __A
/// A 256-bit vector of [16 x fp16].
@@ -1172,7 +1172,7 @@ _mm256_cvtbiassph_phf8(__m256i __A, __m256h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.
///
/// \param __W
/// A 128-bit vector of [16 x fp8].
@@ -1210,7 +1210,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_phf8(
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVT2PS2PHX instruction.
+/// This intrinsic corresponds to the \c VCVTBIASPH2HF8S instruction.
///
/// \param __U
/// A 16-bit zeroing mask.
@@ -1251,7 +1251,7 @@ _mm256_maskz_cvtbiassph_phf8(__mmask16 __U, __m256i __A, __m256h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtne2ph_pbf8(__m128h __A,
@@ -1292,7 +1292,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtne2ph_pbf8(__m128h __A,
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is set, then
/// element from \a __W is taken instead.
@@ -1332,7 +1332,7 @@ _mm_mask_cvtne2ph_pbf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// zero is taken instead.
@@ -1347,7 +1347,7 @@ _mm_maskz_cvtne2ph_pbf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
@@ -1365,7 +1365,7 @@ _mm_maskz_cvtne2ph_pbf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
@@ -1380,7 +1380,7 @@ _mm256_cvtne2ph_pbf8(__m256h __A, __m256h __B) {
/// from \a __W instead.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF __U[i]
/// dst.fp8[i] := __W.fp8[i]
/// ELSE
@@ -1406,7 +1406,7 @@ _mm256_cvtne2ph_pbf8(__m256h __A, __m256h __B) {
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is set, then
/// element from \a __W is taken instead.
@@ -1422,7 +1422,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtne2ph_pbf8(
/// instead.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF __U[i]
/// dst.fp8[i] := 0
/// ELSE
@@ -1446,7 +1446,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtne2ph_pbf8(
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// zero is taken instead.
@@ -1459,7 +1459,7 @@ _mm256_maskz_cvtne2ph_pbf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
-/// Resulting elements are saturated in case of overflow.
+/// Resulting elements are saturated in case of an overflow.
///
/// \code{.operation}
/// FOR i := 0 to 16
@@ -1480,7 +1480,7 @@ _mm256_maskz_cvtne2ph_pbf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -1492,7 +1492,7 @@ _mm_cvtnes2ph_pbf8(__m128h __A, __m128h __B) {
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead. Resulting elements are saturated in case of overflow.
+/// from \a __W instead. Resulting elements are saturated in case of an overflow.
///
/// \code{.operation}
/// FOR i := 0 to 16
@@ -1510,7 +1510,7 @@ _mm_cvtnes2ph_pbf8(__m128h __A, __m128h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
///
/// \param __W
/// A 128-bit vector of [16 x fp8].
@@ -1534,10 +1534,10 @@ _mm_mask_cvtnes2ph_pbf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
/// Zeroing mask \a __U is used to determine if given element should be zeroed
-/// instead. Resulting elements are saturated in case of overflow.
+/// instead. Resulting elements are saturated in case of an overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 16
+/// FOR i := 0 to 15
/// IF __U[i]
/// IF i < 8
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
@@ -1552,7 +1552,7 @@ _mm_mask_cvtnes2ph_pbf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
///
/// \param __U
/// A 16-bit zeroing mask.
@@ -1561,7 +1561,7 @@ _mm_mask_cvtnes2ph_pbf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// zero is taken instead.
@@ -1574,10 +1574,10 @@ _mm_maskz_cvtnes2ph_pbf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
-/// Resulting elements are saturated in case of overflow.
+/// Resulting elements are saturated in case of an overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
@@ -1588,14 +1588,14 @@ _mm_maskz_cvtnes2ph_pbf8(__mmask16 __U, __m128h __A, __m128h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
///
/// \param __A
/// A 256-bit vector of [16 x fp16].
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
@@ -1607,10 +1607,10 @@ _mm256_cvtnes2ph_pbf8(__m256h __A, __m256h __B) {
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead. Resulting elements are saturated in case of overflow.
+/// from \a __W instead. Resulting elements are saturated in case of an overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF __U[i]
/// dst.fp8[i] := __W.fp8[i]
/// ELSE
@@ -1625,7 +1625,7 @@ _mm256_cvtnes2ph_pbf8(__m256h __A, __m256h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
///
/// \param __W
/// A 256-bit vector of [32 x fp8].
@@ -1636,7 +1636,7 @@ _mm256_cvtnes2ph_pbf8(__m256h __A, __m256h __B) {
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is set, then
/// element from \a __W is taken instead.
@@ -1649,10 +1649,10 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtnes2ph_pbf8(
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
/// Merging mask \a __U is used to determine if given element should be zeroed
-/// instead. Resulting elements are saturated in case of overflow.
+/// instead. Resulting elements are saturated in case of an overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF __U[i]
/// dst.fp8[i] := 0
/// ELSE
@@ -1667,7 +1667,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtnes2ph_pbf8(
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
///
/// \param __U
/// A 32-bit zeroing mask.
@@ -1676,7 +1676,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtnes2ph_pbf8(
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// zero is taken instead.
@@ -1691,7 +1691,7 @@ _mm256_maskz_cvtnes2ph_pbf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
///
/// \code{.operation}
-/// FOR i := 0 to 16
+/// FOR i := 0 to 15
/// IF i < 8
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
@@ -1709,7 +1709,7 @@ _mm256_maskz_cvtnes2ph_pbf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtne2ph_phf8(__m128h __A,
@@ -1724,7 +1724,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtne2ph_phf8(__m128h __A,
/// from \a __W instead.
///
/// \code{.operation}
-/// FOR i := 0 to 16
+/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp8[i] := __W[i]
/// ELSE
@@ -1750,7 +1750,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtne2ph_phf8(__m128h __A,
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is set, then
/// element from \a __W is taken instead.
@@ -1766,7 +1766,7 @@ _mm_mask_cvtne2ph_phf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// instead.
///
/// \code{.operation}
-/// FOR i := 0 to 16
+/// FOR i := 0 to 15
/// IF __U[i]
/// IF i < 8
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
@@ -1790,7 +1790,7 @@ _mm_mask_cvtne2ph_phf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// zero is taken instead.
@@ -1805,7 +1805,7 @@ _mm_maskz_cvtne2ph_phf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
@@ -1823,7 +1823,7 @@ _mm_maskz_cvtne2ph_phf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
@@ -1838,7 +1838,7 @@ _mm256_cvtne2ph_phf8(__m256h __A, __m256h __B) {
/// from \a __W instead.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF __U[i]
/// dst.fp8[i] := __W.fp8[i]
/// ELSE
@@ -1864,7 +1864,7 @@ _mm256_cvtne2ph_phf8(__m256h __A, __m256h __B) {
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is set, then
/// element from \a __W is taken instead.
@@ -1880,7 +1880,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtne2ph_phf8(
/// instead.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF __U[i]
/// dst.fp8[i] := 0
/// ELSE
@@ -1904,7 +1904,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtne2ph_phf8(
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// zero is taken instead.
@@ -1917,10 +1917,10 @@ _mm256_maskz_cvtne2ph_phf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
-/// Resulting elements are saturated in case of overflow.
+/// Resulting elements are saturated in case of an overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 16
+/// FOR i := 0 to 15
/// IF i < 8
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
@@ -1931,14 +1931,14 @@ _mm256_maskz_cvtne2ph_phf8(__mmask32 __U, __m256h __A, __m256h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2HF8S instruction.
///
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
@@ -1950,10 +1950,10 @@ _mm_cvtnes2ph_phf8(__m128h __A, __m128h __B) {
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead. Resulting elements are saturated in case of overflow.
+/// from \a __W instead. Resulting elements are saturated in case of an overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 16
+/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp8[i] := __W[i]
/// ELSE
@@ -1968,7 +1968,7 @@ _mm_cvtnes2ph_phf8(__m128h __A, __m128h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2HF8S instruction.
///
/// \param __W
/// A 128-bit vector of [16 x fp8].
@@ -1979,7 +1979,7 @@ _mm_cvtnes2ph_phf8(__m128h __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is set, then
/// element from \a __W is taken instead.
@@ -1992,10 +1992,10 @@ _mm_mask_cvtnes2ph_phf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
/// Zeroing mask \a __U is used to determine if given element should be zeroed
-/// instead. Resulting elements are saturated in case of overflow.
+/// instead. Resulting elements are saturated in case of an overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 16
+/// FOR i := 0 to 15
/// IF __U[i]
/// IF i < 8
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
@@ -2010,7 +2010,7 @@ _mm_mask_cvtnes2ph_phf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2HF8S instruction.
///
/// \param __U
/// A 16-bit zeroing mask.
@@ -2019,7 +2019,7 @@ _mm_mask_cvtnes2ph_phf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// \param __B
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower 8 elements correspond to the
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set, then
/// zero is taken instead.
@@ -2032,11 +2032,11 @@ _mm_maskz_cvtnes2ph_phf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
-/// Resulting elements are saturated in case of overflow.
+/// Resulting elements are saturated in case of an overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 32
-/// IF i < 16
+/// FOR i := 0 to 15
+/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
@@ -2046,14 +2046,14 @@ _mm_maskz_cvtnes2ph_phf8(__mmask16 __U, __m128h __A, __m128h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2HF8S instruction.
///
/// \param __A
/// A 256-bit vector of [16 x fp16].
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A.
static __inline__ __m256i __DEFAULT_FN_ATTRS256
@@ -2065,10 +2065,10 @@ _mm256_cvtnes2ph_phf8(__m256h __A, __m256h __B) {
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead. Resulting elements are saturated in case of overflow.
+/// from \a __W instead. Resulting elements are saturated in case of an overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF __U[i]
/// dst.fp8[i] := __W.fp8[i]
/// ELSE
@@ -2083,7 +2083,7 @@ _mm256_cvtnes2ph_phf8(__m256h __A, __m256h __B) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2HF8S instruction.
///
/// \param __W
/// A 256-bit vector of [32 x fp8].
@@ -2094,7 +2094,7 @@ _mm256_cvtnes2ph_phf8(__m256h __A, __m256h __B) {
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is set, then
/// element from \a __W is taken instead.
@@ -2107,10 +2107,10 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtnes2ph_phf8(
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
/// Merging mask \a __U is used to determine if given element should be zeroed
-/// instead. Resulting elements are saturated in case of overflow.
+/// instead. Resulting elements are saturated in case of an overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 32
+/// FOR i := 0 to 31
/// IF __U[i]
/// dst.fp8[i] := 0
/// ELSE
@@ -2125,7 +2125,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtnes2ph_phf8(
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
///
/// \param __U
/// A 32-bit zeroing mask.
@@ -2134,7 +2134,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtnes2ph_phf8(
/// \param __B
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 256-bit vector of [32 x fp8]. Lower 16 elements correspond to the
+/// A 256-bit vector of [32 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
/// (converted) elements from \a __A. If corresponding mask bit is not set,
/// zero is taken instead.
@@ -2150,7 +2150,7 @@ _mm256_maskz_cvtnes2ph_phf8(__mmask32 __U, __m256h __A, __m256h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 7
-/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// dst.fp16[i] := convert_fp8_to_fp16(__A.fp8[i])
/// ENDFOR
/// \endcode
///
@@ -2178,7 +2178,7 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtnehf8_ph(__m128i __A) {
/// IF __U[i]
/// dst.fp16[i] := __W[i]
/// ELSE
-/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// dst.fp16[i] := convert_fp8_to_fp16(__A.fp8[i])
/// FI
/// ENDFOR
/// \endcode
@@ -2211,7 +2211,7 @@ _mm_mask_cvtnehf8_ph(__m128h __W, __mmask8 __U, __m128i __A) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// dst.fp16[i] := convert_fp8_to_fp16(__A.fp8[i])
/// ELSE
/// dst.fp16[i] := 0
/// FI
@@ -2241,7 +2241,7 @@ _mm_maskz_cvtnehf8_ph(__mmask8 __U, __m128i __A) {
///
/// \code{.operation}
/// FOR i := 0 to 15
-/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// dst.fp16[i] := convert_fp8_to_fp16(__A.fp8[i])
/// ENDFOR
/// \endcode
///
@@ -2270,7 +2270,7 @@ _mm256_cvtnehf8_ph(__m128i __A) {
/// IF __U[i]
/// dst.fp16[i] := __W[i]
/// ELSE
-/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
+/// dst.fp16[i] := convert_fp8_to_fp16(__A.fp8[i])
/// FI
/// ENDFOR
/// \endcode
@@ -2315,7 +2315,7 @@ _mm256_mask_cvtnehf8_ph(__m256h __W, __mmask16 __U, __m128i __A) {
/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
///
/// \param __U
-/// A 16-bit merging mask.
+/// A 16-bit zeroing mask.
/// \param __A
/// A 256-bit vector of [32 x fp8].
/// \returns
@@ -2342,7 +2342,7 @@ _mm256_maskz_cvtnehf8_ph(__mmask16 __U, __m128i __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNEPH2BF8 instruction.
///
/// \param __A
/// A 128-bit vector of [8 x fp16].
@@ -2373,7 +2373,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtneph_pbf8(__m128h __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNEPH2BF8 instruction.
///
/// \param __W
/// A 128-bit vector of [16 x fp8].
@@ -2382,7 +2382,6 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtneph_pbf8(__m128h __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-///
/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is set, then element from \a __W is taken instead.
@@ -2411,7 +2410,7 @@ _mm_mask_cvtneph_pbf8(__m128i __W, __mmask8 __U, __m128h __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNEPH2BF8 instruction.
///
/// \param __U
/// A 8-bit merging mask.
@@ -2510,7 +2509,7 @@ _mm256_mask_cvtneph_pbf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
///
/// \param __U
-/// A 16-bit merging mask.
+/// A 16-bit zeroing mask.
/// \param __A
/// A 256-bit vector of [16 x fp16].
/// \returns
@@ -2537,7 +2536,7 @@ _mm256_maskz_cvtneph_pbf8(__mmask16 __U, __m256h __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
///
/// \param __A
/// A 128-bit vector of [8 x fp16].
@@ -2568,7 +2567,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtnesph_pbf8(__m128h __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
///
/// \param __W
/// A 128-bit vector of [16 x fp8].
@@ -2605,7 +2604,7 @@ _mm_mask_cvtnesph_pbf8(__m128i __W, __mmask8 __U, __m128h __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
///
/// \param __U
/// A 8-bit zeroing mask.
@@ -2634,7 +2633,7 @@ _mm_maskz_cvtnesph_pbf8(__mmask8 __U, __m128h __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
///
/// \param __A
/// A 256-bit vector of [16 x fp16].
@@ -2666,7 +2665,7 @@ _mm256_cvtnesph_pbf8(__m256h __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
///
/// \param __W
/// A 128-bit vector of [16 x fp8].
@@ -2703,10 +2702,10 @@ _mm256_mask_cvtnesph_pbf8(__m128i __W, __mmask16 __U, __m256h __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
///
/// \param __U
-/// A 16-bit merging mask.
+/// A 16-bit zeroing mask.
/// \param __A
/// A 256-bit vector of [16 x fp16].
/// \returns
@@ -2733,7 +2732,7 @@ _mm256_maskz_cvtnesph_pbf8(__mmask16 __U, __m256h __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNEPH2HF8 instruction.
///
/// \param __A
/// A 128-bit vector of [8 x fp16].
@@ -2773,7 +2772,6 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtneph_phf8(__m128h __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-///
/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is set, then element from \a __W is taken instead.
@@ -2805,11 +2803,10 @@ _mm_mask_cvtneph_phf8(__m128i __W, __mmask8 __U, __m128h __A) {
/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
///
/// \param __U
-/// A 8-bit merging mask.
+/// A 8-bit zeroing mask.
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-///
/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __A; upper elements are zeroed. If
/// corresponding mask bit is not set, then element is zeroed.
@@ -2902,7 +2899,7 @@ _mm256_mask_cvtneph_phf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
///
/// \param __U
-/// A 16-bit merging mask.
+/// A 16-bit zeroing mask.
/// \param __A
/// A 256-bit vector of [16 x fp16].
/// \returns
@@ -2929,7 +2926,7 @@ _mm256_maskz_cvtneph_phf8(__mmask16 __U, __m256h __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNEPH2HF8S instruction.
///
/// \param __A
/// A 128-bit vector of [8 x fp16].
@@ -2960,7 +2957,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtnesph_phf8(__m128h __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
///
/// \param __W
/// A 128-bit vector of [16 x fp8].
@@ -2997,10 +2994,10 @@ _mm_mask_cvtnesph_phf8(__m128i __W, __mmask8 __U, __m128h __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
///
/// \param __U
-/// A 8-bit merging mask.
+/// A 8-bit zeroing mask.
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
@@ -3026,7 +3023,7 @@ _mm_maskz_cvtnesph_phf8(__mmask8 __U, __m128h __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
///
/// \param __A
/// A 256-bit vector of [16 x fp16].
@@ -3058,7 +3055,7 @@ _mm256_cvtnesph_phf8(__m256h __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
///
/// \param __W
/// A 128-bit vector of [16 x fp8].
@@ -3095,10 +3092,10 @@ _mm256_mask_cvtnesph_phf8(__m128i __W, __mmask16 __U, __m256h __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTNE2PH2BF8 instruction.
+/// This intrinsic corresponds to the \c VCVTNE2PH2BF8S instruction.
///
/// \param __U
-/// A 16-bit merging mask.
+/// A 16-bit zeroing mask.
/// \param __A
/// A 256-bit vector of [16 x fp16].
/// \returns
@@ -3122,7 +3119,7 @@ _mm256_maskz_cvtnesph_phf8(__mmask16 __U, __m256h __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+/// This intrinsic does not corresponds to a single instruction.
///
/// \param __A
/// A 128-bit vector of [16 x fp8].
@@ -3150,7 +3147,7 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtpbf8_ph(__m128i __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+/// This intrinsic does not corresponds to a single instruction.
///
/// \param __W
/// A 128-bit vector of [8 x fp16].
@@ -3185,7 +3182,7 @@ _mm_mask_cvtpbf8_ph(__m128h __S, __mmask8 __U, __m128i __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+/// This intrinsic does not corresponds to a single instruction.
///
/// \param __U
/// A 8-bit zeroing mask.
@@ -3211,7 +3208,7 @@ _mm_maskz_cvtpbf8_ph(__mmask8 __U, __m128i __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+/// This intrinsic does not corresponds to a single instruction.
///
/// \param __A
/// A 256-bit vector of [32 x fp8].
@@ -3239,7 +3236,7 @@ static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtpbf8_ph(__m128i __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+/// This intrinsic does not corresponds to a single instruction.
///
/// \param __W
/// A 256-bit vector of [16 x fp16].
@@ -3274,10 +3271,10 @@ _mm256_mask_cvtpbf8_ph(__m256h __S, __mmask8 __U, __m128i __A) {
///
/// \headerfile <immintrin.h>
///
-/// This intrinsic corresponds to the \c VCVTHF82PH instruction.
+/// This intrinsic does not corresponds to a single instruction.
///
/// \param __U
-/// A 16-bit merging mask.
+/// A 16-bit zeroing mask.
/// \param __A
/// A 256-bit vector of [32 x fp8].
/// \returns
>From 446b501de2e91387921cb2709baf03bf7a7a0c41 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Fri, 20 Dec 2024 17:25:16 +0100
Subject: [PATCH 6/7] Formatting
---
clang/lib/Headers/avx10_2convertintrin.h | 260 +++++++++++------------
1 file changed, 120 insertions(+), 140 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 52a64a5309763d..38d9f1982b151e 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -143,7 +143,7 @@ _mm_maskz_cvtx2ps_ph(__mmask8 __U, __m128 __A, __m128 __B) {
/// containing FP16 elements.
///
/// \code{.operation}
-/// FOR i := 0 to 15
+/// FOR i := 0 to 15
/// IF i < 8
/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
/// ELSE
@@ -220,7 +220,7 @@ _mm256_mask_cvtx2ps_ph(__m256h __W, __mmask16 __U, __m256 __A, __m256 __B) {
/// element should be zeroed instead.
///
/// \code{.operation}
-/// FOR i := 0 to 15
+/// FOR i := 0 to 15
/// IF mask[i]
/// IF i < 8
/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
@@ -260,7 +260,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// containing FP16 elements. Rounding mode \a __R needs to be provided.
///
/// \code{.operation}
-/// FOR i := 0 to 15
+/// FOR i := 0 to 15
/// IF i < 8
/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
/// ELSE
@@ -279,9 +279,9 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// A 256-bit vector of [8 x float].
/// \param __R
/// Rounding mode. Valid inputs are: _MM_FROUND_CUR_DIRECTION or
-/// result of bitwise or of _MM_FROUND_NO_EXC with at most one of the following:
-/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF,
-/// _MM_FROUND_TO_ZERO.
+/// result of bitwise or of _MM_FROUND_NO_EXC with at most one of the
+/// following: _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF,
+/// _MM_FROUND_TO_POS_INF, _MM_FROUND_TO_ZERO.
/// \returns
/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
@@ -325,9 +325,9 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// A 256-bit vector of [8 x float].
/// \param __R
/// Rounding mode. Valid inputs are: _MM_FROUND_CUR_DIRECTION or
-/// result of bitwise or of _MM_FROUND_NO_EXC with at most one of the following:
-/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF,
-/// _MM_FROUND_TO_ZERO.
+/// result of bitwise or of _MM_FROUND_NO_EXC with at most one of the
+/// following: _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF,
+/// _MM_FROUND_TO_POS_INF, _MM_FROUND_TO_ZERO.
/// \returns
/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
@@ -343,7 +343,7 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// element should be zeroed instead. Rounding mode \a __R needs to be provided.
///
/// \code{.operation}
-/// FOR i := 0 to 15
+/// FOR i := 0 to 15
/// IF mask[i]
/// IF i < 8
/// dst.fp16[i] := convert_fp32_to_fp16(__B.fp32[i])
@@ -368,9 +368,9 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
/// A 256-bit vector of [8 x float].
/// \param __R
/// Rounding mode. Valid inputs are: _MM_FROUND_CUR_DIRECTION or
-/// result of bitwise or of _MM_FROUND_NO_EXC with at most one of the following:
-/// _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF, _MM_FROUND_TO_POS_INF,
-/// _MM_FROUND_TO_ZERO.
+/// result of bitwise or of _MM_FROUND_NO_EXC with at most one of the
+/// following: _MM_FROUND_TO_NEAREST_INT, _MM_FROUND_TO_NEG_INF,
+/// _MM_FROUND_TO_POS_INF, _MM_FROUND_TO_ZERO.
/// \returns
/// A 256-bit vector of [16 x fp16]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
@@ -421,9 +421,8 @@ _mm_cvtbiasph_pbf8(__m128i __A, __m128h __B) {
/// IF __U[i]
/// dst.fp8[i] := _W[i]
/// ELSE
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
-/// FI
-/// ENDFOR
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i],
+/// __B.int8[2i]) FI ENDFOR
///
/// dst[127:64] := 0
/// \endcode
@@ -459,10 +458,8 @@ _mm_mask_cvtbiasph_pbf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
-/// ELSE
-/// dst.fp8[i] := 0
-/// FI
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i],
+///__B.int8[2i]) ELSE dst.fp8[i] := 0 FI
/// ENDFOR
///
/// dst[127:64] := 0
@@ -528,10 +525,8 @@ _mm256_cvtbiasph_pbf8(__m256i __A, __m256h __B) {
/// IF __U[i]
/// dst.fp8[i] := _W[i]
/// ELSE
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
-/// FI
-/// ENDFOR
-/// \endcode
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i],
+/// __B.int8[2i]) FI ENDFOR \endcode
///
/// \headerfile <immintrin.h>
///
@@ -564,10 +559,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_pbf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
-/// ELSE
-/// dst.fp8[i] := 0
-/// FI
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i],
+///__B.int8[2i]) ELSE dst.fp8[i] := 0 FI
/// ENDFOR
/// \endcode
///
@@ -633,9 +626,8 @@ _mm_cvtbiassph_pbf8(__m128i __A, __m128h __B) {
/// IF __U[i]
/// dst.fp8[i] := _W[i]
/// ELSE
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
-/// FI
-/// ENDFOR
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i],
+/// __B.int8[2i]) FI ENDFOR
///
/// dst[127:64] := 0
/// \endcode
@@ -671,10 +663,8 @@ _mm_mask_cvtbiassph_pbf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
-/// ELSE
-/// dst.fp8[i] := 0
-/// FI
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i],
+///__B.int8[2i]) ELSE dst.fp8[i] := 0 FI
/// ENDFOR
///
/// dst[127:64] := 0
@@ -741,10 +731,8 @@ _mm256_cvtbiassph_pbf8(__m256i __A, __m256h __B) {
/// IF __U[i]
/// dst.fp8[i] := _W[i]
/// ELSE
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
-/// FI
-/// ENDFOR
-/// \endcode
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i],
+/// __B.int8[2i]) FI ENDFOR \endcode
///
/// \headerfile <immintrin.h>
///
@@ -777,10 +765,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_pbf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
-/// ELSE
-/// dst.fp8[i] := 0
-/// FI
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i],
+///__B.int8[2i]) ELSE dst.fp8[i] := 0 FI
/// ENDFOR
/// \endcode
///
@@ -845,9 +831,8 @@ _mm_cvtbiasph_phf8(__m128i __A, __m128h __B) {
/// IF __U[i]
/// dst.fp8[i] := _W[i]
/// ELSE
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
-/// FI
-/// ENDFOR
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i],
+/// __B.int8[2i]) FI ENDFOR
///
/// dst[127:64] := 0
/// \endcode
@@ -883,10 +868,8 @@ _mm_mask_cvtbiasph_phf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
-/// ELSE
-/// dst.fp8[i] := 0
-/// FI
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i],
+///__B.int8[2i]) ELSE dst.fp8[i] := 0 FI
/// ENDFOR
///
/// dst[127:64] := 0
@@ -952,10 +935,8 @@ _mm256_cvtbiasph_phf8(__m256i __A, __m256h __B) {
/// IF __U[i]
/// dst.fp8[i] := _W[i]
/// ELSE
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
-/// FI
-/// ENDFOR
-/// \endcode
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i],
+/// __B.int8[2i]) FI ENDFOR \endcode
///
/// \headerfile <immintrin.h>
///
@@ -981,17 +962,15 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiasph_phf8(
/// Add two 256-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements and 8-bit integers stored in the lower half of
-/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3
+/// packed 16-bit integers, respectively. Results are converted to FP8 E4M3
/// Merging mask \a __U is used to determine if given element should be taken
/// from \a __W instead.
///
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
-/// ELSE
-/// dst.fp8[i] := 0
-/// FI
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i],
+///__B.int8[2i]) ELSE dst.fp8[i] := 0 FI
/// ENDFOR
/// \endcode
///
@@ -1057,9 +1036,8 @@ _mm_cvtbiassph_phf8(__m128i __A, __m128h __B) {
/// IF __U[i]
/// dst.fp8[i] := _W[i]
/// ELSE
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
-/// FI
-/// ENDFOR
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i],
+/// __B.int8[2i]) FI ENDFOR
///
/// dst[127:64] := 0
/// \endcode
@@ -1095,10 +1073,8 @@ _mm_mask_cvtbiassph_phf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
/// \code{.operation}
/// FOR i := 0 to 7
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
-/// ELSE
-/// dst.fp8[i] := 0
-/// FI
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i],
+///__B.int8[2i]) ELSE dst.fp8[i] := 0 FI
/// ENDFOR
///
/// dst[127:64] := 0
@@ -1165,10 +1141,8 @@ _mm256_cvtbiassph_phf8(__m256i __A, __m256h __B) {
/// IF __U[i]
/// dst.fp8[i] := _W[i]
/// ELSE
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
-/// FI
-/// ENDFOR
-/// \endcode
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i],
+/// __B.int8[2i]) FI ENDFOR \endcode
///
/// \headerfile <immintrin.h>
///
@@ -1201,10 +1175,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_phf8(
/// \code{.operation}
/// FOR i := 0 to 15
/// IF __U[i]
-/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i], __B.int8[2i])
-/// ELSE
-/// dst.fp8[i] := 0
-/// FI
+/// dst.fp8[i] := add_convert_fp16_to_fp8_bias(__A.fp16[i],
+///__B.int8[2i]) ELSE dst.fp8[i] := 0 FI
/// ENDFOR
/// \endcode
///
@@ -1233,7 +1205,7 @@ _mm256_maskz_cvtbiassph_phf8(__mmask16 __U, __m256i __A, __m256h __B) {
/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
///
/// \code{.operation}
-/// FOR i := 0 to 16
+/// FOR i := 0 to 16
/// IF i < 8
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
@@ -1308,7 +1280,7 @@ _mm_mask_cvtne2ph_pbf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// instead.
///
/// \code{.operation}
-/// FOR i := 0 to 16
+/// FOR i := 0 to 16
/// IF __U[i]
/// IF i < 8
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
@@ -1334,8 +1306,8 @@ _mm_mask_cvtne2ph_pbf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// \returns
/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
-/// (converted) elements from \a __A. If corresponding mask bit is not set, then
-/// zero is taken instead.
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then zero is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtne2ph_pbf8(__mmask16 __U, __m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_selectb_128(
@@ -1347,8 +1319,8 @@ _mm_maskz_cvtne2ph_pbf8(__mmask16 __U, __m128h __A, __m128h __B) {
/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
///
/// \code{.operation}
-/// FOR i := 0 to 31
-/// IF i < 16
+/// FOR i := 0 to 31
+/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
@@ -1380,11 +1352,11 @@ _mm256_cvtne2ph_pbf8(__m256h __A, __m256h __B) {
/// from \a __W instead.
///
/// \code{.operation}
-/// FOR i := 0 to 31
+/// FOR i := 0 to 31
/// IF __U[i]
/// dst.fp8[i] := __W.fp8[i]
/// ELSE
-/// IF i < 16
+/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
@@ -1422,11 +1394,11 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtne2ph_pbf8(
/// instead.
///
/// \code{.operation}
-/// FOR i := 0 to 31
+/// FOR i := 0 to 31
/// IF __U[i]
/// dst.fp8[i] := 0
/// ELSE
-/// IF i < 16
+/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
@@ -1462,7 +1434,7 @@ _mm256_maskz_cvtne2ph_pbf8(__mmask32 __U, __m256h __A, __m256h __B) {
/// Resulting elements are saturated in case of an overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 16
+/// FOR i := 0 to 16
/// IF i < 8
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
@@ -1492,10 +1464,11 @@ _mm_cvtnes2ph_pbf8(__m128h __A, __m128h __B) {
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 128-bit vector containing E5M2 FP8 elements.
/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead. Resulting elements are saturated in case of an overflow.
+/// from \a __W instead. Resulting elements are saturated in case of an
+/// overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 16
+/// FOR i := 0 to 16
/// IF __U[i]
/// dst.fp8[i] := __W[i]
/// ELSE
@@ -1563,8 +1536,8 @@ _mm_mask_cvtnes2ph_pbf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// \returns
/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
-/// (converted) elements from \a __A. If corresponding mask bit is not set, then
-/// zero is taken instead.
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then zero is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtnes2ph_pbf8(__mmask16 __U, __m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_selectb_128(
@@ -1578,7 +1551,7 @@ _mm_maskz_cvtnes2ph_pbf8(__mmask16 __U, __m128h __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 31
-/// IF i < 16
+/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
@@ -1607,14 +1580,15 @@ _mm256_cvtnes2ph_pbf8(__m256h __A, __m256h __B) {
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 256-bit vector containing E5M2 FP8 elements.
/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead. Resulting elements are saturated in case of an overflow.
+/// from \a __W instead. Resulting elements are saturated in case of an
+/// overflow.
///
/// \code{.operation}
/// FOR i := 0 to 31
/// IF __U[i]
/// dst.fp8[i] := __W.fp8[i]
/// ELSE
-/// IF i < 16
+/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
@@ -1656,7 +1630,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtnes2ph_pbf8(
/// IF __U[i]
/// dst.fp8[i] := 0
/// ELSE
-/// IF i < 16
+/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
@@ -1766,7 +1740,7 @@ _mm_mask_cvtne2ph_phf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// instead.
///
/// \code{.operation}
-/// FOR i := 0 to 15
+/// FOR i := 0 to 15
/// IF __U[i]
/// IF i < 8
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
@@ -1792,8 +1766,8 @@ _mm_mask_cvtne2ph_phf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// \returns
/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
-/// (converted) elements from \a __A. If corresponding mask bit is not set, then
-/// zero is taken instead.
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then zero is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtne2ph_phf8(__mmask16 __U, __m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_selectb_128(
@@ -1806,7 +1780,7 @@ _mm_maskz_cvtne2ph_phf8(__mmask16 __U, __m128h __A, __m128h __B) {
///
/// \code{.operation}
/// FOR i := 0 to 31
-/// IF i < 16
+/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
@@ -1842,7 +1816,7 @@ _mm256_cvtne2ph_phf8(__m256h __A, __m256h __B) {
/// IF __U[i]
/// dst.fp8[i] := __W.fp8[i]
/// ELSE
-/// IF i < 16
+/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
@@ -1884,7 +1858,7 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtne2ph_phf8(
/// IF __U[i]
/// dst.fp8[i] := 0
/// ELSE
-/// IF i < 16
+/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
@@ -1950,7 +1924,8 @@ _mm_cvtnes2ph_phf8(__m128h __A, __m128h __B) {
/// Convert two 128-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 128-bit vector containing E4M3 FP8 elements.
/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead. Resulting elements are saturated in case of an overflow.
+/// from \a __W instead. Resulting elements are saturated in case of an
+/// overflow.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -2021,8 +1996,8 @@ _mm_mask_cvtnes2ph_phf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
/// \returns
/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
/// (converted) elements from \a __B; higher order elements correspond to the
-/// (converted) elements from \a __A. If corresponding mask bit is not set, then
-/// zero is taken instead.
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then zero is taken instead.
static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_cvtnes2ph_phf8(__mmask16 __U, __m128h __A, __m128h __B) {
return (__m128i)__builtin_ia32_selectb_128(
@@ -2065,14 +2040,15 @@ _mm256_cvtnes2ph_phf8(__m256h __A, __m256h __B) {
/// Convert two 256-bit vectors, \a __A and \a __B, containing packed FP16
/// floating-point elements to a 256-bit vector containing E4M3 FP8 elements.
/// Merging mask \a __U is used to determine if given element should be taken
-/// from \a __W instead. Resulting elements are saturated in case of an overflow.
+/// from \a __W instead. Resulting elements are saturated in case of an
+/// overflow.
///
/// \code{.operation}
/// FOR i := 0 to 31
/// IF __U[i]
/// dst.fp8[i] := __W.fp8[i]
/// ELSE
-/// IF i < 16
+/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
@@ -2110,11 +2086,11 @@ static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtnes2ph_phf8(
/// instead. Resulting elements are saturated in case of an overflow.
///
/// \code{.operation}
-/// FOR i := 0 to 31
+/// FOR i := 0 to 31
/// IF __U[i]
/// dst.fp8[i] := 0
/// ELSE
-/// IF i < 16
+/// IF i < 16
/// dst.fp8[i] := convert_fp16_to_fp8(__B.fp16[i])
/// ELSE
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i - 16])
@@ -2146,7 +2122,8 @@ _mm256_maskz_cvtnes2ph_phf8(__mmask32 __U, __m256h __A, __m256h __B) {
}
/// Convert 128-bit vector \a __A, containing packed FP8 E4M3 floating-point
-/// elements to a 128-bit vector containing FP16 elements. The conversion is exact.
+/// elements to a 128-bit vector containing FP16 elements. The conversion is
+/// exact.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -2228,8 +2205,8 @@ _mm_mask_cvtnehf8_ph(__m128h __W, __mmask8 __U, __m128i __A) {
/// A 128-bit vector of [16 x fp8].
/// \returns
/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
-/// (converted) elements from \a __A. If corresponding mask bit is not set, then
-/// zero is taken instead.
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then zero is taken instead.
static __inline__ __m128h __DEFAULT_FN_ATTRS128
_mm_maskz_cvtnehf8_ph(__mmask8 __U, __m128i __A) {
return (__m128h)__builtin_ia32_vcvthf8_2ph128_mask(
@@ -2237,7 +2214,8 @@ _mm_maskz_cvtnehf8_ph(__mmask8 __U, __m128i __A) {
}
/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point
-/// elements to a 256-bit vector containing FP16 elements. The conversion is exact.
+/// elements to a 256-bit vector containing FP16 elements. The conversion is
+/// exact.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -2266,7 +2244,7 @@ _mm256_cvtnehf8_ph(__m128i __A) {
/// taken from \a __W instead.
///
/// \code{.operation}
-/// FOR i := 0 to 15
+/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp16[i] := __W[i]
/// ELSE
@@ -2301,7 +2279,7 @@ _mm256_mask_cvtnehf8_ph(__m256h __W, __mmask16 __U, __m128i __A) {
/// zeroed instead.
///
/// \code{.operation}
-/// FOR i := 0 to 15
+/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
/// ELSE
@@ -2320,8 +2298,8 @@ _mm256_mask_cvtnehf8_ph(__m256h __W, __mmask16 __U, __m128i __A) {
/// A 256-bit vector of [32 x fp8].
/// \returns
/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
-/// (converted) elements from \a __A. If corresponding mask bit is not set, then
-/// zero is taken instead.
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then zero is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtnehf8_ph(__mmask16 __U, __m128i __A) {
return (__m256h)__builtin_ia32_vcvthf8_2ph256_mask(
@@ -2347,8 +2325,8 @@ _mm256_maskz_cvtnehf8_ph(__mmask16 __U, __m128i __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the (converted)
-/// elements from \a __A; upper elements are zeroed.
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtneph_pbf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtneph2bf8_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);
@@ -2444,8 +2422,8 @@ _mm_maskz_cvtneph_pbf8(__mmask8 __U, __m128h __A) {
/// \param __A
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the (converted)
-/// elements from \a __A.
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtneph_pbf8(__m256h __A) {
return (__m128i)__builtin_ia32_vcvtneph2bf8_256_mask(
@@ -2541,8 +2519,8 @@ _mm256_maskz_cvtneph_pbf8(__mmask16 __U, __m256h __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the (converted)
-/// elements from \a __A; upper elements are zeroed.
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtnesph_pbf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtneph2bf8s_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);
@@ -2638,8 +2616,8 @@ _mm_maskz_cvtnesph_pbf8(__mmask8 __U, __m128h __A) {
/// \param __A
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the (converted)
-/// elements from \a __A.
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtnesph_pbf8(__m256h __A) {
return (__m128i)__builtin_ia32_vcvtneph2bf8s_256_mask(
@@ -2689,7 +2667,7 @@ _mm256_mask_cvtnesph_pbf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// instead.
///
/// \code{.operation}
-/// FOR i := 0 to 15
+/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
/// ELSE
@@ -2737,8 +2715,8 @@ _mm256_maskz_cvtnesph_pbf8(__mmask16 __U, __m256h __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the (converted)
-/// elements from \a __A; upper elements are zeroed.
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtneph_phf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtneph2hf8_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);
@@ -2834,8 +2812,8 @@ _mm_maskz_cvtneph_phf8(__mmask8 __U, __m128h __A) {
/// \param __A
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the (converted)
-/// elements from \a __A.
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtneph_phf8(__m256h __A) {
return (__m128i)__builtin_ia32_vcvtneph2hf8_256_mask(
@@ -2931,8 +2909,8 @@ _mm256_maskz_cvtneph_phf8(__mmask16 __U, __m256h __A) {
/// \param __A
/// A 128-bit vector of [8 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the (converted)
-/// elements from \a __A; upper elements are zeroed.
+/// A 128-bit vector of [16 x fp8]. Lower elements correspond to the
+/// (converted) elements from \a __A; upper elements are zeroed.
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtnesph_phf8(__m128h __A) {
return (__m128i)__builtin_ia32_vcvtneph2hf8s_128_mask(
(__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);
@@ -3028,8 +3006,8 @@ _mm_maskz_cvtnesph_phf8(__mmask8 __U, __m128h __A) {
/// \param __A
/// A 256-bit vector of [16 x fp16].
/// \returns
-/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the (converted)
-/// elements from \a __A.
+/// A 128-bit vector of [16 x fp8]. Resulting elements correspond to the
+/// (converted) elements from \a __A.
static __inline__ __m128i __DEFAULT_FN_ATTRS256
_mm256_cvtnesph_phf8(__m256h __A) {
return (__m128i)__builtin_ia32_vcvtneph2hf8s_256_mask(
@@ -3079,7 +3057,7 @@ _mm256_mask_cvtnesph_phf8(__m128i __W, __mmask16 __U, __m256h __A) {
/// instead.
///
/// \code{.operation}
-/// FOR i := 0 to 15
+/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp8[i] := convert_fp16_to_fp8(__A.fp16[i])
/// ELSE
@@ -3109,7 +3087,8 @@ _mm256_maskz_cvtnesph_phf8(__mmask16 __U, __m256h __A) {
}
/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point
-/// elements to a 128-bit vector containing FP16 elements. The conversion is exact.
+/// elements to a 128-bit vector containing FP16 elements. The conversion is
+/// exact.
///
/// \code{.operation}
/// FOR i := 0 to 7
@@ -3190,15 +3169,16 @@ _mm_mask_cvtpbf8_ph(__m128h __S, __mmask8 __U, __m128i __A) {
/// A 128-bit vector of [16 x fp8].
/// \returns
/// A 128-bit vector of [8 x fp16]. Resulting elements correspond to the
-/// (converted) elements from \a __A. If corresponding mask bit is not set, then
-/// zero is taken instead.
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then zero is taken instead.
static __inline__ __m128h __DEFAULT_FN_ATTRS128
_mm_maskz_cvtpbf8_ph(__mmask8 __U, __m128i __A) {
return _mm_castsi128_ph(_mm_slli_epi16(_mm_maskz_cvtepi8_epi16(__U, __A), 8));
}
/// Convert 256-bit vector \a __A, containing packed FP8 E4M3 floating-point
-/// elements to a 256-bit vector containing FP16 elements. The conversion is exact.
+/// elements to a 256-bit vector containing FP16 elements. The conversion is
+/// exact.
///
/// \code{.operation}
/// FOR i := 0 to 15
@@ -3225,7 +3205,7 @@ static __inline__ __m256h __DEFAULT_FN_ATTRS256 _mm256_cvtpbf8_ph(__m128i __A) {
/// taken from \a __W instead.
///
/// \code{.operation}
-/// FOR i := 0 to 15
+/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp16[i] := __W[i]
/// ELSE
@@ -3260,7 +3240,7 @@ _mm256_mask_cvtpbf8_ph(__m256h __S, __mmask8 __U, __m128i __A) {
/// zeroed instead.
///
/// \code{.operation}
-/// FOR i := 0 to 15
+/// FOR i := 0 to 15
/// IF __U[i]
/// dst.fp16[i] := convert_fp8_to_fp16(__B.fp8[i])
/// ELSE
@@ -3279,8 +3259,8 @@ _mm256_mask_cvtpbf8_ph(__m256h __S, __mmask8 __U, __m128i __A) {
/// A 256-bit vector of [32 x fp8].
/// \returns
/// A 256-bit vector of [16 x fp16]. Resulting elements correspond to the
-/// (converted) elements from \a __A. If corresponding mask bit is not set, then
-/// zero is taken instead.
+/// (converted) elements from \a __A. If corresponding mask bit is not set,
+/// then zero is taken instead.
static __inline__ __m256h __DEFAULT_FN_ATTRS256
_mm256_maskz_cvtpbf8_ph(__mmask8 __U, __m128i __A) {
return _mm256_castsi256_ph(
>From 2876aae2f4f3c8a647138abd2d442de1fe1103b8 Mon Sep 17 00:00:00 2001
From: "Pirog, Mikolaj Maciej" <mikolaj.maciej.pirog at intel.com>
Date: Fri, 20 Dec 2024 18:01:07 +0100
Subject: [PATCH 7/7] Rename mask vector in one function to __W for consistency
---
clang/lib/Headers/avx10_2convertintrin.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h
index 38d9f1982b151e..1db9ebe26981e3 100644
--- a/clang/lib/Headers/avx10_2convertintrin.h
+++ b/clang/lib/Headers/avx10_2convertintrin.h
@@ -3139,9 +3139,9 @@ static __inline__ __m128h __DEFAULT_FN_ATTRS128 _mm_cvtpbf8_ph(__m128i __A) {
/// (converted) elements from \a __A. If corresponding mask bit is set, then
/// element from \a __W is taken instead.
static __inline__ __m128h __DEFAULT_FN_ATTRS128
-_mm_mask_cvtpbf8_ph(__m128h __S, __mmask8 __U, __m128i __A) {
+_mm_mask_cvtpbf8_ph(__m128h __W, __mmask8 __U, __m128i __A) {
return _mm_castsi128_ph(
- _mm_mask_slli_epi16((__m128i)__S, __U, _mm_cvtepi8_epi16(__A), 8));
+ _mm_mask_slli_epi16((__m128i)__W, __U, _mm_cvtepi8_epi16(__A), 8));
}
/// Convert 128-bit vector \a __A, containing packed FP8 E5M2 floating-point
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