[clang] [llvm] [AArch64] Implement intrinsics for SME FP8 FMOPA (PR #118115)

[Momchil Velikov via cfe-commits]

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@@ -305,6 +305,21 @@ multiclass sme_outer_product_fp32<bit S, bits<2> sz, ZPRRegOp zpr_ty, string mne
   def : SME_ZA_Tile_TwoPred_TwoVec_Pat<NAME, op, timm32_0_3, nxv4i1, nxv4f32>;
 }
 
+multiclass sme2_fp8_fmopa_za32<string mnemonic, SDPatternOperator intrinsic> {
+    def NAME : sme_fp_outer_product_inst<0, 0b01, 0b00, TileOp32, ZPR8, mnemonic>, SMEPseudo2Instr<NAME, 1> {
+      bits<2> ZAda;
+      let Inst{1-0} = ZAda;
+      let Inst{2}   = 0b0;
+
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momchil-velikov wrote:

Yes, only where the ISel pattern and the instruction interact. If the transform sequence is DAG -> pseudo-insn -> real-insn, onlt the pseudo-insn would need flags (and "need" here means "to silence tblgen" not a legit need).

https://github.com/llvm/llvm-project/pull/118115