[clang] [llvm] [ARM] Add Cortex-A510 CPU for AArch32 (PR #118811)
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Thu Dec 5 06:22:46 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-arm
Author: Oliver Stannard (ostannard)
<details>
<summary>Changes</summary>
This core was originally AArch64-only, but the r1p0 revision added optional support for AArch32 at EL0.
TRM: https://developer.arm.com/documentation/101604/0103
---
Full diff: https://github.com/llvm/llvm-project/pull/118811.diff
7 Files Affected:
- (modified) clang/test/Driver/arm-cortex-cpus-2.c (+11)
- (modified) clang/test/Misc/target-invalid-cpu-note/arm.c (+1)
- (modified) llvm/include/llvm/TargetParser/ARMTargetParser.def (+3)
- (modified) llvm/lib/Target/ARM/ARMProcessors.td (+10)
- (modified) llvm/lib/Target/ARM/ARMSubtarget.cpp (+1)
- (modified) llvm/test/CodeGen/ARM/build-attributes.ll (+6)
- (modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+9-1)
``````````diff
diff --git a/clang/test/Driver/arm-cortex-cpus-2.c b/clang/test/Driver/arm-cortex-cpus-2.c
index 2f17a081404361..0ee8e05f378efe 100644
--- a/clang/test/Driver/arm-cortex-cpus-2.c
+++ b/clang/test/Driver/arm-cortex-cpus-2.c
@@ -544,6 +544,17 @@
// CHECK-CORTEX-A78AE-MFPU: "-target-feature" "+sha2"
// CHECK-CORTEX-A78AE-MFPU: "-target-feature" "+aes"
+// RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-a510 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CORTEX-A510 %s
+// RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-a510 -mfpu=crypto-neon-fp-armv8 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CORTEX-A510-MFPU %s
+// CHECK-CORTEX-A510: "-cc1"{{.*}} "-triple" "armv9a-{{.*}} "-target-cpu" "cortex-a510"
+// CHECK-CORTEX-A510-NOT: "-target-feature" "{{[+-]}}sm4"
+// CHECK-CORTEX-A510-NOT: "-target-feature" "{{[+-]}}sha3"
+// CHECK-CORTEX-A510: "-target-feature" "-aes"
+// CHECK-CORTEX-A510-SAME: {{$}}
+// CHECK-CORTEX-A510-MFPU: "-cc1"{{.*}} "-target-feature" "+fp-armv8"
+// CHECK-CORTEX-A510-MFPU: "-target-feature" "+sha2"
+// CHECK-CORTEX-A510-MFPU: "-target-feature" "+aes"
+
// RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-a710 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CORTEX-A710 %s
// RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-a710 -mfpu=crypto-neon-fp-armv8 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CORTEX-A710-MFPU %s
// CHECK-CORTEX-A710: "-cc1"{{.*}} "-triple" "armv9a-{{.*}} "-target-cpu" "cortex-a710"
diff --git a/clang/test/Misc/target-invalid-cpu-note/arm.c b/clang/test/Misc/target-invalid-cpu-note/arm.c
index 17280a9edd221d..12acdabbb77565 100644
--- a/clang/test/Misc/target-invalid-cpu-note/arm.c
+++ b/clang/test/Misc/target-invalid-cpu-note/arm.c
@@ -84,6 +84,7 @@
// CHECK-SAME: {{^}}, cortex-a78
// CHECK-SAME: {{^}}, cortex-a78ae
// CHECK-SAME: {{^}}, cortex-a78c
+// CHECK-SAME: {{^}}, cortex-a510
// CHECK-SAME: {{^}}, cortex-a710
// CHECK-SAME: {{^}}, cortex-x1
// CHECK-SAME: {{^}}, cortex-x1c
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index c5cd1b1bc63765..6b96c3e83c8c4f 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -374,6 +374,9 @@ ARM_CPU_NAME("cortex-a78ae", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
(ARM::AEK_RAS | ARM::AEK_DOTPROD))
ARM_CPU_NAME("cortex-a78c", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_FP16 | ARM::AEK_DOTPROD)
+ARM_CPU_NAME("cortex-a510", ARMV9A, FK_NEON_FP_ARMV8, false,
+ (ARM::AEK_DOTPROD | ARM::AEK_FP16FML | ARM::AEK_BF16 |
+ ARM::AEK_SB | ARM::AEK_I8MM))
ARM_CPU_NAME("cortex-a710", ARMV9A, FK_NEON_FP_ARMV8, false,
(ARM::AEK_DOTPROD | ARM::AEK_FP16FML | ARM::AEK_BF16 |
ARM::AEK_SB | ARM::AEK_I8MM))
diff --git a/llvm/lib/Target/ARM/ARMProcessors.td b/llvm/lib/Target/ARM/ARMProcessors.td
index 22e7e6893c1a82..213b104bcfdb2f 100644
--- a/llvm/lib/Target/ARM/ARMProcessors.td
+++ b/llvm/lib/Target/ARM/ARMProcessors.td
@@ -45,6 +45,8 @@ def ProcA78AE : SubtargetFeature<"cortex-a78ae", "ARMProcFamily", "CortexA78AE
"Cortex-A78AE ARM processors", []>;
def ProcA78C : SubtargetFeature<"a78c", "ARMProcFamily", "CortexA78C",
"Cortex-A78C ARM processors", []>;
+def ProcA510 : SubtargetFeature<"cortex-a510", "ARMProcFamily",
+ "CortexA510", "Cortex-A510 ARM processors", []>;
def ProcA710 : SubtargetFeature<"cortex-a710", "ARMProcFamily",
"CortexA710", "Cortex-A710 ARM processors", []>;
def ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
@@ -518,6 +520,14 @@ def : ProcNoItin<"cortex-a78c", [ARMv82a, ProcA78C,
FeatureDotProd,
FeatureFullFP16]>;
+def : ProcNoItin<"cortex-a510", [ARMv9a, ProcA710,
+ FeatureHWDivThumb,
+ FeatureHWDivARM,
+ FeatureFP16FML,
+ FeatureBF16,
+ FeatureMatMulInt8,
+ FeatureSB]>;
+
def : ProcNoItin<"cortex-a710", [ARMv9a, ProcA710,
FeatureHWDivThumb,
FeatureHWDivARM,
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 61c7fadb20aeb7..07207e29bf7d3a 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -287,6 +287,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
case CortexA78:
case CortexA78AE:
case CortexA78C:
+ case CortexA510:
case CortexA710:
case CortexR4:
case CortexR5:
diff --git a/llvm/test/CodeGen/ARM/build-attributes.ll b/llvm/test/CodeGen/ARM/build-attributes.ll
index 9220f73d94f8bf..68844aed036301 100644
--- a/llvm/test/CodeGen/ARM/build-attributes.ll
+++ b/llvm/test/CodeGen/ARM/build-attributes.ll
@@ -187,6 +187,12 @@
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=exynos-m5 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=exynos-m5 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
+; ARMv9a (AArch32)
+; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a510 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
+; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a510 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
+; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a710 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
+; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a710 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
+
; ARMv7a
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index d281c2cbd55d35..b74255c14dd0bd 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -404,6 +404,14 @@ INSTANTIATE_TEST_SUITE_P(
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC |
ARM::AEK_RAS | ARM::AEK_FP16 | ARM::AEK_DOTPROD,
"8.2-A"),
+ ARMCPUTestParams<uint64_t>("cortex-a510", "armv9-a", "neon-fp-armv8",
+ ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
+ ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
+ ARM::AEK_DSP | ARM::AEK_CRC |
+ ARM::AEK_RAS | ARM::AEK_DOTPROD |
+ ARM::AEK_FP16FML | ARM::AEK_BF16 |
+ ARM::AEK_I8MM | ARM::AEK_SB,
+ "9-A"),
ARMCPUTestParams<uint64_t>("cortex-a710", "armv9-a", "neon-fp-armv8",
ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
@@ -521,7 +529,7 @@ INSTANTIATE_TEST_SUITE_P(
"7-S")),
ARMCPUTestParams<uint64_t>::PrintToStringParamName);
-static constexpr unsigned NumARMCPUArchs = 93;
+static constexpr unsigned NumARMCPUArchs = 94;
TEST(TargetParserTest, testARMCPUArchList) {
SmallVector<StringRef, NumARMCPUArchs> List;
``````````
</details>
https://github.com/llvm/llvm-project/pull/118811
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