[clang] [compiler-rt] [llvm] [SystemZ] Add support for half (fp16) (PR #109164)

[Jonas Paulsson via cfe-commits]

JonPsson1 wrote:

Spill f16 using float instructions into 4-byte stack slots:

- Seems to work to use a RegInfoByHwMode to reset the SpillSize for FP16 to 32 bits. By using two HwMode:s, the spill size can still be 16 bits with vector support.

- Using new LE16/STE16 opcodes seems easier than extracting/inserting subregs in storeRegToStackSlot() / loadRegFromStackSlot() via FP32 regs, although that could also work.


https://github.com/llvm/llvm-project/pull/109164