[clang] [llvm] [AArch64] Implement FP8 SVE Intrinsics for narrowing conversions (PR #118124)

[via cfe-commits]

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@@ -10753,10 +10758,45 @@ class sve2_fp8_down_cvt_single<bits<2> opc, string mnemonic,
   let Inst{5} = 0b0;
   let Inst{4-0} = Zd;
   let Uses = [FPMR, FPCR];
+
+  let mayLoad  = 1;
+  let mayStore = 0;
 }
 
-multiclass sve2_fp8_down_cvt_single<bits<2> opc, string mnemonic, RegisterOperand src> {
+multiclass sve2_fp8_down_cvt_single<bits<2> opc, string mnemonic, RegisterOperand src,
+                                    ValueType ty, SDPatternOperator op> {
   def NAME : sve2_fp8_down_cvt_single<opc, mnemonic, ZPR8, src>;
+
+  def : Pat<(nxv16i8 (op ty:$Zn1, ty:$Zn2)),
+            (!cast<Instruction>(NAME) (REG_SEQUENCE ZPR2Mul2, $Zn1, zsub0, $Zn2, zsub1))>;
+}
+
+class sve2_fp8_down_cvt_single_top<bits<2> opc, string mnemonic, RegisterOperand src_ty>
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CarolineConcatto wrote:

Nothing to do here, but it is really annoying that we cannot use the same multiclass for the FCVTNT,
 because of the Zen being an input and output.
What do you think of using if like this:
!if(!eq(opc, 0b11),(ins ZPR8:$_Zd, src_ty:$Zn), (ins src_ty:$Zn))
?

https://github.com/llvm/llvm-project/pull/118124