[clang] [compiler-rt] [llvm] [SystemZ] Add support for half (fp16) (PR #109164)

[Jonas Paulsson via cfe-commits]

================
@@ -1883,6 +1931,10 @@ void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
   } else if (RC == &SystemZ::FP128BitRegClass) {
     LoadOpcode = SystemZ::LX;
     StoreOpcode = SystemZ::STX;
+  } else if (RC == &SystemZ::FP16BitRegClass ||
+             RC == &SystemZ::VR16BitRegClass) {
+    LoadOpcode = SystemZ::VL16;
----------------
JonPsson1 wrote:

I was assuming this would work, as FP16 should be a sub-registerclass of VR16 - all FP16 regs are also contained in VR16. I see in the generated file:

```
static const TargetRegisterClass *const FP16BitSuperclasses[] = {
  &SystemZ::VR16BitRegClass,
  nullptr
};
```
Given that, and that -verify-machineinstrs is used in spill-half-01.mir, it seems ok to me.

https://github.com/llvm/llvm-project/pull/109164