[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Craig Topper via cfe-commits]

================
@@ -252,9 +252,17 @@ static const char *getLDMOption(const llvm::Triple &T, const ArgList &Args) {
   case llvm::Triple::ppc64le:
     return "elf64lppc";
   case llvm::Triple::riscv32:
-    return "elf32lriscv";
-  case llvm::Triple::riscv64:
-    return "elf64lriscv";
+  case llvm::Triple::riscv64: {
+    bool IsBigEndian = false;
+    if (Arg *A = Args.getLastArg(options::OPT_mlittle_endian,
+                                 options::OPT_mbig_endian))
+      IsBigEndian = A->getOption().matches(options::OPT_mbig_endian);
+
+    if (T.getArch() == llvm::Triple::riscv32)
+      return IsBigEndian ? "elf32briscv" : "elf32lriscv";
+    else
+      return IsBigEndian ? "elf64briscv" : "elf64lriscv";
+  }
----------------
topperc wrote:

> Best as I can tell, this would make RISC-V the only architecture for which there aren't any `llvm::Triple::ArchType` members distinguishing little-endian vs big-endian? That seems like a strange precedent to set.

There had been a patch a long time ago to add riscv32be and riscv64be. Not sure if it was in github or if it got left behind in phabricator.

https://github.com/llvm/llvm-project/pull/117865