[clang] [llvm] [HLSL] Implement elementwise firstbitlow builtin (PR #116858)

[Steven Perron via cfe-commits]

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@@ -3158,6 +3172,166 @@ bool SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg,
   }
 }
 
+bool SPIRVInstructionSelector::selectFirstBitLow16(Register ResVReg,
+                                                   const SPIRVType *ResType,
+                                                   MachineInstr &I) const {
+  // OpUConvert treats the operand bits as an unsigned i16 and zero extends it
+  // to an unsigned i32. As this leaves all the least significant bits unchanged
+  // the first set bit from the LSB side doesn't change.
+  Register ExtReg = MRI->createVirtualRegister(GR.getRegClass(ResType));
+  bool Result = selectNAryOpWithSrcs(
+      ExtReg, ResType, I, {I.getOperand(2).getReg()}, SPIRV::OpUConvert);
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s-perron wrote:

The SPIR-V validator does not complain about 64-bit values in `FindILsb`: https://godbolt.org/z/e4Wh4c9fa

It does complain about 64-bit values in `FindUMsb`: https://godbolt.org/z/faaqEnzhY

I believe we are okay to simplify the code.

https://github.com/llvm/llvm-project/pull/116858