[clang] [compiler-rt] [llvm] [SystemZ] Add support for half (fp16) (PR #109164)

[Jonas Paulsson via cfe-commits]

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@@ -102,6 +102,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
     addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
   addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
   if (!useSoftFloat()) {
+    addRegisterClass(MVT::f16, &SystemZ::FP16BitRegClass);
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JonPsson1 wrote:

So far I have a few points as "todo" for vector support:
  - add a VR16 reg class
  - use VLE/VSTE for reload/spill
  - Use generated vector constants.
 It wouldn't be too hard to add this, but not sure if it's relevant given all the slow conversion function calls. On the other hand, even if it's super-slow, maybe a noticeable speedup might have some value..?

https://github.com/llvm/llvm-project/pull/109164