[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

[Petr Penzin via cfe-commits]

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@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
                                                FeatureStdExtZkn],
                                               [TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
 
+def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
+                                              NoSchedModel,
+                                              [Feature64Bit,
+                                               FeatureStdExtI,
+                                               FeatureStdExtZifencei,
+                                               FeatureStdExtZicsr,
+                                               FeatureStdExtZicntr,
+                                               FeatureStdExtZihpm,
+                                               FeatureStdExtZihintpause,
+                                               FeatureStdExtM,
+                                               FeatureStdExtA,
+                                               FeatureStdExtF,
+                                               FeatureStdExtD,
+                                               FeatureStdExtC,
+                                               FeatureStdExtV,
+                                               FeatureStdExtZvl256b,
+                                               FeatureStdExtZfh,
+                                               FeatureStdExtZvfh,
+                                               FeatureStdExtZba,
+                                               FeatureStdExtZbb,
+                                               FeatureStdExtZbs,
+                                               FeatureStdExtZicbom,
+                                               FeatureStdExtZicbop,
+                                               FeatureStdExtZicboz,
+                                               FeatureStdExtH,
+                                               FeatureStdExtZihintntl,
+                                               FeatureStdExtZfhmin,
+                                               FeatureStdExtZfa,
+                                               FeatureStdExtZkt,
+                                               FeatureStdExtZcb,
+                                               FeatureStdExtZvbb,
+                                               FeatureStdExtZvbc,
+                                               FeatureStdExtZawrs,
+                                               FeatureStdExtZvkng,
+                                               FeatureStdExtZicond,
+                                               FeatureUnalignedScalarMem,
+                                               FeatureUnalignedVectorMem,
+                                               FeatureStdExtSvnapot,
+                                               FeatureStdExtSvpbmt,
+                                               FeatureStdExtSvinval,
+                                               FeatureStdExtZfbfmin,
+                                               FeatureStdExtZvfbfmin,
+                                               FeatureStdExtZvfbfwma],
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ppenzin wrote:

Addressed.

https://github.com/llvm/llvm-project/pull/115100