[clang] [llvm] [RISCV] Add Smdbltrp and Ssdbltrp extension (PR #111837)
via cfe-commits
cfe-commits at lists.llvm.org
Thu Nov 7 08:25:59 PST 2024
https://github.com/T-Tie updated https://github.com/llvm/llvm-project/pull/111837
>From 23aec55337764fc19a6b816ca238972f705dda9a Mon Sep 17 00:00:00 2001
From: T-Tie <160845405+T-Tie at users.noreply.github.com>
Date: Thu, 10 Oct 2024 21:11:39 +0800
Subject: [PATCH 1/9] Update riscv-target-features.c double-trap
---
.../test/Preprocessor/riscv-target-features.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 05a8534ba13da1..d25f96b66a052a 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -29,6 +29,7 @@
// CHECK-NOT: __riscv_smaia {{.*$}}
// CHECK-NOT: __riscv_smcdeleg {{.*$}}
// CHECK-NOT: __riscv_smcsrind {{.*$}}
+// CHECK-NOT: __riscv_smdbltrp {{.*$}}
// CHECK-NOT: __riscv_smepmp {{.*$}}
// CHECK-NOT: __riscv_smstateen {{.*$}}
// CHECK-NOT: __riscv_ssaia {{.*$}}
@@ -37,6 +38,7 @@
// CHECK-NOT: __riscv_sscofpmf {{.*$}}
// CHECK-NOT: __riscv_sscounterenw {{.*$}}
// CHECK-NOT: __riscv_sscsrind {{.*$}}
+// CHECK-NOT: __riscv_ssdbltrp {{.*$}}
// CHECK-NOT: __riscv_ssqosid{{.*$}}
// CHECK-NOT: __riscv_ssstateen {{.*$}}
// CHECK-NOT: __riscv_ssstrict {{.*$}}
@@ -1425,6 +1427,22 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SSCSRIND-EXT %s
// CHECK-SSCSRIND-EXT: __riscv_sscsrind 1000000{{$}}
+// RUN: %clang --target=riscv32 \
+// RUN: -march=rv32ismdbltrp1p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMDBLTRP-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64ismdbltrp1p0 -E -dM %s \
+// RUN: -o | FileCheck --check-prefix=CHECK-SMDBLTRP-EXT %s
+// CHECK-SMDBLTRP-EXT: __riscv_smdbltrp 1000000{{$}}
+
+// RUN: %clang --target=riscv32 \
+// RUN: -march=rv32issdbltrp1p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SSDBLTRP-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64issdbltrp1p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SSDBLTRP-EXT %s
+// CHECK-SSDBLTRP-EXT: __riscv_ssdbltrp 1000000{{$}}
+
// RUN: %clang --target=riscv32 \
// RUN: -march=rv32i_ssqosid1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
>From 481ac24641153a117a07886184c061c09f37445f Mon Sep 17 00:00:00 2001
From: T-Tie <160845405+T-Tie at users.noreply.github.com>
Date: Thu, 10 Oct 2024 21:14:59 +0800
Subject: [PATCH 2/9] Update RISCVUsage.rst double-trap
---
llvm/docs/RISCVUsage.rst | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 5736f3807f131b..4780c20416c165 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -128,6 +128,7 @@ on support follow.
``Smaia`` Supported
``Smcdeleg`` Supported
``Smcsrind`` Supported
+ ``Smdbltrp`` Supported
``Smepmp`` Supported
``Smstateen`` Assembly Support
``Ssaia`` Supported
@@ -136,6 +137,7 @@ on support follow.
``Sscofpmf`` Assembly Support
``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Sscsrind`` Supported
+ ``Ssdbltrp`` Supported
``Ssqosid`` Assembly Support
``Ssstateen`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Ssstrict`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
>From 709c7f78d3a648929073c8d7439565faf13dbf76 Mon Sep 17 00:00:00 2001
From: T-Tie <160845405+T-Tie at users.noreply.github.com>
Date: Thu, 10 Oct 2024 21:17:46 +0800
Subject: [PATCH 3/9] Update RISCVFeatures.td double-trap
---
llvm/lib/Target/RISCV/RISCVFeatures.td | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 3d0e1dae801d39..fc93f7c3e1fea1 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -927,6 +927,13 @@ def FeatureStdExtSscsrind
: RISCVExtension<"sscsrind", 1, 0,
"'Sscsrind' (Indirect CSR Access Supervisor Level)">;
+def FeatureStdExtSmdbltrp
+ : RISCVExtension<"smdbltrp", 1, 0,
+ "'Smdbltrp' (Double Trap Machine Level)">;
+def FeatureStdExtSsdbltrp
+ : RISCVExtension<"ssdbltrp", 1, 0,
+ "'Ssdbltrp' (Double Trap Supervisor Level)">;
+
def FeatureStdExtSmepmp
: RISCVExtension<"smepmp", 1, 0,
"'Smepmp' (Enhanced Physical Memory Protection)">;
>From 3f503cebbac851cbb40ee08eb1b02cc2535a52b1 Mon Sep 17 00:00:00 2001
From: T-Tie <160845405+T-Tie at users.noreply.github.com>
Date: Thu, 10 Oct 2024 21:23:17 +0800
Subject: [PATCH 4/9] Update attributes.ll double-trap
---
llvm/test/CodeGen/RISCV/attributes.ll | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 86ce368bc1db66..b8f97ae0930a15 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -115,6 +115,8 @@
; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+smcsrind %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCSRIND %s
; RUN: llc -mtriple=riscv32 -mattr=+sscsrind %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCSRIND %s
+; RUN: llc -mtriple=riscv32 -mattr=+smdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMDBLTRP %s
+; RUN: llc -mtriple=riscv32 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV32SSDBLTRP %s
; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s
; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
@@ -258,6 +260,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+smcsrind %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCSRIND %s
; RUN: llc -mtriple=riscv64 -mattr=+sscsrind %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCSRIND %s
+; RUN: llc -mtriple=riscv64 -mattr=+smdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMDBLTRP %s
+; RUN: llc -mtriple=riscv64 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV64SSDBLTRP %s
; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s
; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
@@ -407,6 +411,8 @@
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
; RV32SMCSRIND: .attribute 5, "rv32i2p1_smcsrind1p0"
; RV32SSCSRIND: .attribute 5, "rv32i2p1_sscsrind1p0"
+; RV32SMDBLTRP: .attribute 5, "rv32i2p1_smdbltrp1p0"
+; RV32SSDBLTRP: .attribute 5, "rv32i2p1_ssdbltrp1p0"
; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
@@ -548,6 +554,8 @@
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
; RV64SMCSRIND: .attribute 5, "rv64i2p1_smcsrind1p0"
; RV64SSCSRIND: .attribute 5, "rv64i2p1_sscsrind1p0"
+; RV64SMDBLTRP: .attribute 5, "rv64i2p1_smdbltrp1p0"
+; RV64SSDBLTRP: .attribute 5, "rv64i2p1_ssdbltrp1p0"
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
>From 2c9beb296410aa6bd199ce88be6bdb0b3d109cee Mon Sep 17 00:00:00 2001
From: T-Tie <160845405+T-Tie at users.noreply.github.com>
Date: Thu, 10 Oct 2024 21:26:43 +0800
Subject: [PATCH 5/9] Update attribute-arch.s double-trap
---
llvm/test/MC/RISCV/attribute-arch.s | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 1c0b2a59d0693f..8d9d3ac7132431 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -321,6 +321,12 @@
.attribute arch, "rv32i_sscsrind1p0"
# CHECK: attribute 5, "rv32i2p1_sscsrind1p0"
+.attribute arch, "rv32i_smdbltrp1p0"
+# CHECK: attribute 5, "rv32i2p1_smdbltrp1p0"
+
+.attribute arch, "rv32i_ssdbltrp1p0"
+# CHECK: attribute 5, "rv32i2p1_ssdbltrp1p0"
+
.attribute arch, "rv32i_smcdeleg1p0"
# CHECK: attribute 5, "rv32i2p1_smcdeleg1p0"
>From 834c528db5291da3728d74ea6dd6ab1a8456a52a Mon Sep 17 00:00:00 2001
From: T-Tie <160845405+T-Tie at users.noreply.github.com>
Date: Thu, 10 Oct 2024 21:29:33 +0800
Subject: [PATCH 6/9] Update RISCVISAInfoTest.cpp double-trap
---
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 33944b64dc1577..f2e16ac0ac93fb 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1064,6 +1064,7 @@ R"(All available -march extensions for RISC-V
smaia 1.0
smcdeleg 1.0
smcsrind 1.0
+ smdbltrp 1.0
smepmp 1.0
smstateen 1.0
ssaia 1.0
@@ -1072,6 +1073,7 @@ R"(All available -march extensions for RISC-V
sscofpmf 1.0
sscounterenw 1.0
sscsrind 1.0
+ ssdbltrp 1.0
ssqosid 1.0
ssstateen 1.0
ssstrict 1.0
>From f90a7bf84d0970415b739019dc8c30d682e63272 Mon Sep 17 00:00:00 2001
From: T-Tie <160845405+T-Tie at users.noreply.github.com>
Date: Thu, 10 Oct 2024 21:34:04 +0800
Subject: [PATCH 7/9] Update ReleaseNotes.md double-trap
---
llvm/docs/ReleaseNotes.md | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index c8f5d22c15472a..4dbdbf5fe73654 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -171,6 +171,7 @@ Changes to the RISC-V Backend
* Added `Smctr` and `Ssctr` extensions.
* `-mcpu=syntacore-scr7` was added.
* The `Zacas` extension is no longer marked as experimental.
+* Added Smdbltrp, Ssdbltrp extensions to -march.
Changes to the WebAssembly Backend
----------------------------------
>From a25f112a959aae3ac9209954da4674648c2340d5 Mon Sep 17 00:00:00 2001
From: T-Tie <t_tttie at 163.com>
Date: Fri, 11 Oct 2024 13:25:04 +0800
Subject: [PATCH 8/9] Update riscv-target-features.c double-trap
---
clang/test/Preprocessor/riscv-target-features.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index d25f96b66a052a..6bd593ca027fc5 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1432,7 +1432,7 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SMDBLTRP-EXT %s
// RUN: %clang --target=riscv64 \
// RUN: -march=rv64ismdbltrp1p0 -E -dM %s \
-// RUN: -o | FileCheck --check-prefix=CHECK-SMDBLTRP-EXT %s
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMDBLTRP-EXT %s
// CHECK-SMDBLTRP-EXT: __riscv_smdbltrp 1000000{{$}}
// RUN: %clang --target=riscv32 \
>From 7a98c637d72650d062d5914788f9e55eecb9eedd Mon Sep 17 00:00:00 2001
From: T-Tie <t_tttie at 163.com>
Date: Fri, 11 Oct 2024 13:29:48 +0800
Subject: [PATCH 9/9] Update print-supported-extensions-riscv.c double-trap
---
clang/test/Driver/print-supported-extensions-riscv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index a39c1ab36b1db0..fe598991db9380 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -119,6 +119,7 @@
// CHECK-NEXT: smaia 1.0 'Smaia' (Advanced Interrupt Architecture Machine Level)
// CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter Delegation Machine Level)
// CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR Access Machine Level)
+// CHECK-NEXT: smdbltrp 1.0 'Smdbltrp' (Double Trap Machine Level)
// CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection)
// CHECK-NEXT: smstateen 1.0 'Smstateen' (Machine-mode view of the state-enable extension)
// CHECK-NEXT: ssaia 1.0 'Ssaia' (Advanced Interrupt Architecture Supervisor Level)
@@ -127,6 +128,7 @@
// CHECK-NEXT: sscofpmf 1.0 'Sscofpmf' (Count Overflow and Mode-Based Filtering)
// CHECK-NEXT: sscounterenw 1.0 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)
// CHECK-NEXT: sscsrind 1.0 'Sscsrind' (Indirect CSR Access Supervisor Level)
+// CHECK-NEXT: ssdbltrp 1.0 'Ssdbltrp' (Double Trap Supervisor Level)
// CHECK-NEXT: ssqosid 1.0 'Ssqosid' (Quality-of-Service (QoS) Identifiers)
// CHECK-NEXT: ssstateen 1.0 'Ssstateen' (Supervisor-mode view of the state-enable extension)
// CHECK-NEXT: ssstrict 1.0 'Ssstrict' (No non-conforming extensions are present)
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