[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

[Luke Lau via cfe-commits]

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@@ -407,6 +407,53 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
                                                FeatureStdExtZkn],
                                               [TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
 
+def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
+                                                 NoSchedModel,
+                                                 [Feature64Bit,
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lukel97 wrote:

You can include all the RVA23U64 features with a !listconcat, similar to what the other processors have done with RVA22U64

https://github.com/llvm/llvm-project/pull/115100