================
@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
FeatureStdExtZkn],
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
+def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
+ NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtI,
+ FeatureStdExtZifencei,
+ FeatureStdExtZicsr,
+ FeatureStdExtZicntr,
+ FeatureStdExtZihpm,
+ FeatureStdExtZihintpause,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtV,
+ FeatureStdExtZvl256b,
+ FeatureStdExtZfh,
+ FeatureStdExtZvfh,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs,
+ FeatureStdExtZicbom,
+ FeatureStdExtZicbop,
+ FeatureStdExtZicboz,
+ FeatureStdExtH,
+ FeatureStdExtZihintntl,
+ FeatureStdExtZfhmin,
+ FeatureStdExtZfa,
+ FeatureStdExtZkt,
+ FeatureStdExtZcb,
+ FeatureStdExtZvbb,
+ FeatureStdExtZvbc,
+ FeatureStdExtZawrs,
+ FeatureStdExtZvkng,
+ FeatureStdExtZicond,
+ FeatureUnalignedScalarMem,
+ FeatureUnalignedVectorMem,
+ FeatureStdExtSvnapot,
+ FeatureStdExtSvpbmt,
+ FeatureStdExtSvinval,
+ FeatureStdExtZfbfmin,
+ FeatureStdExtZvfbfmin,
+ FeatureStdExtZvfbfwma],
----------------
ppenzin wrote:
Zimop addressed, need to double check the rest, there might be more missing.
https://github.com/llvm/llvm-project/pull/115100