[clang] [llvm] [RISCV] Add TT-Ascalon-d8 processor (PR #115100)

[Michael Maitland via cfe-commits]

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@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
                                                FeatureStdExtZkn],
                                               [TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
 
+def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
+                                              NoSchedModel,
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michaelmaitland wrote:

I he means NoSchedModel needs to be indented more.

https://github.com/llvm/llvm-project/pull/115100