[clang] [llvm] [RISCV] Inline Assembly Support for GPR Pairs ('Pr') (PR #112983)

[Sam Elliott via cfe-commits]

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@@ -2224,6 +2231,17 @@ bool RISCVTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
   return Index == 0 || Index == ResElts;
 }
 
+EVT RISCVTargetLowering::getAsmOperandValueType(const DataLayout &DL, Type *Ty,
+                                                bool AllowUnknown) const {
+  if (!Subtarget.is64Bit() && Ty->isIntegerTy(64))
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lenary wrote:

This file tends to mostly use `Subtarget.is64Bit()` rather than the `isRV64`/`isRV32`, which is what I followed here. This might get a lot more simple if I move to trying `MVT::Other` though.

https://github.com/llvm/llvm-project/pull/112983