[clang] [llvm] [RISCV] Mark the RVA23S64 and RVA23U64 profiles as non-experimental (PR #113826)
Alex Bradbury via cfe-commits
cfe-commits at lists.llvm.org
Mon Oct 28 05:56:30 PDT 2024
https://github.com/asb updated https://github.com/llvm/llvm-project/pull/113826
>From 9bba67ede7450699bfa095c69e24f052a8ef36c7 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb at igalia.com>
Date: Sun, 27 Oct 2024 17:54:47 +0000
Subject: [PATCH] [RISCV] Mark the RVA23S64 and RVA23U64 profiles as
non-experimental
All of the extensions used by these profile are themselves
non-experimental, and RVA23 was just ratified
<https://riscv.org/announcements/2024/10/risc-v-announces-ratification-of-the-rva23-profile-standard/>.
<https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc>
We lack a way of expressing `Ss1p13` (supervisor architecture 1.13), but
this is a problem we have for RVA22 (Ss1p12) and RVA20 (Ss1p11) so I
don't feel it's a blocker.
---
clang/test/Driver/print-supported-extensions-riscv.c | 4 ++--
clang/test/Driver/riscv-profiles.c | 10 +++++-----
llvm/docs/RISCVUsage.rst | 4 ++--
llvm/docs/ReleaseNotes.md | 1 +
llvm/lib/Target/RISCV/RISCVProfiles.td | 4 ++--
llvm/test/CodeGen/RISCV/attributes.ll | 4 ++--
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 8 ++++----
7 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 4d93144724dffb..e39847b9c31a8e 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -191,12 +191,12 @@
// CHECK-NEXT: rva20u64
// CHECK-NEXT: rva22s64
// CHECK-NEXT: rva22u64
+// CHECK-NEXT: rva23s64
+// CHECK-NEXT: rva23u64
// CHECK-NEXT: rvi20u32
// CHECK-NEXT: rvi20u64
// CHECK-EMPTY:
// CHECK-NEXT: Experimental Profiles
-// CHECK-NEXT: rva23s64
-// CHECK-NEXT: rva23u64
// CHECK-NEXT: rvb23s64
// CHECK-NEXT: rvb23u64
// CHECK-NEXT: rvm23u32
diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c
index 42e23cf57c880f..d85ac8baf4edd9 100644
--- a/clang/test/Driver/riscv-profiles.c
+++ b/clang/test/Driver/riscv-profiles.c
@@ -111,7 +111,7 @@
// RVA22S64: "-target-feature" "+svinval"
// RVA22S64: "-target-feature" "+svpbmt"
-// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23u64 -menable-experimental-extensions \
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23u64 \
// RUN: | FileCheck -check-prefix=RVA23U64 %s
// RVA23U64: "-target-feature" "+m"
// RVA23U64: "-target-feature" "+a"
@@ -148,7 +148,7 @@
// RVA23U64: "-target-feature" "+zvfhmin"
// RVA23U64: "-target-feature" "+zvkt"
-// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23s64 -menable-experimental-extensions \
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23s64 \
// RUN: | FileCheck -check-prefix=RVA23S64 %s
// RVA23S64: "-target-feature" "+m"
// RVA23S64: "-target-feature" "+a"
@@ -323,6 +323,6 @@
// RUN: not %clang --target=riscv64 -### -c %s 2>&1 -march=rva22u64zfa | FileCheck -check-prefix=INVALID-ADDITIONAL %s
// INVALID-ADDITIONAL: error: invalid arch name 'rva22u64zfa', additional extensions must be after separator '_'
-// RUN: not %clang --target=riscv64 -### -c %s 2>&1 -march=rva23u64 | FileCheck -check-prefix=EXPERIMENTAL-NOFLAG %s
-// EXPERIMENTAL-NOFLAG: error: invalid arch name 'rva23u64'
-// EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions' for profile 'rva23u64'
+// RUN: not %clang --target=riscv32 -### -c %s 2>&1 -march=rvm23u32 | FileCheck -check-prefix=EXPERIMENTAL-NOFLAG %s
+// EXPERIMENTAL-NOFLAG: error: invalid arch name 'rvm23u32'
+// EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions' for profile 'rvm23u32'
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index dae6f7c46cc48c..04f2c357766d44 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -82,6 +82,8 @@ ISA naming string. Currently supported profiles:
* ``rva20s64``
* ``rva22u64``
* ``rva22s64``
+* ``rva23u64``
+* ``rva23s64``
Note that you can also append additional extension names to be enabled, e.g.
``rva20u64_zicond`` will enable the ``zicond`` extension in addition to those
@@ -91,8 +93,6 @@ Profiles that are not yet ratified cannot be used unless
``-menable-experimental-extensions`` (or equivalent for other tools) is
specified. This applies to the following profiles:
-* ``rva23u64``
-* ``rva23s64``
* ``rvb23u64``
* ``rvb23s64``
* ``rvm23u32``
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 22a32d110855d5..ac7a795daf791a 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -184,6 +184,7 @@ Changes to the RISC-V Backend
* The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions
are no longer marked as experimental.
* The `Sha` extension is now supported.
+* The RVA23U64 and RVA23S64 profiles are no longer marked as experimental.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVProfiles.td b/llvm/lib/Target/RISCV/RISCVProfiles.td
index 78c076fdb0b26e..ea0fe08abd7a14 100644
--- a/llvm/lib/Target/RISCV/RISCVProfiles.td
+++ b/llvm/lib/Target/RISCV/RISCVProfiles.td
@@ -161,8 +161,8 @@ def RVA20U64 : RISCVProfile<"rva20u64", RVA20U64Features>;
def RVA20S64 : RISCVProfile<"rva20s64", RVA20S64Features>;
def RVA22U64 : RISCVProfile<"rva22u64", RVA22U64Features>;
def RVA22S64 : RISCVProfile<"rva22s64", RVA22S64Features>;
-def RVA23U64 : RISCVExperimentalProfile<"rva23u64", RVA23U64Features>;
-def RVA23S64 : RISCVExperimentalProfile<"rva23s64", RVA23S64Features>;
+def RVA23U64 : RISCVProfile<"rva23u64", RVA23U64Features>;
+def RVA23S64 : RISCVProfile<"rva23s64", RVA23S64Features>;
def RVB23U64 : RISCVExperimentalProfile<"rvb23u64", RVB23U64Features>;
def RVB23S64 : RISCVExperimentalProfile<"rvb23s64", RVB23S64Features>;
def RVM23U32 : RISCVExperimentalProfile<"rvm23u32", RVM23U32Features>;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index e5b308a172661c..2545c7075e4cf5 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -291,8 +291,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+rva20s64 %s -o - | FileCheck --check-prefix=RVA20S64 %s
; RUN: llc -mtriple=riscv64 -mattr=+rva22u64 %s -o - | FileCheck --check-prefix=RVA22U64 %s
; RUN: llc -mtriple=riscv64 -mattr=+rva22s64 %s -o - | FileCheck --check-prefix=RVA22S64 %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-rva23u64 %s -o - | FileCheck --check-prefix=RVA23U64 %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-rva23s64 %s -o - | FileCheck --check-prefix=RVA23S64 %s
+; RUN: llc -mtriple=riscv64 -mattr=+rva23u64 %s -o - | FileCheck --check-prefix=RVA23U64 %s
+; RUN: llc -mtriple=riscv64 -mattr=+rva23s64 %s -o - | FileCheck --check-prefix=RVA23S64 %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-rvb23u64 %s -o - | FileCheck --check-prefix=RVB23U64 %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-rvb23s64 %s -o - | FileCheck --check-prefix=RVB23S64 %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-rvm23u32 %s -o - | FileCheck --check-prefix=RVM23U32 %s
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 30b5f3ce3cb084..48792ad0265fc4 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -774,8 +774,8 @@ TEST(ParseArchString,
TEST(ParseArchString,
RejectsExperimentalProfilesIfEnableExperimentalExtensionsNotSet) {
EXPECT_EQ(
- toString(RISCVISAInfo::parseArchString("rva23u64", false).takeError()),
- "requires '-menable-experimental-extensions' for profile 'rva23u64'");
+ toString(RISCVISAInfo::parseArchString("rvm23u32", false).takeError()),
+ "requires '-menable-experimental-extensions' for profile 'rvm23u32'");
}
TEST(ToFeatures, IIsDroppedAndExperimentalExtensionsArePrefixed) {
@@ -1136,12 +1136,12 @@ Supported Profiles
rva20u64
rva22s64
rva22u64
+ rva23s64
+ rva23u64
rvi20u32
rvi20u64
Experimental Profiles
- rva23s64
- rva23u64
rvb23s64
rvb23u64
rvm23u32
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