[clang] [llvm] [RISCV] Add the Sha extension (PR #113820)
Alex Bradbury via cfe-commits
cfe-commits at lists.llvm.org
Sun Oct 27 08:55:28 PDT 2024
https://github.com/asb created https://github.com/llvm/llvm-project/pull/113820
This was introduced in the now-ratified RVA23 profile (and also added to the RVA22 text) as a simple way of referring to H plus the set of supervisor extensions required by RVA23. https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc
This patch simply defines the extension. The next patch will adjust the RVA23 profile to use it, and at that point I think we will be ready to mark RVA23 as non-experimental.
Note that I haven't made it so if you enable all extensions that constitute Sha, Sha is implied. Per #76893 (adding 'B'), the concern is making this implication might break older external assemblers. Perhaps this is less of a concern given the relative frequency of `-march=${foo}_zba_zbb_zbs` vs the collection of H extensions. If we did want to add that implication, we'd probably want to add it in a separate patch so it can be easily reverted if found to cause problems.
>From 0a6e4734def4cb8a3a601c0f4a4f4d5cdea3c990 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb at igalia.com>
Date: Sun, 27 Oct 2024 15:40:21 +0000
Subject: [PATCH] [RISCV] Add the Sha extension
This was introduced in the now-ratified RVA23 profile (and also added to
the RVA22 text) as a simple way of referring to H plus the set of
supervisor extensions required by RVA23.
---
clang/test/Driver/print-supported-extensions-riscv.c | 1 +
clang/test/Preprocessor/riscv-target-features.c | 9 +++++++++
llvm/docs/RISCVUsage.rst | 1 +
llvm/docs/ReleaseNotes.md | 1 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 7 +++++++
llvm/test/CodeGen/RISCV/attributes.ll | 4 ++++
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 1 +
7 files changed, 24 insertions(+)
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 342d6e921a5a83..fc8a9c04667b6b 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -110,6 +110,7 @@
// CHECK-NEXT: zvl8192b 1.0 'Zvl' (Minimum Vector Length) 8192
// CHECK-NEXT: zhinx 1.0 'Zhinx' (Half Float in Integer)
// CHECK-NEXT: zhinxmin 1.0 'Zhinxmin' (Half Float in Integer Minimal)
+// CHECK-NEXT: sha 1.0 'Sha' (Augmented Hypervisor)
// CHECK-NEXT: shcounterenw 1.0 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero)
// CHECK-NEXT: shgatpa 1.0 'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)
// CHECK-NEXT: shtvala 1.0 'Shtvala' (htval provides all needed values)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 98ad564d2b8408..6e586714af84d3 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -20,6 +20,7 @@
// CHECK-NOT: __riscv_m {{.*$}}
// CHECK-NOT: __riscv_mul {{.*$}}
// CHECK-NOT: __riscv_muldiv {{.*$}}
+// CHECK-NOT: __riscv_sha {{.*$}}
// CHECK-NOT: __riscv_shcounterenw {{.*$}}
// CHECK-NOT: __riscv_shgatpa {{.*$}}
// CHECK-NOT: __riscv_shtvala {{.*$}}
@@ -323,6 +324,14 @@
// CHECK-M-EXT: __riscv_mul 1
// CHECK-M-EXT: __riscv_muldiv 1
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32isha -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SHCOUNTERENW-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64isha -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SHCOUNTERENW-EXT %s
+// CHECK-SHA-EXT: __riscv_sha 1000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32ishcounterenw -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SHCOUNTERENW-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index ab58cdaa1b2f95..6075a2289d473d 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -119,6 +119,7 @@ on support follow.
``E`` Supported (`See note <#riscv-rve-note>`__)
``H`` Assembly Support
``M`` Supported
+ ``Sha`` Supported
``Shcounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Shgatpa`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Shtvala`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index e3d93f0dfd0ec5..6ee312aee8c53c 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -176,6 +176,7 @@ Changes to the RISC-V Backend
* The `Zacas` extension is no longer marked as experimental.
* The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions
are no longer marked as experimental.
+* The `Sha` extension is now supported.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 778df542022f22..559f0e5950eddd 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1029,6 +1029,13 @@ def FeatureStdExtSvpbmt
: RISCVExtension<"svpbmt", 1, 0,
"'Svpbmt' (Page-Based Memory Types)">;
+def FeatureStdExtSha
+ : RISCVExtension<"sha", 1, 0,
+ "'Sha' (Augmented Hypervisor)",
+ [FeatureStdExtH, FeatureStdExtSsstateen, FeatureStdExtShcounterenw,
+ FeatureStdExtShvstvala, FeatureStdExtShtvala, FeatureStdExtShvstvecd,
+ FeatureStdExtShvsatpa, FeatureStdExtShgatpa]>;
+
// Pointer Masking extensions
// A supervisor-level extension that provides pointer masking for the next lower
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 9be9ddd05ee290..4cc9ef2ea0d7ff 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -39,6 +39,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+zicbom %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOM %s
; RUN: llc -mtriple=riscv32 -mattr=+zicboz %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOZ %s
; RUN: llc -mtriple=riscv32 -mattr=+zicbop %s -o - | FileCheck --check-prefixes=CHECK,RV32ZICBOP %s
+; RUN: llc -mtriple=riscv32 -mattr=+sha %s -o - | FileCheck --check-prefixes=CHECK,RV32SHA %s
; RUN: llc -mtriple=riscv32 -mattr=+shcounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV32SHCOUNTERENW %s
; RUN: llc -mtriple=riscv32 -mattr=+shgatpa %s -o - | FileCheck --check-prefixes=CHECK,RV32SHGATPA %s
; RUN: llc -mtriple=riscv32 -mattr=+shvsatpa %s -o - | FileCheck --check-prefixes=CHECK,RV32SHVSATPA %s
@@ -178,6 +179,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zicbom %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOM %s
; RUN: llc -mtriple=riscv64 -mattr=+zicboz %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOZ %s
; RUN: llc -mtriple=riscv64 -mattr=+zicbop %s -o - | FileCheck --check-prefixes=CHECK,RV64ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+sha %s -o - | FileCheck --check-prefixes=CHECK,RV64SHA %s
; RUN: llc -mtriple=riscv64 -mattr=+shcounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV64SHCOUNTERENW %s
; RUN: llc -mtriple=riscv64 -mattr=+shgatpa %s -o - | FileCheck --check-prefixes=CHECK,RV64SHGATPA %s
; RUN: llc -mtriple=riscv64 -mattr=+shvsatpa %s -o - | FileCheck --check-prefixes=CHECK,RV64SHVSATPA %s
@@ -333,6 +335,7 @@
; RV32ZICBOM: .attribute 5, "rv32i2p1_zicbom1p0"
; RV32ZICBOZ: .attribute 5, "rv32i2p1_zicboz1p0"
; RV32ZICBOP: .attribute 5, "rv32i2p1_zicbop1p0"
+; RV32SHA: .attribute 5, "rv32i2p1_h1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssstateen1p0"
; RV32SHCOUNTERENW: .attribute 5, "rv32i2p1_shcounterenw1p0"
; RV32SHGATPA: .attribute 5, "rv32i2p1_shgatpa1p0"
; RV32SHVSATPA: .attribute 5, "rv32i2p1_shvsatpa1p0"
@@ -474,6 +477,7 @@
; RV64ZAMA16B: .attribute 5, "rv64i2p1_zama16b1p0"
; RV64ZAWRS: .attribute 5, "rv64i2p1_zawrs1p0"
; RV64ZICBOP: .attribute 5, "rv64i2p1_zicbop1p0"
+; RV64SHA: .attribute 5, "rv64i2p1_h1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssstateen1p0"
; RV64SHCOUNTERENW: .attribute 5, "rv64i2p1_shcounterenw1p0"
; RV64SHGATPA: .attribute 5, "rv64i2p1_shgatpa1p0"
; RV64SHVSATPA: .attribute 5, "rv64i2p1_shvsatpa1p0"
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 2e9c548ae872f3..e402b1a40de34d 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1055,6 +1055,7 @@ R"(All available -march extensions for RISC-V
zvl8192b 1.0
zhinx 1.0
zhinxmin 1.0
+ sha 1.0
shcounterenw 1.0
shgatpa 1.0
shtvala 1.0
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