[clang] [llvm] [BPF] Add load-acquire and store-release instructions under -mcpu=v4 (PR #108636)

[Peilin Ye via cfe-commits]

peilin-ye wrote:

Another problem is, right now, if I do this:
```diff
--- a/llvm/lib/Target/BPF/BPFInstrInfo.td
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.td
@@ -1343,11 +1343,11 @@ let Predicates = [BPFHasALU32] in {
 
   let Predicates = [BPFHasLoadAcquire] in {
     foreach P = [[relaxed_load<atomic_load_32>, LDWACQ32],
-                 [relaxed_load<atomic_load_az_16>, LDHACQ32],
-                 [relaxed_load<atomic_load_az_8>, LDBACQ32],
+                 [relaxed_load<atomic_load_zext_16>, LDHACQ32],
+                 [relaxed_load<atomic_load_zext_8>, LDBACQ32],
                  [acquiring_load<atomic_load_32>, LDWACQ32],
-                 [acquiring_load<atomic_load_az_16>, LDHACQ32],
-                 [acquiring_load<atomic_load_az_8>, LDBACQ32],
+                 [acquiring_load<atomic_load_zext_16>, LDHACQ32],
+                 [acquiring_load<atomic_load_zext_8>, LDBACQ32],
                 ] in {
       def : Pat<(P[0] ADDRri:$addr), (P[1] ADDRri:$addr)>;
     }
```
The above toy program no longer compiles:
```
fatal error: error in backend: Cannot select: t9: i32,ch = AtomicLoad<(load acquire (s8) from %ir.ptr), zext from i8> t0, t2, demo.bpf.c:3:12
  t2: i64,ch = CopyFromReg t0, Register:i64 %0
    t1: i64 = Register %0
In function: bar
...
```
This is because commit 1ee6ce9bad4d ("GlobalISel: Allow forming atomic/volatile G_ZEXTLOAD") did this in `llvm/utils/TableGen/CodeGenDAGPatterns.cpp`:
```diff
@@ -1105,6 +1109,10 @@ std::string TreePredicateFn::getPredCode() const {
     Code += "if (isReleaseOrStronger(cast<AtomicSDNode>(N)->getMergedOrdering())) "
             "return false;\n";
 
+  // TODO: Handle atomic sextload/zextload normally when ATOMIC_LOAD is removed.
+  if (isAtomic() && (isZeroExtLoad() || isSignExtLoad()))
+    Code += "return false;\n";
+
   if (isLoad() || isStore()) {
     StringRef SDNodeName = isLoad() ? "LoadSDNode" : "StoreSDNode";
```
As a result, nothing would match `atomic_load_zext_{8,16}` because these patterns are **explicitly** marked as `zext` (`isZeroExtLoad()`).
- - -
If our plan is to:
 - generate `zext` BPF 8- and 16-bit load-acquire for `atomic_load_zext_{8,16}`
 - (if needed) generate `sext` BPF 8- and 16-bit load-acquire for `atomic_load_sext_{8,16}`

Then this problem needs to be solved, and I can include the author of 1ee6ce9bad4d into discussion.

https://github.com/llvm/llvm-project/pull/108636