[clang] [llvm] [HLSL] implement elementwise firstbithigh hlsl builtin (PR #111082)

[Farzon Lotfi via cfe-commits]

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@@ -424,7 +424,7 @@ Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
     LLT LLTy = LLT::scalar(64);
     Register SpvVecConst =
         CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
-    CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::iIDRegClass);
+    CurMF->getRegInfo().setRegClass(SpvVecConst, getRegClass(SpvType));
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farzonl wrote:

I imagine there are other places in the SPIRV backend that might require a fix like this and want to give a future person a hint at how to fix it.

Alternatively create a second issue which refrences the problem you found. Add it to the pr description as fixed by this pr. drop a link to the issue in this comment section. That way if anyone searches github issues for something similar to this they will find your issue and see how you fixed it.

https://github.com/llvm/llvm-project/pull/111082