[clang] [llvm] [LLVM] Trim intrinsics (PR #112791)
Rahul Joshi via cfe-commits
cfe-commits at lists.llvm.org
Mon Oct 21 14:20:50 PDT 2024
https://github.com/jurahul updated https://github.com/llvm/llvm-project/pull/112791
>From 99b1f61a780427488ee7a2df6f44c1c7fcace6ca Mon Sep 17 00:00:00 2001
From: Rahul Joshi <rjoshi at nvidia.com>
Date: Wed, 16 Oct 2024 14:00:52 -0700
Subject: [PATCH] [LLVM] Trim intrinsics
---
clang/test/SemaHLSL/GlobalConstructors.hlsl | 1 +
llvm/CMakeLists.txt | 35 +++
.../GlobalISel/GIMatchTableExecutorImpl.h | 4 +-
llvm/include/llvm/IR/CMakeLists.txt | 40 +--
llvm/include/llvm/IR/Intrinsics.h | 13 +
llvm/include/llvm/Support/IntrinsicID.h | 59 +++++
llvm/lib/CodeGen/MachineOperand.cpp | 2 +-
llvm/lib/CodeGen/MachineVerifier.cpp | 4 +-
.../SelectionDAG/SelectionDAGDumper.cpp | 2 +-
.../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 2 +-
llvm/lib/IR/Core.cpp | 3 +-
llvm/lib/IR/Intrinsics.cpp | 133 ++++++++--
.../Target/AArch64/AArch64ISelLowering.cpp | 2 +-
llvm/lib/Target/AArch64/CMakeLists.txt | 8 +-
llvm/lib/Target/AMDGPU/CMakeLists.txt | 14 +-
llvm/lib/Target/ARC/CMakeLists.txt | 4 +-
llvm/lib/Target/ARM/CMakeLists.txt | 8 +-
llvm/lib/Target/AVR/CMakeLists.txt | 4 +-
llvm/lib/Target/BPF/CMakeLists.txt | 6 +-
llvm/lib/Target/CSKY/CMakeLists.txt | 4 +-
llvm/lib/Target/DirectX/CMakeLists.txt | 3 +-
llvm/lib/Target/Hexagon/CMakeLists.txt | 4 +-
llvm/lib/Target/Lanai/CMakeLists.txt | 4 +-
llvm/lib/Target/LoongArch/CMakeLists.txt | 4 +-
llvm/lib/Target/M68k/CMakeLists.txt | 6 +-
llvm/lib/Target/MSP430/CMakeLists.txt | 4 +-
llvm/lib/Target/Mips/CMakeLists.txt | 8 +-
llvm/lib/Target/NVPTX/CMakeLists.txt | 4 +-
llvm/lib/Target/PowerPC/CMakeLists.txt | 8 +-
llvm/lib/Target/RISCV/CMakeLists.txt | 6 +-
llvm/lib/Target/SPIRV/CMakeLists.txt | 4 +-
llvm/lib/Target/Sparc/CMakeLists.txt | 4 +-
llvm/lib/Target/SystemZ/CMakeLists.txt | 4 +-
llvm/lib/Target/VE/CMakeLists.txt | 4 +-
llvm/lib/Target/WebAssembly/CMakeLists.txt | 6 +-
llvm/lib/Target/X86/CMakeLists.txt | 9 +-
llvm/lib/Target/X86/X86IntrinsicsInfo.h | 3 +-
llvm/lib/Target/XCore/CMakeLists.txt | 4 +-
llvm/lib/Target/Xtensa/CMakeLists.txt | 4 +-
.../Analysis/CtxProfAnalysis/full-cycle.ll | 1 +
.../DXILResource/buffer-frombinding.ll | 1 +
llvm/test/Analysis/MemorySSA/pr36883.ll | 1 +
.../Analysis/ValueTracking/aarch64.irg.ll | 1 +
.../ValueTracking/knownbits-x86-hadd-hsub.ll | 1 +
.../amdgpu-image-atomic-attributes.ll | 1 +
.../Assembler/autoupgrade-wasm-intrinsics.ll | 1 +
.../opaque-ptr-intrinsic-remangling.ll | 1 +
llvm/test/Bitcode/aarch64-addp-upgrade.ll | 1 +
llvm/test/Bitcode/aarch64-bf16-upgrade.ll | 1 +
llvm/test/Bitcode/arm-bf16-upgrade.ll | 1 +
llvm/test/Bitcode/arm-intrinsics.ll | 1 +
.../intrinsics-struct-upgrade-attributes.ll | 1 +
.../test/Bitcode/intrinsics-struct-upgrade.ll | 1 +
llvm/test/Bitcode/ptest-new.ll | 1 +
llvm/test/Bitcode/upgrade-aarch64-ldstxr.ll | 1 +
.../Bitcode/upgrade-aarch64-sve-intrinsics.ll | 1 +
llvm/test/CodeGen/AArch64/arm64-vshift.ll | 1 +
.../MemorySanitizer/AArch64/arm64-vshift.ll | 1 +
.../MemorySanitizer/AArch64/neon_vst.ll | 1 +
.../MemorySanitizer/AArch64/neon_vst_float.ll | 1 +
.../MemorySanitizer/AArch64/neon_vst_lane.ll | 1 +
.../AArch64/neon_vst_origins.ll | 1 +
llvm/test/TableGen/ContextlessPredicates.td | 4 +-
llvm/test/TableGen/DAGDefaultOps.td | 2 +-
llvm/test/TableGen/DefaultOpsGlobalISel.td | 2 +-
llvm/test/TableGen/DuplicateFieldValues.td | 2 +-
llvm/test/TableGen/FastISelEmitter.td | 2 +-
.../match-table-intrinsics.td | 14 +-
.../TableGen/GlobalISelEmitter-PR39045.td | 2 +-
.../GlobalISelEmitter-SDNodeXForm-timm.td | 6 +-
.../GlobalISelEmitter-atomic_store.td | 2 +-
.../TableGen/GlobalISelEmitter-frameindex.td | 2 +-
.../GlobalISelEmitter-immAllZeroOne.td | 4 +-
...lobalISelEmitter-immarg-literal-pattern.td | 6 +-
.../GlobalISelEmitter-input-discard.td | 4 +-
...obalISelEmitter-multiple-output-discard.td | 2 +-
.../GlobalISelEmitter-multiple-output.td | 2 +-
.../GlobalISelEmitter-nested-subregs.td | 2 +-
...GlobalISelEmitter-notype-output-pattern.td | 2 +-
.../GlobalISelEmitter-output-discard.td | 2 +-
llvm/test/TableGen/GlobalISelEmitter-setcc.td | 2 +-
.../TableGen/GlobalISelEmitter-zero-instr.td | 2 +-
.../TableGen/GlobalISelEmitter-zero-reg.td | 2 +-
llvm/test/TableGen/GlobalISelEmitter.td | 14 +-
.../GlobalISelEmitterCustomPredicate.td | 2 +-
llvm/test/TableGen/GlobalISelEmitterFlags.td | 2 +-
.../test/TableGen/GlobalISelEmitterHwModes.td | 2 +-
.../GlobalISelEmitterMatchTableOptimizer.td | 2 +-
...rMatchTableOptimizerSameOperand-invalid.td | 2 +-
...elEmitterMatchTableOptimizerSameOperand.td | 2 +-
.../GlobalISelEmitterOverloadedPtr.td | 4 +-
.../TableGen/GlobalISelEmitterRegSequence.td | 2 +-
.../GlobalISelEmitterSkippedPatterns.td | 4 +-
llvm/test/TableGen/GlobalISelEmitterSubreg.td | 2 +-
.../TableGen/GlobalISelEmitterVariadic.td | 2 +-
llvm/test/TableGen/HasNoUse.td | 4 +-
llvm/test/TableGen/RelTest.td | 2 +-
llvm/test/TableGen/address-space-patfrags.td | 4 +-
llvm/test/TableGen/dag-isel-complexpattern.td | 2 +-
.../TableGen/dag-isel-regclass-emit-enum.td | 2 +-
llvm/test/TableGen/dag-isel-res-order.td | 2 +-
llvm/test/TableGen/dag-isel-subregs.td | 2 +-
llvm/test/TableGen/def-multiple-operands.td | 2 +-
.../TableGen/get-operand-type-no-expand.td | 4 +-
llvm/test/TableGen/get-operand-type.td | 2 +-
llvm/test/TableGen/gisel-physreg-input.td | 2 +-
llvm/test/TableGen/immarg-predicated.td | 4 +-
llvm/test/TableGen/immarg.td | 4 +-
llvm/test/TableGen/intrinsic-attrs.td | 2 +-
.../test/TableGen/intrinsic-duplicate-name.td | 2 +-
llvm/test/TableGen/intrinsic-long-name.td | 2 +-
.../TableGen/intrinsic-overload-conflict.td | 6 +-
llvm/test/TableGen/intrinsic-prefix-error.td | 2 +-
llvm/test/TableGen/intrinsic-struct.td | 8 +-
...ic-target-prefix-for-target-independent.td | 2 +-
llvm/test/TableGen/intrinsic-varargs.td | 2 +-
.../TableGen/invalid-type-cast-patfrags.td | 8 +-
.../TableGen/multiple-type-casts-patfrags.td | 4 +-
llvm/test/TableGen/predicate-patfags.td | 12 +-
llvm/test/TableGen/simplify-patfrag.td | 4 +-
llvm/unittests/IR/VPIntrinsicTest.cpp | 15 +-
.../TableGen/Basic/CodeGenIntrinsics.cpp | 208 ++++++++++++----
llvm/utils/TableGen/Basic/CodeGenIntrinsics.h | 38 ++-
.../TableGen/Common/CodeGenDAGPatterns.cpp | 2 +-
.../TableGen/Common/CodeGenDAGPatterns.h | 14 +-
.../GlobalISel/GlobalISelMatchTable.cpp | 4 +-
llvm/utils/TableGen/IntrinsicEmitter.cpp | 235 +++++++++++-------
.../utils/TableGen/SearchableTableEmitter.cpp | 2 +-
128 files changed, 783 insertions(+), 397 deletions(-)
create mode 100644 llvm/include/llvm/Support/IntrinsicID.h
diff --git a/clang/test/SemaHLSL/GlobalConstructors.hlsl b/clang/test/SemaHLSL/GlobalConstructors.hlsl
index ddd09422d74852..dc12053b178316 100644
--- a/clang/test/SemaHLSL/GlobalConstructors.hlsl
+++ b/clang/test/SemaHLSL/GlobalConstructors.hlsl
@@ -1,3 +1,4 @@
+// REQUIRES: directx-registered-target
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -fsyntax-only %s -verify
int i;
diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt
index cde4a999ea2e74..1c153ce83c8c38 100644
--- a/llvm/CMakeLists.txt
+++ b/llvm/CMakeLists.txt
@@ -625,6 +625,41 @@ set(LLVM_TARGETS_TO_BUILD
${LLVM_EXPERIMENTAL_TARGETS_TO_BUILD})
list(REMOVE_DUPLICATES LLVM_TARGETS_TO_BUILD)
+#set(ENABLED_INTRINSIC_TARGETS ${LLVM_ALL_TARGETS} ${LLVM_ALL_EXPERIMENTAL_TARGETS})
+set(ENABLED_INTRINSIC_TARGETS ${LLVM_TARGETS_TO_BUILD})
+
+# Build a list of intrinsic target prefixes for targets that have been enabled.
+string(REPLACE ";" "," ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(CONCAT ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}" ",")
+string(REPLACE "AMDGPU" "R600,AMDGCN" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "PowerPC" "ppc" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "SPIRV" "spv" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "NVPTX" "nvvm" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "DirectX" "dx" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "WebAssembly" "wasm" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "SystemZ" "s390" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+# Remove target prefixes that do not have any intrinscs defined for them.
+string(REPLACE "M68k," "" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "ARC," "" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "AVR," "" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "CSKY," "" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "Lanai," "" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "Sparc," "" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "MSP430," "" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+string(REPLACE "Xtensa," "" ENABLED_INTRINSIC_TARGETS "${ENABLED_INTRINSIC_TARGETS}")
+
+# strip the last ,
+string(LENGTH "${ENABLED_INTRINSIC_TARGETS}" enabled_len)
+math(EXPR enabled_len "${enabled_len} - 1")
+string(SUBSTRING "${ENABLED_INTRINSIC_TARGETS}" 0 "${enabled_len}" ENABLED_INTRINSIC_TARGETS)
+if ("${ENABLED_INTRINSIC_TARGETS}" STREQUAL "")
+ set(ENABLED_INTRINSIC_TARGETS "none")
+else()
+ string(TOLOWER ${ENABLED_INTRINSIC_TARGETS} ENABLED_INTRINSIC_TARGETS)
+endif()
+message(STATUS "Enabling intrinsic targets: ${ENABLED_INTRINSIC_TARGETS}")
+set(ENABLED_INTRINSIC_TARGETS --enabled-targets=${ENABLED_INTRINSIC_TARGETS})
+
if (NOT CMAKE_SYSTEM_NAME MATCHES "OS390")
option(LLVM_ENABLE_PIC "Build Position-Independent Code" ON)
endif()
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
index 9f8eb030a96c64..775998fe53a7be 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
@@ -889,7 +889,7 @@ bool GIMatchTableExecutor::executeMatchTable(
case GIM_CheckIntrinsicID: {
uint64_t InsnID = readULEB();
uint64_t OpIdx = readULEB();
- uint16_t Value = readU16();
+ uint32_t Value = readU32();
DEBUG_WITH_TYPE(TgtExecutor::getName(),
dbgs() << CurrentIdx << ": GIM_CheckIntrinsicID(MIs["
<< InsnID << "]->getOperand(" << OpIdx
@@ -1185,7 +1185,7 @@ bool GIMatchTableExecutor::executeMatchTable(
}
case GIR_AddIntrinsicID: {
uint64_t InsnID = readULEB();
- uint16_t Value = readU16();
+ uint32_t Value = readU32();
assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
OutMIs[InsnID].addIntrinsicID((Intrinsic::ID)Value);
DEBUG_WITH_TYPE(TgtExecutor::getName(),
diff --git a/llvm/include/llvm/IR/CMakeLists.txt b/llvm/include/llvm/IR/CMakeLists.txt
index 468d663796ed43..719d64fc292539 100644
--- a/llvm/include/llvm/IR/CMakeLists.txt
+++ b/llvm/include/llvm/IR/CMakeLists.txt
@@ -2,24 +2,24 @@ set(LLVM_TARGET_DEFINITIONS Attributes.td)
tablegen(LLVM Attributes.inc -gen-attrs)
set(LLVM_TARGET_DEFINITIONS Intrinsics.td)
-tablegen(LLVM IntrinsicImpl.inc -gen-intrinsic-impl)
-tablegen(LLVM IntrinsicEnums.inc -gen-intrinsic-enums)
-tablegen(LLVM IntrinsicsAArch64.h -gen-intrinsic-enums -intrinsic-prefix=aarch64)
-tablegen(LLVM IntrinsicsAMDGPU.h -gen-intrinsic-enums -intrinsic-prefix=amdgcn)
-tablegen(LLVM IntrinsicsARM.h -gen-intrinsic-enums -intrinsic-prefix=arm)
-tablegen(LLVM IntrinsicsBPF.h -gen-intrinsic-enums -intrinsic-prefix=bpf)
-tablegen(LLVM IntrinsicsDirectX.h -gen-intrinsic-enums -intrinsic-prefix=dx)
-tablegen(LLVM IntrinsicsHexagon.h -gen-intrinsic-enums -intrinsic-prefix=hexagon)
-tablegen(LLVM IntrinsicsLoongArch.h -gen-intrinsic-enums -intrinsic-prefix=loongarch)
-tablegen(LLVM IntrinsicsMips.h -gen-intrinsic-enums -intrinsic-prefix=mips)
-tablegen(LLVM IntrinsicsNVPTX.h -gen-intrinsic-enums -intrinsic-prefix=nvvm)
-tablegen(LLVM IntrinsicsPowerPC.h -gen-intrinsic-enums -intrinsic-prefix=ppc)
-tablegen(LLVM IntrinsicsR600.h -gen-intrinsic-enums -intrinsic-prefix=r600)
-tablegen(LLVM IntrinsicsRISCV.h -gen-intrinsic-enums -intrinsic-prefix=riscv)
-tablegen(LLVM IntrinsicsSPIRV.h -gen-intrinsic-enums -intrinsic-prefix=spv)
-tablegen(LLVM IntrinsicsS390.h -gen-intrinsic-enums -intrinsic-prefix=s390)
-tablegen(LLVM IntrinsicsWebAssembly.h -gen-intrinsic-enums -intrinsic-prefix=wasm)
-tablegen(LLVM IntrinsicsX86.h -gen-intrinsic-enums -intrinsic-prefix=x86)
-tablegen(LLVM IntrinsicsXCore.h -gen-intrinsic-enums -intrinsic-prefix=xcore)
-tablegen(LLVM IntrinsicsVE.h -gen-intrinsic-enums -intrinsic-prefix=ve)
+tablegen(LLVM IntrinsicImpl.inc -gen-intrinsic-impl ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicEnums.inc -gen-intrinsic-enums ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsAArch64.h -gen-intrinsic-enums -intrinsic-prefix=aarch64 ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsAMDGPU.h -gen-intrinsic-enums -intrinsic-prefix=amdgcn ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsARM.h -gen-intrinsic-enums -intrinsic-prefix=arm ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsBPF.h -gen-intrinsic-enums -intrinsic-prefix=bpf ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsDirectX.h -gen-intrinsic-enums -intrinsic-prefix=dx ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsHexagon.h -gen-intrinsic-enums -intrinsic-prefix=hexagon ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsLoongArch.h -gen-intrinsic-enums -intrinsic-prefix=loongarch ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsMips.h -gen-intrinsic-enums -intrinsic-prefix=mips ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsNVPTX.h -gen-intrinsic-enums -intrinsic-prefix=nvvm ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsPowerPC.h -gen-intrinsic-enums -intrinsic-prefix=ppc ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsR600.h -gen-intrinsic-enums -intrinsic-prefix=r600 ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsRISCV.h -gen-intrinsic-enums -intrinsic-prefix=riscv ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsSPIRV.h -gen-intrinsic-enums -intrinsic-prefix=spv ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsS390.h -gen-intrinsic-enums -intrinsic-prefix=s390 ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsWebAssembly.h -gen-intrinsic-enums -intrinsic-prefix=wasm ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsX86.h -gen-intrinsic-enums -intrinsic-prefix=x86 ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsXCore.h -gen-intrinsic-enums -intrinsic-prefix=xcore ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM IntrinsicsVE.h -gen-intrinsic-enums -intrinsic-prefix=ve ${ENABLED_INTRINSIC_TARGETS})
add_public_tablegen_target(intrinsics_gen)
diff --git a/llvm/include/llvm/IR/Intrinsics.h b/llvm/include/llvm/IR/Intrinsics.h
index e893295e3272b9..ce1949b38cf793 100644
--- a/llvm/include/llvm/IR/Intrinsics.h
+++ b/llvm/include/llvm/IR/Intrinsics.h
@@ -47,8 +47,21 @@ namespace Intrinsic {
#define GET_INTRINSIC_ENUM_VALUES
#include "llvm/IR/IntrinsicEnums.inc"
#undef GET_INTRINSIC_ENUM_VALUES
+ end_id = ~0U,
};
+ // Is this a valid intrinsic ID. Validity means that it is a valid value of
+ // a defined enum in Intrinsic::ID enum.
+ bool IsIntrinsicIDValid(ID id);
+
+ // Is this an enabled intrinsic ID. This means that LLVM has support for this
+ // intrinsic ID enabled.
+ bool IsIntrinsicIDEnabled(ID id);
+
+ // Get the next valid ID. This is used in test cases that iterate over valid
+ // intrinsic ID enums.
+ ID GetNextValidIntrinsicID(ID id);
+
/// Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx".
/// Note, this version is for intrinsics with no overloads. Use the other
/// version of getName if overloads are required.
diff --git a/llvm/include/llvm/Support/IntrinsicID.h b/llvm/include/llvm/Support/IntrinsicID.h
new file mode 100644
index 00000000000000..60b13d85ec9070
--- /dev/null
+++ b/llvm/include/llvm/Support/IntrinsicID.h
@@ -0,0 +1,59 @@
+//===- llvm/Support/IntrinsicID.h - Intrinsic ID encoding -------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains functions to support intrinsic ID encoding. The
+// Intrinsic::ID enum value is constructed using a target prefix index in bits
+// 23-16 (8-bit) and an intrinsic index (index within the list of intrinsics for
+// tha target) in lower 16 bits. To support Intrinsic::ID 0 being not used, the
+// intrinsic index is encoded as Index + 1 for all targets.
+//
+// This file defines functions that encapsulate this encoding.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_SUPPORT_INTRINSIC_ID_H
+#define LLVM_SUPPORT_INTRINSIC_ID_H
+
+#include "llvm/Support/FormatVariadic.h"
+#include <limits>
+#include <optional>
+#include <utility>
+
+namespace llvm::Intrinsic {
+typedef unsigned ID;
+
+inline ID EncodeIntrinsicID(unsigned TargetIndex, unsigned IntrinsicIndex) {
+ assert(IntrinsicIndex < std::numeric_limits<uint16_t>::max());
+ assert(TargetIndex <= std::numeric_limits<uint8_t>::max());
+ return (TargetIndex << 16) | (IntrinsicIndex + 1);
+}
+
+inline std::pair<unsigned, unsigned> DecodeIntrinsicID(ID id) {
+ unsigned IntrinsicIndex = id & 0xFFFF;
+ unsigned TargetIndex = id >> 16;
+ assert(IntrinsicIndex != 0);
+ return {TargetIndex, IntrinsicIndex - 1};
+}
+
+inline std::optional<std::pair<unsigned, unsigned>>
+DecodeIntrinsicIDNoFail(ID id) {
+ unsigned IntrinsicIndex = id & 0xFFFF;
+ unsigned TargetIndex = id >> 16;
+ if (IntrinsicIndex == 0)
+ return std::nullopt;
+ return std::make_pair(TargetIndex, IntrinsicIndex - 1);
+}
+
+inline void PrintIntrinsicIDEncoding(raw_ostream &OS, unsigned TargetIndex,
+ unsigned IntrinsicIndex) {
+ OS << formatv(" = ({} << 16) + {} + 1", TargetIndex, IntrinsicIndex);
+}
+
+} // end namespace llvm::Intrinsic
+
+#endif // LLVM_SUPPORT_INTRINSIC_ID_H
diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp
index 89d32c3f005e00..c5d6e6718b5729 100644
--- a/llvm/lib/CodeGen/MachineOperand.cpp
+++ b/llvm/lib/CodeGen/MachineOperand.cpp
@@ -992,7 +992,7 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
}
case MachineOperand::MO_IntrinsicID: {
Intrinsic::ID ID = getIntrinsicID();
- if (ID < Intrinsic::num_intrinsics)
+ if (Intrinsic::IsIntrinsicIDValid(ID))
OS << "intrinsic(@" << Intrinsic::getBaseName(ID) << ')';
else if (IntrinsicInfo)
OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index e2c09fe25d55cd..77440e5e7275f7 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1055,7 +1055,7 @@ bool MachineVerifier::verifyGIntrinsicSideEffects(const MachineInstr *MI) {
bool NoSideEffects = Opcode == TargetOpcode::G_INTRINSIC ||
Opcode == TargetOpcode::G_INTRINSIC_CONVERGENT;
unsigned IntrID = cast<GIntrinsic>(MI)->getIntrinsicID();
- if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
+ if (IntrID != 0 && Intrinsic::IsIntrinsicIDValid(IntrID)) {
AttributeList Attrs = Intrinsic::getAttributes(
MF->getFunction().getContext(), static_cast<Intrinsic::ID>(IntrID));
bool DeclHasSideEffects = !Attrs.getMemoryEffects().doesNotAccessMemory();
@@ -1079,7 +1079,7 @@ bool MachineVerifier::verifyGIntrinsicConvergence(const MachineInstr *MI) {
bool NotConvergent = Opcode == TargetOpcode::G_INTRINSIC ||
Opcode == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS;
unsigned IntrID = cast<GIntrinsic>(MI)->getIntrinsicID();
- if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
+ if (IntrID != 0 && Intrinsic::IsIntrinsicIDValid(IntrID)) {
AttributeList Attrs = Intrinsic::getAttributes(
MF->getFunction().getContext(), static_cast<Intrinsic::ID>(IntrID));
bool DeclIsConvergent = Attrs.hasFnAttr(Attribute::Convergent);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
index 703efb70089742..d9e3324c6a4981 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
@@ -160,7 +160,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::INTRINSIC_W_CHAIN: {
unsigned OpNo = getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1;
unsigned IID = getOperand(OpNo)->getAsZExtVal();
- if (IID < Intrinsic::num_intrinsics)
+ if (Intrinsic::IsIntrinsicIDValid(IID))
return Intrinsic::getBaseName((Intrinsic::ID)IID).str();
if (!G)
return "Unknown intrinsic";
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 9bd894dd952bda..0b48184afb1239 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -4431,7 +4431,7 @@ void SelectionDAGISel::CannotYetSelect(SDNode *N) {
} else {
bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
unsigned iid = N->getConstantOperandVal(HasInputChain);
- if (iid < Intrinsic::num_intrinsics)
+ if (Intrinsic::IsIntrinsicIDValid(iid))
Msg << "intrinsic %" << Intrinsic::getBaseName((Intrinsic::ID)iid);
else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
Msg << "target intrinsic %" << TII->getName(iid);
diff --git a/llvm/lib/IR/Core.cpp b/llvm/lib/IR/Core.cpp
index 1cf998c6850068..32f31e9900880d 100644
--- a/llvm/lib/IR/Core.cpp
+++ b/llvm/lib/IR/Core.cpp
@@ -2458,7 +2458,8 @@ unsigned LLVMGetIntrinsicID(LLVMValueRef Fn) {
}
static Intrinsic::ID llvm_map_to_intrinsic_id(unsigned ID) {
- assert(ID < llvm::Intrinsic::num_intrinsics && "Intrinsic ID out of range");
+ assert(llvm::Intrinsic::IsIntrinsicIDValid(ID) &&
+ "Intrinsic ID out of range");
return llvm::Intrinsic::ID(ID);
}
diff --git a/llvm/lib/IR/Intrinsics.cpp b/llvm/lib/IR/Intrinsics.cpp
index 1b92daf15b463e..688e19109ec6bd 100644
--- a/llvm/lib/IR/Intrinsics.cpp
+++ b/llvm/lib/IR/Intrinsics.cpp
@@ -33,8 +33,65 @@
#include "llvm/IR/IntrinsicsXCore.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/Type.h"
+#include "llvm/Support/IntrinsicID.h"
using namespace llvm;
+using namespace Intrinsic;
+
+/// Table of per-target intrinsic name tables.
+#define GET_INTRINSIC_TARGET_DATA
+#include "llvm/IR/IntrinsicImpl.inc"
+#undef GET_INTRINSIC_TARGET_DATA
+size_t constexpr NumTargets = sizeof(TargetInfos) / sizeof(TargetInfos[0]);
+
+// Returns true if the given intrinsic ID is valid. ID 0 for not_intrinsic is
+// considered valid. Note that Valid != Enabled. This is essntially replacement
+// for earlier (ID < num_intrinsics) checks.
+bool Intrinsic::IsIntrinsicIDValid(ID ID) {
+ if (ID == 0)
+ return true;
+ auto Decoded = DecodeIntrinsicIDNoFail(ID);
+ if (!Decoded)
+ return false;
+ unsigned TargetIdx = Decoded->first;
+ unsigned IntrinsicIdx = Decoded->second;
+ return TargetIdx < NumTargets && IntrinsicIdx < TargetInfos[TargetIdx].Count;
+}
+
+// Returns linear index of ID if its enabled, else returns 0.
+inline unsigned getLinearIndex(Intrinsic::ID ID) {
+ auto Decoded = DecodeIntrinsicIDNoFail(ID);
+ if (!Decoded)
+ return 0;
+ unsigned TargetIdx = Decoded->first;
+ unsigned IntrinsicIdx = Decoded->second;
+ if (!TargetInfos[TargetIdx].Enabled)
+ return 0;
+ unsigned EnabledIndex = TargetInfos[TargetIdx].EnabledIndex;
+ return TargetLinearIndexInfos[EnabledIndex].FirstLinearIndex + IntrinsicIdx;
+}
+
+bool Intrinsic::IsIntrinsicIDEnabled(Intrinsic::ID ID) {
+ if (!IsIntrinsicIDValid(ID))
+ return false;
+ auto [TargetIdx, _] = DecodeIntrinsicID(ID);
+ return TargetInfos[TargetIdx].Enabled;
+}
+
+ID Intrinsic::GetNextValidIntrinsicID(Intrinsic::ID ID) {
+ if (ID == Intrinsic::not_intrinsic)
+ return 1;
+ if (ID == Intrinsic::last_valid_intrinsic)
+ return Intrinsic::end_id;
+ if (ID == Intrinsic::end_id)
+ llvm_unreachable("Cannot find the next valid intrisnic");
+ auto [TargetIndex, IntrinsicIndex] = DecodeIntrinsicID(ID);
+ if (IntrinsicIndex + 1 < TargetInfos[TargetIndex].Count)
+ return EncodeIntrinsicID(TargetIndex, IntrinsicIndex + 1);
+ else if (TargetIndex + 1 < NumTargets)
+ return EncodeIntrinsicID(TargetIndex + 1, 0);
+ llvm_unreachable("Cannot find the next valid intrisnic");
+}
/// Table of string intrinsic names indexed by enum value.
static constexpr const char *const IntrinsicNameTable[] = {
@@ -45,12 +102,12 @@ static constexpr const char *const IntrinsicNameTable[] = {
};
StringRef Intrinsic::getBaseName(ID id) {
- assert(id < num_intrinsics && "Invalid intrinsic ID!");
- return IntrinsicNameTable[id];
+ assert(IsIntrinsicIDValid(id) && "Invalid intrinsic ID!");
+ return ArrayRef(IntrinsicNameTable)[getLinearIndex(id)];
}
StringRef Intrinsic::getName(ID id) {
- assert(id < num_intrinsics && "Invalid intrinsic ID!");
+ assert(IsIntrinsicIDValid(id) && "Invalid intrinsic ID!");
assert(!Intrinsic::isOverloaded(id) &&
"This version of getName does not support overloading");
return getBaseName(id);
@@ -157,8 +214,7 @@ static std::string getMangledTypeStr(Type *Ty, bool &HasUnnamedType) {
static std::string getIntrinsicNameImpl(Intrinsic::ID Id, ArrayRef<Type *> Tys,
Module *M, FunctionType *FT,
bool EarlyModuleCheck) {
-
- assert(Id < Intrinsic::num_intrinsics && "Invalid intrinsic ID!");
+ assert(IsIntrinsicIDEnabled(Id) && "Invalid intrinsic ID!");
assert((Tys.empty() || Intrinsic::isOverloaded(Id)) &&
"This version of getName is for overloaded intrinsics only");
(void)EarlyModuleCheck;
@@ -450,11 +506,15 @@ DecodeIITType(unsigned &NextElt, ArrayRef<unsigned char> Infos,
#undef GET_INTRINSIC_GENERATOR_GLOBAL
void Intrinsic::getIntrinsicInfoTableEntries(
- ID id, SmallVectorImpl<IITDescriptor> &T) {
+ ID IntrinsicID, SmallVectorImpl<IITDescriptor> &T) {
static_assert(sizeof(IIT_Table[0]) == 2,
"Expect 16-bit entries in IIT_Table");
+ assert(IsIntrinsicIDValid(IntrinsicID));
+ unsigned Idx = getLinearIndex(IntrinsicID);
+ if (Idx == 0)
+ return;
// Check to see if the intrinsic's type was expressible by the table.
- uint16_t TableVal = IIT_Table[id - 1];
+ uint16_t TableVal = IIT_Table[Idx - 1];
// Decode the TableVal into an array of IITValues.
SmallVector<unsigned char> IITValues;
@@ -609,19 +669,20 @@ FunctionType *Intrinsic::getType(LLVMContext &Context, ID id,
return FunctionType::get(ResultTy, ArgTys, false);
}
-bool Intrinsic::isOverloaded(ID id) {
+// Check if an intrinsic is overloaded or not using its linear index.
+static bool isOverloadedUsingLinearIndex(unsigned Idx) {
#define GET_INTRINSIC_OVERLOAD_TABLE
#include "llvm/IR/IntrinsicImpl.inc"
#undef GET_INTRINSIC_OVERLOAD_TABLE
}
-/// Table of per-target intrinsic name tables.
-#define GET_INTRINSIC_TARGET_DATA
-#include "llvm/IR/IntrinsicImpl.inc"
-#undef GET_INTRINSIC_TARGET_DATA
+bool Intrinsic::isOverloaded(ID id) {
+ assert(IsIntrinsicIDValid(id));
+ return isOverloadedUsingLinearIndex(getLinearIndex(id));
+}
bool Intrinsic::isTargetIntrinsic(Intrinsic::ID IID) {
- return IID > TargetInfos[0].Count;
+ return DecodeIntrinsicID(IID).first != 0;
}
int llvm::Intrinsic::lookupLLVMIntrinsicByName(ArrayRef<const char *> NameTable,
@@ -682,8 +743,31 @@ findTargetSubtable(StringRef Name) {
Targets, [=](const IntrinsicTargetInfo &TI) { return TI.Name < Target; });
// We've either found the target or just fall back to the generic set, which
// is always first.
- const auto &TI = It != Targets.end() && It->Name == Target ? *It : Targets[0];
- return {ArrayRef(&IntrinsicNameTable[1] + TI.Offset, TI.Count), TI.Name};
+ const auto &TI = It != Targets.end() && It->Name == Target && It->Enabled
+ ? *It
+ : Targets[0];
+ unsigned LinearIndex =
+ TargetLinearIndexInfos[TI.EnabledIndex].FirstLinearIndex;
+ return {ArrayRef(IntrinsicNameTable + LinearIndex, TI.Count), TI.Name};
+}
+
+static Intrinsic::ID getIntrinsicIDFromIndex(unsigned Idx) {
+ if (Idx == 0)
+ return Intrinsic::not_intrinsic;
+
+ auto It = partition_point(TargetLinearIndexInfos,
+ [Idx](const IntrinsicLinearIndexInfo &Info) {
+ return Info.FirstLinearIndex + Info.Count < Idx;
+ });
+ // Idx, if present, will be in the entry at It or It + 1.
+ if (It == std::end(TargetLinearIndexInfos))
+ return Intrinsic::not_intrinsic;
+ if (It->FirstLinearIndex <= Idx && Idx < It->FirstLinearIndex + It->Count)
+ return EncodeIntrinsicID(It->TargetIdx, Idx - It->FirstLinearIndex);
+ ++It;
+ if (It->FirstLinearIndex <= Idx && Idx < It->FirstLinearIndex + It->Count)
+ return EncodeIntrinsicID(It->TargetIdx, Idx - It->FirstLinearIndex);
+ return Intrinsic::not_intrinsic;
}
/// This does the actual lookup of an intrinsic ID which matches the given
@@ -693,19 +777,19 @@ Intrinsic::ID Intrinsic::lookupIntrinsicID(StringRef Name) {
int Idx = Intrinsic::lookupLLVMIntrinsicByName(NameTable, Name, Target);
if (Idx == -1)
return Intrinsic::not_intrinsic;
-
- // Intrinsic IDs correspond to the location in IntrinsicNameTable, but we have
- // an index into a sub-table.
+ const auto MatchSize = strlen(NameTable[Idx]);
+ // Adjust the index from sub-table index to index into the global table.
int Adjust = NameTable.data() - IntrinsicNameTable;
- Intrinsic::ID ID = static_cast<Intrinsic::ID>(Idx + Adjust);
+ Idx += Adjust;
// If the intrinsic is not overloaded, require an exact match. If it is
// overloaded, require either exact or prefix match.
- const auto MatchSize = strlen(NameTable[Idx]);
assert(Name.size() >= MatchSize && "Expected either exact or prefix match");
bool IsExactMatch = Name.size() == MatchSize;
- return IsExactMatch || Intrinsic::isOverloaded(ID) ? ID
- : Intrinsic::not_intrinsic;
+ Intrinsic::ID r = IsExactMatch || isOverloadedUsingLinearIndex(Idx)
+ ? getIntrinsicIDFromIndex(Idx)
+ : Intrinsic::not_intrinsic;
+ return r;
}
/// This defines the "Intrinsic::getAttributes(ID id)" method.
@@ -718,10 +802,11 @@ Function *Intrinsic::getOrInsertDeclaration(Module *M, ID id,
// There can never be multiple globals with the same name of different types,
// because intrinsics must be a specific type.
auto *FT = getType(M->getContext(), id, Tys);
- return cast<Function>(
+ Function *F = cast<Function>(
M->getOrInsertFunction(
Tys.empty() ? getName(id) : getName(id, Tys, M, FT), FT)
.getCallee());
+ return F;
}
Function *Intrinsic::getDeclarationIfExists(const Module *M, ID id) {
@@ -1043,7 +1128,7 @@ bool Intrinsic::matchIntrinsicVarArg(
bool Intrinsic::getIntrinsicSignature(Intrinsic::ID ID, FunctionType *FT,
SmallVectorImpl<Type *> &ArgTys) {
- if (!ID)
+ if (!ID || !IsIntrinsicIDEnabled(ID))
return false;
SmallVector<Intrinsic::IITDescriptor, 8> Table;
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 4aa123b42d1966..85c675f0a6e092 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -7534,7 +7534,7 @@ static unsigned getIntrinsicID(const SDNode *N) {
return Intrinsic::not_intrinsic;
case ISD::INTRINSIC_WO_CHAIN: {
unsigned IID = N->getConstantOperandVal(0);
- if (IID < Intrinsic::num_intrinsics)
+ if (Intrinsic::IsIntrinsicIDValid(IID))
return IID;
return Intrinsic::not_intrinsic;
}
diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt b/llvm/lib/Target/AArch64/CMakeLists.txt
index da13db8e68b0e6..deca0ab4f839e1 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -6,10 +6,10 @@ tablegen(LLVM AArch64GenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM AArch64GenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AArch64GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv)
-tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM AArch64GenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel)
-tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM AArch64GenFastISel.inc -gen-fast-isel ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AArch64GenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
-combiners="AArch64O0PreLegalizerCombiner")
tablegen(LLVM AArch64GenPreLegalizeGICombiner.inc -gen-global-isel-combiner
@@ -18,7 +18,7 @@ tablegen(LLVM AArch64GenPostLegalizeGICombiner.inc -gen-global-isel-combiner
-combiners="AArch64PostLegalizerCombiner")
tablegen(LLVM AArch64GenPostLegalizeGILowering.inc -gen-global-isel-combiner
-combiners="AArch64PostLegalizerLowering")
-tablegen(LLVM AArch64GenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM AArch64GenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AArch64GenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AArch64GenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(LLVM AArch64GenRegisterBank.inc -gen-register-bank)
diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt
index fed29c3e14aae2..e50a56231160ac 100644
--- a/llvm/lib/Target/AMDGPU/CMakeLists.txt
+++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt
@@ -2,12 +2,12 @@ add_llvm_component_group(AMDGPU)
set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
-tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
+tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AMDGPUGenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank)
@@ -16,20 +16,20 @@ tablegen(LLVM AMDGPUGenSearchableTables.inc -gen-searchable-tables)
tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
set(LLVM_TARGET_DEFINITIONS AMDGPUGISel.td)
-tablegen(LLVM AMDGPUGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM AMDGPUGenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AMDGPUGenPreLegalizeGICombiner.inc -gen-global-isel-combiner
-combiners="AMDGPUPreLegalizerCombiner")
tablegen(LLVM AMDGPUGenPostLegalizeGICombiner.inc -gen-global-isel-combiner
- -combiners="AMDGPUPostLegalizerCombiner")
+ -combiners="AMDGPUPostLegalizerCombiner" ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AMDGPUGenRegBankGICombiner.inc -gen-global-isel-combiner
-combiners="AMDGPURegBankCombiner")
set(LLVM_TARGET_DEFINITIONS R600.td)
tablegen(LLVM R600GenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM R600GenCallingConv.inc -gen-callingconv)
-tablegen(LLVM R600GenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM R600GenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM R600GenDFAPacketizer.inc -gen-dfa-packetizer)
-tablegen(LLVM R600GenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM R600GenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM R600GenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM R600GenRegisterInfo.inc -gen-register-info)
tablegen(LLVM R600GenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/ARC/CMakeLists.txt b/llvm/lib/Target/ARC/CMakeLists.txt
index 9f3c1787c5635e..0ef7f1a7174bb4 100644
--- a/llvm/lib/Target/ARC/CMakeLists.txt
+++ b/llvm/lib/Target/ARC/CMakeLists.txt
@@ -4,9 +4,9 @@ set(LLVM_TARGET_DEFINITIONS ARC.td)
tablegen(LLVM ARCGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM ARCGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM ARCGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM ARCGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM ARCGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM ARCGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM ARCGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM ARCGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM ARCGenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/ARM/CMakeLists.txt b/llvm/lib/Target/ARM/CMakeLists.txt
index 3d6af28b437538..a3b5517c06fe36 100644
--- a/llvm/lib/Target/ARM/CMakeLists.txt
+++ b/llvm/lib/Target/ARM/CMakeLists.txt
@@ -5,11 +5,11 @@ set(LLVM_TARGET_DEFINITIONS ARM.td)
tablegen(LLVM ARMGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM ARMGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM ARMGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM ARMGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM ARMGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM ARMGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM ARMGenFastISel.inc -gen-fast-isel)
-tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel)
-tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM ARMGenFastISel.inc -gen-fast-isel ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM ARMGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM ARMGenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(LLVM ARMGenRegisterBank.inc -gen-register-bank)
diff --git a/llvm/lib/Target/AVR/CMakeLists.txt b/llvm/lib/Target/AVR/CMakeLists.txt
index 817ba739d8418a..4fede075558e89 100644
--- a/llvm/lib/Target/AVR/CMakeLists.txt
+++ b/llvm/lib/Target/AVR/CMakeLists.txt
@@ -5,9 +5,9 @@ set(LLVM_TARGET_DEFINITIONS AVR.td)
tablegen(LLVM AVRGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM AVRGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM AVRGenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/BPF/CMakeLists.txt b/llvm/lib/Target/BPF/CMakeLists.txt
index eade4cacb7100e..a876dca443c0b2 100644
--- a/llvm/lib/Target/BPF/CMakeLists.txt
+++ b/llvm/lib/Target/BPF/CMakeLists.txt
@@ -5,13 +5,13 @@ set(LLVM_TARGET_DEFINITIONS BPF.td)
tablegen(LLVM BPFGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM BPFGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM BPFGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM BPFGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM BPFGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM BPFGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM BPFGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM BPFGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM BPFGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM BPFGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM BPFGenSubtargetInfo.inc -gen-subtarget)
-tablegen(LLVM BPFGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM BPFGenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM BPFGenRegisterBank.inc -gen-register-bank)
add_public_tablegen_target(BPFCommonTableGen)
diff --git a/llvm/lib/Target/CSKY/CMakeLists.txt b/llvm/lib/Target/CSKY/CMakeLists.txt
index cdce80591a2fd2..81d720d4404f03 100644
--- a/llvm/lib/Target/CSKY/CMakeLists.txt
+++ b/llvm/lib/Target/CSKY/CMakeLists.txt
@@ -6,9 +6,9 @@ tablegen(LLVM CSKYGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM CSKYGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM CSKYGenCallingConv.inc -gen-callingconv)
tablegen(LLVM CSKYGenCompressInstEmitter.inc -gen-compress-inst-emitter)
-tablegen(LLVM CSKYGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM CSKYGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM CSKYGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM CSKYGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM CSKYGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM CSKYGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM CSKYGenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(LLVM CSKYGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/DirectX/CMakeLists.txt b/llvm/lib/Target/DirectX/CMakeLists.txt
index c8ef0ef6f7e702..328657079f685f 100644
--- a/llvm/lib/Target/DirectX/CMakeLists.txt
+++ b/llvm/lib/Target/DirectX/CMakeLists.txt
@@ -3,7 +3,7 @@ add_llvm_component_group(DirectX)
set(LLVM_TARGET_DEFINITIONS DirectX.td)
tablegen(LLVM DirectXGenSubtargetInfo.inc -gen-subtarget)
-tablegen(LLVM DirectXGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM DirectXGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM DirectXGenRegisterInfo.inc -gen-register-info)
set(LLVM_TARGET_DEFINITIONS DXIL.td)
@@ -45,6 +45,7 @@ add_llvm_target(DirectXCodeGen
FrontendHLSL
MC
SelectionDAG
+ Scalar
Support
Target
TargetParser
diff --git a/llvm/lib/Target/Hexagon/CMakeLists.txt b/llvm/lib/Target/Hexagon/CMakeLists.txt
index e8ec93dd5ee63c..2e0299c0baad45 100644
--- a/llvm/lib/Target/Hexagon/CMakeLists.txt
+++ b/llvm/lib/Target/Hexagon/CMakeLists.txt
@@ -5,10 +5,10 @@ set(LLVM_TARGET_DEFINITIONS Hexagon.td)
tablegen(LLVM HexagonGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM HexagonGenDFAPacketizer.inc -gen-dfa-packetizer)
tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM HexagonGenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/Lanai/CMakeLists.txt b/llvm/lib/Target/Lanai/CMakeLists.txt
index 16d5f727043fe9..aff46035b6b3cf 100644
--- a/llvm/lib/Target/Lanai/CMakeLists.txt
+++ b/llvm/lib/Target/Lanai/CMakeLists.txt
@@ -5,9 +5,9 @@ set(LLVM_TARGET_DEFINITIONS Lanai.td)
tablegen(LLVM LanaiGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM LanaiGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM LanaiGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM LanaiGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM LanaiGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM LanaiGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM LanaiGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM LanaiGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM LanaiGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM LanaiGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM LanaiGenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/LoongArch/CMakeLists.txt b/llvm/lib/Target/LoongArch/CMakeLists.txt
index 0f674b1b0fa9e2..fde92b1193f493 100644
--- a/llvm/lib/Target/LoongArch/CMakeLists.txt
+++ b/llvm/lib/Target/LoongArch/CMakeLists.txt
@@ -4,9 +4,9 @@ set(LLVM_TARGET_DEFINITIONS LoongArch.td)
tablegen(LLVM LoongArchGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM LoongArchGenAsmWriter.inc -gen-asm-writer)
-tablegen(LLVM LoongArchGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM LoongArchGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM LoongArchGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM LoongArchGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM LoongArchGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM LoongArchGenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(LLVM LoongArchGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM LoongArchGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/M68k/CMakeLists.txt b/llvm/lib/Target/M68k/CMakeLists.txt
index 1661dccece3dd8..70856d123255cb 100644
--- a/llvm/lib/Target/M68k/CMakeLists.txt
+++ b/llvm/lib/Target/M68k/CMakeLists.txt
@@ -2,14 +2,14 @@ add_llvm_component_group(M68k)
set(LLVM_TARGET_DEFINITIONS M68k.td)
-tablegen(LLVM M68kGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM M68kGenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM M68kGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM M68kGenRegisterBank.inc -gen-register-bank)
-tablegen(LLVM M68kGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM M68kGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM M68kGenSubtargetInfo.inc -gen-subtarget)
tablegen(LLVM M68kGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM M68kGenMCPseudoLowering.inc -gen-pseudo-lowering)
-tablegen(LLVM M68kGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM M68kGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM M68kGenCallingConv.inc -gen-callingconv)
tablegen(LLVM M68kGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM M68kGenAsmMatcher.inc -gen-asm-matcher)
diff --git a/llvm/lib/Target/MSP430/CMakeLists.txt b/llvm/lib/Target/MSP430/CMakeLists.txt
index 1dfe8635acb32b..6a8a9248f6577e 100644
--- a/llvm/lib/Target/MSP430/CMakeLists.txt
+++ b/llvm/lib/Target/MSP430/CMakeLists.txt
@@ -5,9 +5,9 @@ set(LLVM_TARGET_DEFINITIONS MSP430.td)
tablegen(LLVM MSP430GenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM MSP430GenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM MSP430GenCallingConv.inc -gen-callingconv)
-tablegen(LLVM MSP430GenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM MSP430GenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM MSP430GenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM MSP430GenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM MSP430GenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM MSP430GenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM MSP430GenRegisterInfo.inc -gen-register-info)
tablegen(LLVM MSP430GenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/Mips/CMakeLists.txt b/llvm/lib/Target/Mips/CMakeLists.txt
index 28f66a4ad94826..5bfadf0f317a11 100644
--- a/llvm/lib/Target/Mips/CMakeLists.txt
+++ b/llvm/lib/Target/Mips/CMakeLists.txt
@@ -5,13 +5,13 @@ set(LLVM_TARGET_DEFINITIONS Mips.td)
tablegen(LLVM MipsGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM MipsGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM MipsGenFastISel.inc -gen-fast-isel)
-tablegen(LLVM MipsGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM MipsGenFastISel.inc -gen-fast-isel ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM MipsGenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM MipsGenPostLegalizeGICombiner.inc -gen-global-isel-combiner
-combiners="MipsPostLegalizerCombiner")
-tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM MipsGenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(LLVM MipsGenRegisterBank.inc -gen-register-bank)
diff --git a/llvm/lib/Target/NVPTX/CMakeLists.txt b/llvm/lib/Target/NVPTX/CMakeLists.txt
index 693365161330f5..fa9004a6c2978f 100644
--- a/llvm/lib/Target/NVPTX/CMakeLists.txt
+++ b/llvm/lib/Target/NVPTX/CMakeLists.txt
@@ -3,8 +3,8 @@ add_llvm_component_group(NVPTX)
set(LLVM_TARGET_DEFINITIONS NVPTX.td)
tablegen(LLVM NVPTXGenAsmWriter.inc -gen-asm-writer)
-tablegen(LLVM NVPTXGenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM NVPTXGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM NVPTXGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM NVPTXGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM NVPTXGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM NVPTXGenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/PowerPC/CMakeLists.txt b/llvm/lib/Target/PowerPC/CMakeLists.txt
index cd4c76013d2041..45adcccdcdc749 100644
--- a/llvm/lib/Target/PowerPC/CMakeLists.txt
+++ b/llvm/lib/Target/PowerPC/CMakeLists.txt
@@ -5,16 +5,16 @@ set(LLVM_TARGET_DEFINITIONS PPC.td)
tablegen(LLVM PPCGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM PPCGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM PPCGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM PPCGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM PPCGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM PPCGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM PPCGenFastISel.inc -gen-fast-isel)
-tablegen(LLVM PPCGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM PPCGenFastISel.inc -gen-fast-isel ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM PPCGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM PPCGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM PPCGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM PPCGenSubtargetInfo.inc -gen-subtarget)
tablegen(LLVM PPCGenExegesis.inc -gen-exegesis)
tablegen(LLVM PPCGenRegisterBank.inc -gen-register-bank)
-tablegen(LLVM PPCGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM PPCGenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
add_public_tablegen_target(PowerPCCommonTableGen)
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
index fd049d1a57860e..832496c6fcf8f0 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -6,9 +6,9 @@ tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)
-tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
tablegen(LLVM RISCVGenRegisterBank.inc -gen-register-bank)
@@ -17,7 +17,7 @@ tablegen(LLVM RISCVGenSearchableTables.inc -gen-searchable-tables)
tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
set(LLVM_TARGET_DEFINITIONS RISCVGISel.td)
-tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM RISCVGenO0PreLegalizeGICombiner.inc -gen-global-isel-combiner
-combiners="RISCVO0PreLegalizerCombiner")
tablegen(LLVM RISCVGenPreLegalizeGICombiner.inc -gen-global-isel-combiner
diff --git a/llvm/lib/Target/SPIRV/CMakeLists.txt b/llvm/lib/Target/SPIRV/CMakeLists.txt
index 326343ae278148..e4c4ccbe6ba949 100644
--- a/llvm/lib/Target/SPIRV/CMakeLists.txt
+++ b/llvm/lib/Target/SPIRV/CMakeLists.txt
@@ -3,8 +3,8 @@ add_llvm_component_group(SPIRV)
set(LLVM_TARGET_DEFINITIONS SPIRV.td)
tablegen(LLVM SPIRVGenAsmWriter.inc -gen-asm-writer)
-tablegen(LLVM SPIRVGenGlobalISel.inc -gen-global-isel)
-tablegen(LLVM SPIRVGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM SPIRVGenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM SPIRVGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM SPIRVGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM SPIRVGenRegisterBank.inc -gen-register-bank)
tablegen(LLVM SPIRVGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/Sparc/CMakeLists.txt b/llvm/lib/Target/Sparc/CMakeLists.txt
index bf76ed9d671b97..abf0e3c264c6ff 100644
--- a/llvm/lib/Target/Sparc/CMakeLists.txt
+++ b/llvm/lib/Target/Sparc/CMakeLists.txt
@@ -5,9 +5,9 @@ set(LLVM_TARGET_DEFINITIONS Sparc.td)
tablegen(LLVM SparcGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM SparcGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM SparcGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM SparcGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM SparcGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM SparcGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM SparcGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM SparcGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM SparcGenSearchableTables.inc -gen-searchable-tables)
diff --git a/llvm/lib/Target/SystemZ/CMakeLists.txt b/llvm/lib/Target/SystemZ/CMakeLists.txt
index 063e5bcd44171e..2e81812b1f7da2 100644
--- a/llvm/lib/Target/SystemZ/CMakeLists.txt
+++ b/llvm/lib/Target/SystemZ/CMakeLists.txt
@@ -5,9 +5,9 @@ set(LLVM_TARGET_DEFINITIONS SystemZ.td)
tablegen(LLVM SystemZGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM SystemZGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM SystemZGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM SystemZGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM SystemZGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM SystemZGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM SystemZGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM SystemZGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM SystemZGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM SystemZGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM SystemZGenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/VE/CMakeLists.txt b/llvm/lib/Target/VE/CMakeLists.txt
index 76684d39450d8b..b4e43ef2080c11 100644
--- a/llvm/lib/Target/VE/CMakeLists.txt
+++ b/llvm/lib/Target/VE/CMakeLists.txt
@@ -3,12 +3,12 @@ add_llvm_component_group(VE)
set(LLVM_TARGET_DEFINITIONS VE.td)
tablegen(LLVM VEGenRegisterInfo.inc -gen-register-info)
-tablegen(LLVM VEGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM VEGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM VEGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM VEGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM VEGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM VEGenAsmMatcher.inc -gen-asm-matcher)
-tablegen(LLVM VEGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM VEGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM VEGenSubtargetInfo.inc -gen-subtarget)
tablegen(LLVM VEGenCallingConv.inc -gen-callingconv)
add_public_tablegen_target(VECommonTableGen)
diff --git a/llvm/lib/Target/WebAssembly/CMakeLists.txt b/llvm/lib/Target/WebAssembly/CMakeLists.txt
index 1e83cbeac50d6d..9a5574ce0c561b 100644
--- a/llvm/lib/Target/WebAssembly/CMakeLists.txt
+++ b/llvm/lib/Target/WebAssembly/CMakeLists.txt
@@ -4,10 +4,10 @@ set(LLVM_TARGET_DEFINITIONS WebAssembly.td)
tablegen(LLVM WebAssemblyGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM WebAssemblyGenAsmWriter.inc -gen-asm-writer)
-tablegen(LLVM WebAssemblyGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM WebAssemblyGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM WebAssemblyGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM WebAssemblyGenFastISel.inc -gen-fast-isel)
-tablegen(LLVM WebAssemblyGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM WebAssemblyGenFastISel.inc -gen-fast-isel ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM WebAssemblyGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM WebAssemblyGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM WebAssemblyGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM WebAssemblyGenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/X86/CMakeLists.txt b/llvm/lib/Target/X86/CMakeLists.txt
index 9553a8619feb51..2065dd118e7bfd 100644
--- a/llvm/lib/Target/X86/CMakeLists.txt
+++ b/llvm/lib/Target/X86/CMakeLists.txt
@@ -6,14 +6,15 @@ tablegen(LLVM X86GenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM X86GenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
tablegen(LLVM X86GenCallingConv.inc -gen-callingconv)
-tablegen(LLVM X86GenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM X86GenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM X86GenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM X86GenInstrMapping.inc -gen-x86-instr-mapping)
tablegen(LLVM X86GenExegesis.inc -gen-exegesis)
-tablegen(LLVM X86GenFastISel.inc -gen-fast-isel)
-tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM X86GenFastISel.inc -gen-fast-isel ${ENABLED_INTRINSIC_TARGETS})
+tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM X86GenInstrInfo.inc -gen-instr-info
- -instr-info-expand-mi-operand-info=0)
+ -instr-info-expand-mi-operand-info=0
+ ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM X86GenMnemonicTables.inc -gen-x86-mnemonic-tables -asmwriternum=1)
tablegen(LLVM X86GenRegisterBank.inc -gen-register-bank)
tablegen(LLVM X86GenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/X86/X86IntrinsicsInfo.h b/llvm/lib/Target/X86/X86IntrinsicsInfo.h
index 86fd04046d16a0..f5477ec2f81315 100644
--- a/llvm/lib/Target/X86/X86IntrinsicsInfo.h
+++ b/llvm/lib/Target/X86/X86IntrinsicsInfo.h
@@ -79,8 +79,7 @@ enum IntrinsicType : uint16_t {
};
struct IntrinsicData {
-
- uint16_t Id;
+ unsigned Id;
IntrinsicType Type;
uint16_t Opc0;
uint16_t Opc1;
diff --git a/llvm/lib/Target/XCore/CMakeLists.txt b/llvm/lib/Target/XCore/CMakeLists.txt
index 447f5c54528850..54a55c4a42a422 100644
--- a/llvm/lib/Target/XCore/CMakeLists.txt
+++ b/llvm/lib/Target/XCore/CMakeLists.txt
@@ -4,9 +4,9 @@ set(LLVM_TARGET_DEFINITIONS XCore.td)
tablegen(LLVM XCoreGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM XCoreGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM XCoreGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM XCoreGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM XCoreGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM XCoreGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM XCoreGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM XCoreGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM XCoreGenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt
index 726efadc87c0b2..5d3dd7b09e7308 100644
--- a/llvm/lib/Target/Xtensa/CMakeLists.txt
+++ b/llvm/lib/Target/Xtensa/CMakeLists.txt
@@ -5,9 +5,9 @@ set(LLVM_TARGET_DEFINITIONS Xtensa.td)
tablegen(LLVM XtensaGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM XtensaGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM XtensaGenCallingConv.inc -gen-callingconv)
-tablegen(LLVM XtensaGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM XtensaGenDAGISel.inc -gen-dag-isel ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM XtensaGenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM XtensaGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM XtensaGenInstrInfo.inc -gen-instr-info ${ENABLED_INTRINSIC_TARGETS})
tablegen(LLVM XtensaGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM XtensaGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM XtensaGenSubtargetInfo.inc -gen-subtarget)
diff --git a/llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll b/llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll
index 905e7eea9f49ee..5734fc65e14fec 100644
--- a/llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll
+++ b/llvm/test/Analysis/CtxProfAnalysis/full-cycle.ll
@@ -1,4 +1,5 @@
; REQUIRES: x86_64-linux
+; REQUIRES: x86-registered-target
;
; RUN: rm -rf %t
; RUN: split-file %s %t
diff --git a/llvm/test/Analysis/DXILResource/buffer-frombinding.ll b/llvm/test/Analysis/DXILResource/buffer-frombinding.ll
index b26a185423597d..ece1e7b60e6d14 100644
--- a/llvm/test/Analysis/DXILResource/buffer-frombinding.ll
+++ b/llvm/test/Analysis/DXILResource/buffer-frombinding.ll
@@ -1,3 +1,4 @@
+; REQUIRES: dx-registered-target
; RUN: opt -S -disable-output -passes="print<dxil-resource>" < %s 2>&1 | FileCheck %s
@G = external constant <4 x float>, align 4
diff --git a/llvm/test/Analysis/MemorySSA/pr36883.ll b/llvm/test/Analysis/MemorySSA/pr36883.ll
index 329026beb2895d..0a1c0b600ec1de 100644
--- a/llvm/test/Analysis/MemorySSA/pr36883.ll
+++ b/llvm/test/Analysis/MemorySSA/pr36883.ll
@@ -1,3 +1,4 @@
+; REQUIRES: arm-registered-target
; RUN: opt -aa-pipeline=basic-aa -passes='print<memoryssa>,verify<memoryssa>' -S < %s 2>&1 | FileCheck %s
;
; We weren't properly considering the args in callsites in equality or hashing.
diff --git a/llvm/test/Analysis/ValueTracking/aarch64.irg.ll b/llvm/test/Analysis/ValueTracking/aarch64.irg.ll
index cef2e9edff3409..8db930373702cd 100644
--- a/llvm/test/Analysis/ValueTracking/aarch64.irg.ll
+++ b/llvm/test/Analysis/ValueTracking/aarch64.irg.ll
@@ -1,3 +1,4 @@
+; REQUIRES: aarch64-registered-target
; RUN: opt -S -passes=instsimplify,instcombine < %s | FileCheck %s
; CHECK-LABEL: define void @checkNonnullIrg()
diff --git a/llvm/test/Analysis/ValueTracking/knownbits-x86-hadd-hsub.ll b/llvm/test/Analysis/ValueTracking/knownbits-x86-hadd-hsub.ll
index e2fe873d715cd6..d41033b2a33aca 100644
--- a/llvm/test/Analysis/ValueTracking/knownbits-x86-hadd-hsub.ll
+++ b/llvm/test/Analysis/ValueTracking/knownbits-x86-hadd-hsub.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; REQUIRES: x86-registered-target
; RUN: opt -S -passes=instcombine < %s | FileCheck %s
define <4 x i1> @hadd_and_eq_v4i32(<4 x i32> %x, <4 x i32> %y) {
diff --git a/llvm/test/Assembler/amdgpu-image-atomic-attributes.ll b/llvm/test/Assembler/amdgpu-image-atomic-attributes.ll
index bc03908d5f218b..abe06c6fd872f7 100644
--- a/llvm/test/Assembler/amdgpu-image-atomic-attributes.ll
+++ b/llvm/test/Assembler/amdgpu-image-atomic-attributes.ll
@@ -1,3 +1,4 @@
+; REQUIRES: amdgpu-registered-target
; RUN: opt -S -mtriple=amdgcn-unknown-unknown < %s | FileCheck %s
define amdgpu_ps float @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
diff --git a/llvm/test/Assembler/autoupgrade-wasm-intrinsics.ll b/llvm/test/Assembler/autoupgrade-wasm-intrinsics.ll
index 012fa1dfe7e281..89674ff5dc8a41 100644
--- a/llvm/test/Assembler/autoupgrade-wasm-intrinsics.ll
+++ b/llvm/test/Assembler/autoupgrade-wasm-intrinsics.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; REQUIRES: wasm-registered-target
; RUN: opt -S < %s | FileCheck %s
define <16 x i8> @test_laneselect(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
diff --git a/llvm/test/Assembler/opaque-ptr-intrinsic-remangling.ll b/llvm/test/Assembler/opaque-ptr-intrinsic-remangling.ll
index 070bcd40438df2..431f00a1843371 100644
--- a/llvm/test/Assembler/opaque-ptr-intrinsic-remangling.ll
+++ b/llvm/test/Assembler/opaque-ptr-intrinsic-remangling.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; REQUIRES: wasm-registered-target
; RUN: opt -S < %s | FileCheck %s
; Make sure that opaque pointer intrinsic remangling upgrade works.
diff --git a/llvm/test/Bitcode/aarch64-addp-upgrade.ll b/llvm/test/Bitcode/aarch64-addp-upgrade.ll
index 4e78996aa0b636..29c36edfe41602 100644
--- a/llvm/test/Bitcode/aarch64-addp-upgrade.ll
+++ b/llvm/test/Bitcode/aarch64-addp-upgrade.ll
@@ -1,3 +1,4 @@
+; REQUIRES: aarch64-registered-target
; RUN: llvm-dis %p/aarch64-addp-upgrade.bc -o - | FileCheck %s
; Bitcode was generated from file below, which may or may not even assemble any
diff --git a/llvm/test/Bitcode/aarch64-bf16-upgrade.ll b/llvm/test/Bitcode/aarch64-bf16-upgrade.ll
index a1ae9f172994d0..d888df03c14817 100644
--- a/llvm/test/Bitcode/aarch64-bf16-upgrade.ll
+++ b/llvm/test/Bitcode/aarch64-bf16-upgrade.ll
@@ -1,3 +1,4 @@
+; REQUIRES: aarch64-registered-target
; RUN: llvm-dis < %s.bc | FileCheck %s
; Bitcode was generated from file below
diff --git a/llvm/test/Bitcode/arm-bf16-upgrade.ll b/llvm/test/Bitcode/arm-bf16-upgrade.ll
index a8ee8e4ac7e50b..f7b4d09d63e563 100644
--- a/llvm/test/Bitcode/arm-bf16-upgrade.ll
+++ b/llvm/test/Bitcode/arm-bf16-upgrade.ll
@@ -1,3 +1,4 @@
+; REQUIRES: arm-registered-target
; RUN: llvm-dis < %s.bc | FileCheck %s
; Bitcode was generated from file below
diff --git a/llvm/test/Bitcode/arm-intrinsics.ll b/llvm/test/Bitcode/arm-intrinsics.ll
index be52c59b5518b5..c22421937f1138 100644
--- a/llvm/test/Bitcode/arm-intrinsics.ll
+++ b/llvm/test/Bitcode/arm-intrinsics.ll
@@ -1,3 +1,4 @@
+; REQUIRES: arm-registered-target
; RUN: llvm-dis < %S/arm-intrinsics.bc | FileCheck %s
define void @f(i32* %p) {
diff --git a/llvm/test/Bitcode/intrinsics-struct-upgrade-attributes.ll b/llvm/test/Bitcode/intrinsics-struct-upgrade-attributes.ll
index 4962144899ae4b..6d98d34edd81aa 100644
--- a/llvm/test/Bitcode/intrinsics-struct-upgrade-attributes.ll
+++ b/llvm/test/Bitcode/intrinsics-struct-upgrade-attributes.ll
@@ -1,3 +1,4 @@
+; REQUIRES: aarch64-registered-target
; RUN: llvm-as < %s | llvm-dis | FileCheck %s
%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
diff --git a/llvm/test/Bitcode/intrinsics-struct-upgrade.ll b/llvm/test/Bitcode/intrinsics-struct-upgrade.ll
index e7e944ed131215..bc9adf2ecb9658 100644
--- a/llvm/test/Bitcode/intrinsics-struct-upgrade.ll
+++ b/llvm/test/Bitcode/intrinsics-struct-upgrade.ll
@@ -1,3 +1,4 @@
+; REQUIRES: aarch64-registered-target
; RUN: llvm-dis < %s.bc | FileCheck %s
%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
diff --git a/llvm/test/Bitcode/ptest-new.ll b/llvm/test/Bitcode/ptest-new.ll
index 952ea795d62fb5..ab2383694761f2 100644
--- a/llvm/test/Bitcode/ptest-new.ll
+++ b/llvm/test/Bitcode/ptest-new.ll
@@ -1,4 +1,5 @@
; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+; REQUIRES: x86-registered-target
; RUN: verify-uselistorder < %s
define i32 @foo(<2 x i64> %bar) nounwind {
diff --git a/llvm/test/Bitcode/upgrade-aarch64-ldstxr.ll b/llvm/test/Bitcode/upgrade-aarch64-ldstxr.ll
index cd5f32ec68e4e5..714b1e8a789fb1 100644
--- a/llvm/test/Bitcode/upgrade-aarch64-ldstxr.ll
+++ b/llvm/test/Bitcode/upgrade-aarch64-ldstxr.ll
@@ -1,3 +1,4 @@
+; REQUIRES: aarch64-registered-target
; RUN: llvm-dis < %S/upgrade-aarch64-ldstxr.bc | FileCheck %s
define void @f(i32* %p) {
diff --git a/llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll b/llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll
index a97ed0a9851e5f..75d970da5001e2 100644
--- a/llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll
+++ b/llvm/test/Bitcode/upgrade-aarch64-sve-intrinsics.ll
@@ -1,3 +1,4 @@
+; REQUIRES: aarch64-registered-target
; RUN: llvm-as %s -o - | llvm-dis - | FileCheck %s
define <vscale x 32 x i8> @ld2.nxv32i8(<vscale x 16 x i1> %Pg, i8 *%base_ptr) {
diff --git a/llvm/test/CodeGen/AArch64/arm64-vshift.ll b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
index 1dfd977186b0e7..bbecef7397f97c 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vshift.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; REQUIRES: aarch64-registered-target
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -enable-misched=false | FileCheck %s
define <8 x i8> @sqshl8b(ptr %A, ptr %B) nounwind {
diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll
index 4cc038f03ff2c3..5ca11cc0ca6630 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vshift.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --tool opt --version 4
;
+; REQUIRES: aarch64-registered-target
; RUN: opt < %s -passes=msan -S | FileCheck %s
;
; Forked from llvm/test/CodeGen/AArch64/arm64-vshift.ll
diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst.ll
index 421f00fcbc56bf..01a38af2fb7ad5 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
; Test memory sanitizer instrumentation for Arm NEON VST instructions.
;
+; REQUIRES: aarch64-registered-target
; RUN: opt < %s -passes=msan -S | FileCheck %s
;
; Forked from llvm/test/CodeGen/AArch64/arm64-st1.ll
diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_float.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_float.ll
index 8fed5a78d6b79f..cd2bb501837e6b 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_float.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_float.ll
@@ -3,6 +3,7 @@
; Test memory sanitizer instrumentation for Arm NEON VST_{2,3,4} and
; VST_1x{2,3,4} instructions, including floating-point parameters.
;
+; REQUIRES: aarch64-registered-target
; RUN: opt < %s -passes=msan -S | FileCheck %s
;
; Generated with:
diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_lane.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_lane.ll
index 9ed364df3e677f..6e888531653e8c 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_lane.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_lane.ll
@@ -3,6 +3,7 @@
; Test memory sanitizer instrumentation for Arm store with lane instructions.
; Note: st{2,3,4}lane uses Arm NEON but st1lane does not.
;
+; REQUIRES: aarch64-registered-target
; RUN: opt < %s -passes=msan -S | FileCheck %s
;
; Forked from llvm/test/CodeGen/AArch64/arm64-st1.ll
diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_origins.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_origins.ll
index 52283811e30653..2791b1f9588d71 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_origins.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/neon_vst_origins.ll
@@ -3,6 +3,7 @@
; origin tracking. These tests are deliberately shorter than neon_vst.ll, due
; to the verbosity of the output.
;
+; REQUIRES: aarch64-registered-target
; RUN: opt < %s -passes=msan -msan-track-origins=2 -S | FileCheck %s
;
; Forked from llvm/test/CodeGen/AArch64/arm64-st1.ll
diff --git a/llvm/test/TableGen/ContextlessPredicates.td b/llvm/test/TableGen/ContextlessPredicates.td
index eead9655111e68..d80da7b8d633a8 100644
--- a/llvm/test/TableGen/ContextlessPredicates.td
+++ b/llvm/test/TableGen/ContextlessPredicates.td
@@ -1,6 +1,6 @@
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/context-non-optimized.cpp
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/context-non-optimized.cpp
// RUN: FileCheck %s --check-prefixes=CHECK_NOPT -input-file=%T/context-non-optimized.cpp
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true %s -o %T/context-optimized.cpp
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common -optimize-match-table=true %s -o %T/context-optimized.cpp
// RUN: FileCheck %s --check-prefixes=CHECK_OPT -input-file=%T/context-optimized.cpp
diff --git a/llvm/test/TableGen/DAGDefaultOps.td b/llvm/test/TableGen/DAGDefaultOps.td
index 70c8413f2c053a..0ff4b8828a6039 100644
--- a/llvm/test/TableGen/DAGDefaultOps.td
+++ b/llvm/test/TableGen/DAGDefaultOps.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s -o %t
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include %s -o %t
// RUN: FileCheck --check-prefix=ADD %s < %t
// RUN: FileCheck --check-prefix=ADDINT %s < %t
// RUN: FileCheck --check-prefix=SUB %s < %t
diff --git a/llvm/test/TableGen/DefaultOpsGlobalISel.td b/llvm/test/TableGen/DefaultOpsGlobalISel.td
index 8f4176a2aa730b..5dc2e0645f1be2 100644
--- a/llvm/test/TableGen/DefaultOpsGlobalISel.td
+++ b/llvm/test/TableGen/DefaultOpsGlobalISel.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: llvm-tblgen %s -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/DuplicateFieldValues.td b/llvm/test/TableGen/DuplicateFieldValues.td
index 50c77fa88ccecc..d07bb121a73d39 100644
--- a/llvm/test/TableGen/DuplicateFieldValues.td
+++ b/llvm/test/TableGen/DuplicateFieldValues.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s
+// RUN: llvm-tblgen -gen-instr-info --enabled-targets=all -I %p/../../include %s | FileCheck %s
// CHECK: ABCForm_A
// CHECK-NOT: ABCForm_A
diff --git a/llvm/test/TableGen/FastISelEmitter.td b/llvm/test/TableGen/FastISelEmitter.td
index d5fea8dd1e0c0d..980601afa036f3 100644
--- a/llvm/test/TableGen/FastISelEmitter.td
+++ b/llvm/test/TableGen/FastISelEmitter.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen --gen-fast-isel -I %p/../../include %s 2>&1 | FileCheck %s
+// RUN: llvm-tblgen --gen-fast-isel --enabled-targets=all -I %p/../../include %s 2>&1 | FileCheck %s
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
index 365d0c9fbff494..8d96f703f97892 100644
--- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
+++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
@@ -36,7 +36,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4([[L72:[0-9]+]]), // Rule ID 0 //
// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled),
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
-// CHECK-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::1in_1out),
+// CHECK-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode4(Intrinsic::1in_1out),
// CHECK-NEXT: // MIs[0] a
// CHECK-NEXT: // No operand predicates
// CHECK-NEXT: // MIs[0] Operand 2
@@ -45,10 +45,10 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: // Combiner Rule #0: IntrinTest0
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC),
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
-// CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/0, GIMT_Encode2(Intrinsic::0in_1out),
+// CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/0, GIMT_Encode4(Intrinsic::0in_1out),
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a
-// CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/1, GIMT_Encode2(Intrinsic::1in_1out),
+// CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/1, GIMT_Encode4(Intrinsic::1in_1out),
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
// CHECK-NEXT: // Label 3: @[[L72]]
@@ -57,7 +57,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4([[L131:[0-9]+]]), // Rule ID 1 //
// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule1Enabled),
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
-// CHECK-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::sideeffects_1in_1out),
+// CHECK-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode4(Intrinsic::sideeffects_1in_1out),
// CHECK-NEXT: // MIs[0] a
// CHECK-NEXT: // No operand predicates
// CHECK-NEXT: // MIs[0] b
@@ -66,11 +66,11 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: // Combiner Rule #1: SpecialIntrins
// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC_CONVERGENT),
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
-// CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/0, GIMT_Encode2(Intrinsic::convergent_1in_1out),
+// CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/0, GIMT_Encode4(Intrinsic::convergent_1in_1out),
// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // b
// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS),
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a
-// CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/1, GIMT_Encode2(Intrinsic::convergent_sideeffects_1in_1out),
+// CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/1, GIMT_Encode4(Intrinsic::convergent_sideeffects_1in_1out),
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
// CHECK-NEXT: GIR_EraseRootFromParent_Done,
@@ -78,6 +78,6 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
// CHECK-NEXT: GIM_Reject,
// CHECK-NEXT: // Label 2: @[[L132]]
// CHECK-NEXT: GIM_Reject,
-// CHECK-NEXT: }; // Size: 125 bytes
+// CHECK-NEXT: }; // Size: 137 bytes
// CHECK-NEXT: return MatchTable0;
// CHECK-NEXT: }
diff --git a/llvm/test/TableGen/GlobalISelEmitter-PR39045.td b/llvm/test/TableGen/GlobalISelEmitter-PR39045.td
index 5407222121bb3a..6ee7e286d8da14 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-PR39045.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-PR39045.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o %t
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common %s -o %t
// RUN: FileCheck %s < %t
// Both predicates should be tested
diff --git a/llvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td b/llvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td
index 8d6dedf2f920ce..4bdd6cf4c165f4 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
@@ -19,7 +19,7 @@ def SLEEP : I<(outs), (ins i32imm:$src0), []>;
def FOO : I<(outs GPR32:$dst), (ins GPR32:$src0, i32imm:$src1), []>;
// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
-// GISEL: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mytarget_foo),
+// GISEL: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode4(Intrinsic::mytarget_foo),
// GISEL: GIM_CheckIsImm, /*MI*/0, /*Op*/3,
// GISEL: GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderShiftImml1), // src1
def : Pat<
@@ -28,7 +28,7 @@ def : Pat<
>;
// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
-// GISEL: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mytarget_sleep),
+// GISEL: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode4(Intrinsic::mytarget_sleep),
// GISEL: GIM_CheckIsImm, /*MI*/0, /*Op*/1,
// GISEL: GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*OperandRenderer*/GIMT_Encode2(GICR_renderShiftImml1), // src0
def : Pat<
diff --git a/llvm/test/TableGen/GlobalISelEmitter-atomic_store.td b/llvm/test/TableGen/GlobalISelEmitter-atomic_store.td
index da2dfe8004289d..1aaa6368a51252 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-atomic_store.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-atomic_store.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-frameindex.td b/llvm/test/TableGen/GlobalISelEmitter-frameindex.td
index 232691465bb3bd..6b449661bba9df 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-frameindex.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-frameindex.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td b/llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td
index 0125aa5c30fa6d..6c6a4171620894 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td
@@ -1,5 +1,5 @@
-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-NOOPT %s
-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=true -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-OPT %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-NOOPT %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -warn-on-skipped-patterns -optimize-match-table=true -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-OPT %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td b/llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td
index 6b4012eb736cb3..07ee678ed6597a 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
@@ -23,7 +23,7 @@ def CAT1 : I<(outs GPR32:$dst), (ins GPR32:$src0), []>;
// Make sure there is no type check.
// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
-// GISEL: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mytarget_sleep),
+// GISEL: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode4(Intrinsic::mytarget_sleep),
// GISEL-NEXT: // MIs[0] Operand 1
// GISEL-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(0),
def : Pat<
@@ -32,7 +32,7 @@ def : Pat<
>;
// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
-// GISEL: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mytarget_sleep),
+// GISEL: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode4(Intrinsic::mytarget_sleep),
// GISEL-NEXT: // MIs[0] Operand 1
// GISEL-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(1),
def : Pat<
diff --git a/llvm/test/TableGen/GlobalISelEmitter-input-discard.td b/llvm/test/TableGen/GlobalISelEmitter-input-discard.td
index 202ff4a5758d7f..bb99a1e782dfa3 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-input-discard.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-input-discard.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
@@ -10,7 +10,7 @@ def FOO : I<(outs GPR32:$dst), (ins GPR32Op:$src0, GPR32Op:$src1), []>;
// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
// GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
-// GISEL-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::tgt_foo),
+// GISEL-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode4(Intrinsic::tgt_foo),
// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
// GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
// GISEL-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
diff --git a/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td b/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td
index 2d968bebbc65e0..9c2c2aac4d6e6b 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td b/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td
index dea3b549607170..ea9545301a273e 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td b/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
index 25a39a40da6188..3c26d2785b385f 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false --enabled-targets=all -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td b/llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td
index 622d7fa1f7955c..55017117409498 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s | FileCheck %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common %s | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-output-discard.td b/llvm/test/TableGen/GlobalISelEmitter-output-discard.td
index 7a0242d9a99243..bad3524c0bb2fd 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-output-discard.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-output-discard.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-setcc.td b/llvm/test/TableGen/GlobalISelEmitter-setcc.td
index 38add7627f5030..b72341f6d16989 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-setcc.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-setcc.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - 2> %t < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - 2> %t < %s | FileCheck -check-prefix=GISEL %s
// RUN: FileCheck -DFILE=%s -check-prefix=ERR %s < %t
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-zero-instr.td b/llvm/test/TableGen/GlobalISelEmitter-zero-instr.td
index c8a8cab2b65232..71fe36caa85257 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-zero-instr.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-zero-instr.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o /dev/null --warn-on-skipped-patterns 2>&1 < %s 2>&1 | FileCheck %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include -I %p/Common %s -o /dev/null --warn-on-skipped-patterns 2>&1 < %s 2>&1 | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td b/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td
index ddf02240ee1f8b..47b5b1ef367906 100644
--- a/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td
+++ b/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter.td
index 7dbaf4390c0f70..b1758aeb1a86c3 100644
--- a/llvm/test/TableGen/GlobalISelEmitter.td
+++ b/llvm/test/TableGen/GlobalISelEmitter.td
@@ -1,6 +1,6 @@
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/non-optimized.cpp
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true %s -o %T/optimized.cpp
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o %T/default.cpp
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/non-optimized.cpp
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common -optimize-match-table=true %s -o %T/optimized.cpp
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common %s -o %T/default.cpp
// RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19N -input-file=%T/non-optimized.cpp
// RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19O -input-file=%T/optimized.cpp
@@ -513,7 +513,7 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3),
// R00O-NEXT: GIM_Reject,
// R00O: // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
// R00O-NEXT: GIM_Reject,
-// R00O-NEXT: }; // Size: 1832 bytes
+// R00O-NEXT: }; // Size: 1834 bytes
def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, GPR32:$src4),
[(set GPR32:$dst,
@@ -534,7 +534,7 @@ def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, G
// R01C-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // Rule ID 1 //
// R01C-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
//
-// R01O-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mytarget_nop),
+// R01O-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode4(Intrinsic::mytarget_nop),
// R01O-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
// R01O-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
// R01O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
@@ -544,7 +544,7 @@ def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, G
// R01N-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
// R01N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// R01N-NEXT: // MIs[0] Operand 1
-// R01N-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mytarget_nop),
+// R01N-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode4(Intrinsic::mytarget_nop),
// R01N-NEXT: // MIs[0] src1
// R01N-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
//
@@ -1206,5 +1206,5 @@ def BR : I<(outs), (ins unknown:$target),
[(br bb:$target)]>;
// NOOPT-NEXT: GIM_Reject,
-// NOOPT-NEXT: }; // Size: 1459 bytes
+// NOOPT-NEXT: }; // Size: 1461 bytes
// NOOPT-NEXT: return MatchTable0;
diff --git a/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td b/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td
index 3ceadf32f06425..0f18c72e3d9f92 100644
--- a/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td
+++ b/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: llvm-tblgen %s -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
// Verify that all MI predicates are enumerated.
//
diff --git a/llvm/test/TableGen/GlobalISelEmitterFlags.td b/llvm/test/TableGen/GlobalISelEmitterFlags.td
index fa8f2a79fbce89..001d48a1abe8c8 100644
--- a/llvm/test/TableGen/GlobalISelEmitterFlags.td
+++ b/llvm/test/TableGen/GlobalISelEmitterFlags.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: llvm-tblgen %s -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitterHwModes.td b/llvm/test/TableGen/GlobalISelEmitterHwModes.td
index 9d235f5f07a74b..c8df4f46ff8807 100644
--- a/llvm/test/TableGen/GlobalISelEmitterHwModes.td
+++ b/llvm/test/TableGen/GlobalISelEmitterHwModes.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/hwmode-non-optimized.cpp
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/hwmode-non-optimized.cpp
// RUN: FileCheck %s --check-prefixes=CHECK -input-file=%T/hwmode-non-optimized.cpp
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td
index 3db31bea8612ee..ca71ec41bd4db8 100644
--- a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td
+++ b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: llvm-tblgen %s -gen-global-isel --enabled-targets=all -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td
index d93805b612a19e..d612f3e5c29e47 100644
--- a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td
+++ b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: llvm-tblgen %s -gen-global-isel --enabled-targets=all -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td
index 1ac33990ab3b10..a2a2a8b6da07ec 100644
--- a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td
+++ b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: llvm-tblgen %s -gen-global-isel --enabled-targets=all -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td b/llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td
index 422edbba0e7a0f..aa377253373deb 100644
--- a/llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td
+++ b/llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common %s -o - | FileCheck %s
// Boilerplate code.
include "llvm/Target/Target.td"
@@ -11,7 +11,7 @@ let TargetPrefix = "mytarget" in {
// Ensure that llvm_anyptr_ty on an intrinsic results in a
// GIM_CheckPointerToAny rather than a GIM_CheckType.
//
-// CHECK: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mytarget_anyptr),
+// CHECK: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode4(Intrinsic::mytarget_anyptr),
// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
// CHECK-NEXT: // MIs[0] src
diff --git a/llvm/test/TableGen/GlobalISelEmitterRegSequence.td b/llvm/test/TableGen/GlobalISelEmitterRegSequence.td
index 3829070b28efeb..019f279d3fed4a 100644
--- a/llvm/test/TableGen/GlobalISelEmitterRegSequence.td
+++ b/llvm/test/TableGen/GlobalISelEmitterRegSequence.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
+// RUN: llvm-tblgen %s -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td b/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
index fc8abc6fbc547e..5c4808b44d61c9 100644
--- a/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
+++ b/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
@@ -1,5 +1,5 @@
-// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -I %p/Common -o /dev/null 2>&1 | FileCheck %s
-// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -I %p/Common -o /dev/null -DIGNORE 2>&1 | FileCheck --allow-empty --check-prefix=IGNORED %s
+// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel --enabled-targets=all -I %p/../../include %s -I %p/Common -o /dev/null 2>&1 | FileCheck %s
+// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel --enabled-targets=all -I %p/../../include %s -I %p/Common -o /dev/null -DIGNORE 2>&1 | FileCheck --allow-empty --check-prefix=IGNORED %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitterSubreg.td b/llvm/test/TableGen/GlobalISelEmitterSubreg.td
index 8df3238f6cc21e..8d2796dd4f1707 100644
--- a/llvm/test/TableGen/GlobalISelEmitterSubreg.td
+++ b/llvm/test/TableGen/GlobalISelEmitterSubreg.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen %s -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common -o - 2> %t.skipped | FileCheck %s
+// RUN: llvm-tblgen %s -gen-global-isel --enabled-targets=all -warn-on-skipped-patterns -I %p/../../include -I %p/Common -o - 2> %t.skipped | FileCheck %s
// RUN: cat %t.skipped | FileCheck %s --check-prefix=SKIPPED
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/GlobalISelEmitterVariadic.td b/llvm/test/TableGen/GlobalISelEmitterVariadic.td
index 992e1a4b907c30..630c7b501b813b 100644
--- a/llvm/test/TableGen/GlobalISelEmitterVariadic.td
+++ b/llvm/test/TableGen/GlobalISelEmitterVariadic.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common %s -o - | FileCheck %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/HasNoUse.td b/llvm/test/TableGen/HasNoUse.td
index 6e6bcc2a81df70..24965f7e2bf524 100644
--- a/llvm/test/TableGen/HasNoUse.td
+++ b/llvm/test/TableGen/HasNoUse.td
@@ -1,5 +1,5 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=SDAG %s
-// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=SDAG %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/RelTest.td b/llvm/test/TableGen/RelTest.td
index dc8b4e559f1904..7bf04578006755 100644
--- a/llvm/test/TableGen/RelTest.td
+++ b/llvm/test/TableGen/RelTest.td
@@ -1,4 +1,4 @@
-// RUN: not llvm-tblgen -gen-instr-info -I %p/../../include %s 2>&1 | FileCheck %s
+// RUN: not llvm-tblgen -gen-instr-info --enabled-targets=all -I %p/../../include %s 2>&1 | FileCheck %s
// This test verifies that TableGen is displaying an error when mapped instruction
// does not contain a field listed under RowFields.
diff --git a/llvm/test/TableGen/address-space-patfrags.td b/llvm/test/TableGen/address-space-patfrags.td
index 582b97d55a5185..da422c456111c3 100644
--- a/llvm/test/TableGen/address-space-patfrags.td
+++ b/llvm/test/TableGen/address-space-patfrags.td
@@ -1,5 +1,5 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck -check-prefix=SDAG %s
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include %s 2>&1 | FileCheck -check-prefix=SDAG %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/dag-isel-complexpattern.td b/llvm/test/TableGen/dag-isel-complexpattern.td
index b8f517a1fc2890..704724c8302c70 100644
--- a/llvm/test/TableGen/dag-isel-complexpattern.td
+++ b/llvm/test/TableGen/dag-isel-complexpattern.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
index c41a19e97e763d..de2153ce6c51f5 100644
--- a/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
+++ b/llvm/test/TableGen/dag-isel-regclass-emit-enum.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/dag-isel-res-order.td b/llvm/test/TableGen/dag-isel-res-order.td
index 6937dd8c6b807c..e025ac51afb55f 100644
--- a/llvm/test/TableGen/dag-isel-res-order.td
+++ b/llvm/test/TableGen/dag-isel-res-order.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/dag-isel-subregs.td b/llvm/test/TableGen/dag-isel-subregs.td
index 52ac0377bd2c9f..6a11b435a937c0 100644
--- a/llvm/test/TableGen/dag-isel-subregs.td
+++ b/llvm/test/TableGen/dag-isel-subregs.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s | FileCheck %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -I %p/Common %s | FileCheck %s
include "reg-with-subregs-common.td"
diff --git a/llvm/test/TableGen/def-multiple-operands.td b/llvm/test/TableGen/def-multiple-operands.td
index b747c58907505a..b20a4d63871acb 100644
--- a/llvm/test/TableGen/def-multiple-operands.td
+++ b/llvm/test/TableGen/def-multiple-operands.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s
+// RUN: llvm-tblgen -gen-instr-info --enabled-targets=all -I %p/../../include %s | FileCheck %s
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/get-operand-type-no-expand.td b/llvm/test/TableGen/get-operand-type-no-expand.td
index 9dfcbfaec76af1..d090675877682d 100644
--- a/llvm/test/TableGen/get-operand-type-no-expand.td
+++ b/llvm/test/TableGen/get-operand-type-no-expand.td
@@ -30,7 +30,7 @@ def InstA : Instruction {
}
// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s \
-// RUN: -instr-info-expand-mi-operand-info=1 \
+// RUN: -instr-info-expand-mi-operand-info=1 --enabled-targets=all \
// RUN: | FileCheck %s --check-prefix=CHECK-EXPAND
// CHECK-EXPAND: #ifdef GET_INSTRINFO_OPERAND_TYPE
// CHECK-EXPAND: OpcodeOperandTypes[] = {
@@ -39,7 +39,7 @@ def InstA : Instruction {
// CHECK-EXPAND: #endif // GET_INSTRINFO_OPERAND_TYPE
// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s \
-// RUN: -instr-info-expand-mi-operand-info=0 \
+// RUN: -instr-info-expand-mi-operand-info=0 --enabled-targets=all \
// RUN: | FileCheck %s --check-prefix=CHECK-NOEXPAND
// CHECK-NOEXPAND: #ifdef GET_INSTRINFO_OPERAND_TYPE
// CHECK-NOEXPAND: OpcodeOperandTypes[] = {
diff --git a/llvm/test/TableGen/get-operand-type.td b/llvm/test/TableGen/get-operand-type.td
index 6ebda5cffe8af0..438ce5fa243981 100644
--- a/llvm/test/TableGen/get-operand-type.td
+++ b/llvm/test/TableGen/get-operand-type.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s
+// RUN: llvm-tblgen -gen-instr-info --enabled-targets=all -I %p/../../include %s | FileCheck %s
// Check that getOperandType has the expected info in it
diff --git a/llvm/test/TableGen/gisel-physreg-input.td b/llvm/test/TableGen/gisel-physreg-input.td
index f19872a331fc89..1a707db28a8b86 100644
--- a/llvm/test/TableGen/gisel-physreg-input.td
+++ b/llvm/test/TableGen/gisel-physreg-input.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
diff --git a/llvm/test/TableGen/immarg-predicated.td b/llvm/test/TableGen/immarg-predicated.td
index dcacb2f8f1de35..8af8d5fb40d6dd 100644
--- a/llvm/test/TableGen/immarg-predicated.td
+++ b/llvm/test/TableGen/immarg-predicated.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
@@ -9,7 +9,7 @@ def int_mytarget_sleep0 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
// GISEL-NEXT: // MIs[0] Operand 0
-// GISEL-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mytarget_sleep0),
+// GISEL-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode4(Intrinsic::mytarget_sleep0),
// GISEL-NEXT: // MIs[0] src
// GISEL-NEXT: GIM_CheckIsImm, /*MI*/0, /*Op*/1,
// GISEL-NEXT: GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tuimm9),
diff --git a/llvm/test/TableGen/immarg.td b/llvm/test/TableGen/immarg.td
index e5fd06ce6c083f..80b0d17eb21bcf 100644
--- a/llvm/test/TableGen/immarg.td
+++ b/llvm/test/TableGen/immarg.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
@@ -10,7 +10,7 @@ def int_mytarget_sleep1 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
// GISEL-NEXT: // MIs[0] Operand 0
-// GISEL-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mytarget_sleep0),
+// GISEL-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode4(Intrinsic::mytarget_sleep0),
// GISEL-NEXT: // MIs[0] src
// GISEL-NEXT: GIM_CheckIsImm, /*MI*/0, /*Op*/1,
// GISEL-NEXT: // (intrinsic_void {{[0-9]+}}:{ *:[iPTR] }, (timm:{ *:[i32] }):$src) => (SLEEP0 (timm:{ *:[i32] }):$src)
diff --git a/llvm/test/TableGen/intrinsic-attrs.td b/llvm/test/TableGen/intrinsic-attrs.td
index 579b5e8a21b868..bebeadd291ae7c 100644
--- a/llvm/test/TableGen/intrinsic-attrs.td
+++ b/llvm/test/TableGen/intrinsic-attrs.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-intrinsic-impl -I %p/../../include -DTEST_INTRINSICS_SUPPRESS_DEFS %s | FileCheck %s
+// RUN: llvm-tblgen -gen-intrinsic-impl --enabled-targets=all -I %p/../../include -DTEST_INTRINSICS_SUPPRESS_DEFS %s | FileCheck %s
include "llvm/IR/Intrinsics.td"
diff --git a/llvm/test/TableGen/intrinsic-duplicate-name.td b/llvm/test/TableGen/intrinsic-duplicate-name.td
index 64d94d3192541d..acb60a0ffba075 100644
--- a/llvm/test/TableGen/intrinsic-duplicate-name.td
+++ b/llvm/test/TableGen/intrinsic-duplicate-name.td
@@ -1,4 +1,4 @@
-// RUN: not llvm-tblgen -gen-intrinsic-impl -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS 2>&1 | FileCheck %s -DFILE=%s
+// RUN: not llvm-tblgen -gen-intrinsic-impl --enabled-targets=all -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS 2>&1 | FileCheck %s -DFILE=%s
include "llvm/IR/Intrinsics.td"
diff --git a/llvm/test/TableGen/intrinsic-long-name.td b/llvm/test/TableGen/intrinsic-long-name.td
index c19910d474ed10..224d9f988f5cc5 100644
--- a/llvm/test/TableGen/intrinsic-long-name.td
+++ b/llvm/test/TableGen/intrinsic-long-name.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-intrinsic-enums -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS | FileCheck %s
+// RUN: llvm-tblgen -gen-intrinsic-enums --enabled-targets=all -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS | FileCheck %s
// XFAIL: vg_leak
include "llvm/IR/Intrinsics.td"
diff --git a/llvm/test/TableGen/intrinsic-overload-conflict.td b/llvm/test/TableGen/intrinsic-overload-conflict.td
index 84333119d41f53..3fb87813fc3cc1 100644
--- a/llvm/test/TableGen/intrinsic-overload-conflict.td
+++ b/llvm/test/TableGen/intrinsic-overload-conflict.td
@@ -1,9 +1,9 @@
-// RUN: llvm-tblgen -gen-intrinsic-enums -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS | FileCheck %s
-// RUN: not llvm-tblgen -gen-intrinsic-enums -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS -DCONFLICT 2>&1 | FileCheck %s -DFILE=%s --check-prefix=CHECK-CONFLICT
+// RUN: llvm-tblgen -gen-intrinsic-enums --enabled-targets=all -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS | FileCheck %s
+// RUN: not llvm-tblgen -gen-intrinsic-enums --enabled-targets=all -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS -DCONFLICT 2>&1 | FileCheck %s -DFILE=%s --check-prefix=CHECK-CONFLICT
include "llvm/IR/Intrinsics.td"
-// CHECK: foo = 1,
+// CHECK: foo = {{.+}},
def int_foo : Intrinsic<[llvm_any_ty]>;
// No conflicts, since .bar is not a vaid mangled type.
diff --git a/llvm/test/TableGen/intrinsic-prefix-error.td b/llvm/test/TableGen/intrinsic-prefix-error.td
index 3869bde3a4ba76..ef05c59222ff48 100644
--- a/llvm/test/TableGen/intrinsic-prefix-error.td
+++ b/llvm/test/TableGen/intrinsic-prefix-error.td
@@ -1,4 +1,4 @@
-// RUN: not llvm-tblgen -gen-intrinsic-enums --intrinsic-prefix=gen3 -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS 2>&1 | FileCheck %s
+// RUN: not llvm-tblgen -gen-intrinsic-enums --enabled-targets=all --intrinsic-prefix=gen3 -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS 2>&1 | FileCheck %s
include "llvm/IR/Intrinsics.td"
diff --git a/llvm/test/TableGen/intrinsic-struct.td b/llvm/test/TableGen/intrinsic-struct.td
index 467fd9057c1833..b3704916e69a07 100644
--- a/llvm/test/TableGen/intrinsic-struct.td
+++ b/llvm/test/TableGen/intrinsic-struct.td
@@ -1,13 +1,13 @@
-// RUN: llvm-tblgen -gen-intrinsic-enums -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS | FileCheck %s --check-prefix=CHECK-ENUM
-// RUN: llvm-tblgen -gen-intrinsic-impl -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS > /dev/null 2>&1
-// RUN: not llvm-tblgen -gen-intrinsic-impl -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS -DENABLE_ERROR 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-tblgen -gen-intrinsic-enums --enabled-targets=all -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS | FileCheck %s --check-prefix=CHECK-ENUM
+// RUN: llvm-tblgen -gen-intrinsic-impl --enabled-targets=all -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS > /dev/null 2>&1
+// RUN: not llvm-tblgen -gen-intrinsic-impl --enabled-targets=all -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS -DENABLE_ERROR 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
// XFAIL: vg_leak
include "llvm/IR/Intrinsics.td"
// Make sure we can return up to 9 values.
-// CHECK-ENUM: returns_9_results = {{[0-9]+}}, // llvm.returns.9.results
+// CHECK-ENUM: returns_9_results = {{.+}}, // llvm.returns.9.results
def int_returns_9_results : Intrinsic<
!listsplat(llvm_anyint_ty, 9),
[], [], "llvm.returns.9.results">;
diff --git a/llvm/test/TableGen/intrinsic-target-prefix-for-target-independent.td b/llvm/test/TableGen/intrinsic-target-prefix-for-target-independent.td
index 84e365f02d968c..ce770bf97b5eb3 100644
--- a/llvm/test/TableGen/intrinsic-target-prefix-for-target-independent.td
+++ b/llvm/test/TableGen/intrinsic-target-prefix-for-target-independent.td
@@ -1,4 +1,4 @@
-// RUN: not llvm-tblgen -gen-intrinsic-enums -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
+// RUN: not llvm-tblgen -gen-intrinsic-enums --enabled-targets=all -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
include "llvm/IR/Intrinsics.td"
diff --git a/llvm/test/TableGen/intrinsic-varargs.td b/llvm/test/TableGen/intrinsic-varargs.td
index 3634e16e205653..ccc29c9758a982 100644
--- a/llvm/test/TableGen/intrinsic-varargs.td
+++ b/llvm/test/TableGen/intrinsic-varargs.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-intrinsic-impl -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS | FileCheck %s
+// RUN: llvm-tblgen -gen-intrinsic-impl --enabled-targets=all -I %p/../../include %s -DTEST_INTRINSICS_SUPPRESS_DEFS | FileCheck %s
// XFAIL: vg_leak
include "llvm/IR/Intrinsics.td"
diff --git a/llvm/test/TableGen/invalid-type-cast-patfrags.td b/llvm/test/TableGen/invalid-type-cast-patfrags.td
index 49d8a73b810788..02a82636e28088 100644
--- a/llvm/test/TableGen/invalid-type-cast-patfrags.td
+++ b/llvm/test/TableGen/invalid-type-cast-patfrags.td
@@ -1,7 +1,7 @@
-// RUN: not llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common -DERROR1 %s 2>&1 | FileCheck --check-prefix=ERROR1 %s
-// RUN: not llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common -DERROR2 %s 2>&1 | FileCheck --check-prefix=ERROR2 %s
-// RUN: not llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common -DERROR3 %s 2>&1 | FileCheck --check-prefix=ERROR3 %s
-// RUN: not llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common -DERROR4 %s 2>&1 | FileCheck --check-prefix=ERROR4 %s
+// RUN: not llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -I %p/Common -DERROR1 %s 2>&1 | FileCheck --check-prefix=ERROR1 %s
+// RUN: not llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -I %p/Common -DERROR2 %s 2>&1 | FileCheck --check-prefix=ERROR2 %s
+// RUN: not llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -I %p/Common -DERROR3 %s 2>&1 | FileCheck --check-prefix=ERROR3 %s
+// RUN: not llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -I %p/Common -DERROR4 %s 2>&1 | FileCheck --check-prefix=ERROR4 %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/multiple-type-casts-patfrags.td b/llvm/test/TableGen/multiple-type-casts-patfrags.td
index c4b4b62995fdb3..93d0429b1cb613 100644
--- a/llvm/test/TableGen/multiple-type-casts-patfrags.td
+++ b/llvm/test/TableGen/multiple-type-casts-patfrags.td
@@ -1,5 +1,5 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s | FileCheck -check-prefix=SDAG %s
-// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -I %p/Common %s | FileCheck -check-prefix=SDAG %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
diff --git a/llvm/test/TableGen/predicate-patfags.td b/llvm/test/TableGen/predicate-patfags.td
index 39133f324f305d..c6bbd4651f352f 100644
--- a/llvm/test/TableGen/predicate-patfags.td
+++ b/llvm/test/TableGen/predicate-patfags.td
@@ -1,7 +1,7 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s 2>&1 | FileCheck -check-prefixes=SDAG,SCUSTOM %s
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -I %p/Common %s -DHASONEUSE 2>&1 | FileCheck -check-prefixes=SDAG,SBUILTIN %s
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s 2>&1 | FileCheck -check-prefixes=GISEL,GCUSTOM %s
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -DHASONEUSE 2>&1 | FileCheck -check-prefixes=GISEL,GBUILTIN %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -I %p/Common %s 2>&1 | FileCheck -check-prefixes=SDAG,SCUSTOM %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -I %p/Common %s -DHASONEUSE 2>&1 | FileCheck -check-prefixes=SDAG,SBUILTIN %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common %s 2>&1 | FileCheck -check-prefixes=GISEL,GCUSTOM %s
+// RUN: llvm-tblgen -gen-global-isel --enabled-targets=all -I %p/../../include -I %p/Common %s -DHASONEUSE 2>&1 | FileCheck -check-prefixes=GISEL,GBUILTIN %s
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
@@ -55,12 +55,12 @@ def TGTmul24_oneuse : PatFrag<
// SBUILTIN: if (!SDValue(N, 0).hasOneUse()) return false;
// GISEL: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
-// GISEL: GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::tgt_mul24),
+// GISEL: GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode4(Intrinsic::tgt_mul24),
// GBUILTIN: GIM_CheckHasOneUse, /*MI*/1,
// GCUSTOM: GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_TGTmul24_oneuse),
// GISEL: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
-// GISEL: GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::tgt_mul24),
+// GISEL: GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode4(Intrinsic::tgt_mul24),
// GBUILTIN: GIM_CheckHasOneUse, /*MI*/1,
// GCUSTOM: GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_TGTmul24_oneuse),
diff --git a/llvm/test/TableGen/simplify-patfrag.td b/llvm/test/TableGen/simplify-patfrag.td
index fbb6f97f286311..b6bb6bc41226f6 100644
--- a/llvm/test/TableGen/simplify-patfrag.td
+++ b/llvm/test/TableGen/simplify-patfrag.td
@@ -1,5 +1,5 @@
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s
-// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include -DIGNORE %s 2>&1 | FileCheck %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include %s 2>&1 | FileCheck %s
+// RUN: llvm-tblgen -gen-dag-isel --enabled-targets=all -I %p/../../include -DIGNORE %s 2>&1 | FileCheck %s
include "llvm/Target/Target.td"
diff --git a/llvm/unittests/IR/VPIntrinsicTest.cpp b/llvm/unittests/IR/VPIntrinsicTest.cpp
index d6ad7599ce4610..48a0dc86724d41 100644
--- a/llvm/unittests/IR/VPIntrinsicTest.cpp
+++ b/llvm/unittests/IR/VPIntrinsicTest.cpp
@@ -370,27 +370,28 @@ TEST_F(VPIntrinsicTest, IntrinsicIDRoundTrip) {
/// Check that going from intrinsic to VP intrinsic and back results in the same
/// intrinsic.
TEST_F(VPIntrinsicTest, IntrinsicToVPRoundTrip) {
+ using namespace Intrinsic;
bool IsFullTrip = false;
- Intrinsic::ID IntrinsicID = Intrinsic::not_intrinsic + 1;
- for (; IntrinsicID < Intrinsic::num_intrinsics; IntrinsicID++) {
- Intrinsic::ID VPID = VPIntrinsic::getForIntrinsic(IntrinsicID);
+ for (ID IID = GetNextValidIntrinsicID(not_intrinsic); IID != end_id;
+ IID = GetNextValidIntrinsicID(IID)) {
+ ID VPID = VPIntrinsic::getForIntrinsic(IID);
// No equivalent VP intrinsic available.
if (VPID == Intrinsic::not_intrinsic)
continue;
// Return itself if passed intrinsic ID is VP intrinsic.
- if (VPIntrinsic::isVPIntrinsic(IntrinsicID)) {
- ASSERT_EQ(IntrinsicID, VPID);
+ if (VPIntrinsic::isVPIntrinsic(IID)) {
+ ASSERT_EQ(IID, VPID);
continue;
}
- std::optional<Intrinsic::ID> RoundTripIntrinsicID =
+ std::optional<ID> RoundTripIntrinsicID =
VPIntrinsic::getFunctionalIntrinsicIDForVP(VPID);
// No equivalent non-predicated intrinsic available.
if (!RoundTripIntrinsicID)
continue;
- ASSERT_EQ(*RoundTripIntrinsicID, IntrinsicID);
+ ASSERT_EQ(*RoundTripIntrinsicID, IID);
IsFullTrip = true;
}
ASSERT_TRUE(IsFullTrip);
diff --git a/llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp b/llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
index 18e0b8fd135bb0..8dbcc1ca707040 100644
--- a/llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
+++ b/llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
@@ -13,14 +13,23 @@
#include "CodeGenIntrinsics.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringMap.h"
+#include "llvm/ADT/StringSet.h"
#include "llvm/ADT/Twine.h"
+#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/IntrinsicID.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include <algorithm>
#include <cassert>
using namespace llvm;
+cl::list<std::string> EnabledTargets(
+ "enabled-targets", cl::CommaSeparated,
+ cl::desc("Targets prefixes for enabled targets"),
+ cl::value_desc("set of target prefixes for targets that are enabled"));
+
//===----------------------------------------------------------------------===//
// CodeGenIntrinsic Implementation
//===----------------------------------------------------------------------===//
@@ -44,41 +53,97 @@ CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) {
CodeGenIntrinsicContext Ctx(RC);
ArrayRef<const Record *> Defs = RC.getAllDerivedDefinitions("Intrinsic");
- Intrinsics.reserve(Defs.size());
-
- for (const Record *Def : Defs)
- Intrinsics.emplace_back(CodeGenIntrinsic(Def, Ctx));
-
- llvm::sort(Intrinsics,
- [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) {
- // Order target independent intrinsics before target dependent
- // ones.
- bool LHSHasTarget = !LHS.TargetPrefix.empty();
- bool RHSHasTarget = !RHS.TargetPrefix.empty();
-
- // To ensure deterministic sorted order when duplicates are
- // present, use record ID as a tie-breaker similar to
- // sortAndReportDuplicates in Utils.cpp.
- unsigned LhsID = LHS.TheDef->getID();
- unsigned RhsID = RHS.TheDef->getID();
-
- return std::tie(LHSHasTarget, LHS.Name, LhsID) <
- std::tie(RHSHasTarget, RHS.Name, RhsID);
- });
-
- Targets.push_back({"", 0, 0});
- for (size_t I = 0, E = Intrinsics.size(); I < E; ++I)
- if (Intrinsics[I].TargetPrefix != Targets.back().Name) {
- Targets.back().Count = I - Targets.back().Offset;
- Targets.push_back({Intrinsics[I].TargetPrefix, I, 0});
+
+ // Bucket each intrinsic into a per-target list of intrinsics. Use std::map
+ // so that the targets also get sorted by name,
+ std::map<StringRef, TargetSet> TargetMap;
+
+ // Always create an entry for target independent intrinsics.
+ TargetMap[""].Name = "";
+ for (const Record *Def : Defs) {
+ CodeGenIntrinsic Int(Def, Ctx);
+ TargetMap[Int.TargetPrefix].Intrinsics.push_back(Int);
+ }
+
+ if (EnabledTargets.empty())
+ PrintFatalError("Enabled targets not specified");
+
+ StringSet<> EnabledTargetsSet(EnabledTargets);
+
+ const bool AllEnabled = EnabledTargetsSet.contains("all");
+ if (AllEnabled && EnabledTargets.size() > 1)
+ PrintFatalError(
+ "Additional enabled targets cannot be specified with 'all'");
+
+ if (EnabledTargetsSet.contains("none")) {
+ if (EnabledTargets.size() > 1)
+ PrintFatalError(
+ "Additional enabled targets cannot be specified with 'none'");
+ EnabledTargetsSet.clear();
+ }
+
+ // Verify that all targets provided on the command line were valid.
+ if (!AllEnabled) {
+ StringSet<> InvalidTargets;
+ for (const auto &[TargetPrefix, _] : TargetMap)
+ if (TargetMap.find(TargetPrefix) == TargetMap.end())
+ InvalidTargets.insert(TargetPrefix);
+
+ if (!InvalidTargets.empty()) {
+ PrintFatalError([&InvalidTargets, &TargetMap](raw_ostream &OS) {
+ OS << "Unknown enabled targets: ";
+ interleaveComma(InvalidTargets, OS,
+ [&OS](const auto &Entry) { OS << Entry.first(); });
+ OS << "\nKnown targets are: ";
+ interleaveComma(TargetMap, OS,
+ [&OS](const auto &Entry) { OS << Entry.first; });
+ OS << '\n';
+ });
}
- Targets.back().Count = Intrinsics.size() - Targets.back().Offset;
+ }
+
+ auto IntrinsicCmp = [](const CodeGenIntrinsic &LHS,
+ const CodeGenIntrinsic &RHS) {
+ // To ensure deterministic sorted order when duplicates are present, use
+ // record ID as a tie-breaker similar to sortAndReportDuplicates in
+ // Utils.cpp.
+ unsigned LhsID = LHS.TheDef->getID();
+ unsigned RhsID = RHS.TheDef->getID();
+
+ return std::tie(LHS.Name, LhsID) < std::tie(RHS.Name, RhsID);
+ };
+
+ // Sort intrinsics by name within each target, and collect all targets
+ // (alreay sorted by target name). Also assign linear index to all of them.
+ // Linear index 0 is reserved.
+ unsigned LinearIndex = 1;
+ unsigned TargetIndex = 0;
+ for (auto &[TargetName, TSet] : TargetMap) {
+ Targets.push_back(std::move(TSet));
+ TargetSet &T = Targets.back();
+ T.Name = TargetName;
+ T.TargetIndex = TargetIndex++;
+ llvm::sort(T.Intrinsics, IntrinsicCmp);
+ T.Enabled = AllEnabled || TargetName.empty() ||
+ EnabledTargetsSet.contains(TargetName);
+ if (T.Enabled) {
+ T.FirstLinearIndex = LinearIndex;
+ LinearIndex += T.Intrinsics.size();
+ } else {
+ T.FirstLinearIndex = ~0U;
+ }
+ }
+ NumEnabledIntrinsics = LinearIndex;
CheckDuplicateIntrinsics();
CheckTargetIndependentIntrinsics();
CheckOverloadSuffixConflicts();
}
+ArrayRef<std::string> CodeGenIntrinsicTable::getEnabledCommandLineTargets() {
+ return EnabledTargets;
+}
+
// Check for duplicate intrinsic names.
void CodeGenIntrinsicTable::CheckDuplicateIntrinsics() const {
// Since the Intrinsics vector is already sorted by name, if there are 2 or
@@ -87,20 +152,23 @@ void CodeGenIntrinsicTable::CheckDuplicateIntrinsics() const {
// there cannot be be duplicate as TableGen parser would have flagged that.
// However, if the name was specified in the intrinsic definition, then its
// possible to have duplicate names.
- auto I = std::adjacent_find(
- Intrinsics.begin(), Intrinsics.end(),
- [](const CodeGenIntrinsic &Int1, const CodeGenIntrinsic &Int2) {
- return Int1.Name == Int2.Name;
- });
- if (I == Intrinsics.end())
- return;
-
- // Found a duplicate intrinsics.
- const CodeGenIntrinsic &First = *I;
- const CodeGenIntrinsic &Second = *(I + 1);
- PrintError(Second.TheDef,
- Twine("Intrinsic `") + First.Name + "` is already defined");
- PrintFatalNote(First.TheDef, "Previous definition here");
+ for (const TargetSet &T : getAllTargets()) {
+ ArrayRef<CodeGenIntrinsic> Intrinsics = T.getIntrinsics();
+ auto I = std::adjacent_find(
+ Intrinsics.begin(), Intrinsics.end(),
+ [](const CodeGenIntrinsic &Int1, const CodeGenIntrinsic &Int2) {
+ return Int1.Name == Int2.Name;
+ });
+ if (I == Intrinsics.end())
+ return;
+
+ // Found a duplicate intrinsics.
+ const CodeGenIntrinsic &First = *I;
+ const CodeGenIntrinsic &Second = *(I + 1);
+ PrintError(Second.TheDef,
+ Twine("Intrinsic `") + First.Name + "` is already defined");
+ PrintFatalNote(First.TheDef, "Previous definition here");
+ }
}
// For target independent intrinsics, check that their second dotted component
@@ -111,8 +179,7 @@ void CodeGenIntrinsicTable::CheckTargetIndependentIntrinsics() const {
TargetNames.insert(Target.Name);
// Set of target independent intrinsics.
- const auto &Set = Targets[0];
- for (const auto &Int : ArrayRef(&Intrinsics[Set.Offset], Set.Count)) {
+ for (const auto &Int : Targets[0].getIntrinsics()) {
StringRef Name = Int.Name;
StringRef Prefix = Name.drop_front(5).split('.').first;
if (!TargetNames.contains(Prefix))
@@ -204,7 +271,7 @@ static bool doesSuffixLookLikeMangledType(StringRef Suffix) {
void CodeGenIntrinsicTable::CheckOverloadSuffixConflicts() const {
for (const TargetSet &Set : Targets) {
const CodeGenIntrinsic *Overloaded = nullptr;
- for (const CodeGenIntrinsic &Int : (*this)[Set]) {
+ for (const CodeGenIntrinsic &Int : Set.getIntrinsics()) {
// If we do not have an overloaded intrinsic to check against, nothing
// to do except potentially identifying this as a candidate for checking
// against in future iteration.
@@ -248,6 +315,57 @@ void CodeGenIntrinsicTable::CheckOverloadSuffixConflicts() const {
}
}
+// Enumerate all enabled intrinsics and call back the visitor function with the
+// intrinsic and its index. Returns the total count of enabled intrinsics. Note
+// that the index is different from its LinearIndex (LinearIndex = Idx + 1)
+void CodeGenIntrinsicTable::enumerateEnabledIntrinsics(
+ CodeGenIntrinsicTable::IntrinsicVisitor Visitor) const {
+ unsigned Idx = 0;
+ for (const TargetSet &T : getEnabledTargets())
+ for (const CodeGenIntrinsic &Int : T.getIntrinsics())
+ Visitor(Idx++, Int);
+}
+
+unsigned CodeGenIntrinsicTable::getIntrinsicID(const Record *Def) const {
+ for (const auto &T : getEnabledTargets())
+ for (const auto &[IntrinsicIndex, Int] : enumerate(T.getIntrinsics()))
+ if (Int.TheDef == Def)
+ return Intrinsic::EncodeIntrinsicID(T.TargetIndex, IntrinsicIndex);
+ errs() << "Cannot find intrinsic for record: " << Def->getName() << '\n';
+ llvm_unreachable("Unknown intrinsic!");
+}
+
+const CodeGenIntrinsic &
+CodeGenIntrinsicTable::getIntrinsic(const Record *Def) const {
+ for (const TargetSet &T : getEnabledTargets())
+ for (const CodeGenIntrinsic &Int : T.getIntrinsics())
+ if (Int.TheDef == Def)
+ return Int;
+ errs() << "Cannot find intrinsic for record: " << Def->getName() << '\n';
+ llvm_unreachable("Unknown intrinsic!");
+}
+
+const CodeGenIntrinsic &CodeGenIntrinsicTable::getIntrinsic(unsigned ID) const {
+ auto getIntrinsicImpl = [&](unsigned ID) -> const CodeGenIntrinsic * {
+ auto Decoded = Intrinsic::DecodeIntrinsicIDNoFail(ID);
+ if (!Decoded)
+ return nullptr;
+ unsigned TargetIndex = Decoded->first;
+ unsigned IntrinsicIndex = Decoded->second;
+ if (TargetIndex >= getAllTargets().size())
+ return nullptr;
+ const TargetSet &T = getAllTargets()[TargetIndex];
+ ArrayRef<CodeGenIntrinsic> Ints = T.getIntrinsics();
+ if (!T.Enabled || IntrinsicIndex >= Ints.size())
+ return nullptr;
+ return &Ints[IntrinsicIndex];
+ };
+ if (const CodeGenIntrinsic *Result = getIntrinsicImpl(ID))
+ return *Result;
+ errs() << "Cannot find intrinsic for ID: 0x" << Twine::utohexstr(ID) << '\n';
+ llvm_unreachable("Unknown intrinsic!");
+}
+
const CodeGenIntrinsic &CodeGenIntrinsicMap::operator[](const Record *Record) {
if (!Record->isSubClassOf("Intrinsic"))
PrintFatalError("Intrinsic defs should be subclass of 'Intrinsic' class");
diff --git a/llvm/utils/TableGen/Basic/CodeGenIntrinsics.h b/llvm/utils/TableGen/Basic/CodeGenIntrinsics.h
index 8428d09a94009e..bad4fce5523a17 100644
--- a/llvm/utils/TableGen/Basic/CodeGenIntrinsics.h
+++ b/llvm/utils/TableGen/Basic/CodeGenIntrinsics.h
@@ -16,6 +16,7 @@
#include "SDNodeProperties.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/ModRef.h"
#include <string>
@@ -172,31 +173,42 @@ class CodeGenIntrinsicTable {
public:
struct TargetSet {
StringRef Name;
- size_t Offset;
- size_t Count;
+ unsigned TargetIndex;
+ std::vector<CodeGenIntrinsic> Intrinsics;
+ size_t FirstLinearIndex;
+ bool Enabled;
+
+ ArrayRef<CodeGenIntrinsic> getIntrinsics() const { return Intrinsics; }
};
explicit CodeGenIntrinsicTable(const RecordKeeper &RC);
- bool empty() const { return Intrinsics.empty(); }
- size_t size() const { return Intrinsics.size(); }
- auto begin() const { return Intrinsics.begin(); }
- auto end() const { return Intrinsics.end(); }
- const CodeGenIntrinsic &operator[](size_t Pos) const {
- return Intrinsics[Pos];
- }
- ArrayRef<CodeGenIntrinsic> operator[](const TargetSet &Set) const {
- return ArrayRef(&Intrinsics[Set.Offset], Set.Count);
+ ArrayRef<TargetSet> getAllTargets() const { return Targets; }
+
+ auto getEnabledTargets() const {
+ return make_filter_range(getAllTargets(),
+ [](const TargetSet &T) { return T.Enabled; });
}
- ArrayRef<TargetSet> getTargets() const { return Targets; }
+
+ using IntrinsicVisitor =
+ function_ref<void(unsigned Idx, const CodeGenIntrinsic &Int)>;
+ void enumerateEnabledIntrinsics(IntrinsicVisitor Visitor) const;
+ unsigned getNumEnabledIntrinsics() const { return NumEnabledIntrinsics; }
+
+ // Find the intrinsic corresponding to the given record.
+ unsigned getIntrinsicID(const Record *Def) const;
+ const CodeGenIntrinsic &getIntrinsic(const Record *Def) const;
+ const CodeGenIntrinsic &getIntrinsic(unsigned ID) const;
+
+ static ArrayRef<std::string> getEnabledCommandLineTargets();
private:
void CheckDuplicateIntrinsics() const;
void CheckTargetIndependentIntrinsics() const;
void CheckOverloadSuffixConflicts() const;
- std::vector<CodeGenIntrinsic> Intrinsics;
std::vector<TargetSet> Targets;
+ unsigned NumEnabledIntrinsics;
};
// This class builds `CodeGenIntrinsic` on demand for a given Def.
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index d2228c902a56b4..7b75600dcb3d02 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -2985,7 +2985,7 @@ TreePatternNodePtr TreePattern::ParseTreePattern(const Init *TheInit,
// convert the intrinsic name to a number.
if (Operator->isSubClassOf("Intrinsic")) {
const CodeGenIntrinsic &Int = getDAGPatterns().getIntrinsic(Operator);
- unsigned IID = getDAGPatterns().getIntrinsicID(Operator) + 1;
+ unsigned IID = getDAGPatterns().getIntrinsicID(Operator);
// If this intrinsic returns void, it must have side-effects and thus a
// chain.
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
index f85753ff5ac80b..0cfb07a07f54c4 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
@@ -1158,23 +1158,15 @@ class CodeGenDAGPatterns {
}
const CodeGenIntrinsic &getIntrinsic(const Record *R) const {
- for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i)
- if (Intrinsics[i].TheDef == R)
- return Intrinsics[i];
- llvm_unreachable("Unknown intrinsic!");
+ return Intrinsics.getIntrinsic(R);
}
const CodeGenIntrinsic &getIntrinsicInfo(unsigned IID) const {
- if (IID - 1 < Intrinsics.size())
- return Intrinsics[IID - 1];
- llvm_unreachable("Bad intrinsic ID!");
+ return Intrinsics.getIntrinsic(IID);
}
unsigned getIntrinsicID(const Record *R) const {
- for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i)
- if (Intrinsics[i].TheDef == R)
- return i;
- llvm_unreachable("Unknown intrinsic!");
+ return Intrinsics.getIntrinsicID(R);
}
const DAGDefaultOperand &getDefaultOperand(const Record *R) const {
diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
index 5de5dd894f84ec..4bb8ab2043389f 100644
--- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
@@ -1305,7 +1305,7 @@ void IntrinsicIDOperandMatcher::emitPredicateOpcodes(MatchTable &Table,
Table << MatchTable::Opcode("GIM_CheckIntrinsicID")
<< MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID)
<< MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx)
- << MatchTable::NamedValue(2, "Intrinsic::" + II->EnumName.str())
+ << MatchTable::NamedValue(4, "Intrinsic::" + II->EnumName.str())
<< MatchTable::LineBreak;
}
@@ -2095,7 +2095,7 @@ void IntrinsicIDRenderer::emitRenderOpcodes(MatchTable &Table,
RuleMatcher &Rule) const {
Table << MatchTable::Opcode("GIR_AddIntrinsicID") << MatchTable::Comment("MI")
<< MatchTable::ULEB128Value(InsnID)
- << MatchTable::NamedValue(2, "Intrinsic::" + II->EnumName.str())
+ << MatchTable::NamedValue(4, "Intrinsic::" + II->EnumName.str())
<< MatchTable::LineBreak;
}
diff --git a/llvm/utils/TableGen/IntrinsicEmitter.cpp b/llvm/utils/TableGen/IntrinsicEmitter.cpp
index 1968e7eac21e33..01e72f538a5d3b 100644
--- a/llvm/utils/TableGen/IntrinsicEmitter.cpp
+++ b/llvm/utils/TableGen/IntrinsicEmitter.cpp
@@ -19,6 +19,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/FormatVariadic.h"
+#include "llvm/Support/IntrinsicID.h"
#include "llvm/Support/ModRef.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/TableGen/Error.h"
@@ -36,6 +37,7 @@
#include <utility>
#include <vector>
using namespace llvm;
+using TargetSet = CodeGenIntrinsicTable::TargetSet;
static cl::OptionCategory GenIntrinsicCat("Options for -gen-intrinsic-enums");
static cl::opt<std::string>
@@ -83,13 +85,18 @@ void IntrinsicEmitter::run(raw_ostream &OS, bool Enums) {
emitSourceFileHeader("Intrinsic Function Source Fragment", OS);
CodeGenIntrinsicTable Ints(Records);
+ OS << "// Enabled targets: ";
+ interleaveComma(Ints.getEnabledCommandLineTargets(), OS);
+ OS << "\n\n";
if (Enums) {
// Emit the enum information.
EmitEnumInfo(Ints, OS);
- // Emit ArgKind for Intrinsics.h.
- EmitArgKind(OS);
+ if (IntrinsicPrefix.empty()) {
+ // Emit ArgKind for Intrinsics.h.
+ EmitArgKind(OS);
+ }
} else {
// Emit IIT_Info constants.
EmitIITInfo(OS);
@@ -122,9 +129,8 @@ void IntrinsicEmitter::EmitEnumInfo(const CodeGenIntrinsicTable &Ints,
// Find the TargetSet for which to generate enums. There will be an initial
// set with an empty target prefix which will include target independent
// intrinsics like dbg.value.
- using TargetSet = CodeGenIntrinsicTable::TargetSet;
const TargetSet *Set = nullptr;
- for (const auto &Target : Ints.getTargets()) {
+ for (const auto &[Idx, Target] : enumerate(Ints.getAllTargets())) {
if (Target.Name == IntrinsicPrefix) {
Set = &Target;
break;
@@ -132,7 +138,7 @@ void IntrinsicEmitter::EmitEnumInfo(const CodeGenIntrinsicTable &Ints,
}
if (!Set) {
// The first entry is for target independent intrinsics, so drop it.
- auto KnowTargets = Ints.getTargets().drop_front();
+ auto KnowTargets = Ints.getAllTargets().drop_front();
PrintFatalError([KnowTargets](raw_ostream &OS) {
OS << "tried to generate intrinsics for unknown target "
<< IntrinsicPrefix << "\nKnown targets are: ";
@@ -143,10 +149,10 @@ void IntrinsicEmitter::EmitEnumInfo(const CodeGenIntrinsicTable &Ints,
}
// Generate a complete header for target specific intrinsics.
+ std::string UpperPrefix = StringRef(IntrinsicPrefix).upper();
if (IntrinsicPrefix.empty()) {
OS << "#ifdef GET_INTRINSIC_ENUM_VALUES\n";
} else {
- std::string UpperPrefix = StringRef(IntrinsicPrefix).upper();
OS << formatv("#ifndef LLVM_IR_INTRINSIC_{}_ENUMS_H\n", UpperPrefix);
OS << formatv("#define LLVM_IR_INTRINSIC_{}_ENUMS_H\n", UpperPrefix);
OS << "namespace llvm::Intrinsic {\n";
@@ -155,13 +161,13 @@ void IntrinsicEmitter::EmitEnumInfo(const CodeGenIntrinsicTable &Ints,
OS << "// Enum values for intrinsics.\n";
bool First = true;
- for (const auto &Int : Ints[*Set]) {
+ for (const auto &Int : Set->getIntrinsics()) {
OS << " " << Int.EnumName;
// Assign a value to the first intrinsic in this target set so that all
// intrinsic ids are distinct.
if (First) {
- OS << " = " << Set->Offset + 1;
+ Intrinsic::PrintIntrinsicIDEncoding(OS, Set->TargetIndex, 0);
First = false;
}
@@ -171,22 +177,25 @@ void IntrinsicEmitter::EmitEnumInfo(const CodeGenIntrinsicTable &Ints,
OS << formatv(" // {}\n", Int.Name);
}
- // Emit num_intrinsics into the target neutral enum.
if (IntrinsicPrefix.empty()) {
- OS << formatv(" num_intrinsics = {}\n", Ints.size() + 1);
+ const TargetSet &LastTarget = Ints.getAllTargets().back();
+ const size_t LastCount = LastTarget.getIntrinsics().size();
+ OS << " last_valid_intrinsic";
+ Intrinsic::PrintIntrinsicIDEncoding(OS, LastTarget.TargetIndex,
+ LastCount - 1);
+ OS << ",\n";
OS << "#endif\n\n";
} else {
- OS << R"(}; // enum
+ OS << formatv(R"(}; // enum {}Intrinsics
} // namespace llvm::Intrinsic
#endif
-)";
+)",
+ UpperPrefix);
}
}
void IntrinsicEmitter::EmitArgKind(raw_ostream &OS) {
- if (!IntrinsicPrefix.empty())
- return;
OS << "// llvm::Intrinsic::IITDescriptor::ArgKind.\n";
OS << "#ifdef GET_INTRINSIC_ARGKIND\n";
if (const auto RecArgKind = Records.getDef("ArgKind")) {
@@ -225,13 +234,32 @@ void IntrinsicEmitter::EmitTargetInfo(const CodeGenIntrinsicTable &Ints,
#ifdef GET_INTRINSIC_TARGET_DATA
struct IntrinsicTargetInfo {
StringLiteral Name;
- size_t Offset;
- size_t Count;
+ unsigned Count;
+ bool Enabled;
+ unsigned EnabledIndex;
};
static constexpr IntrinsicTargetInfo TargetInfos[] = {
)";
- for (const auto [Name, Offset, Count] : Ints.getTargets())
- OS << formatv(" {{\"{}\", {}, {}},\n", Name, Offset, Count);
+ unsigned EnabledIndex = 0;
+ const unsigned InvalidEnabledIndex = Ints.getAllTargets().size() + 1;
+ for (const TargetSet &T : Ints.getAllTargets())
+ OS << formatv(" {{\"{}\", {}, {}, {}},\n", T.Name, T.Intrinsics.size(),
+ T.Enabled, T.Enabled ? EnabledIndex++ : InvalidEnabledIndex);
+ OS << R"(};
+
+struct IntrinsicLinearIndexInfo {
+ unsigned FirstLinearIndex;
+ unsigned Count;
+ unsigned TargetIdx;
+};
+static constexpr IntrinsicLinearIndexInfo TargetLinearIndexInfos[] = {
+)";
+ for (const auto &T : Ints.getAllTargets()) {
+ if (!T.Enabled)
+ continue;
+ OS << formatv(" {{{}, {}, {}}, // {}\n", T.FirstLinearIndex,
+ T.Intrinsics.size(), T.TargetIndex, T.Name);
+ }
OS << R"(};
#endif
@@ -244,30 +272,31 @@ void IntrinsicEmitter::EmitIntrinsicToNameTable(
#ifdef GET_INTRINSIC_NAME_TABLE
// Note that entry #0 is the invalid intrinsic!
)";
- for (const auto &Int : Ints)
+ Ints.enumerateEnabledIntrinsics([&OS](unsigned, const CodeGenIntrinsic &Int) {
OS << " \"" << Int.Name << "\",\n";
+ });
OS << "#endif\n\n";
}
void IntrinsicEmitter::EmitIntrinsicToOverloadTable(
const CodeGenIntrinsicTable &Ints, raw_ostream &OS) {
- OS << R"(// Intrinsic ID to overload bitset.
+ OS << formatv(R"(// Intrinsic ID to overload bitset.
#ifdef GET_INTRINSIC_OVERLOAD_TABLE
-static constexpr uint8_t OTable[] = {
- 0
- )";
- for (auto [I, Int] : enumerate(Ints)) {
- // Add one to the index so we emit a null bit for the invalid #0 intrinsic.
- size_t Idx = I + 1;
-
- if (Idx % 8 == 0)
- OS << ",\n 0";
- if (Int.isOverloaded)
- OS << " | (1<<" << Idx % 8 << ')';
- }
+static constexpr uint8_t OTable[] = {{
+ 0)");
+ Ints.enumerateEnabledIntrinsics(
+ [&OS](unsigned Idx, const CodeGenIntrinsic &Int) {
+ // Add one to the index so we emit a null bit for the invalid #0
+ // intrinsic.
+ unsigned LinearIndex = Idx + 1;
+ if (LinearIndex % 8 == 0)
+ OS << ",\n 0";
+ if (Int.isOverloaded)
+ OS << " | (1<<" << LinearIndex % 8 << ')';
+ });
OS << "\n};\n\n";
// OTable contains a true bit at the position if the intrinsic is overloaded.
- OS << "return (OTable[id/8] & (1 << (id%8))) != 0;\n";
+ OS << "return (ArrayRef(OTable)[Idx/8] & (1 << (Idx%8))) != 0;\n";
OS << "#endif\n\n";
}
@@ -317,10 +346,10 @@ void IntrinsicEmitter::EmitGenerator(const CodeGenIntrinsicTable &Ints,
std::vector<FixedEncodingTy> FixedEncodings;
SequenceToOffsetTable<TypeSigTy> LongEncodingTable;
- FixedEncodings.reserve(Ints.size());
+ FixedEncodings.reserve(Ints.getNumEnabledIntrinsics());
// Compute the unique argument type info.
- for (const CodeGenIntrinsic &Int : Ints) {
+ Ints.enumerateEnabledIntrinsics([&](unsigned, const CodeGenIntrinsic &Int) {
// Get the signature for the intrinsic.
TypeSigTy TypeSig = ComputeTypeSignature(Int);
@@ -328,14 +357,14 @@ void IntrinsicEmitter::EmitGenerator(const CodeGenIntrinsicTable &Ints,
std::optional<uint32_t> Result = encodePacked(TypeSig);
if (Result && (*Result & Mask) == Result) {
FixedEncodings.push_back(static_cast<FixedEncodingTy>(*Result));
- continue;
+ return;
}
LongEncodingTable.add(TypeSig);
// This is a placehold that we'll replace after the table is laid out.
FixedEncodings.push_back(static_cast<FixedEncodingTy>(~0U));
- }
+ });
LongEncodingTable.layout();
@@ -346,24 +375,26 @@ static constexpr {} IIT_Table[] = {{
FixedEncodingTypeName);
unsigned MaxOffset = 0;
- for (auto [Idx, FixedEncoding, Int] : enumerate(FixedEncodings, Ints)) {
- if ((Idx & 7) == 7)
- OS << "\n ";
-
- // If the entry fit in the table, just emit it.
- if ((FixedEncoding & Mask) == FixedEncoding) {
- OS << "0x" << Twine::utohexstr(FixedEncoding) << ", ";
- continue;
- }
-
- TypeSigTy TypeSig = ComputeTypeSignature(Int);
- unsigned Offset = LongEncodingTable.get(TypeSig);
- MaxOffset = std::max(MaxOffset, Offset);
-
- // Otherwise, emit the offset into the long encoding table. We emit it this
- // way so that it is easier to read the offset in the .def file.
- OS << formatv("(1U<<{}) | {}, ", MSBPostion, Offset);
- }
+ Ints.enumerateEnabledIntrinsics(
+ [&](unsigned Idx, const CodeGenIntrinsic &Int) {
+ const FixedEncodingTy &FixedEncoding = FixedEncodings[Idx];
+ if ((Idx & 7) == 7)
+ OS << "\n ";
+
+ // If the entry fit in the table, just emit it.
+ if ((FixedEncoding & Mask) == FixedEncoding) {
+ OS << "0x" << Twine::utohexstr(FixedEncoding) << ", ";
+ return;
+ }
+
+ TypeSigTy TypeSig = ComputeTypeSignature(Int);
+ unsigned Offset = LongEncodingTable.get(TypeSig);
+ MaxOffset = std::max(MaxOffset, Offset);
+
+ // Otherwise, emit the offset into the long encoding table. We emit it
+ // this way so that it is easier to read the offset in the .def file.
+ OS << formatv("(1U<<{}) | {}, ", MSBPostion, Offset);
+ });
OS << "0\n};\n\n";
@@ -486,7 +517,7 @@ static AttributeSet getIntrinsicArgAttributeSet(LLVMContext &C, unsigned ID) {
// Compute unique argument attribute sets.
std::map<SmallVector<CodeGenIntrinsic::ArgAttribute, 0>, unsigned>
UniqArgAttributes;
- for (const CodeGenIntrinsic &Int : Ints) {
+ Ints.enumerateEnabledIntrinsics([&](unsigned, const CodeGenIntrinsic &Int) {
for (auto &Attrs : Int.ArgumentAttributes) {
if (Attrs.empty())
continue;
@@ -513,7 +544,7 @@ static AttributeSet getIntrinsicArgAttributeSet(LLVMContext &C, unsigned ID) {
}
OS << " });";
}
- }
+ });
OS << R"(
}
} // getIntrinsicArgAttributeSet
@@ -527,12 +558,12 @@ static AttributeSet getIntrinsicFnAttributeSet(LLVMContext &C, unsigned ID) {
switch (ID) {
default: llvm_unreachable("Invalid attribute set number");)";
- for (const CodeGenIntrinsic &Int : Ints) {
+ Ints.enumerateEnabledIntrinsics([&](unsigned, const CodeGenIntrinsic &Int) {
if (!hasFnAttributes(Int))
- continue;
+ return;
unsigned ID = UniqFnAttributes.size();
if (!UniqFnAttributes.try_emplace(&Int, ID).second)
- continue;
+ return;
OS << formatv(R"(
case {}:
return AttributeSet::get(C, {{
@@ -574,7 +605,7 @@ static AttributeSet getIntrinsicFnAttributeSet(LLVMContext &C, unsigned ID) {
ME.toIntValue());
}
OS << " });";
- }
+ });
OS << R"(
}
} // getIntrinsicFnAttributeSet
@@ -587,10 +618,10 @@ AttributeList Intrinsic::getAttributes(LLVMContext &C, ID id) {
// arguments or not.
std::map<const CodeGenIntrinsic *, unsigned, AttributeComparator>
UniqAttributes;
- for (const CodeGenIntrinsic &Int : Ints) {
+ Ints.enumerateEnabledIntrinsics([&](unsigned, const CodeGenIntrinsic &Int) {
unsigned ID = UniqAttributes.size();
UniqAttributes.try_emplace(&Int, ID);
- }
+ });
// Assign a 16-bit packed ID for each intrinsic. The lower 8-bits will be its
// "argument attribute ID" (index in UniqAttributes) and upper 8 bits will be
@@ -603,18 +634,20 @@ AttributeList Intrinsic::getAttributes(LLVMContext &C, ID id) {
// Emit an array of AttributeList. Most intrinsics will have at least one
// entry, for the function itself (index ~1), which is usually nounwind.
OS << " static constexpr uint16_t IntrinsicsToAttributesMap[] = {";
- for (const CodeGenIntrinsic &Int : Ints) {
+ Ints.enumerateEnabledIntrinsics([&](unsigned, const CodeGenIntrinsic &Int) {
uint16_t FnAttrIndex = hasFnAttributes(Int) ? UniqFnAttributes[&Int] : 0;
OS << formatv("\n {} << 8 | {}, // {}", FnAttrIndex,
UniqAttributes[&Int], Int.Name);
- }
+ });
OS << formatv(R"(
};
- if (id == 0)
+ // First remap the Intrinsic::ID to intrinsic index.
+ unsigned Idx = getLinearIndex(id);
+ if (Idx == 0)
return AttributeList();
- uint16_t PackedID = IntrinsicsToAttributesMap[id - 1];
+ uint16_t PackedID = IntrinsicsToAttributesMap[Idx - 1];
uint8_t FnAttrID = PackedID >> 8;
switch(PackedID & 0xFF) {{
default: llvm_unreachable("Invalid attribute number");
@@ -677,10 +710,10 @@ void IntrinsicEmitter::EmitIntrinsicToBuiltinMap(
std::pair<std::map<StringRef, StringRef>, std::optional<StringRef>>;
std::map<StringRef, BIMEntryTy> BuiltinMap;
- for (const CodeGenIntrinsic &Int : Ints) {
+ Ints.enumerateEnabledIntrinsics([&](unsigned, const CodeGenIntrinsic &Int) {
StringRef BuiltinName = IsClang ? Int.ClangBuiltinName : Int.MSBuiltinName;
if (BuiltinName.empty())
- continue;
+ return;
// Get the map for this target prefix.
auto &[Map, CommonPrefix] = BuiltinMap[Int.TargetPrefix];
@@ -693,14 +726,14 @@ void IntrinsicEmitter::EmitIntrinsicToBuiltinMap(
if (!CommonPrefix) {
// For the first builtin for this target, initialize the common prefix.
CommonPrefix = BuiltinName;
- continue;
+ return;
}
// Update the common prefix. Note that this assumes that `take_front` will
// never set the `Data` pointer in CommonPrefix to nullptr.
const char *Mismatch = mismatch(*CommonPrefix, BuiltinName).first;
*CommonPrefix = CommonPrefix->take_front(Mismatch - CommonPrefix->begin());
- }
+ });
// Populate the string table with the names of all the builtins after
// removing this common prefix.
@@ -728,7 +761,7 @@ Intrinsic::getIntrinsicFor{}Builtin(StringRef TargetPrefix,
if (BuiltinMap.empty()) {
OS << formatv(R"(
return not_intrinsic;
- }
+}
#endif // GET_LLVM_INTRINSIC_FOR_{}_BUILTIN
)",
UpperCompilerName);
@@ -753,11 +786,13 @@ Intrinsic::getIntrinsicFor{}Builtin(StringRef TargetPrefix,
// Emit a per target table of bultin names.
bool HasTargetIndependentBuiltins = false;
+ bool HasTargetDependentBuiltins = false;
StringRef TargetIndepndentCommonPrefix;
for (const auto &[TargetPrefix, Entry] : BuiltinMap) {
const auto &[Map, CommonPrefix] = Entry;
if (!TargetPrefix.empty()) {
OS << formatv(" // Builtins for {0}.\n", TargetPrefix);
+ HasTargetDependentBuiltins = true;
} else {
OS << " // Target independent builtins.\n";
HasTargetIndependentBuiltins = true;
@@ -775,30 +810,32 @@ Intrinsic::getIntrinsicFor{}Builtin(StringRef TargetPrefix,
OS << formatv(" }; // {}Names\n\n", TargetPrefix);
}
- // After emitting the builtin tables for all targets, emit a lookup table for
- // all targets. We will use binary search, similar to the table for builtin
- // names to lookup into this table.
- OS << R"(
- struct TargetEntry {
- StringLiteral TargetPrefix;
- ArrayRef<BuiltinEntry> Names;
- StringLiteral CommonPrefix;
- bool operator<(StringRef RHS) const {
- return TargetPrefix < RHS;
+ if (HasTargetDependentBuiltins) {
+ // After emitting the builtin tables for all targets, emit a lookup table
+ // for all targets. We will use binary search, similar to the table for
+ // builtin names to lookup into this table.
+ OS << R"(
+ struct TargetEntry {
+ StringLiteral TargetPrefix;
+ ArrayRef<BuiltinEntry> Names;
+ StringLiteral CommonPrefix;
+ bool operator<(StringRef RHS) const {
+ return TargetPrefix < RHS;
+ };
};
- };
- static constexpr TargetEntry TargetTable[] = {
-)";
+ static constexpr TargetEntry TargetTable[] = {
+ )";
- for (const auto &[TargetPrefix, Entry] : BuiltinMap) {
- const auto &[Map, CommonPrefix] = Entry;
- if (TargetPrefix.empty())
- continue;
- OS << formatv(R"( {{"{0}", {0}Names, "{1}"},)", TargetPrefix,
- CommonPrefix)
- << "\n";
+ for (const auto &[TargetPrefix, Entry] : BuiltinMap) {
+ const auto &[Map, CommonPrefix] = Entry;
+ if (TargetPrefix.empty())
+ continue;
+ OS << formatv(R"( {{"{0}", {0}Names, "{1}"},)", TargetPrefix,
+ CommonPrefix)
+ << "\n";
+ }
+ OS << " };\n";
}
- OS << " };\n";
// Now for the actual lookup, first check the target independent table if
// we emitted one.
@@ -817,8 +854,10 @@ Intrinsic::getIntrinsicFor{}Builtin(StringRef TargetPrefix,
TargetIndepndentCommonPrefix);
}
- // If a target independent builtin was not found, lookup the target specific.
- OS << formatv(R"(
+ if (HasTargetDependentBuiltins) {
+ // If a target independent builtin was not found, lookup the target
+ // specific.
+ OS << R"(
auto TI = lower_bound(TargetTable, TargetPrefix);
if (TI == std::end(TargetTable) || TI->TargetPrefix != TargetPrefix)
return not_intrinsic;
@@ -830,6 +869,12 @@ Intrinsic::getIntrinsicFor{}Builtin(StringRef TargetPrefix,
if (II == std::end(TI->Names) || II->getName() != BuiltinName)
return not_intrinsic;
return II->IntrinsicID;
+)";
+ } else {
+ OS << " return not_intrinsic;";
+ }
+
+ OS << formatv(R"(
}
#endif // GET_LLVM_INTRINSIC_FOR_{}_BUILTIN
diff --git a/llvm/utils/TableGen/SearchableTableEmitter.cpp b/llvm/utils/TableGen/SearchableTableEmitter.cpp
index 4bf4df692acb47..34fec230d1ab85 100644
--- a/llvm/utils/TableGen/SearchableTableEmitter.cpp
+++ b/llvm/utils/TableGen/SearchableTableEmitter.cpp
@@ -96,7 +96,7 @@ struct GenericTable {
class SearchableTableEmitter {
const RecordKeeper &Records;
std::unique_ptr<CodeGenTarget> Target;
- std::unique_ptr<CodeGenIntrinsicMap> Intrinsics;
+ // std::unique_ptr<CodeGenIntrinsicMap> Intrinsics;
std::vector<std::unique_ptr<GenericEnum>> Enums;
DenseMap<const Record *, GenericEnum *> EnumMap;
std::set<std::string> PreprocessorGuards;
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