[clang] [RISCV] Check if v extension is enabled by the function features for the builtins not in Zve64*. (PR #112827)

[Jim Lin via cfe-commits]

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/112827

>From a1b6a764dd93ecb33b493c14c396c5c040be0412 Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Fri, 18 Oct 2024 11:11:02 +0800
Subject: [PATCH 1/3] [RISCV] Check if v extension is enabled by the function
 features for the builtins not in Zve64*.

Fixes: https://github.com/llvm/llvm-project/issues/109694
---
 clang/lib/Sema/SemaRISCV.cpp | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index 3da4b515b1b114..3f1c2999286f3f 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -623,7 +623,12 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
     ASTContext::BuiltinVectorTypeInfo Info = Context.getBuiltinVectorTypeInfo(
         TheCall->getType()->castAs<BuiltinType>());
 
-    if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v"))
+    const FunctionDecl *FD = SemaRef.getCurFunctionDecl();
+    llvm::StringMap<bool> FunctionFeatureMap;
+    Context.getFunctionFeatureMap(FunctionFeatureMap, FD);
+
+    if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v")
+        && !FunctionFeatureMap.lookup("v"))
       return Diag(TheCall->getBeginLoc(),
                   diag::err_riscv_builtin_requires_extension)
              << /* IsExtension */ true << TheCall->getSourceRange() << "v";

>From ef6850dc40ad19fead0b8eecac8a0676d66df292 Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Fri, 18 Oct 2024 11:43:55 +0800
Subject: [PATCH 2/3] clang-format

---
 clang/lib/Sema/SemaRISCV.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index 3f1c2999286f3f..d1ccc2774152b1 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -627,8 +627,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI,
     llvm::StringMap<bool> FunctionFeatureMap;
     Context.getFunctionFeatureMap(FunctionFeatureMap, FD);
 
-    if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v")
-        && !FunctionFeatureMap.lookup("v"))
+    if (Context.getTypeSize(Info.ElementType) == 64 && !TI.hasFeature("v") &&
+        !FunctionFeatureMap.lookup("v"))
       return Diag(TheCall->getBeginLoc(),
                   diag::err_riscv_builtin_requires_extension)
              << /* IsExtension */ true << TheCall->getSourceRange() << "v";

>From 9958a5e8068113106974ca913bed7fb5ff90462e Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Fri, 18 Oct 2024 14:03:41 +0800
Subject: [PATCH 3/3] Add testcase

---
 clang/test/CodeGen/RISCV/riscv-func-attr-target.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
index aeddbc4ebf6895..1a40cb72575926 100644
--- a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
+++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -65,6 +65,13 @@ void test_rvv_f64_type_w_zve64d() {
   vfloat64m1_t v;
 }
 
+__attribute__((target("arch=+v")))
+vint64m1_t test_rvv_vmulh_eew64_w_v(vint64m1_t a, vint64m1_t b) {
+// CHECK-LABEL: test_rvv_vmulh_eew64_w_v
+// CHECK-SAME: #13
+  return __riscv_vmulh_vv_i64m1(a, b, 2);
+}
+
 //.
 // CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,+zmmul,-relax,-zbb,-zfa" }
 // CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" }
@@ -79,3 +86,4 @@ void test_rvv_f64_type_w_zve64d() {
 // CHECK: attributes #9 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
 // CHECK: attributes #11 = { {{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
 // CHECK: attributes #12 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa" }
+// CHECK: attributes #13 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" }