[clang] [lldb] [llvm] [APInt] Fix APInt constructions where value does not fit bitwidth (NFCI) (PR #80309)

[Nikita Popov via cfe-commits]

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@@ -171,7 +171,7 @@ bool HexagonGenExtract::convert(Instruction *In) {
     // this value.
     if (!LogicalSR && (SR > SL))
       return false;
-    APInt A = APInt(BW, ~0ULL).lshr(SR).shl(SL);
+    APInt A = APInt(BW, ~0ULL, true).lshr(SR).shl(SL);
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nikic wrote:

I tried this, but it's pretty awkward. Note that the shifts are by different values, so this is not just a simple high bits pattern. Doing this as two shifts directly matches the pattern that's being matched above.

https://github.com/llvm/llvm-project/pull/80309