[clang] 253ff32 - [clang-format] Stop crashing when formatting Verilog (#112043)

[via cfe-commits]

Author: sstwcw
Date: 2024-10-14T13:57:35Z
New Revision: 253ff327241be2b6d4f6321d0e917357d5f310df

URL: https://github.com/llvm/llvm-project/commit/253ff327241be2b6d4f6321d0e917357d5f310df
DIFF: https://github.com/llvm/llvm-project/commit/253ff327241be2b6d4f6321d0e917357d5f310df.diff

LOG: [clang-format] Stop crashing when formatting Verilog (#112043)

The part of the code for parsing Verilog module instantiations
dereferenced a pointer without checking for null pointer. The pointer
may be null if the input is not complete and a line starts with a comma.

Added: 
    

Modified: 
    clang/lib/Format/TokenAnnotator.cpp
    clang/unittests/Format/FormatTestVerilog.cpp

Removed: 
    


################################################################################
diff  --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp
index 364d7e9855e8cf..f41cf3b32f74e2 100644
--- a/clang/lib/Format/TokenAnnotator.cpp
+++ b/clang/lib/Format/TokenAnnotator.cpp
@@ -1551,7 +1551,8 @@ class AnnotatingParser {
           // Case D.
           if (Keywords.isVerilogIdentifier(*Prev) && PrevPrev->is(tok::comma)) {
             const FormatToken *PrevParen = PrevPrev->getPreviousNonComment();
-            if (PrevParen->is(tok::r_paren) && PrevParen->MatchingParen &&
+            if (PrevParen && PrevParen->is(tok::r_paren) &&
+                PrevParen->MatchingParen &&
                 PrevParen->MatchingParen->is(TT_VerilogInstancePortLParen)) {
               return true;
             }

diff  --git a/clang/unittests/Format/FormatTestVerilog.cpp b/clang/unittests/Format/FormatTestVerilog.cpp
index fbaf289fbc4d6d..49d276fc78d81b 100644
--- a/clang/unittests/Format/FormatTestVerilog.cpp
+++ b/clang/unittests/Format/FormatTestVerilog.cpp
@@ -964,6 +964,7 @@ TEST_F(FormatTestVerilog, Instantiation) {
                "        .qbar(out1),\n"
                "        .clear(in1),\n"
                "        .preset(in2));");
+  verifyNoCrash(", ff1();");
   // With breaking between instance ports disabled.
   auto Style = getDefaultStyle();
   Style.VerilogBreakBetweenInstancePorts = false;