[clang] [lld] [llvm] [clang][MIPS] Add support for mipsel-windows-* targets (PR #107744)

[Jiaxun Yang via cfe-commits]

=?utf-8?q?Herv=C3=A9?= Poussineau <hpoussin at reactos.org>,
=?utf-8?q?Herv=C3=A9?= Poussineau <hpoussin at reactos.org>,
=?utf-8?q?Herv=C3=A9?= Poussineau <hpoussin at reactos.org>,
=?utf-8?q?Herv=C3=A9?= Poussineau <hpoussin at reactos.org>,
=?utf-8?q?Herv=C3=A9?= Poussineau <hpoussin at reactos.org>,
=?utf-8?q?Herv=C3=A9?= Poussineau <hpoussin at reactos.org>,
=?utf-8?q?Herv=C3=A9?= Poussineau <hpoussin at reactos.org>,
=?utf-8?q?Herv=C3=A9?= Poussineau <hpoussin at reactos.org>,
=?utf-8?q?Herv=C3=A9?= Poussineau <hpoussin at reactos.org>,
=?utf-8?q?Herv=C3=A9?= Poussineau <hpoussin at reactos.org>,
=?utf-8?q?Herv=C3=A9?= Poussineau <hpoussin at reactos.org>,
=?utf-8?q?Herv=C3=A9?= Poussineau <hpoussin at reactos.org>
Message-ID:
In-Reply-To: <llvm.org/llvm/llvm-project/pull/107744 at github.com>


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@@ -45,6 +46,86 @@ using namespace llvm;
 #define GET_REGINFO_MC_DESC
 #include "MipsGenRegisterInfo.inc"
 
+void MIPS_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
+  // Mapping from CodeView to MC register id.
+  static const struct {
+    codeview::RegisterId CVReg;
+    MCPhysReg Reg;
+  } RegMap[] = {
+      {codeview::RegisterId::MIPS_ZERO, Mips::ZERO},
+      {codeview::RegisterId::MIPS_AT, Mips::AT},
+      {codeview::RegisterId::MIPS_V0, Mips::V0},
+      {codeview::RegisterId::MIPS_V1, Mips::V1},
+      {codeview::RegisterId::MIPS_A0, Mips::A0},
+      {codeview::RegisterId::MIPS_A1, Mips::A1},
+      {codeview::RegisterId::MIPS_A2, Mips::A2},
+      {codeview::RegisterId::MIPS_A3, Mips::A3},
+      {codeview::RegisterId::MIPS_T0, Mips::T0},
+      {codeview::RegisterId::MIPS_T1, Mips::T1},
+      {codeview::RegisterId::MIPS_T2, Mips::T2},
+      {codeview::RegisterId::MIPS_T3, Mips::T3},
+      {codeview::RegisterId::MIPS_T4, Mips::T4},
+      {codeview::RegisterId::MIPS_T5, Mips::T5},
+      {codeview::RegisterId::MIPS_T6, Mips::T6},
+      {codeview::RegisterId::MIPS_T7, Mips::T7},
+      {codeview::RegisterId::MIPS_S0, Mips::S0},
+      {codeview::RegisterId::MIPS_S1, Mips::S1},
+      {codeview::RegisterId::MIPS_S2, Mips::S2},
+      {codeview::RegisterId::MIPS_S3, Mips::S3},
+      {codeview::RegisterId::MIPS_S4, Mips::S4},
+      {codeview::RegisterId::MIPS_S5, Mips::S5},
+      {codeview::RegisterId::MIPS_S6, Mips::S6},
+      {codeview::RegisterId::MIPS_S7, Mips::S7},
+      {codeview::RegisterId::MIPS_T8, Mips::T8},
+      {codeview::RegisterId::MIPS_T9, Mips::T9},
+      {codeview::RegisterId::MIPS_K0, Mips::K0},
+      {codeview::RegisterId::MIPS_K1, Mips::K1},
+      {codeview::RegisterId::MIPS_GP, Mips::GP},
+      {codeview::RegisterId::MIPS_SP, Mips::SP},
+      {codeview::RegisterId::MIPS_S8, Mips::FP},
+      {codeview::RegisterId::MIPS_RA, Mips::RA},
+      {codeview::RegisterId::MIPS_LO, Mips::HI0},
+      {codeview::RegisterId::MIPS_HI, Mips::LO0},
+      //{codeview::RegisterId::MIPS_Fir, Mips::},
----------------
FlyGoat wrote:

As per my observation, FIR is FCR0, Psr is COP012 (CP0.Status), Fsr is FCR31. 

https://github.com/llvm/llvm-project/pull/107744