[clang-tools-extra] [libunwind] [llvm] [mlir] [AArch64][Libunwind] Add Support for FEAT_PAuthLR DWARF Instruction (PR #112171)
Jack Styles via cfe-commits
cfe-commits at lists.llvm.org
Mon Oct 14 02:13:16 PDT 2024
https://github.com/Stylie777 updated https://github.com/llvm/llvm-project/pull/112171
>From ef8f52e5bec31b8fb0e96312b2bcdabc31a5c10c Mon Sep 17 00:00:00 2001
From: Jack Styles <jack.styles at arm.com>
Date: Thu, 3 Oct 2024 14:20:10 +0100
Subject: [PATCH 01/10] [PAuthLR] Add support for FEAT_PAuth_LR to libunwind
This introduces support for unwinding programs where return addresses
have been signed using FEAT_PAuth_Lr, where the value of PC is used as
a diversifier (-mbranch-protection=pac-ret+pc).
A new vendor specific call frame instruction is added,
named `DW_CFA_AARCH64_negate_ra_state_with_pc`, to instruct the unwinder
tocapture the value of PC at the point of signing and update bit 1 of
the existing `RA_SIGN_STATE` pseudo-register to flag the need to use it
for authentication.
See https://github.com/ARM-software/abi-aa/pull/245 for the ABI change.
Authored-by: pratlucas <lucas.prates at arm.com>
---
libunwind/src/DwarfInstructions.hpp | 54 ++++++++++++++++++++++-------
libunwind/src/DwarfParser.hpp | 20 +++++++++++
libunwind/src/dwarf2.h | 3 +-
3 files changed, 64 insertions(+), 13 deletions(-)
diff --git a/libunwind/src/DwarfInstructions.hpp b/libunwind/src/DwarfInstructions.hpp
index bd9ece60ee5881..e7c467de80adb6 100644
--- a/libunwind/src/DwarfInstructions.hpp
+++ b/libunwind/src/DwarfInstructions.hpp
@@ -74,8 +74,10 @@ class DwarfInstructions {
__builtin_unreachable();
}
#if defined(_LIBUNWIND_TARGET_AARCH64)
- static bool getRA_SIGN_STATE(A &addressSpace, R registers, pint_t cfa,
- PrologInfo &prolog);
+ static bool isReturnAddressSigned(A &addressSpace, R registers, pint_t cfa,
+ PrologInfo &prolog);
+ static bool isReturnAddressSignedWithPC(A &addressSpace, R registers,
+ pint_t cfa, PrologInfo &prolog);
#endif
};
@@ -173,8 +175,9 @@ v128 DwarfInstructions<A, R>::getSavedVectorRegister(
}
#if defined(_LIBUNWIND_TARGET_AARCH64)
template <typename A, typename R>
-bool DwarfInstructions<A, R>::getRA_SIGN_STATE(A &addressSpace, R registers,
- pint_t cfa, PrologInfo &prolog) {
+bool DwarfInstructions<A, R>::isReturnAddressSigned(A &addressSpace,
+ R registers, pint_t cfa,
+ PrologInfo &prolog) {
pint_t raSignState;
auto regloc = prolog.savedRegisters[UNW_AARCH64_RA_SIGN_STATE];
if (regloc.location == CFI_Parser<A>::kRegisterUnused)
@@ -185,6 +188,22 @@ bool DwarfInstructions<A, R>::getRA_SIGN_STATE(A &addressSpace, R registers,
// Only bit[0] is meaningful.
return raSignState & 0x01;
}
+
+template <typename A, typename R>
+bool DwarfInstructions<A, R>::isReturnAddressSignedWithPC(A &addressSpace,
+ R registers,
+ pint_t cfa,
+ PrologInfo &prolog) {
+ pint_t raSignState;
+ auto regloc = prolog.savedRegisters[UNW_AARCH64_RA_SIGN_STATE];
+ if (regloc.location == CFI_Parser<A>::kRegisterUnused)
+ raSignState = static_cast<pint_t>(regloc.value);
+ else
+ raSignState = getSavedRegister(addressSpace, registers, cfa, regloc);
+
+ // Only bit[1] is meaningful.
+ return raSignState & 0x02;
+}
#endif
template <typename A, typename R>
@@ -288,7 +307,7 @@ int DwarfInstructions<A, R>::stepWithDwarf(A &addressSpace, pint_t pc,
// restored. autia1716 is used instead of autia as autia1716 assembles
// to a NOP on pre-v8.3a architectures.
if ((R::getArch() == REGISTERS_ARM64) &&
- getRA_SIGN_STATE(addressSpace, registers, cfa, prolog) &&
+ isReturnAddressSigned(addressSpace, registers, cfa, prolog) &&
returnAddress != 0) {
#if !defined(_LIBUNWIND_IS_NATIVE_ONLY)
return UNW_ECROSSRASIGNING;
@@ -296,13 +315,24 @@ int DwarfInstructions<A, R>::stepWithDwarf(A &addressSpace, pint_t pc,
register unsigned long long x17 __asm("x17") = returnAddress;
register unsigned long long x16 __asm("x16") = cfa;
- // These are the autia1716/autib1716 instructions. The hint instructions
- // are used here as gcc does not assemble autia1716/autib1716 for pre
- // armv8.3a targets.
- if (cieInfo.addressesSignedWithBKey)
- asm("hint 0xe" : "+r"(x17) : "r"(x16)); // autib1716
- else
- asm("hint 0xc" : "+r"(x17) : "r"(x16)); // autia1716
+ // We use the hint versions of the authentication instructions below to
+ // ensure they're assembled by the compiler even for targets with no
+ // FEAT_PAuth/FEAT_PAuth_LR support.
+ if(isReturnAddressSignedWithPC(addressSpace, registers, cfa, prolog)) {
+ register unsigned long long x15 __asm("x15") = prolog.ptrAuthDiversifier;
+ if(cieInfo.addressesSignedWithBKey) {
+ asm("hint 0x27\n\t" // pacm
+ "hint 0xe" : "+r"(x17) : "r"(x16), "r"(x15)); // autib1716
+ } else {
+ asm("hint 0x27\n\t" // pacm
+ "hint 0xc" : "+r"(x17) : "r"(x16), "r"(x15)); // autia1716
+ }
+ } else {
+ if (cieInfo.addressesSignedWithBKey)
+ asm("hint 0xe" : "+r"(x17) : "r"(x16)); // autib1716
+ else
+ asm("hint 0xc" : "+r"(x17) : "r"(x16)); // autia1716
+ }
returnAddress = x17;
#endif
}
diff --git a/libunwind/src/DwarfParser.hpp b/libunwind/src/DwarfParser.hpp
index 0682942ce13799..b104d773ed4440 100644
--- a/libunwind/src/DwarfParser.hpp
+++ b/libunwind/src/DwarfParser.hpp
@@ -91,6 +91,9 @@ class CFI_Parser {
int64_t cfaExpression; // CFA = expression
uint32_t spExtraArgSize;
RegisterLocation savedRegisters[kMaxRegisterNumber + 1];
+ #if defined(_LIBUNWIND_TARGET_AARCH64)
+ pint_t ptrAuthDiversifier;
+ #endif
enum class InitializeTime { kLazy, kNormal };
// When saving registers, this data structure is lazily initialized.
@@ -799,6 +802,23 @@ bool CFI_Parser<A>::parseFDEInstructions(A &addressSpace,
}
break;
+#if defined(_LIBUNWIND_TARGET_AARCH64)
+ case DW_CFA_AARCH64_negate_ra_state_with_pc: {
+ int64_t value =
+ results->savedRegisters[UNW_AARCH64_RA_SIGN_STATE].value ^ 0x3;
+ results->setRegisterValue(UNW_AARCH64_RA_SIGN_STATE, value,
+ initialState);
+ // When calucating the value of the PC, it is assumed that the CFI instruction
+ // is placed before the signing instruction, however it is placed after. Because
+ // of this, we need to take into account the CFI instruction is one instruction
+ // call later than expected, and reduce the PC value by 4 bytes to compensate.
+ results->ptrAuthDiversifier = fdeInfo.pcStart + codeOffset - 0x4;
+ _LIBUNWIND_TRACE_DWARF("DW_CFA_AARCH64_negate_ra_state_with_pc(pc=0x%" PRIx64 ")\n",
+ static_cast<uint64_t>(results->ptrAuthDiversifier));
+ }
+ break;
+#endif
+
#else
(void)arch;
#endif
diff --git a/libunwind/src/dwarf2.h b/libunwind/src/dwarf2.h
index 174277d5a79508..2ad3d3c464e80d 100644
--- a/libunwind/src/dwarf2.h
+++ b/libunwind/src/dwarf2.h
@@ -51,7 +51,8 @@ enum {
DW_CFA_GNU_negative_offset_extended = 0x2F,
// AARCH64 extensions
- DW_CFA_AARCH64_negate_ra_state = 0x2D
+ DW_CFA_AARCH64_negate_ra_state_with_pc = 0x2C,
+ DW_CFA_AARCH64_negate_ra_state = 0x2D
};
>From cbc5c12c15f88b53dce421f9003e56920a69fa7a Mon Sep 17 00:00:00 2001
From: Jack Styles <jack.styles at arm.com>
Date: Thu, 3 Oct 2024 14:31:55 +0100
Subject: [PATCH 02/10] [PAuthLR] Add support for FEAT_PAuth_LR's DWARF frame
instruction
This introduces compiler and dwarfdump support for emitting
and parsing the new `DW_CFA_AARCH64_negate_ra_state_with_pc`
DWARF instruction for FEAT_PAuth_LR.
This does mean that, when using FEAT_PAuthLR, the improvements
introduced in #96337 cannot be utilised. `.cfi_negate_ra_state_with_pc`
must be emitted directly after the signing instruction, and when bundled
with other CFI calls, leads to faults when running a program. There are
no changes seen when not using FEAT_PAuthLR to how the CFI Instructions
are generated.
See https://github.com/ARM-software/abi-aa/pull/245 for the ABI change
that incororates FEAT_PAuthLR.
Authored-by: pratlucas <lucas.prates at arm.com>
Co-authored by: vhscampos <victor.campos at arm.com>
Co-authored by: Stylie777 <jack.styles at arm.com>
---
llvm/include/llvm/BinaryFormat/Dwarf.def | 1 +
llvm/include/llvm/MC/MCDwarf.h | 8 +
llvm/include/llvm/MC/MCStreamer.h | 1 +
.../CodeGen/AsmPrinter/AsmPrinterDwarf.cpp | 3 +
llvm/lib/CodeGen/CFIInstrInserter.cpp | 1 +
llvm/lib/CodeGen/MIRParser/MILexer.cpp | 2 +
llvm/lib/CodeGen/MIRParser/MILexer.h | 1 +
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 5 +
llvm/lib/CodeGen/MachineOperand.cpp | 4 +
llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp | 24 +++
llvm/lib/MC/MCAsmStreamer.cpp | 7 +
llvm/lib/MC/MCDwarf.cpp | 4 +
llvm/lib/MC/MCStreamer.cpp | 10 ++
.../Target/AArch64/AArch64FrameLowering.cpp | 5 +-
.../lib/Target/AArch64/AArch64PointerAuth.cpp | 90 ++++++----
.../AArch64/AsmParser/AArch64AsmParser.cpp | 10 ++
...sign-return-address-cfi-negate-ra-state.ll | 3 +-
.../AArch64/sign-return-address-pauth-lr.ll | 162 ++++++++++++------
.../MIR/AArch64/return-address-signing.mir | 23 +++
.../MC/AArch64/directives-case_insensitive.s | 2 +
.../test/MC/AArch64/negate_ra_state_with_pc.s | 7 +
.../DebugInfo/DWARF/DWARFDebugFrameTest.cpp | 1 +
22 files changed, 283 insertions(+), 91 deletions(-)
create mode 100644 llvm/test/MC/AArch64/negate_ra_state_with_pc.s
diff --git a/llvm/include/llvm/BinaryFormat/Dwarf.def b/llvm/include/llvm/BinaryFormat/Dwarf.def
index d55947fc5103ac..9336f2a454ae47 100644
--- a/llvm/include/llvm/BinaryFormat/Dwarf.def
+++ b/llvm/include/llvm/BinaryFormat/Dwarf.def
@@ -1238,6 +1238,7 @@ HANDLE_DW_CFA(0x16, val_expression)
// Vendor extensions:
HANDLE_DW_CFA_PRED(0x1d, MIPS_advance_loc8, SELECT_MIPS64)
HANDLE_DW_CFA_PRED(0x2d, GNU_window_save, SELECT_SPARC)
+HANDLE_DW_CFA_PRED(0x2c, AARCH64_negate_ra_state_with_pc, SELECT_AARCH64)
HANDLE_DW_CFA_PRED(0x2d, AARCH64_negate_ra_state, SELECT_AARCH64)
HANDLE_DW_CFA_PRED(0x2e, GNU_args_size, SELECT_X86)
// Heterogeneous Debugging Extension defined at
diff --git a/llvm/include/llvm/MC/MCDwarf.h b/llvm/include/llvm/MC/MCDwarf.h
index bea79545d1ab96..2ceea906ea57a7 100644
--- a/llvm/include/llvm/MC/MCDwarf.h
+++ b/llvm/include/llvm/MC/MCDwarf.h
@@ -515,6 +515,7 @@ class MCCFIInstruction {
OpRegister,
OpWindowSave,
OpNegateRAState,
+ OpNegateRAStateWithPC,
OpGnuArgsSize,
OpLabel,
};
@@ -642,6 +643,13 @@ class MCCFIInstruction {
return MCCFIInstruction(OpNegateRAState, L, 0, INT64_C(0), Loc);
}
+ /// .cfi_negate_ra_state_with_pc AArch64 negate RA state with PC.
+ static MCCFIInstruction createNegateRAStateWithPC(MCSymbol *L,
+ SMLoc Loc = {}) {
+ return MCCFIInstruction(OpNegateRAStateWithPC, L, 0, INT64_C(0), Loc);
+ }
+
+
/// .cfi_restore says that the rule for Register is now the same as it
/// was at the beginning of the function, after all initial instructions added
/// by .cfi_startproc were executed.
diff --git a/llvm/include/llvm/MC/MCStreamer.h b/llvm/include/llvm/MC/MCStreamer.h
index 707aecc5dc578e..a376ba810ba515 100644
--- a/llvm/include/llvm/MC/MCStreamer.h
+++ b/llvm/include/llvm/MC/MCStreamer.h
@@ -1022,6 +1022,7 @@ class MCStreamer {
SMLoc Loc = {});
virtual void emitCFIWindowSave(SMLoc Loc = {});
virtual void emitCFINegateRAState(SMLoc Loc = {});
+ virtual void emitCFINegateRAStateWithPC(SMLoc Loc = {});
virtual void emitCFILabelDirective(SMLoc Loc, StringRef Name);
virtual void emitWinCFIStartProc(const MCSymbol *Symbol, SMLoc Loc = SMLoc());
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
index 21d0d070c247f4..daad82d26da652 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
@@ -236,6 +236,9 @@ void AsmPrinter::emitCFIInstruction(const MCCFIInstruction &Inst) const {
case MCCFIInstruction::OpNegateRAState:
OutStreamer->emitCFINegateRAState(Loc);
break;
+ case MCCFIInstruction::OpNegateRAStateWithPC:
+ OutStreamer->emitCFINegateRAStateWithPC(Loc);
+ break;
case MCCFIInstruction::OpSameValue:
OutStreamer->emitCFISameValue(Inst.getRegister(), Loc);
break;
diff --git a/llvm/lib/CodeGen/CFIInstrInserter.cpp b/llvm/lib/CodeGen/CFIInstrInserter.cpp
index f5bedc7b8ecdfc..4217ec6a1cca8a 100644
--- a/llvm/lib/CodeGen/CFIInstrInserter.cpp
+++ b/llvm/lib/CodeGen/CFIInstrInserter.cpp
@@ -260,6 +260,7 @@ void CFIInstrInserter::calculateOutgoingCFAInfo(MBBCFAInfo &MBBInfo) {
case MCCFIInstruction::OpEscape:
case MCCFIInstruction::OpWindowSave:
case MCCFIInstruction::OpNegateRAState:
+ case MCCFIInstruction::OpNegateRAStateWithPC:
case MCCFIInstruction::OpGnuArgsSize:
case MCCFIInstruction::OpLabel:
break;
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.cpp b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
index 0809f88fde56b1..5a3806ce57335a 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
@@ -238,6 +238,8 @@ static MIToken::TokenKind getIdentifierKind(StringRef Identifier) {
.Case("window_save", MIToken::kw_cfi_window_save)
.Case("negate_ra_sign_state",
MIToken::kw_cfi_aarch64_negate_ra_sign_state)
+ .Case("negate_ra_sign_state_with_pc",
+ MIToken::kw_cfi_aarch64_negate_ra_sign_state_with_pc)
.Case("blockaddress", MIToken::kw_blockaddress)
.Case("intrinsic", MIToken::kw_intrinsic)
.Case("target-index", MIToken::kw_target_index)
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.h b/llvm/lib/CodeGen/MIRParser/MILexer.h
index 22547483a8a86b..3931da3eaae1d3 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.h
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.h
@@ -96,6 +96,7 @@ struct MIToken {
kw_cfi_undefined,
kw_cfi_window_save,
kw_cfi_aarch64_negate_ra_sign_state,
+ kw_cfi_aarch64_negate_ra_sign_state_with_pc,
kw_blockaddress,
kw_intrinsic,
kw_target_index,
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 74f38e886a6b97..a00cf0b906d5a0 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -2565,6 +2565,10 @@ bool MIParser::parseCFIOperand(MachineOperand &Dest) {
case MIToken::kw_cfi_aarch64_negate_ra_sign_state:
CFIIndex = MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr));
break;
+ case MIToken::kw_cfi_aarch64_negate_ra_sign_state_with_pc:
+ CFIIndex =
+ MF.addFrameInst(MCCFIInstruction::createNegateRAStateWithPC(nullptr));
+ break;
case MIToken::kw_cfi_escape: {
std::string Values;
if (parseCFIEscapeValues(Values))
@@ -2920,6 +2924,7 @@ bool MIParser::parseMachineOperand(const unsigned OpCode, const unsigned OpIdx,
case MIToken::kw_cfi_undefined:
case MIToken::kw_cfi_window_save:
case MIToken::kw_cfi_aarch64_negate_ra_sign_state:
+ case MIToken::kw_cfi_aarch64_negate_ra_sign_state_with_pc:
return parseCFIOperand(Dest);
case MIToken::kw_blockaddress:
return parseBlockAddressOperand(Dest);
diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp
index 89d32c3f005e00..cd94213da79893 100644
--- a/llvm/lib/CodeGen/MachineOperand.cpp
+++ b/llvm/lib/CodeGen/MachineOperand.cpp
@@ -768,6 +768,10 @@ static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
if (MCSymbol *Label = CFI.getLabel())
MachineOperand::printSymbol(OS, *Label);
break;
+ case MCCFIInstruction::OpNegateRAStateWithPC:
+ OS << "negate_ra_sign_state_with_pc ";
+ if (MCSymbol *Label = CFI.getLabel())
+ MachineOperand::printSymbol(OS, *Label);
default:
// TODO: Print the other CFI Operations.
OS << "<unserializable cfi directive>";
diff --git a/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp b/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp
index aff26824dda104..38e264f233e39b 100644
--- a/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp
+++ b/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp
@@ -288,6 +288,7 @@ Error CFIProgram::parse(DWARFDataExtractor Data, uint64_t *Offset,
case DW_CFA_remember_state:
case DW_CFA_restore_state:
case DW_CFA_GNU_window_save:
+ case DW_CFA_AARCH64_negate_ra_state_with_pc:
// No operands
addInstruction(Opcode);
break;
@@ -666,6 +667,28 @@ Error UnwindTable::parseRows(const CFIProgram &CFIP, UnwindRow &Row,
}
break;
+ case dwarf::DW_CFA_AARCH64_negate_ra_state_with_pc: {
+ constexpr uint32_t AArch64DWARFPAuthRaState = 34;
+ auto LRLoc = Row.getRegisterLocations().getRegisterLocation(
+ AArch64DWARFPAuthRaState);
+ if (LRLoc) {
+ if (LRLoc->getLocation() == UnwindLocation::Constant) {
+ // Toggle the constant value of bits[1:0] from 0 to 1 or 1 to 0.
+ LRLoc->setConstant(LRLoc->getConstant() ^ 0x3);
+ } else {
+ return createStringError(
+ errc::invalid_argument,
+ "%s encountered when existing rule for this register is not "
+ "a constant",
+ CFIP.callFrameString(Inst.Opcode).str().c_str());
+ }
+ } else {
+ Row.getRegisterLocations().setRegisterLocation(
+ AArch64DWARFPAuthRaState, UnwindLocation::createIsConstant(0x3));
+ }
+ break;
+ }
+
case dwarf::DW_CFA_undefined: {
llvm::Expected<uint64_t> RegNum = Inst.getOperandAsUnsigned(CFIP, 0);
if (!RegNum)
@@ -847,6 +870,7 @@ CFIProgram::getOperandTypes() {
DECLARE_OP0(DW_CFA_remember_state);
DECLARE_OP0(DW_CFA_restore_state);
DECLARE_OP0(DW_CFA_GNU_window_save);
+ DECLARE_OP0(DW_CFA_AARCH64_negate_ra_state_with_pc);
DECLARE_OP1(DW_CFA_GNU_args_size, OT_Offset);
DECLARE_OP0(DW_CFA_nop);
diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp
index 31b519a3e5c56a..b9ad0b4eac9c7b 100644
--- a/llvm/lib/MC/MCAsmStreamer.cpp
+++ b/llvm/lib/MC/MCAsmStreamer.cpp
@@ -373,6 +373,7 @@ class MCAsmStreamer final : public MCStreamer {
SMLoc Loc) override;
void emitCFIWindowSave(SMLoc Loc) override;
void emitCFINegateRAState(SMLoc Loc) override;
+ void emitCFINegateRAStateWithPC(SMLoc Loc) override;
void emitCFIReturnColumn(int64_t Register) override;
void emitCFILabelDirective(SMLoc Loc, StringRef Name) override;
@@ -2145,6 +2146,12 @@ void MCAsmStreamer::emitCFINegateRAState(SMLoc Loc) {
EmitEOL();
}
+void MCAsmStreamer::emitCFINegateRAStateWithPC(SMLoc Loc) {
+ MCStreamer::emitCFINegateRAStateWithPC(Loc);
+ OS << "\t.cfi_negate_ra_state_with_pc";
+ EmitEOL();
+}
+
void MCAsmStreamer::emitCFIReturnColumn(int64_t Register) {
MCStreamer::emitCFIReturnColumn(Register);
OS << "\t.cfi_return_column ";
diff --git a/llvm/lib/MC/MCDwarf.cpp b/llvm/lib/MC/MCDwarf.cpp
index 8ff097f29aebd1..e058358fb8ad4b 100644
--- a/llvm/lib/MC/MCDwarf.cpp
+++ b/llvm/lib/MC/MCDwarf.cpp
@@ -1381,6 +1381,10 @@ void FrameEmitterImpl::emitCFIInstruction(const MCCFIInstruction &Instr) {
Streamer.emitInt8(dwarf::DW_CFA_AARCH64_negate_ra_state);
return;
+ case MCCFIInstruction::OpNegateRAStateWithPC:
+ Streamer.emitInt8(dwarf::DW_CFA_AARCH64_negate_ra_state_with_pc);
+ return;
+
case MCCFIInstruction::OpUndefined: {
unsigned Reg = Instr.getRegister();
Streamer.emitInt8(dwarf::DW_CFA_undefined);
diff --git a/llvm/lib/MC/MCStreamer.cpp b/llvm/lib/MC/MCStreamer.cpp
index 13b162768578c5..5474db1315f141 100644
--- a/llvm/lib/MC/MCStreamer.cpp
+++ b/llvm/lib/MC/MCStreamer.cpp
@@ -688,6 +688,16 @@ void MCStreamer::emitCFINegateRAState(SMLoc Loc) {
CurFrame->Instructions.push_back(Instruction);
}
+void MCStreamer::emitCFINegateRAStateWithPC(SMLoc Loc) {
+ MCSymbol *Label = emitCFILabel();
+ MCCFIInstruction Instruction =
+ MCCFIInstruction::createNegateRAStateWithPC(Label, Loc);
+ MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo();
+ if (!CurFrame)
+ return;
+ CurFrame->Instructions.push_back(Instruction);
+}
+
void MCStreamer::emitCFIReturnColumn(int64_t Register) {
MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo();
if (!CurFrame)
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index be33331be4e8ff..98293bc7ac30e2 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -702,7 +702,10 @@ void AArch64FrameLowering::resetCFIToInitialState(
// Flip the RA sign state.
if (MFI.shouldSignReturnAddress(MF)) {
- CFIIndex = MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr));
+ auto CFIInst = MFI.branchProtectionPAuthLR()
+ ? MCCFIInstruction::createNegateRAStateWithPC(nullptr)
+ : MCCFIInstruction::createNegateRAState(nullptr);
+ CFIIndex = MF.addFrameInst(CFIInst);
BuildMI(MBB, InsertPt, DL, CFIDesc).addCFIIndex(CFIIndex);
}
diff --git a/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp b/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
index 92ab4b5c3d251f..0879b5aec37aea 100644
--- a/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
+++ b/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
@@ -71,6 +71,18 @@ FunctionPass *llvm::createAArch64PointerAuthPass() {
char AArch64PointerAuth::ID = 0;
+static void emitPACSymOffsetIntoX16(const TargetInstrInfo &TII,
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I, DebugLoc DL,
+ MCSymbol *PACSym) {
+ BuildMI(MBB, I, DL, TII.get(AArch64::ADRP), AArch64::X16)
+ .addSym(PACSym, AArch64II::MO_PAGE);
+ BuildMI(MBB, I, DL, TII.get(AArch64::ADDXri), AArch64::X16)
+ .addReg(AArch64::X16)
+ .addSym(PACSym, AArch64II::MO_PAGEOFF | AArch64II::MO_NC)
+ .addImm(0);
+}
+
// Where PAuthLR support is not known at compile time, it is supported using
// PACM. PACM is in the hint space so has no effect when PAuthLR is not
// supported by the hardware, but will alter the behaviour of PACI*SP, AUTI*SP
@@ -81,12 +93,10 @@ static void BuildPACM(const AArch64Subtarget &Subtarget, MachineBasicBlock &MBB,
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
auto &MFnI = *MBB.getParent()->getInfo<AArch64FunctionInfo>();
- // ADR X16,<address_of_PACIASP>
+ // Offset to PAC*SP using ADRP + ADD.
if (PACSym) {
assert(Flags == MachineInstr::FrameDestroy);
- BuildMI(MBB, MBBI, DL, TII->get(AArch64::ADR))
- .addReg(AArch64::X16, RegState::Define)
- .addSym(PACSym);
+ emitPACSymOffsetIntoX16(*TII, MBB, MBBI, DL, PACSym);
}
// Only emit PACM if -mbranch-protection has +pc and the target does not
@@ -95,12 +105,49 @@ static void BuildPACM(const AArch64Subtarget &Subtarget, MachineBasicBlock &MBB,
BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACM)).setMIFlag(Flags);
}
+static void emitPACCFI(const AArch64Subtarget &Subtarget,
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ DebugLoc DL, MachineInstr::MIFlag Flags, bool EmitCFI) {
+ if (!EmitCFI)
+ return;
+
+ const TargetInstrInfo *TII = Subtarget.getInstrInfo();
+ auto &MF = *MBB.getParent();
+ auto &MFnI = *MF.getInfo<AArch64FunctionInfo>();
+ bool EmitAsyncCFI = MFnI.needsAsyncDwarfUnwindInfo(MF);
+
+ auto CFIInst = MFnI.branchProtectionPAuthLR()
+ ? MCCFIInstruction::createNegateRAStateWithPC(nullptr)
+ : MCCFIInstruction::createNegateRAState(nullptr);
+
+ // Because of PAuthLR, when using NegateRAStateWithPC, the CFI instruction cannot
+ // be bundled with other CFI instructions in the prolog, as it needs to directly
+ // follow the signing instruction. This ensures the PC value is captured incase of
+ // an error in the following the following instructions.
+ if (!EmitAsyncCFI && !(MFnI.branchProtectionPAuthLR())) {
+ // Reduce the size of the generated call frame information for synchronous
+ // CFI by bundling the new CFI instruction with others in the prolog, so
+ // that no additional DW_CFA_advance_loc is needed.
+ for (auto I = MBBI; I != MBB.end(); ++I) {
+ if (I->getOpcode() == TargetOpcode::CFI_INSTRUCTION &&
+ I->getFlag(MachineInstr::FrameSetup)) {
+ MBBI = I;
+ break;
+ }
+ }
+ }
+
+ unsigned CFIIndex = MF.addFrameInst(CFIInst);
+ BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+ .addCFIIndex(CFIIndex)
+ .setMIFlags(Flags);
+}
+
void AArch64PointerAuth::signLR(MachineFunction &MF,
MachineBasicBlock::iterator MBBI) const {
auto &MFnI = *MF.getInfo<AArch64FunctionInfo>();
bool UseBKey = MFnI.shouldSignWithBKey();
bool EmitCFI = MFnI.needsDwarfUnwindInfo(MF);
- bool EmitAsyncCFI = MFnI.needsAsyncDwarfUnwindInfo(MF);
bool NeedsWinCFI = MF.hasWinCFI();
MachineBasicBlock &MBB = *MBBI->getParent();
@@ -128,6 +175,7 @@ void AArch64PointerAuth::signLR(MachineFunction &MF,
: AArch64::PACIASPPC))
.setMIFlag(MachineInstr::FrameSetup)
->setPreInstrSymbol(MF, MFnI.getSigningInstrLabel());
+ emitPACCFI(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameSetup, EmitCFI);
} else {
BuildPACM(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameSetup);
BuildMI(MBB, MBBI, DL,
@@ -135,27 +183,10 @@ void AArch64PointerAuth::signLR(MachineFunction &MF,
: AArch64::PACIASP))
.setMIFlag(MachineInstr::FrameSetup)
->setPreInstrSymbol(MF, MFnI.getSigningInstrLabel());
+ emitPACCFI(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameSetup, EmitCFI);
}
- if (EmitCFI) {
- if (!EmitAsyncCFI) {
- // Reduce the size of the generated call frame information for synchronous
- // CFI by bundling the new CFI instruction with others in the prolog, so
- // that no additional DW_CFA_advance_loc is needed.
- for (auto I = MBBI; I != MBB.end(); ++I) {
- if (I->getOpcode() == TargetOpcode::CFI_INSTRUCTION &&
- I->getFlag(MachineInstr::FrameSetup)) {
- MBBI = I;
- break;
- }
- }
- }
- unsigned CFIIndex =
- MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr));
- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameSetup);
- } else if (NeedsWinCFI) {
+ if (!EmitCFI && NeedsWinCFI) {
BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_PACSignLR))
.setMIFlag(MachineInstr::FrameSetup);
}
@@ -190,6 +221,7 @@ void AArch64PointerAuth::authenticateLR(
!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack)) {
if (MFnI->branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) {
assert(PACSym && "No PAC instruction to refer to");
+ emitPACSymOffsetIntoX16(*TII, MBB, MBBI, DL, PACSym);
BuildMI(MBB, TI, DL,
TII->get(UseBKey ? AArch64::RETABSPPCi : AArch64::RETAASPPCi))
.addSym(PACSym)
@@ -205,24 +237,20 @@ void AArch64PointerAuth::authenticateLR(
} else {
if (MFnI->branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) {
assert(PACSym && "No PAC instruction to refer to");
+ emitPACSymOffsetIntoX16(*TII, MBB, MBBI, DL, PACSym);
BuildMI(MBB, MBBI, DL,
TII->get(UseBKey ? AArch64::AUTIBSPPCi : AArch64::AUTIASPPCi))
.addSym(PACSym)
.setMIFlag(MachineInstr::FrameDestroy);
+ emitPACCFI(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameDestroy, EmitAsyncCFI);
} else {
BuildPACM(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameDestroy, PACSym);
BuildMI(MBB, MBBI, DL,
TII->get(UseBKey ? AArch64::AUTIBSP : AArch64::AUTIASP))
.setMIFlag(MachineInstr::FrameDestroy);
+ emitPACCFI(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameDestroy, EmitAsyncCFI);
}
- if (EmitAsyncCFI) {
- unsigned CFIIndex =
- MF.addFrameInst(MCCFIInstruction::createNegateRAState(nullptr));
- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex)
- .setMIFlags(MachineInstr::FrameDestroy);
- }
if (NeedsWinCFI) {
BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_PACSignLR))
.setMIFlag(MachineInstr::FrameDestroy);
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index df69c20b1359fc..cbd8bd1f20558c 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -195,6 +195,7 @@ class AArch64AsmParser : public MCTargetAsmParser {
bool parseDirectiveReq(StringRef Name, SMLoc L);
bool parseDirectiveUnreq(SMLoc L);
bool parseDirectiveCFINegateRAState();
+ bool parseDirectiveCFINegateRAStateWithPC();
bool parseDirectiveCFIBKeyFrame();
bool parseDirectiveCFIMTETaggedFrame();
@@ -6821,6 +6822,8 @@ bool AArch64AsmParser::ParseDirective(AsmToken DirectiveID) {
parseDirectiveInst(Loc);
else if (IDVal == ".cfi_negate_ra_state")
parseDirectiveCFINegateRAState();
+ else if (IDVal == ".cfi_negate_ra_state_with_pc")
+ parseDirectiveCFINegateRAStateWithPC();
else if (IDVal == ".cfi_b_key_frame")
parseDirectiveCFIBKeyFrame();
else if (IDVal == ".cfi_mte_tagged_frame")
@@ -7271,6 +7274,13 @@ bool AArch64AsmParser::parseDirectiveCFINegateRAState() {
return false;
}
+bool AArch64AsmParser::parseDirectiveCFINegateRAStateWithPC() {
+ if (parseEOL())
+ return true;
+ getStreamer().emitCFINegateRAStateWithPC();
+ return false;
+}
+
/// parseDirectiveCFIBKeyFrame
/// ::= .cfi_b_key
bool AArch64AsmParser::parseDirectiveCFIBKeyFrame() {
diff --git a/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll b/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
index eb224bbbd601fb..fbf571eabd8015 100644
--- a/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
+++ b/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
@@ -229,7 +229,6 @@ attributes #0 = { "sign-return-address"="all" }
; CHECK-DUMP: DW_CFA_restore_state:
; CHECK-DUMP: DW_CFA_AARCH64_negate_ra_state:
-; CHECK-DUMP: CFA=WSP{{$}}
;; First DW_CFA_AARCH64_negate_ra_state:
; CHECK-DUMP: reg34=1
;; Second DW_CFA_AARCH64_negate_ra_state:
@@ -238,7 +237,7 @@ attributes #0 = { "sign-return-address"="all" }
; CHECK-DUMP: reg34=1
;; Third DW_CFA_AARCH64_negate_ra_state:
; CHECK-DUMP: reg34=0
-; CHECK-DUMP-NOT: reg34=
+; CHECK-DUMP-NOT: reg34=1
; baz_sync
; CHECK-DUMP-LABEL: FDE
diff --git a/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll b/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
index 3d133e02106bc8..fa689d2b9d7fdd 100644
--- a/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
+++ b/llvm/test/CodeGen/AArch64/sign-return-address-pauth-lr.ll
@@ -62,8 +62,9 @@ define i32 @leaf_sign_all(i32 %x) "branch-protection-pauth-lr" "sign-return-addr
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: .Ltmp0:
; COMPAT-NEXT: hint #25
-; COMPAT-NEXT: .cfi_negate_ra_state
-; COMPAT-NEXT: adr x16, .Ltmp0
+; COMPAT-NEXT: .cfi_negate_ra_state_with_pc
+; COMPAT-NEXT: adrp x16, .Ltmp0
+; COMPAT-NEXT: add x16, x16, :lo12:.Ltmp0
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: hint #29
; COMPAT-NEXT: ret
@@ -73,8 +74,9 @@ define i32 @leaf_sign_all(i32 %x) "branch-protection-pauth-lr" "sign-return-addr
; V83A-NEXT: hint #39
; V83A-NEXT: .Ltmp0:
; V83A-NEXT: paciasp
-; V83A-NEXT: .cfi_negate_ra_state
-; V83A-NEXT: adr x16, .Ltmp0
+; V83A-NEXT: .cfi_negate_ra_state_with_pc
+; V83A-NEXT: adrp x16, .Ltmp0
+; V83A-NEXT: add x16, x16, :lo12:.Ltmp0
; V83A-NEXT: hint #39
; V83A-NEXT: retaa
;
@@ -82,7 +84,9 @@ define i32 @leaf_sign_all(i32 %x) "branch-protection-pauth-lr" "sign-return-addr
; PAUTHLR: // %bb.0:
; PAUTHLR-NEXT: .Ltmp0:
; PAUTHLR-NEXT: paciasppc
-; PAUTHLR-NEXT: .cfi_negate_ra_state
+; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
+; PAUTHLR-NEXT: adrp x16, .Ltmp0
+; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp0
; PAUTHLR-NEXT: retaasppc .Ltmp0
ret i32 %x
}
@@ -93,15 +97,16 @@ define i64 @leaf_clobbers_lr(i64 %x) "branch-protection-pauth-lr" "sign-return-a
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: .Ltmp1:
; COMPAT-NEXT: hint #25
+; COMPAT-NEXT: .cfi_negate_ra_state_with_pc
; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; COMPAT-NEXT: .cfi_negate_ra_state
; COMPAT-NEXT: .cfi_def_cfa_offset 16
; COMPAT-NEXT: .cfi_offset w30, -16
; COMPAT-NEXT: //APP
; COMPAT-NEXT: mov x30, x0
; COMPAT-NEXT: //NO_APP
; COMPAT-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; COMPAT-NEXT: adr x16, .Ltmp1
+; COMPAT-NEXT: adrp x16, .Ltmp1
+; COMPAT-NEXT: add x16, x16, :lo12:.Ltmp1
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: hint #29
; COMPAT-NEXT: ret
@@ -111,15 +116,16 @@ define i64 @leaf_clobbers_lr(i64 %x) "branch-protection-pauth-lr" "sign-return-a
; V83A-NEXT: hint #39
; V83A-NEXT: .Ltmp1:
; V83A-NEXT: paciasp
+; V83A-NEXT: .cfi_negate_ra_state_with_pc
; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; V83A-NEXT: .cfi_negate_ra_state
; V83A-NEXT: .cfi_def_cfa_offset 16
; V83A-NEXT: .cfi_offset w30, -16
; V83A-NEXT: //APP
; V83A-NEXT: mov x30, x0
; V83A-NEXT: //NO_APP
; V83A-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; V83A-NEXT: adr x16, .Ltmp1
+; V83A-NEXT: adrp x16, .Ltmp1
+; V83A-NEXT: add x16, x16, :lo12:.Ltmp1
; V83A-NEXT: hint #39
; V83A-NEXT: retaa
;
@@ -127,14 +133,16 @@ define i64 @leaf_clobbers_lr(i64 %x) "branch-protection-pauth-lr" "sign-return-a
; PAUTHLR: // %bb.0:
; PAUTHLR-NEXT: .Ltmp1:
; PAUTHLR-NEXT: paciasppc
+; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; PAUTHLR-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; PAUTHLR-NEXT: .cfi_negate_ra_state
; PAUTHLR-NEXT: .cfi_def_cfa_offset 16
; PAUTHLR-NEXT: .cfi_offset w30, -16
; PAUTHLR-NEXT: //APP
; PAUTHLR-NEXT: mov x30, x0
; PAUTHLR-NEXT: //NO_APP
; PAUTHLR-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; PAUTHLR-NEXT: adrp x16, .Ltmp1
+; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp1
; PAUTHLR-NEXT: retaasppc .Ltmp1
call void asm sideeffect "mov x30, $0", "r,~{lr}"(i64 %x) #1
ret i64 %x
@@ -148,13 +156,14 @@ define i32 @non_leaf_sign_all(i32 %x) "branch-protection-pauth-lr" "sign-return-
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: .Ltmp2:
; COMPAT-NEXT: hint #25
+; COMPAT-NEXT: .cfi_negate_ra_state_with_pc
; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; COMPAT-NEXT: .cfi_negate_ra_state
; COMPAT-NEXT: .cfi_def_cfa_offset 16
; COMPAT-NEXT: .cfi_offset w30, -16
; COMPAT-NEXT: bl foo
; COMPAT-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; COMPAT-NEXT: adr x16, .Ltmp2
+; COMPAT-NEXT: adrp x16, .Ltmp2
+; COMPAT-NEXT: add x16, x16, :lo12:.Ltmp2
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: hint #29
; COMPAT-NEXT: ret
@@ -164,13 +173,14 @@ define i32 @non_leaf_sign_all(i32 %x) "branch-protection-pauth-lr" "sign-return-
; V83A-NEXT: hint #39
; V83A-NEXT: .Ltmp2:
; V83A-NEXT: paciasp
+; V83A-NEXT: .cfi_negate_ra_state_with_pc
; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; V83A-NEXT: .cfi_negate_ra_state
; V83A-NEXT: .cfi_def_cfa_offset 16
; V83A-NEXT: .cfi_offset w30, -16
; V83A-NEXT: bl foo
; V83A-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; V83A-NEXT: adr x16, .Ltmp2
+; V83A-NEXT: adrp x16, .Ltmp2
+; V83A-NEXT: add x16, x16, :lo12:.Ltmp2
; V83A-NEXT: hint #39
; V83A-NEXT: retaa
;
@@ -178,12 +188,14 @@ define i32 @non_leaf_sign_all(i32 %x) "branch-protection-pauth-lr" "sign-return-
; PAUTHLR: // %bb.0:
; PAUTHLR-NEXT: .Ltmp2:
; PAUTHLR-NEXT: paciasppc
+; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; PAUTHLR-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; PAUTHLR-NEXT: .cfi_negate_ra_state
; PAUTHLR-NEXT: .cfi_def_cfa_offset 16
; PAUTHLR-NEXT: .cfi_offset w30, -16
; PAUTHLR-NEXT: bl foo
; PAUTHLR-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; PAUTHLR-NEXT: adrp x16, .Ltmp2
+; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp2
; PAUTHLR-NEXT: retaasppc .Ltmp2
%call = call i32 @foo(i32 %x)
ret i32 %call
@@ -195,13 +207,14 @@ define i32 @non_leaf_sign_non_leaf(i32 %x) "branch-protection-pauth-lr" "sign-re
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: .Ltmp3:
; COMPAT-NEXT: hint #25
+; COMPAT-NEXT: .cfi_negate_ra_state_with_pc
; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; COMPAT-NEXT: .cfi_negate_ra_state
; COMPAT-NEXT: .cfi_def_cfa_offset 16
; COMPAT-NEXT: .cfi_offset w30, -16
; COMPAT-NEXT: bl foo
; COMPAT-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; COMPAT-NEXT: adr x16, .Ltmp3
+; COMPAT-NEXT: adrp x16, .Ltmp3
+; COMPAT-NEXT: add x16, x16, :lo12:.Ltmp3
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: hint #29
; COMPAT-NEXT: ret
@@ -211,13 +224,14 @@ define i32 @non_leaf_sign_non_leaf(i32 %x) "branch-protection-pauth-lr" "sign-re
; V83A-NEXT: hint #39
; V83A-NEXT: .Ltmp3:
; V83A-NEXT: paciasp
+; V83A-NEXT: .cfi_negate_ra_state_with_pc
; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; V83A-NEXT: .cfi_negate_ra_state
; V83A-NEXT: .cfi_def_cfa_offset 16
; V83A-NEXT: .cfi_offset w30, -16
; V83A-NEXT: bl foo
; V83A-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; V83A-NEXT: adr x16, .Ltmp3
+; V83A-NEXT: adrp x16, .Ltmp3
+; V83A-NEXT: add x16, x16, :lo12:.Ltmp3
; V83A-NEXT: hint #39
; V83A-NEXT: retaa
;
@@ -225,12 +239,14 @@ define i32 @non_leaf_sign_non_leaf(i32 %x) "branch-protection-pauth-lr" "sign-re
; PAUTHLR: // %bb.0:
; PAUTHLR-NEXT: .Ltmp3:
; PAUTHLR-NEXT: paciasppc
+; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; PAUTHLR-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; PAUTHLR-NEXT: .cfi_negate_ra_state
; PAUTHLR-NEXT: .cfi_def_cfa_offset 16
; PAUTHLR-NEXT: .cfi_offset w30, -16
; PAUTHLR-NEXT: bl foo
; PAUTHLR-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; PAUTHLR-NEXT: adrp x16, .Ltmp3
+; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp3
; PAUTHLR-NEXT: retaasppc .Ltmp3
%call = call i32 @foo(i32 %x)
ret i32 %call
@@ -245,13 +261,14 @@ define i32 @non_leaf_scs(i32 %x) "branch-protection-pauth-lr" "sign-return-addre
; CHECK-NEXT: hint #39
; CHECK-NEXT: .Ltmp4:
; CHECK-NEXT: paciasp
+; CHECK-NEXT: .cfi_negate_ra_state_with_pc
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; CHECK-NEXT: .cfi_negate_ra_state
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: bl foo
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; CHECK-NEXT: adr x16, .Ltmp4
+; CHECK-NEXT: adrp x16, .Ltmp4
+; CHECK-NEXT: add x16, x16, :lo12:.Ltmp4
; CHECK-NEXT: hint #39
; CHECK-NEXT: autiasp
; CHECK-NEXT: ldr x30, [x18, #-8]!
@@ -263,12 +280,14 @@ define i32 @non_leaf_scs(i32 %x) "branch-protection-pauth-lr" "sign-return-addre
; PAUTHLR-NEXT: .cfi_escape 0x16, 0x12, 0x02, 0x82, 0x78 //
; PAUTHLR-NEXT: .Ltmp4:
; PAUTHLR-NEXT: paciasppc
+; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; PAUTHLR-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; PAUTHLR-NEXT: .cfi_negate_ra_state
; PAUTHLR-NEXT: .cfi_def_cfa_offset 16
; PAUTHLR-NEXT: .cfi_offset w30, -16
; PAUTHLR-NEXT: bl foo
; PAUTHLR-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; PAUTHLR-NEXT: adrp x16, .Ltmp4
+; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp4
; PAUTHLR-NEXT: autiasppc .Ltmp4
; PAUTHLR-NEXT: ldr x30, [x18, #-8]!
; PAUTHLR-NEXT: ret
@@ -282,8 +301,9 @@ define i32 @leaf_sign_all_v83(i32 %x) "branch-protection-pauth-lr" "sign-return-
; CHECK-NEXT: hint #39
; CHECK-NEXT: .Ltmp5:
; CHECK-NEXT: paciasp
-; CHECK-NEXT: .cfi_negate_ra_state
-; CHECK-NEXT: adr x16, .Ltmp5
+; CHECK-NEXT: .cfi_negate_ra_state_with_pc
+; CHECK-NEXT: adrp x16, .Ltmp5
+; CHECK-NEXT: add x16, x16, :lo12:.Ltmp5
; CHECK-NEXT: hint #39
; CHECK-NEXT: retaa
;
@@ -291,7 +311,9 @@ define i32 @leaf_sign_all_v83(i32 %x) "branch-protection-pauth-lr" "sign-return-
; PAUTHLR: // %bb.0:
; PAUTHLR-NEXT: .Ltmp5:
; PAUTHLR-NEXT: paciasppc
-; PAUTHLR-NEXT: .cfi_negate_ra_state
+; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
+; PAUTHLR-NEXT: adrp x16, .Ltmp5
+; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp5
; PAUTHLR-NEXT: retaasppc .Ltmp5
ret i32 %x
}
@@ -304,15 +326,16 @@ define fastcc void @spill_lr_and_tail_call(i64 %x) "branch-protection-pauth-lr"
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: .Ltmp6:
; COMPAT-NEXT: hint #25
+; COMPAT-NEXT: .cfi_negate_ra_state_with_pc
; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; COMPAT-NEXT: .cfi_negate_ra_state
; COMPAT-NEXT: .cfi_def_cfa_offset 16
; COMPAT-NEXT: .cfi_offset w30, -16
; COMPAT-NEXT: //APP
; COMPAT-NEXT: mov x30, x0
; COMPAT-NEXT: //NO_APP
; COMPAT-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; COMPAT-NEXT: adr x16, .Ltmp6
+; COMPAT-NEXT: adrp x16, .Ltmp6
+; COMPAT-NEXT: add x16, x16, :lo12:.Ltmp6
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: hint #29
; COMPAT-NEXT: b bar
@@ -322,15 +345,16 @@ define fastcc void @spill_lr_and_tail_call(i64 %x) "branch-protection-pauth-lr"
; V83A-NEXT: hint #39
; V83A-NEXT: .Ltmp6:
; V83A-NEXT: paciasp
+; V83A-NEXT: .cfi_negate_ra_state_with_pc
; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; V83A-NEXT: .cfi_negate_ra_state
; V83A-NEXT: .cfi_def_cfa_offset 16
; V83A-NEXT: .cfi_offset w30, -16
; V83A-NEXT: //APP
; V83A-NEXT: mov x30, x0
; V83A-NEXT: //NO_APP
; V83A-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
-; V83A-NEXT: adr x16, .Ltmp6
+; V83A-NEXT: adrp x16, .Ltmp6
+; V83A-NEXT: add x16, x16, :lo12:.Ltmp6
; V83A-NEXT: hint #39
; V83A-NEXT: autiasp
; V83A-NEXT: b bar
@@ -339,14 +363,16 @@ define fastcc void @spill_lr_and_tail_call(i64 %x) "branch-protection-pauth-lr"
; PAUTHLR: // %bb.0:
; PAUTHLR-NEXT: .Ltmp6:
; PAUTHLR-NEXT: paciasppc
+; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
; PAUTHLR-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
-; PAUTHLR-NEXT: .cfi_negate_ra_state
; PAUTHLR-NEXT: .cfi_def_cfa_offset 16
; PAUTHLR-NEXT: .cfi_offset w30, -16
; PAUTHLR-NEXT: //APP
; PAUTHLR-NEXT: mov x30, x0
; PAUTHLR-NEXT: //NO_APP
; PAUTHLR-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; PAUTHLR-NEXT: adrp x16, .Ltmp6
+; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp6
; PAUTHLR-NEXT: autiasppc .Ltmp6
; PAUTHLR-NEXT: b bar
call void asm sideeffect "mov x30, $0", "r,~{lr}"(i64 %x) #1
@@ -360,8 +386,9 @@ define i32 @leaf_sign_all_a_key(i32 %x) "branch-protection-pauth-lr" "sign-retur
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: .Ltmp7:
; COMPAT-NEXT: hint #25
-; COMPAT-NEXT: .cfi_negate_ra_state
-; COMPAT-NEXT: adr x16, .Ltmp7
+; COMPAT-NEXT: .cfi_negate_ra_state_with_pc
+; COMPAT-NEXT: adrp x16, .Ltmp7
+; COMPAT-NEXT: add x16, x16, :lo12:.Ltmp7
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: hint #29
; COMPAT-NEXT: ret
@@ -371,8 +398,9 @@ define i32 @leaf_sign_all_a_key(i32 %x) "branch-protection-pauth-lr" "sign-retur
; V83A-NEXT: hint #39
; V83A-NEXT: .Ltmp7:
; V83A-NEXT: paciasp
-; V83A-NEXT: .cfi_negate_ra_state
-; V83A-NEXT: adr x16, .Ltmp7
+; V83A-NEXT: .cfi_negate_ra_state_with_pc
+; V83A-NEXT: adrp x16, .Ltmp7
+; V83A-NEXT: add x16, x16, :lo12:.Ltmp7
; V83A-NEXT: hint #39
; V83A-NEXT: retaa
;
@@ -380,7 +408,9 @@ define i32 @leaf_sign_all_a_key(i32 %x) "branch-protection-pauth-lr" "sign-retur
; PAUTHLR: // %bb.0:
; PAUTHLR-NEXT: .Ltmp7:
; PAUTHLR-NEXT: paciasppc
-; PAUTHLR-NEXT: .cfi_negate_ra_state
+; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
+; PAUTHLR-NEXT: adrp x16, .Ltmp7
+; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp7
; PAUTHLR-NEXT: retaasppc .Ltmp7
ret i32 %x
}
@@ -392,8 +422,9 @@ define i32 @leaf_sign_all_b_key(i32 %x) "branch-protection-pauth-lr" "sign-retur
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: .Ltmp8:
; COMPAT-NEXT: hint #27
-; COMPAT-NEXT: .cfi_negate_ra_state
-; COMPAT-NEXT: adr x16, .Ltmp8
+; COMPAT-NEXT: .cfi_negate_ra_state_with_pc
+; COMPAT-NEXT: adrp x16, .Ltmp8
+; COMPAT-NEXT: add x16, x16, :lo12:.Ltmp8
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: hint #31
; COMPAT-NEXT: ret
@@ -404,8 +435,9 @@ define i32 @leaf_sign_all_b_key(i32 %x) "branch-protection-pauth-lr" "sign-retur
; V83A-NEXT: hint #39
; V83A-NEXT: .Ltmp8:
; V83A-NEXT: pacibsp
-; V83A-NEXT: .cfi_negate_ra_state
-; V83A-NEXT: adr x16, .Ltmp8
+; V83A-NEXT: .cfi_negate_ra_state_with_pc
+; V83A-NEXT: adrp x16, .Ltmp8
+; V83A-NEXT: add x16, x16, :lo12:.Ltmp8
; V83A-NEXT: hint #39
; V83A-NEXT: retab
;
@@ -414,7 +446,9 @@ define i32 @leaf_sign_all_b_key(i32 %x) "branch-protection-pauth-lr" "sign-retur
; PAUTHLR-NEXT: .cfi_b_key_frame
; PAUTHLR-NEXT: .Ltmp8:
; PAUTHLR-NEXT: pacibsppc
-; PAUTHLR-NEXT: .cfi_negate_ra_state
+; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
+; PAUTHLR-NEXT: adrp x16, .Ltmp8
+; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp8
; PAUTHLR-NEXT: retabsppc .Ltmp8
ret i32 %x
}
@@ -426,8 +460,9 @@ define i32 @leaf_sign_all_v83_b_key(i32 %x) "branch-protection-pauth-lr" "sign-r
; CHECK-NEXT: hint #39
; CHECK-NEXT: .Ltmp9:
; CHECK-NEXT: pacibsp
-; CHECK-NEXT: .cfi_negate_ra_state
-; CHECK-NEXT: adr x16, .Ltmp9
+; CHECK-NEXT: .cfi_negate_ra_state_with_pc
+; CHECK-NEXT: adrp x16, .Ltmp9
+; CHECK-NEXT: add x16, x16, :lo12:.Ltmp9
; CHECK-NEXT: hint #39
; CHECK-NEXT: retab
;
@@ -436,7 +471,9 @@ define i32 @leaf_sign_all_v83_b_key(i32 %x) "branch-protection-pauth-lr" "sign-r
; PAUTHLR-NEXT: .cfi_b_key_frame
; PAUTHLR-NEXT: .Ltmp9:
; PAUTHLR-NEXT: pacibsppc
-; PAUTHLR-NEXT: .cfi_negate_ra_state
+; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
+; PAUTHLR-NEXT: adrp x16, .Ltmp9
+; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp9
; PAUTHLR-NEXT: retabsppc .Ltmp9
ret i32 %x
}
@@ -449,8 +486,9 @@ define i32 @leaf_sign_all_a_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: .Ltmp10:
; COMPAT-NEXT: hint #25
-; COMPAT-NEXT: .cfi_negate_ra_state
-; COMPAT-NEXT: adr x16, .Ltmp10
+; COMPAT-NEXT: .cfi_negate_ra_state_with_pc
+; COMPAT-NEXT: adrp x16, .Ltmp10
+; COMPAT-NEXT: add x16, x16, :lo12:.Ltmp10
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: hint #29
; COMPAT-NEXT: ret
@@ -461,8 +499,9 @@ define i32 @leaf_sign_all_a_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r
; V83A-NEXT: hint #39
; V83A-NEXT: .Ltmp10:
; V83A-NEXT: paciasp
-; V83A-NEXT: .cfi_negate_ra_state
-; V83A-NEXT: adr x16, .Ltmp10
+; V83A-NEXT: .cfi_negate_ra_state_with_pc
+; V83A-NEXT: adrp x16, .Ltmp10
+; V83A-NEXT: add x16, x16, :lo12:.Ltmp10
; V83A-NEXT: hint #39
; V83A-NEXT: retaa
;
@@ -471,7 +510,9 @@ define i32 @leaf_sign_all_a_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r
; PAUTHLR-NEXT: bti c
; PAUTHLR-NEXT: .Ltmp10:
; PAUTHLR-NEXT: paciasppc
-; PAUTHLR-NEXT: .cfi_negate_ra_state
+; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
+; PAUTHLR-NEXT: adrp x16, .Ltmp10
+; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp10
; PAUTHLR-NEXT: retaasppc .Ltmp10
ret i32 %x
}
@@ -485,8 +526,9 @@ define i32 @leaf_sign_all_b_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: .Ltmp11:
; COMPAT-NEXT: hint #27
-; COMPAT-NEXT: .cfi_negate_ra_state
-; COMPAT-NEXT: adr x16, .Ltmp11
+; COMPAT-NEXT: .cfi_negate_ra_state_with_pc
+; COMPAT-NEXT: adrp x16, .Ltmp11
+; COMPAT-NEXT: add x16, x16, :lo12:.Ltmp11
; COMPAT-NEXT: hint #39
; COMPAT-NEXT: hint #31
; COMPAT-NEXT: ret
@@ -498,8 +540,9 @@ define i32 @leaf_sign_all_b_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r
; V83A-NEXT: hint #39
; V83A-NEXT: .Ltmp11:
; V83A-NEXT: pacibsp
-; V83A-NEXT: .cfi_negate_ra_state
-; V83A-NEXT: adr x16, .Ltmp11
+; V83A-NEXT: .cfi_negate_ra_state_with_pc
+; V83A-NEXT: adrp x16, .Ltmp11
+; V83A-NEXT: add x16, x16, :lo12:.Ltmp11
; V83A-NEXT: hint #39
; V83A-NEXT: retab
;
@@ -509,7 +552,9 @@ define i32 @leaf_sign_all_b_key_bti(i32 %x) "branch-protection-pauth-lr" "sign-r
; PAUTHLR-NEXT: .cfi_b_key_frame
; PAUTHLR-NEXT: .Ltmp11:
; PAUTHLR-NEXT: pacibsppc
-; PAUTHLR-NEXT: .cfi_negate_ra_state
+; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
+; PAUTHLR-NEXT: adrp x16, .Ltmp11
+; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp11
; PAUTHLR-NEXT: retabsppc .Ltmp11
ret i32 %x
}
@@ -523,8 +568,9 @@ define i32 @leaf_sign_all_v83_b_key_bti(i32 %x) "branch-protection-pauth-lr" "si
; CHECK-NEXT: hint #39
; CHECK-NEXT: .Ltmp12:
; CHECK-NEXT: pacibsp
-; CHECK-NEXT: .cfi_negate_ra_state
-; CHECK-NEXT: adr x16, .Ltmp12
+; CHECK-NEXT: .cfi_negate_ra_state_with_pc
+; CHECK-NEXT: adrp x16, .Ltmp12
+; CHECK-NEXT: add x16, x16, :lo12:.Ltmp12
; CHECK-NEXT: hint #39
; CHECK-NEXT: retab
;
@@ -534,7 +580,9 @@ define i32 @leaf_sign_all_v83_b_key_bti(i32 %x) "branch-protection-pauth-lr" "si
; PAUTHLR-NEXT: .cfi_b_key_frame
; PAUTHLR-NEXT: .Ltmp12:
; PAUTHLR-NEXT: pacibsppc
-; PAUTHLR-NEXT: .cfi_negate_ra_state
+; PAUTHLR-NEXT: .cfi_negate_ra_state_with_pc
+; PAUTHLR-NEXT: adrp x16, .Ltmp12
+; PAUTHLR-NEXT: add x16, x16, :lo12:.Ltmp12
; PAUTHLR-NEXT: retabsppc .Ltmp12
ret i32 %x
}
diff --git a/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir b/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
index a63bb8452ebbe1..d2b063a057139b 100644
--- a/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
@@ -12,6 +12,11 @@
entry:
ret i32 2
}
+
+ define dso_local i32 @foobar() "sign-return-address"="all" "branch-protection-pauth-lr"="true" {
+ entry:
+ ret i32 2
+ }
...
---
#CHECK: foo
@@ -46,3 +51,21 @@ body: |
RET_ReallyLR implicit killed $w0
...
+---
+#CHECK: foobar
+name: foobar
+alignment: 4
+tracksRegLiveness: true
+frameInfo:
+ maxCallFrameSize: 0
+#CHECK: frame-setup PACM
+#CHECK: frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp, pre-instr-symbol <mcsymbol >
+#CHECK: frame-setup CFI_INSTRUCTION negate_ra_sign_state_with_pc
+#CHECK: frame-destroy PACM
+#CHECK: frame-destroy AUTIASP implicit-def $lr, implicit $lr, implicit $sp
+body: |
+ bb.0.entry:
+ $w0 = MOVi32imm 2
+ RET_ReallyLR implicit killed $w0
+
+...
diff --git a/llvm/test/MC/AArch64/directives-case_insensitive.s b/llvm/test/MC/AArch64/directives-case_insensitive.s
index be92e00cfad11a..35a90a1bffea8d 100644
--- a/llvm/test/MC/AArch64/directives-case_insensitive.s
+++ b/llvm/test/MC/AArch64/directives-case_insensitive.s
@@ -32,10 +32,12 @@ fred .REQ x5
.CFI_STARTPROC
.CFI_NEGATE_RA_STATE
+.CFI_NEGATE_RA_STATE_WITH_PC
.CFI_B_KEY_FRAME
.CFI_ENDPROC
// CHECK: .cfi_startproc
// CHECK: .cfi_negate_ra_state
+// CHECK: .cfi_negate_ra_state_with_pc
// CHECK: .cfi_b_key_frame
// CHECK: .cfi_endproc
diff --git a/llvm/test/MC/AArch64/negate_ra_state_with_pc.s b/llvm/test/MC/AArch64/negate_ra_state_with_pc.s
new file mode 100644
index 00000000000000..44b8ab2df9a908
--- /dev/null
+++ b/llvm/test/MC/AArch64/negate_ra_state_with_pc.s
@@ -0,0 +1,7 @@
+//RUN: llvm-mc -triple=aarch64-arm-none-eabi -o - %s | FileCheck %s
+
+// CHECK: .cfi_negate_ra_state_with_pc
+foo:
+ .cfi_startproc
+ .cfi_negate_ra_state_with_pc
+ .cfi_endproc
diff --git a/llvm/unittests/DebugInfo/DWARF/DWARFDebugFrameTest.cpp b/llvm/unittests/DebugInfo/DWARF/DWARFDebugFrameTest.cpp
index 17fb18fc6b4d24..2be656547c92e0 100644
--- a/llvm/unittests/DebugInfo/DWARF/DWARFDebugFrameTest.cpp
+++ b/llvm/unittests/DebugInfo/DWARF/DWARFDebugFrameTest.cpp
@@ -174,6 +174,7 @@ TEST(DWARFDebugFrame, InvalidCFIOpcodesTest) {
dwarf::DW_CFA_MIPS_advance_loc8,
dwarf::DW_CFA_GNU_window_save,
dwarf::DW_CFA_AARCH64_negate_ra_state,
+ dwarf::DW_CFA_AARCH64_negate_ra_state_with_pc,
dwarf::DW_CFA_GNU_args_size};
dwarf::CIE TestCIE = createCIE(/*IsDWARF64=*/false,
>From 18b24b0f077dbca8b2296b8d18acbaf69eeac834 Mon Sep 17 00:00:00 2001
From: Jack Styles <jack.styles at arm.com>
Date: Wed, 9 Oct 2024 10:38:03 +0100
Subject: [PATCH 03/10] [PAuthLR] Make CFI Instruction Location Consistent
With the introduction of `.cfi_negate_ra_state_with_pc`, the location of the CFI
Instructions are inconsistent, with `.cfi_negate_ra_state_with_pc` needing to be
emitted directly after the signing instruction, and `.cfi_negate_ra_state` being
emitted with other CFI instructions as part of the prolog.
To ensure consistency between the two CFI Instructions, they are now emitted
after the CFI Instruction, regardless of which one is being used. This reverses the
changes made in #96377, as this is the commit that moved the CFI instructions
initially.
---
.../lib/Target/AArch64/AArch64PointerAuth.cpp | 18 --
.../machine-outliner-retaddr-sign-cfi.ll | 3 +-
...tliner-retaddr-sign-diff-scope-same-key.ll | 6 +-
.../machine-outliner-retaddr-sign-non-leaf.ll | 121 +++++++++++--
.../machine-outliner-retaddr-sign-regsave.mir | 3 +-
...tliner-retaddr-sign-same-scope-diff-key.ll | 139 +++++++++++---
...machine-outliner-retaddr-sign-subtarget.ll | 9 +-
.../machine-outliner-retaddr-sign-thunk.ll | 169 ++++++++++++++----
.../AArch64/pacbti-llvm-generated-funcs-2.ll | 3 +-
...sign-return-address-cfi-negate-ra-state.ll | 8 +-
.../CodeGen/AArch64/sign-return-address.ll | 18 +-
11 files changed, 370 insertions(+), 127 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp b/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
index 0879b5aec37aea..c3ad488fb8e4d1 100644
--- a/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
+++ b/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
@@ -114,29 +114,11 @@ static void emitPACCFI(const AArch64Subtarget &Subtarget,
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
auto &MF = *MBB.getParent();
auto &MFnI = *MF.getInfo<AArch64FunctionInfo>();
- bool EmitAsyncCFI = MFnI.needsAsyncDwarfUnwindInfo(MF);
auto CFIInst = MFnI.branchProtectionPAuthLR()
? MCCFIInstruction::createNegateRAStateWithPC(nullptr)
: MCCFIInstruction::createNegateRAState(nullptr);
- // Because of PAuthLR, when using NegateRAStateWithPC, the CFI instruction cannot
- // be bundled with other CFI instructions in the prolog, as it needs to directly
- // follow the signing instruction. This ensures the PC value is captured incase of
- // an error in the following the following instructions.
- if (!EmitAsyncCFI && !(MFnI.branchProtectionPAuthLR())) {
- // Reduce the size of the generated call frame information for synchronous
- // CFI by bundling the new CFI instruction with others in the prolog, so
- // that no additional DW_CFA_advance_loc is needed.
- for (auto I = MBBI; I != MBB.end(); ++I) {
- if (I->getOpcode() == TargetOpcode::CFI_INSTRUCTION &&
- I->getFlag(MachineInstr::FrameSetup)) {
- MBBI = I;
- break;
- }
- }
- }
-
unsigned CFIIndex = MF.addFrameInst(CFIInst);
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex)
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll
index c64b3842aa5baa..4bbbe40176313a 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-cfi.ll
@@ -11,8 +11,7 @@ define void @a() "sign-return-address"="all" "sign-return-address-key"="b_key" {
; CHECK-NEXT: .cfi_b_key_frame
; V8A-NEXT: hint #27
; V83A-NEXT: pacibsp
-; CHECK: .cfi_negate_ra_state
-; CHECK-NEXT: .cfi_def_cfa_offset
+; CHECK-NEXT: .cfi_negate_ra_state
%1 = alloca i32, align 4
%2 = alloca i32, align 4
%3 = alloca i32, align 4
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll
index 3221815da33c5e..6a11bef08c7406 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-diff-scope-same-key.ll
@@ -7,8 +7,7 @@ define void @a() "sign-return-address"="all" {
; CHECK-LABEL: a: // @a
; V8A: hint #25
; V83A: paciasp
-; CHECK: .cfi_negate_ra_state
-; CHECK-NEXT: .cfi_def_cfa_offset
+; CHECK-NEXT: .cfi_negate_ra_state
%1 = alloca i32, align 4
%2 = alloca i32, align 4
%3 = alloca i32, align 4
@@ -55,8 +54,7 @@ define void @c() "sign-return-address"="all" {
; CHECK-LABEL: c: // @c
; V8A: hint #25
; V83A: paciasp
-; CHECK: .cfi_negate_ra_state
-; CHECK-NEXT: .cfi_def_cfa_offset
+; CHECK-NEXT .cfi_negate_ra_state
%1 = alloca i32, align 4
%2 = alloca i32, align 4
%3 = alloca i32, align 4
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll
index d43b74b9451aae..1e7224683c6c89 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-non-leaf.ll
@@ -1,15 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple aarch64 %s -o - | \
; RUN: FileCheck %s --check-prefixes CHECK,V8A
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple aarch64 -mattr=+v8.3a %s -o - | \
; RUN: FileCheck %s --check-prefixes CHECK,V83A
define i64 @a(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" {
-; CHECK-LABEL: a: // @a
-; CHECK: .cfi_b_key_frame
-; V8A-NEXT: hint #27
-; V83A-NEXT: pacibsp
-; CHECK: .cfi_negate_ra_state
-; CHECK-NEXT: .cfi_def_cfa_offset
+; V8A-LABEL: a:
+; V8A: // %bb.0:
+; V8A-NEXT: .cfi_b_key_frame
+; V8A-NEXT: hint #27
+; V8A-NEXT: .cfi_negate_ra_state
+; V8A-NEXT: sub sp, sp, #32
+; V8A-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; V8A-NEXT: .cfi_def_cfa_offset 32
+; V8A-NEXT: .cfi_offset w30, -16
+; V8A-NEXT: bl OUTLINED_FUNCTION_0
+; V8A-NEXT: //APP
+; V8A-NEXT: mov x30, x0
+; V8A-NEXT: //NO_APP
+; V8A-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; V8A-NEXT: add sp, sp, #32
+; V8A-NEXT: hint #31
+; V8A-NEXT: ret
+;
+; V83A-LABEL: a:
+; V83A: // %bb.0:
+; V83A-NEXT: .cfi_b_key_frame
+; V83A-NEXT: pacibsp
+; V83A-NEXT: .cfi_negate_ra_state
+; V83A-NEXT: sub sp, sp, #32
+; V83A-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; V83A-NEXT: .cfi_def_cfa_offset 32
+; V83A-NEXT: .cfi_offset w30, -16
+; V83A-NEXT: bl OUTLINED_FUNCTION_0
+; V83A-NEXT: //APP
+; V83A-NEXT: mov x30, x0
+; V83A-NEXT: //NO_APP
+; V83A-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; V83A-NEXT: add sp, sp, #32
+; V83A-NEXT: retab
%1 = alloca i32, align 4
%2 = alloca i32, align 4
%3 = alloca i32, align 4
@@ -27,12 +56,40 @@ define i64 @a(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"
}
define i64 @b(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" {
-; CHECK-LABEL: b: // @b
-; CHECK: .cfi_b_key_frame
-; V8A-NEXT: hint #27
-; V83A-NEXT: pacibsp
-; CHECK: .cfi_negate_ra_state
-; CHECK-NEXT: .cfi_def_cfa_offset
+; V8A-LABEL: b:
+; V8A: // %bb.0:
+; V8A-NEXT: .cfi_b_key_frame
+; V8A-NEXT: hint #27
+; V8A-NEXT: .cfi_negate_ra_state
+; V8A-NEXT: sub sp, sp, #32
+; V8A-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; V8A-NEXT: .cfi_def_cfa_offset 32
+; V8A-NEXT: .cfi_offset w30, -16
+; V8A-NEXT: bl OUTLINED_FUNCTION_0
+; V8A-NEXT: //APP
+; V8A-NEXT: mov x30, x0
+; V8A-NEXT: //NO_APP
+; V8A-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; V8A-NEXT: add sp, sp, #32
+; V8A-NEXT: hint #31
+; V8A-NEXT: ret
+;
+; V83A-LABEL: b:
+; V83A: // %bb.0:
+; V83A-NEXT: .cfi_b_key_frame
+; V83A-NEXT: pacibsp
+; V83A-NEXT: .cfi_negate_ra_state
+; V83A-NEXT: sub sp, sp, #32
+; V83A-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; V83A-NEXT: .cfi_def_cfa_offset 32
+; V83A-NEXT: .cfi_offset w30, -16
+; V83A-NEXT: bl OUTLINED_FUNCTION_0
+; V83A-NEXT: //APP
+; V83A-NEXT: mov x30, x0
+; V83A-NEXT: //NO_APP
+; V83A-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; V83A-NEXT: add sp, sp, #32
+; V83A-NEXT: retab
%1 = alloca i32, align 4
%2 = alloca i32, align 4
%3 = alloca i32, align 4
@@ -50,12 +107,40 @@ define i64 @b(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"
}
define i64 @c(i64 %x) "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" {
-; CHECK-LABEL: c: // @c
-; CHECK: .cfi_b_key_frame
-; V8A-NEXT: hint #27
-; V83A-NEXT: pacibsp
-; CHECK: .cfi_negate_ra_state
-; CHECK-NEXT: .cfi_def_cfa_offset
+; V8A-LABEL: c:
+; V8A: // %bb.0:
+; V8A-NEXT: .cfi_b_key_frame
+; V8A-NEXT: hint #27
+; V8A-NEXT: .cfi_negate_ra_state
+; V8A-NEXT: sub sp, sp, #32
+; V8A-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; V8A-NEXT: .cfi_def_cfa_offset 32
+; V8A-NEXT: .cfi_offset w30, -16
+; V8A-NEXT: bl OUTLINED_FUNCTION_0
+; V8A-NEXT: //APP
+; V8A-NEXT: mov x30, x0
+; V8A-NEXT: //NO_APP
+; V8A-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; V8A-NEXT: add sp, sp, #32
+; V8A-NEXT: hint #31
+; V8A-NEXT: ret
+;
+; V83A-LABEL: c:
+; V83A: // %bb.0:
+; V83A-NEXT: .cfi_b_key_frame
+; V83A-NEXT: pacibsp
+; V83A-NEXT: .cfi_negate_ra_state
+; V83A-NEXT: sub sp, sp, #32
+; V83A-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; V83A-NEXT: .cfi_def_cfa_offset 32
+; V83A-NEXT: .cfi_offset w30, -16
+; V83A-NEXT: bl OUTLINED_FUNCTION_0
+; V83A-NEXT: //APP
+; V83A-NEXT: mov x30, x0
+; V83A-NEXT: //NO_APP
+; V83A-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; V83A-NEXT: add sp, sp, #32
+; V83A-NEXT: retab
%1 = alloca i32, align 4
%2 = alloca i32, align 4
%3 = alloca i32, align 4
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
index ba27d1c681e3f4..9a983cbd6714ee 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
@@ -82,8 +82,7 @@ body: |
# CHECK: bb.0:
# CHECK: frame-setup EMITBKEY
# CHECK-NEXT: frame-setup PACIBSP implicit-def $lr, implicit $lr, implicit $sp
-# CHECK: frame-setup CFI_INSTRUCTION negate_ra_sign_state
-# CHECK-NEXT: frame-setup CFI_INSTRUCTION
+# CHECK-NEXT: frame-setup CFI_INSTRUCTION negate_ra_sign_state
# CHECK-NOT: OUTLINED_FUNCTION_
# CHECK: bb.1:
# CHECK-NOT: OUTLINED_FUNCTION_
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-diff-key.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-diff-key.ll
index 8c36ab4d8f403a..87771f5de4f699 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-diff-key.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-diff-key.ll
@@ -1,14 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple aarch64 %s -o - | \
; RUN: FileCheck %s --check-prefixes CHECK,V8A
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple aarch64 -mattr=+v8.3a %s -o - | \
; RUN: FileCheck %s --check-prefixes CHECK,V83A
define void @a() "sign-return-address"="all" {
-; CHECK-LABEL: a: // @a
-; V8A: hint #25
-; V83A: paciasp
-; CHECK: .cfi_negate_ra_state
-; CHECK-NEXT: .cfi_def_cfa_offset
+; V8A-LABEL: a:
+; V8A: // %bb.0:
+; V8A-NEXT: hint #25
+; V8A-NEXT: .cfi_negate_ra_state
+; V8A-NEXT: sub sp, sp, #32
+; V8A-NEXT: .cfi_def_cfa_offset 32
+; V8A-NEXT: mov w8, #1 // =0x1
+; V8A-NEXT: mov w9, #2 // =0x2
+; V8A-NEXT: stp w9, w8, [sp, #24]
+; V8A-NEXT: mov w9, #3 // =0x3
+; V8A-NEXT: mov w8, #4 // =0x4
+; V8A-NEXT: stp w8, w9, [sp, #16]
+; V8A-NEXT: mov w9, #5 // =0x5
+; V8A-NEXT: mov w8, #6 // =0x6
+; V8A-NEXT: stp w8, w9, [sp, #8]
+; V8A-NEXT: add sp, sp, #32
+; V8A-NEXT: hint #29
+; V8A-NEXT: ret
+;
+; V83A-LABEL: a:
+; V83A: // %bb.0:
+; V83A-NEXT: paciasp
+; V83A-NEXT: .cfi_negate_ra_state
+; V83A-NEXT: sub sp, sp, #32
+; V83A-NEXT: .cfi_def_cfa_offset 32
+; V83A-NEXT: mov w8, #1 // =0x1
+; V83A-NEXT: mov w9, #2 // =0x2
+; V83A-NEXT: stp w9, w8, [sp, #24]
+; V83A-NEXT: mov w9, #3 // =0x3
+; V83A-NEXT: mov w8, #4 // =0x4
+; V83A-NEXT: stp w8, w9, [sp, #16]
+; V83A-NEXT: mov w9, #5 // =0x5
+; V83A-NEXT: mov w8, #6 // =0x6
+; V83A-NEXT: stp w8, w9, [sp, #8]
+; V83A-NEXT: add sp, sp, #32
+; V83A-NEXT: retaa
%1 = alloca i32, align 4
%2 = alloca i32, align 4
%3 = alloca i32, align 4
@@ -21,19 +53,48 @@ define void @a() "sign-return-address"="all" {
store i32 4, ptr %4, align 4
store i32 5, ptr %5, align 4
store i32 6, ptr %6, align 4
-; V8A: hint #29
-; V83A: retaa
ret void
-; CHECK: .cfi_endproc
}
define void @b() "sign-return-address"="all" "sign-return-address-key"="b_key" {
-; CHECK-LABEL: b: // @b
-; CHECK: .cfi_b_key_frame
-; V8A-NEXT: hint #27
-; V83A-NEXT: pacibsp
-; CHECK: .cfi_negate_ra_state
-; CHECK-NEXT: .cfi_def_cfa_offset
+; V8A-LABEL: b:
+; V8A: // %bb.0:
+; V8A-NEXT: .cfi_b_key_frame
+; V8A-NEXT: hint #27
+; V8A-NEXT: .cfi_negate_ra_state
+; V8A-NEXT: sub sp, sp, #32
+; V8A-NEXT: .cfi_def_cfa_offset 32
+; V8A-NEXT: mov w8, #1 // =0x1
+; V8A-NEXT: mov w9, #2 // =0x2
+; V8A-NEXT: stp w9, w8, [sp, #24]
+; V8A-NEXT: mov w9, #3 // =0x3
+; V8A-NEXT: mov w8, #4 // =0x4
+; V8A-NEXT: stp w8, w9, [sp, #16]
+; V8A-NEXT: mov w9, #5 // =0x5
+; V8A-NEXT: mov w8, #6 // =0x6
+; V8A-NEXT: stp w8, w9, [sp, #8]
+; V8A-NEXT: add sp, sp, #32
+; V8A-NEXT: hint #31
+; V8A-NEXT: ret
+;
+; V83A-LABEL: b:
+; V83A: // %bb.0:
+; V83A-NEXT: .cfi_b_key_frame
+; V83A-NEXT: pacibsp
+; V83A-NEXT: .cfi_negate_ra_state
+; V83A-NEXT: sub sp, sp, #32
+; V83A-NEXT: .cfi_def_cfa_offset 32
+; V83A-NEXT: mov w8, #1 // =0x1
+; V83A-NEXT: mov w9, #2 // =0x2
+; V83A-NEXT: stp w9, w8, [sp, #24]
+; V83A-NEXT: mov w9, #3 // =0x3
+; V83A-NEXT: mov w8, #4 // =0x4
+; V83A-NEXT: stp w8, w9, [sp, #16]
+; V83A-NEXT: mov w9, #5 // =0x5
+; V83A-NEXT: mov w8, #6 // =0x6
+; V83A-NEXT: stp w8, w9, [sp, #8]
+; V83A-NEXT: add sp, sp, #32
+; V83A-NEXT: retab
%1 = alloca i32, align 4
%2 = alloca i32, align 4
%3 = alloca i32, align 4
@@ -46,19 +107,46 @@ define void @b() "sign-return-address"="all" "sign-return-address-key"="b_key" {
store i32 4, ptr %4, align 4
store i32 5, ptr %5, align 4
store i32 6, ptr %6, align 4
-; V8A-NOT: hint #29
-; V83A-NOT: autiasp
-; V83A-NOT: retaa
ret void
-; CHECK: .cfi_endproc
}
define void @c() "sign-return-address"="all" {
-; CHECK-LABEL: c: // @c
-; V8A: hint #25
-; V83A: paciasp
-; CHECK: .cfi_negate_ra_state
-; CHECK-NEXT: .cfi_def_cfa_offset
+; V8A-LABEL: c:
+; V8A: // %bb.0:
+; V8A-NEXT: hint #25
+; V8A-NEXT: .cfi_negate_ra_state
+; V8A-NEXT: sub sp, sp, #32
+; V8A-NEXT: .cfi_def_cfa_offset 32
+; V8A-NEXT: mov w8, #1 // =0x1
+; V8A-NEXT: mov w9, #2 // =0x2
+; V8A-NEXT: stp w9, w8, [sp, #24]
+; V8A-NEXT: mov w9, #3 // =0x3
+; V8A-NEXT: mov w8, #4 // =0x4
+; V8A-NEXT: stp w8, w9, [sp, #16]
+; V8A-NEXT: mov w9, #5 // =0x5
+; V8A-NEXT: mov w8, #6 // =0x6
+; V8A-NEXT: stp w8, w9, [sp, #8]
+; V8A-NEXT: add sp, sp, #32
+; V8A-NEXT: hint #29
+; V8A-NEXT: ret
+;
+; V83A-LABEL: c:
+; V83A: // %bb.0:
+; V83A-NEXT: paciasp
+; V83A-NEXT: .cfi_negate_ra_state
+; V83A-NEXT: sub sp, sp, #32
+; V83A-NEXT: .cfi_def_cfa_offset 32
+; V83A-NEXT: mov w8, #1 // =0x1
+; V83A-NEXT: mov w9, #2 // =0x2
+; V83A-NEXT: stp w9, w8, [sp, #24]
+; V83A-NEXT: mov w9, #3 // =0x3
+; V83A-NEXT: mov w8, #4 // =0x4
+; V83A-NEXT: stp w8, w9, [sp, #16]
+; V83A-NEXT: mov w9, #5 // =0x5
+; V83A-NEXT: mov w8, #6 // =0x6
+; V83A-NEXT: stp w8, w9, [sp, #8]
+; V83A-NEXT: add sp, sp, #32
+; V83A-NEXT: retaa
%1 = alloca i32, align 4
%2 = alloca i32, align 4
%3 = alloca i32, align 4
@@ -71,11 +159,10 @@ define void @c() "sign-return-address"="all" {
store i32 4, ptr %4, align 4
store i32 5, ptr %5, align 4
store i32 6, ptr %6, align 4
-; V8A: hint #29
-; V83A: retaa
ret void
-; CHECK: .cfi_endproc
}
; CHECK-NOT: OUTLINED_FUNCTION_0:
; CHECK-NOT: // -- Begin function
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll
index d5ef94e900993c..a7ea32952f3b78 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-subtarget.ll
@@ -10,8 +10,7 @@ define void @a() #0 {
; CHECK: // %bb.0:
; CHECK-NEXT: .cfi_b_key_frame
; CHECK-NEXT: pacibsp
-; CHECK: .cfi_negate_ra_state
-; CHECK-NEXT: .cfi_def_cfa_offset
+; CHECK-NEXT: .cfi_negate_ra_state
; CHECK-NOT: OUTLINED_FUNCTION_
%1 = alloca i32, align 4
%2 = alloca i32, align 4
@@ -35,8 +34,7 @@ define void @b() #0 {
; CHECK: // %bb.0:
; CHECK-NEXT: .cfi_b_key_frame
; CHECK-NEXT: pacibsp
-; CHECK: .cfi_negate_ra_state
-; CHECK-NEXT: .cfi_def_cfa_offset
+; CHECK-NEXT: .cfi_negate_ra_state
; CHECK-NOT: OUTLINED_FUNCTION_
%1 = alloca i32, align 4
%2 = alloca i32, align 4
@@ -60,8 +58,7 @@ define void @c() #1 {
; CHECK: // %bb.0:
; CHECK-NEXT: .cfi_b_key_frame
; CHECK-NEXT: hint #27
-; CHECK: .cfi_negate_ra_state
-; CHECK-NEXT: .cfi_def_cfa_offset
+; CHECK-NEXT: .cfi_negate_ra_state
; CHECK-NOT: OUTLINED_FUNCTION_
%1 = alloca i32, align 4
%2 = alloca i32, align 4
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll
index 3e361111b54553..da68ea5bf0dbcb 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-thunk.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple aarch64-arm-linux-gnu --enable-machine-outliner -outliner-leaf-descendants=false \
; RUN: -verify-machineinstrs %s -o - | FileCheck --check-prefixes CHECK,V8A %s
; RUN: llc -mtriple aarch64 -enable-machine-outliner -outliner-leaf-descendants=false \
@@ -7,15 +8,38 @@
declare i32 @thunk_called_fn(i32, i32, i32, i32)
define i32 @a() #0 {
-; CHECK-LABEL: a: // @a
-; CHECK: // %bb.0: // %entry
-; V8A-NEXT: hint #25
-; V83A-NEXT: paciasp
-; CHECK: .cfi_negate_ra_state
-; CHECK-NEXT: .cfi_def_cfa_offset
-; V8A: hint #29
-; V8A-NEXT: ret
-; V83A: retaa
+; V8A-LABEL: a:
+; V8A: // %bb.0: // %entry
+; V8A-NEXT: hint #25
+; V8A-NEXT: .cfi_negate_ra_state
+; V8A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; V8A-NEXT: .cfi_def_cfa_offset 16
+; V8A-NEXT: .cfi_offset w30, -16
+; V8A-NEXT: mov w0, #1 // =0x1
+; V8A-NEXT: mov w1, #2 // =0x2
+; V8A-NEXT: mov w2, #3 // =0x3
+; V8A-NEXT: mov w3, #4 // =0x4
+; V8A-NEXT: bl thunk_called_fn
+; V8A-NEXT: add w0, w0, #8
+; V8A-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; V8A-NEXT: hint #29
+; V8A-NEXT: ret
+;
+; V83A-LABEL: a:
+; V83A: // %bb.0: // %entry
+; V83A-NEXT: paciasp
+; V83A-NEXT: .cfi_negate_ra_state
+; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; V83A-NEXT: .cfi_def_cfa_offset 16
+; V83A-NEXT: .cfi_offset w30, -16
+; V83A-NEXT: mov w0, #1 // =0x1
+; V83A-NEXT: mov w1, #2 // =0x2
+; V83A-NEXT: mov w2, #3 // =0x3
+; V83A-NEXT: mov w3, #4 // =0x4
+; V83A-NEXT: bl thunk_called_fn
+; V83A-NEXT: add w0, w0, #8
+; V83A-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; V83A-NEXT: retaa
entry:
%call = tail call i32 @thunk_called_fn(i32 1, i32 2, i32 3, i32 4)
%cx = add i32 %call, 8
@@ -23,15 +47,38 @@ entry:
}
define i32 @b() #0 {
-; CHECK-LABEL: b: // @b
-; CHECK: // %bb.0: // %entry
-; V8A-NEXT: hint #25
-; V83A-NEXT: paciasp
-; CHECK: .cfi_negate_ra_state
-; CHECK-NEXT: .cfi_def_cfa_offset
-; V8A: hint #29
-; V8A-NEXT: ret
-; V83A: retaa
+; V8A-LABEL: b:
+; V8A: // %bb.0: // %entry
+; V8A-NEXT: hint #25
+; V8A-NEXT: .cfi_negate_ra_state
+; V8A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; V8A-NEXT: .cfi_def_cfa_offset 16
+; V8A-NEXT: .cfi_offset w30, -16
+; V8A-NEXT: mov w0, #1 // =0x1
+; V8A-NEXT: mov w1, #2 // =0x2
+; V8A-NEXT: mov w2, #3 // =0x3
+; V8A-NEXT: mov w3, #4 // =0x4
+; V8A-NEXT: bl thunk_called_fn
+; V8A-NEXT: add w0, w0, #88
+; V8A-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; V8A-NEXT: hint #29
+; V8A-NEXT: ret
+;
+; V83A-LABEL: b:
+; V83A: // %bb.0: // %entry
+; V83A-NEXT: paciasp
+; V83A-NEXT: .cfi_negate_ra_state
+; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; V83A-NEXT: .cfi_def_cfa_offset 16
+; V83A-NEXT: .cfi_offset w30, -16
+; V83A-NEXT: mov w0, #1 // =0x1
+; V83A-NEXT: mov w1, #2 // =0x2
+; V83A-NEXT: mov w2, #3 // =0x3
+; V83A-NEXT: mov w3, #4 // =0x4
+; V83A-NEXT: bl thunk_called_fn
+; V83A-NEXT: add w0, w0, #88
+; V83A-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; V83A-NEXT: retaa
entry:
%call = tail call i32 @thunk_called_fn(i32 1, i32 2, i32 3, i32 4)
%cx = add i32 %call, 88
@@ -39,15 +86,40 @@ entry:
}
define hidden i32 @c(ptr %fptr) #0 {
-; CHECK-LABEL: c: // @c
-; CHECK: // %bb.0: // %entry
-; V8A-NEXT: hint #25
-; V83A-NEXT: paciasp
-; CHECK: .cfi_negate_ra_state
-; CHECK-NEXT: .cfi_def_cfa_offset
-; V8A: hint #29
-; V8A-NEXT: ret
-; V83A: retaa
+; V8A-LABEL: c:
+; V8A: // %bb.0: // %entry
+; V8A-NEXT: hint #25
+; V8A-NEXT: .cfi_negate_ra_state
+; V8A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; V8A-NEXT: .cfi_def_cfa_offset 16
+; V8A-NEXT: .cfi_offset w30, -16
+; V8A-NEXT: mov x8, x0
+; V8A-NEXT: mov w0, #1 // =0x1
+; V8A-NEXT: mov w1, #2 // =0x2
+; V8A-NEXT: mov w2, #3 // =0x3
+; V8A-NEXT: mov w3, #4 // =0x4
+; V8A-NEXT: blr x8
+; V8A-NEXT: add w0, w0, #8
+; V8A-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; V8A-NEXT: hint #29
+; V8A-NEXT: ret
+;
+; V83A-LABEL: c:
+; V83A: // %bb.0: // %entry
+; V83A-NEXT: paciasp
+; V83A-NEXT: .cfi_negate_ra_state
+; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; V83A-NEXT: .cfi_def_cfa_offset 16
+; V83A-NEXT: .cfi_offset w30, -16
+; V83A-NEXT: mov x8, x0
+; V83A-NEXT: mov w0, #1 // =0x1
+; V83A-NEXT: mov w1, #2 // =0x2
+; V83A-NEXT: mov w2, #3 // =0x3
+; V83A-NEXT: mov w3, #4 // =0x4
+; V83A-NEXT: blr x8
+; V83A-NEXT: add w0, w0, #8
+; V83A-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; V83A-NEXT: retaa
entry:
%call = tail call i32 %fptr(i32 1, i32 2, i32 3, i32 4)
%add = add nsw i32 %call, 8
@@ -55,15 +127,40 @@ entry:
}
define hidden i32 @d(ptr %fptr) #0 {
-; CHECK-LABEL: d: // @d
-; CHECK: // %bb.0: // %entry
-; V8A-NEXT: hint #25
-; V83A-NEXT: paciasp
-; CHECK: .cfi_negate_ra_state
-; CHECK-NEXT: .cfi_def_cfa_offset
-; V8A: hint #29
-; V8A-NEXT: ret
-; V83A: retaa
+; V8A-LABEL: d:
+; V8A: // %bb.0: // %entry
+; V8A-NEXT: hint #25
+; V8A-NEXT: .cfi_negate_ra_state
+; V8A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; V8A-NEXT: .cfi_def_cfa_offset 16
+; V8A-NEXT: .cfi_offset w30, -16
+; V8A-NEXT: mov x8, x0
+; V8A-NEXT: mov w0, #1 // =0x1
+; V8A-NEXT: mov w1, #2 // =0x2
+; V8A-NEXT: mov w2, #3 // =0x3
+; V8A-NEXT: mov w3, #4 // =0x4
+; V8A-NEXT: blr x8
+; V8A-NEXT: add w0, w0, #88
+; V8A-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; V8A-NEXT: hint #29
+; V8A-NEXT: ret
+;
+; V83A-LABEL: d:
+; V83A: // %bb.0: // %entry
+; V83A-NEXT: paciasp
+; V83A-NEXT: .cfi_negate_ra_state
+; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
+; V83A-NEXT: .cfi_def_cfa_offset 16
+; V83A-NEXT: .cfi_offset w30, -16
+; V83A-NEXT: mov x8, x0
+; V83A-NEXT: mov w0, #1 // =0x1
+; V83A-NEXT: mov w1, #2 // =0x2
+; V83A-NEXT: mov w2, #3 // =0x3
+; V83A-NEXT: mov w3, #4 // =0x4
+; V83A-NEXT: blr x8
+; V83A-NEXT: add w0, w0, #88
+; V83A-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
+; V83A-NEXT: retaa
entry:
%call = tail call i32 %fptr(i32 1, i32 2, i32 3, i32 4)
%add = add nsw i32 %call, 88
diff --git a/llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll b/llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll
index 0969ec246399fe..373c4969a9405c 100644
--- a/llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll
+++ b/llvm/test/CodeGen/AArch64/pacbti-llvm-generated-funcs-2.ll
@@ -35,8 +35,7 @@ entry:
;; CHECK-LABEL: __llvm_gcov_writeout:
;; CHECK: .cfi_b_key_frame
;; CHECK-NEXT: pacibsp
-;; CHECK: .cfi_negate_ra_state
-;; CHECK-NEXT: .cfi_def_cfa_offset
+;; CHECK-NEXT: .cfi_negate_ra_state
define internal void @__llvm_gcov_reset() unnamed_addr #2 {
entry:
diff --git a/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll b/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
index fbf571eabd8015..4d4b7c215b978a 100644
--- a/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
+++ b/llvm/test/CodeGen/AArch64/sign-return-address-cfi-negate-ra-state.ll
@@ -10,8 +10,8 @@ define dso_local i32 @_Z3fooi(i32 %x) #0 {
; CHECK-V8A-LABEL: _Z3fooi:
; CHECK-V8A: // %bb.0: // %entry
; CHECK-V8A-NEXT: hint #25
-; CHECK-V8A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-V8A-NEXT: .cfi_negate_ra_state
+; CHECK-V8A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-V8A-NEXT: .cfi_def_cfa_offset 16
; CHECK-V8A-NEXT: .cfi_offset w30, -16
; CHECK-V8A-NEXT: str w0, [sp, #8]
@@ -28,8 +28,8 @@ define dso_local i32 @_Z3fooi(i32 %x) #0 {
; CHECK-V83A-LABEL: _Z3fooi:
; CHECK-V83A: // %bb.0: // %entry
; CHECK-V83A-NEXT: paciasp
-; CHECK-V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-V83A-NEXT: .cfi_negate_ra_state
+; CHECK-V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-V83A-NEXT: .cfi_def_cfa_offset 16
; CHECK-V83A-NEXT: .cfi_offset w30, -16
; CHECK-V83A-NEXT: str w0, [sp, #8]
@@ -144,8 +144,8 @@ define hidden noundef i32 @baz_sync(i32 noundef %a) #0 uwtable(sync) {
; CHECK-V8A-LABEL: baz_sync:
; CHECK-V8A: // %bb.0: // %entry
; CHECK-V8A-NEXT: hint #25
-; CHECK-V8A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-V8A-NEXT: .cfi_negate_ra_state
+; CHECK-V8A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-V8A-NEXT: .cfi_def_cfa_offset 16
; CHECK-V8A-NEXT: .cfi_offset w30, -16
; CHECK-V8A-NEXT: cbz w0, .LBB2_2
@@ -165,8 +165,8 @@ define hidden noundef i32 @baz_sync(i32 noundef %a) #0 uwtable(sync) {
; CHECK-V83A-LABEL: baz_sync:
; CHECK-V83A: // %bb.0: // %entry
; CHECK-V83A-NEXT: paciasp
-; CHECK-V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-V83A-NEXT: .cfi_negate_ra_state
+; CHECK-V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-V83A-NEXT: .cfi_def_cfa_offset 16
; CHECK-V83A-NEXT: .cfi_offset w30, -16
; CHECK-V83A-NEXT: cbz w0, .LBB2_2
diff --git a/llvm/test/CodeGen/AArch64/sign-return-address.ll b/llvm/test/CodeGen/AArch64/sign-return-address.ll
index c33463eb96a687..dafe0d71ceb5f7 100644
--- a/llvm/test/CodeGen/AArch64/sign-return-address.ll
+++ b/llvm/test/CodeGen/AArch64/sign-return-address.ll
@@ -46,8 +46,8 @@ define i64 @leaf_clobbers_lr(i64 %x) "sign-return-address"="non-leaf" {
; COMPAT-LABEL: leaf_clobbers_lr:
; COMPAT: // %bb.0:
; COMPAT-NEXT: hint #25
-; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; COMPAT-NEXT: .cfi_negate_ra_state
+; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; COMPAT-NEXT: .cfi_def_cfa_offset 16
; COMPAT-NEXT: .cfi_offset w30, -16
; COMPAT-NEXT: //APP
@@ -60,8 +60,8 @@ define i64 @leaf_clobbers_lr(i64 %x) "sign-return-address"="non-leaf" {
; V83A-LABEL: leaf_clobbers_lr:
; V83A: // %bb.0:
; V83A-NEXT: paciasp
-; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; V83A-NEXT: .cfi_negate_ra_state
+; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; V83A-NEXT: .cfi_def_cfa_offset 16
; V83A-NEXT: .cfi_offset w30, -16
; V83A-NEXT: //APP
@@ -79,8 +79,8 @@ define i32 @non_leaf_sign_all(i32 %x) "sign-return-address"="all" {
; COMPAT-LABEL: non_leaf_sign_all:
; COMPAT: // %bb.0:
; COMPAT-NEXT: hint #25
-; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; COMPAT-NEXT: .cfi_negate_ra_state
+; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; COMPAT-NEXT: .cfi_def_cfa_offset 16
; COMPAT-NEXT: .cfi_offset w30, -16
; COMPAT-NEXT: bl foo
@@ -91,8 +91,8 @@ define i32 @non_leaf_sign_all(i32 %x) "sign-return-address"="all" {
; V83A-LABEL: non_leaf_sign_all:
; V83A: // %bb.0:
; V83A-NEXT: paciasp
-; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; V83A-NEXT: .cfi_negate_ra_state
+; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; V83A-NEXT: .cfi_def_cfa_offset 16
; V83A-NEXT: .cfi_offset w30, -16
; V83A-NEXT: bl foo
@@ -106,8 +106,8 @@ define i32 @non_leaf_sign_non_leaf(i32 %x) "sign-return-address"="non-leaf" {
; COMPAT-LABEL: non_leaf_sign_non_leaf:
; COMPAT: // %bb.0:
; COMPAT-NEXT: hint #25
-; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; COMPAT-NEXT: .cfi_negate_ra_state
+; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; COMPAT-NEXT: .cfi_def_cfa_offset 16
; COMPAT-NEXT: .cfi_offset w30, -16
; COMPAT-NEXT: bl foo
@@ -118,8 +118,8 @@ define i32 @non_leaf_sign_non_leaf(i32 %x) "sign-return-address"="non-leaf" {
; V83A-LABEL: non_leaf_sign_non_leaf:
; V83A: // %bb.0:
; V83A-NEXT: paciasp
-; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; V83A-NEXT: .cfi_negate_ra_state
+; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; V83A-NEXT: .cfi_def_cfa_offset 16
; V83A-NEXT: .cfi_offset w30, -16
; V83A-NEXT: bl foo
@@ -136,8 +136,8 @@ define i32 @non_leaf_scs(i32 %x) "sign-return-address"="non-leaf" shadowcallstac
; CHECK-NEXT: str x30, [x18], #8
; CHECK-NEXT: .cfi_escape 0x16, 0x12, 0x02, 0x82, 0x78 //
; CHECK-NEXT: paciasp
-; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_negate_ra_state
+; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: bl foo
@@ -164,8 +164,8 @@ define fastcc void @spill_lr_and_tail_call(i64 %x) "sign-return-address"="all" {
; COMPAT-LABEL: spill_lr_and_tail_call:
; COMPAT: // %bb.0:
; COMPAT-NEXT: hint #25
-; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; COMPAT-NEXT: .cfi_negate_ra_state
+; COMPAT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; COMPAT-NEXT: .cfi_def_cfa_offset 16
; COMPAT-NEXT: .cfi_offset w30, -16
; COMPAT-NEXT: //APP
@@ -178,8 +178,8 @@ define fastcc void @spill_lr_and_tail_call(i64 %x) "sign-return-address"="all" {
; V83A-LABEL: spill_lr_and_tail_call:
; V83A: // %bb.0:
; V83A-NEXT: paciasp
-; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; V83A-NEXT: .cfi_negate_ra_state
+; V83A-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; V83A-NEXT: .cfi_def_cfa_offset 16
; V83A-NEXT: .cfi_offset w30, -16
; V83A-NEXT: //APP
>From a9b291d454cd55f6d02769e941ee966185106135 Mon Sep 17 00:00:00 2001
From: Thomas Preud'homme <thomas.preudhomme at arm.com>
Date: Mon, 14 Oct 2024 09:44:44 +0100
Subject: [PATCH 04/10] Fix CMake dependencies on mlir-linalg-ods-yaml-gen
(#111973)
Fix a number of dependencies issue to build mlir-linalg-ods-yaml-gen
host binary which make a cross-build using the Make generator fail.
Namely:
- do not use binary path for the custom target created when
LLVM_USE_HOST_TOOLS is true;
- use target name instead of name of variable holding the target name
for add_custom_target and set_target_properties in setup_host_tool();
- remove dependency on target defined in different directory in
add_linalg_ods_yaml_gen() since add_custom_target DEPENDS can only be
used on "files and outputs of custom commands created with
add_custom_command() command calls in the same directory";
- remove unneeded dependency on ${MLIR_LINALG_ODS_YAML_GEN_EXE}, the
target dependency will ensure the binary will be built.
Note that we keep using ${MLIR_LINALG_ODS_YAML_GEN_EXE} in the COMMAND
rather than use ${MLIR_LINALG_ODS_YAML_GEN_TARGET} because when
LLVM_NATIVE_TOOL_DIR is used the latter is an empty string.
Testing-wise, all three codepaths in get_host_tool_path() were tested
with both GNU Make and Ninja generators:
- cross-compiling with LLVM_NATIVE_TOOL_DIR checks the if path;
- cross-compiling without LLVM_NATIVE_TOOL_DIR checks the elseif path;
- native build without LLVM_NATIVE_TOOL_DIR checks the else path.
---
llvm/cmake/modules/AddLLVM.cmake | 6 +++---
mlir/include/mlir/Dialect/Linalg/IR/CMakeLists.txt | 3 ---
2 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/llvm/cmake/modules/AddLLVM.cmake b/llvm/cmake/modules/AddLLVM.cmake
index c62b5649facae1..abffa3ec20386f 100644
--- a/llvm/cmake/modules/AddLLVM.cmake
+++ b/llvm/cmake/modules/AddLLVM.cmake
@@ -2618,7 +2618,7 @@ function(get_host_tool_path tool_name setting_name exe_var_name target_var_name)
set(target_name "")
elseif(LLVM_USE_HOST_TOOLS)
get_native_tool_path(${tool_name} exe_name)
- set(target_name ${exe_name})
+ set(target_name host_${tool_name})
else()
set(exe_name $<TARGET_FILE:${tool_name}>)
set(target_name ${tool_name})
@@ -2632,8 +2632,8 @@ function(setup_host_tool tool_name setting_name exe_var_name target_var_name)
# Set up a native tool build if necessary
if(LLVM_USE_HOST_TOOLS AND NOT ${setting_name})
build_native_tool(${tool_name} exe_name DEPENDS ${tool_name})
- add_custom_target(${target_var_name} DEPENDS ${exe_name})
+ add_custom_target(${${target_var_name}} DEPENDS ${exe_name})
get_subproject_title(subproject_title)
- set_target_properties(${target_var_name} PROPERTIES FOLDER "${subproject_title}/Native")
+ set_target_properties(${${target_var_name}} PROPERTIES FOLDER "${subproject_title}/Native")
endif()
endfunction()
diff --git a/mlir/include/mlir/Dialect/Linalg/IR/CMakeLists.txt b/mlir/include/mlir/Dialect/Linalg/IR/CMakeLists.txt
index 289c0e4bbdaf68..71214b4404c550 100644
--- a/mlir/include/mlir/Dialect/Linalg/IR/CMakeLists.txt
+++ b/mlir/include/mlir/Dialect/Linalg/IR/CMakeLists.txt
@@ -15,13 +15,10 @@ function(add_linalg_ods_yaml_gen yaml_ast_file output_file)
MAIN_DEPENDENCY
${YAML_AST_SOURCE}
DEPENDS
- ${MLIR_LINALG_ODS_YAML_GEN_EXE}
${MLIR_LINALG_ODS_YAML_GEN_TARGET})
add_custom_target(
MLIR${output_file}YamlIncGen
DEPENDS
- ${MLIR_LINALG_ODS_YAML_GEN_EXE}
- ${MLIR_LINALG_ODS_YAML_GEN_TARGET}
${GEN_ODS_FILE} ${GEN_CPP_FILE})
set_target_properties(MLIR${output_file}YamlIncGen PROPERTIES FOLDER "MLIR/Tablegenning")
list(APPEND LLVM_TARGET_DEPENDS ${GEN_ODS_FILE})
>From 900bda4c8457e43697345444c4a66b1efd4ef804 Mon Sep 17 00:00:00 2001
From: Akshat Oke <76596238+optimisan at users.noreply.github.com>
Date: Mon, 14 Oct 2024 14:19:53 +0530
Subject: [PATCH 05/10] [MIR] Serialize virtual register flags (#110228)
[MIR] Serialize virtual register flags
This introduces target-specific vreg flag serialization. Flags are represented as `uint8_t` and the `TargetRegisterInfo` override provides methods `getVRegFlagValue` to deserialize and `getVRegFlagsOfReg` to serialize.
---
.../include/llvm/CodeGen/MIRParser/MIParser.h | 7 +-
llvm/include/llvm/CodeGen/MIRYamlMapping.h | 3 +
.../include/llvm/CodeGen/TargetRegisterInfo.h | 9 +++
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 10 +++
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 9 +++
llvm/lib/CodeGen/MIRPrinter.cpp | 27 +++++--
llvm/test/CodeGen/AMDGPU/limit-coalesce.mir | 14 ++--
.../MIR/Generic/register-flag-error.mir | 13 ++++
...cted-named-register-in-allocation-hint.mir | 4 +-
.../CodeGen/MIR/X86/generic-instr-type.mir | 10 +--
.../MIR/X86/register-operand-class.mir | 10 +--
llvm/test/CodeGen/MIR/X86/roundtrip.mir | 4 +-
.../X86/simple-register-allocation-hints.mir | 6 +-
.../CodeGen/MIR/X86/virtual-registers.mir | 12 ++--
.../X86/GlobalISel/legalize-mul-v128.mir | 18 ++---
.../X86/GlobalISel/legalize-mul-v256.mir | 18 ++---
.../X86/GlobalISel/legalize-mul-v512.mir | 18 ++---
.../X86/GlobalISel/regbankselect-AVX2.mir | 20 +++---
.../X86/GlobalISel/regbankselect-AVX512.mir | 20 +++---
.../X86/GlobalISel/regbankselect-X32.mir | 10 +--
.../CodeGen/X86/GlobalISel/select-GV-32.mir | 12 ++--
.../CodeGen/X86/GlobalISel/select-GV-64.mir | 8 +--
.../X86/GlobalISel/select-add-v128.mir | 72 +++++++++----------
.../X86/GlobalISel/select-add-v256.mir | 72 +++++++++----------
.../CodeGen/X86/GlobalISel/select-copy.mir | 38 +++++-----
.../X86/GlobalISel/select-extract-vec256.mir | 16 ++---
.../X86/GlobalISel/select-extract-vec512.mir | 16 ++---
.../CodeGen/X86/GlobalISel/select-inc.mir | 8 +--
.../X86/GlobalISel/select-memop-v256.mir | 24 +++----
.../X86/GlobalISel/x86-legalize-GV.mir | 2 +-
.../X86/GlobalISel/x86_64-legalize-GV.mir | 2 +-
.../llvm-reduce/mir/preserve-reg-hints.mir | 10 +--
32 files changed, 290 insertions(+), 232 deletions(-)
create mode 100644 llvm/test/CodeGen/MIR/Generic/register-flag-error.mir
diff --git a/llvm/include/llvm/CodeGen/MIRParser/MIParser.h b/llvm/include/llvm/CodeGen/MIRParser/MIParser.h
index 7fd9d99ded6995..4d93213de5e070 100644
--- a/llvm/include/llvm/CodeGen/MIRParser/MIParser.h
+++ b/llvm/include/llvm/CodeGen/MIRParser/MIParser.h
@@ -37,9 +37,7 @@ class TargetRegisterClass;
class TargetSubtargetInfo;
struct VRegInfo {
- enum uint8_t {
- UNKNOWN, NORMAL, GENERIC, REGBANK
- } Kind = UNKNOWN;
+ enum : uint8_t { UNKNOWN, NORMAL, GENERIC, REGBANK } Kind = UNKNOWN;
bool Explicit = false; ///< VReg was explicitly specified in the .mir file.
union {
const TargetRegisterClass *RC;
@@ -47,6 +45,7 @@ struct VRegInfo {
} D;
Register VReg;
Register PreferredReg;
+ std::vector<uint8_t> Flags;
};
using Name2RegClassMap = StringMap<const TargetRegisterClass *>;
@@ -150,6 +149,8 @@ struct PerTargetMIParsingState {
/// Return null if the name isn't a register bank.
const RegisterBank *getRegBank(StringRef Name);
+ bool getVRegFlagValue(StringRef FlagName, uint8_t &FlagValue) const;
+
PerTargetMIParsingState(const TargetSubtargetInfo &STI)
: Subtarget(STI) {
initNames2RegClasses();
diff --git a/llvm/include/llvm/CodeGen/MIRYamlMapping.h b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
index c5bf6971df4535..09a6ca936fe1f4 100644
--- a/llvm/include/llvm/CodeGen/MIRYamlMapping.h
+++ b/llvm/include/llvm/CodeGen/MIRYamlMapping.h
@@ -191,6 +191,7 @@ struct VirtualRegisterDefinition {
UnsignedValue ID;
StringValue Class;
StringValue PreferredRegister;
+ std::vector<FlowStringValue> RegisterFlags;
// TODO: Serialize the target specific register hints.
@@ -206,6 +207,8 @@ template <> struct MappingTraits<VirtualRegisterDefinition> {
YamlIO.mapRequired("class", Reg.Class);
YamlIO.mapOptional("preferred-register", Reg.PreferredRegister,
StringValue()); // Don't print out when it's empty.
+ YamlIO.mapOptional("flags", Reg.RegisterFlags,
+ std::vector<FlowStringValue>());
}
static const bool flow = true;
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 9ea0fba1144b13..292fa3c94969be 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -1213,6 +1213,15 @@ class TargetRegisterInfo : public MCRegisterInfo {
virtual bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const {
return false;
}
+
+ virtual std::optional<uint8_t> getVRegFlagValue(StringRef Name) const {
+ return {};
+ }
+
+ virtual SmallVector<StringLiteral>
+ getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const {
+ return {};
+ }
};
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index a00cf0b906d5a0..5e7c93f329302e 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -127,6 +127,16 @@ bool PerTargetMIParsingState::getRegisterByName(StringRef RegName,
return false;
}
+bool PerTargetMIParsingState::getVRegFlagValue(StringRef FlagName,
+ uint8_t &FlagValue) const {
+ const auto *TRI = Subtarget.getRegisterInfo();
+ std::optional<uint8_t> FV = TRI->getVRegFlagValue(FlagName);
+ if (!FV)
+ return true;
+ FlagValue = *FV;
+ return false;
+}
+
void PerTargetMIParsingState::initNames2InstrOpCodes() {
if (!Names2InstrOpCodes.empty())
return;
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 30b1a717caaab9..0c8a3eb6c2d83d 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -696,6 +696,15 @@ bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
VReg.PreferredRegister.Value, Error))
return error(Error, VReg.PreferredRegister.SourceRange);
}
+
+ for (const auto &FlagStringValue : VReg.RegisterFlags) {
+ uint8_t FlagValue;
+ if (Target->getVRegFlagValue(FlagStringValue.Value, FlagValue))
+ return error(FlagStringValue.SourceRange.Start,
+ Twine("use of undefined register flag '") +
+ FlagStringValue.Value + "'");
+ Info.Flags.push_back(FlagValue);
+ }
}
// Parse the liveins.
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index d52c1d831267f6..a015cd3c2a55f9 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -113,7 +113,8 @@ class MIRPrinter {
void print(const MachineFunction &MF);
- void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
+ void convert(yaml::MachineFunction &YamlMF, const MachineFunction &MF,
+ const MachineRegisterInfo &RegInfo,
const TargetRegisterInfo *TRI);
void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
const MachineFrameInfo &MFI);
@@ -231,7 +232,7 @@ void MIRPrinter::print(const MachineFunction &MF) {
YamlMF.NoVRegs = MF.getProperties().hasProperty(
MachineFunctionProperties::Property::NoVRegs);
- convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
+ convert(YamlMF, MF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
MachineModuleSlotTracker MST(MMI, &MF);
MST.incorporateFunction(MF.getFunction());
convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
@@ -316,10 +317,21 @@ printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar,
}
}
-void MIRPrinter::convert(yaml::MachineFunction &MF,
+static void printRegFlags(Register Reg,
+ std::vector<yaml::FlowStringValue> &RegisterFlags,
+ const MachineFunction &MF,
+ const TargetRegisterInfo *TRI) {
+ auto FlagValues = TRI->getVRegFlagsOfReg(Reg, MF);
+ for (auto &Flag : FlagValues) {
+ RegisterFlags.push_back(yaml::FlowStringValue(Flag.str()));
+ }
+}
+
+void MIRPrinter::convert(yaml::MachineFunction &YamlMF,
+ const MachineFunction &MF,
const MachineRegisterInfo &RegInfo,
const TargetRegisterInfo *TRI) {
- MF.TracksRegLiveness = RegInfo.tracksLiveness();
+ YamlMF.TracksRegLiveness = RegInfo.tracksLiveness();
// Print the virtual register definitions.
for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
@@ -332,7 +344,8 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
Register PreferredReg = RegInfo.getSimpleHint(Reg);
if (PreferredReg)
printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
- MF.VirtualRegisters.push_back(VReg);
+ printRegFlags(Reg, VReg.RegisterFlags, MF, TRI);
+ YamlMF.VirtualRegisters.push_back(VReg);
}
// Print the live ins.
@@ -341,7 +354,7 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
printRegMIR(LI.first, LiveIn.Register, TRI);
if (LI.second)
printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
- MF.LiveIns.push_back(LiveIn);
+ YamlMF.LiveIns.push_back(LiveIn);
}
// Prints the callee saved registers.
@@ -353,7 +366,7 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
printRegMIR(*I, Reg, TRI);
CalleeSavedRegisters.push_back(Reg);
}
- MF.CalleeSavedRegisters = CalleeSavedRegisters;
+ YamlMF.CalleeSavedRegisters = CalleeSavedRegisters;
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir b/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
index b9105418a588c3..ca774825f4ddef 100644
--- a/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
+++ b/llvm/test/CodeGen/AMDGPU/limit-coalesce.mir
@@ -2,13 +2,13 @@
# Check that coalescer does not create wider register tuple than in source
-# CHECK: - { id: 2, class: vreg_64, preferred-register: '' }
-# CHECK: - { id: 3, class: vreg_64, preferred-register: '' }
-# CHECK: - { id: 4, class: vreg_64, preferred-register: '' }
-# CHECK: - { id: 5, class: vreg_96, preferred-register: '' }
-# CHECK: - { id: 6, class: vreg_96, preferred-register: '' }
-# CHECK: - { id: 7, class: vreg_128, preferred-register: '' }
-# CHECK: - { id: 8, class: vreg_128, preferred-register: '' }
+# CHECK: - { id: 2, class: vreg_64, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 3, class: vreg_64, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 4, class: vreg_64, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 5, class: vreg_96, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 6, class: vreg_96, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 7, class: vreg_128, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 8, class: vreg_128, preferred-register: '', flags: [ ] }
# No more registers shall be defined
# CHECK-NEXT: liveins:
# CHECK: FLAT_STORE_DWORDX2 $vgpr0_vgpr1, %4,
diff --git a/llvm/test/CodeGen/MIR/Generic/register-flag-error.mir b/llvm/test/CodeGen/MIR/Generic/register-flag-error.mir
new file mode 100644
index 00000000000000..efbcf23af071ed
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/Generic/register-flag-error.mir
@@ -0,0 +1,13 @@
+# RUN: not llc -run-pass=none -filetype=null %s 2>&1 | FileCheck %s --check-prefix=ERR
+
+---
+name: flags
+registers:
+ - { id: 0, class: _, flags: [ 'VFLAG_ERR' ] }
+body: |
+ bb.0:
+ liveins: $w0
+ %0 = G_ADD $w0, $w0
+...
+# ERR: use of undefined register flag
+# ERR: VFLAG_ERR
diff --git a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
index 7ed390570adc7c..03f2ec4d6cd3f7 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
@@ -14,8 +14,8 @@ name: test
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
- # CHECK: - { id: 1, class: gr32, preferred-register: '%0' }
- # CHECK: - { id: 2, class: gr32, preferred-register: '$edi' }
+ # CHECK: - { id: 1, class: gr32, preferred-register: '%0', flags: [ ] }
+ # CHECK: - { id: 2, class: gr32, preferred-register: '$edi', flags: [ ] }
- { id: 1, class: gr32, preferred-register: '%0' }
- { id: 2, class: gr32, preferred-register: '$edi' }
body: |
diff --git a/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
index 710a18ac3aeff4..7514cdab0ab110 100644
--- a/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
+++ b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir
@@ -18,11 +18,11 @@
---
name: test_vregs
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' }
-# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' }
-# CHECK-NEXT: - { id: 3, class: _, preferred-register: '' }
-# CHECK-NEXT: - { id: 4, class: _, preferred-register: '' }
+# CHECK-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 3, class: _, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 4, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
diff --git a/llvm/test/CodeGen/MIR/X86/register-operand-class.mir b/llvm/test/CodeGen/MIR/X86/register-operand-class.mir
index f62d7294eabc10..521722d9f24c54 100644
--- a/llvm/test/CodeGen/MIR/X86/register-operand-class.mir
+++ b/llvm/test/CodeGen/MIR/X86/register-operand-class.mir
@@ -6,11 +6,11 @@
---
# CHECK-LABEL: name: func
# CHECK: registers:
-# CHECK: - { id: 0, class: gr32, preferred-register: '' }
-# CHECK: - { id: 1, class: gr64, preferred-register: '' }
-# CHECK: - { id: 2, class: gr32, preferred-register: '' }
-# CHECK: - { id: 3, class: gr16, preferred-register: '' }
-# CHECK: - { id: 4, class: _, preferred-register: '' }
+# CHECK: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 2, class: gr32, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 3, class: gr16, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 4, class: _, preferred-register: '', flags: [ ] }
name: func
body: |
bb.0:
diff --git a/llvm/test/CodeGen/MIR/X86/roundtrip.mir b/llvm/test/CodeGen/MIR/X86/roundtrip.mir
index 46f08ad1a214da..6124113a0dd88f 100644
--- a/llvm/test/CodeGen/MIR/X86/roundtrip.mir
+++ b/llvm/test/CodeGen/MIR/X86/roundtrip.mir
@@ -2,8 +2,8 @@
---
# CHECK-LABEL: name: func0
# CHECK: registers:
-# CHECK: - { id: 0, class: gr32, preferred-register: '' }
-# CHECK: - { id: 1, class: gr32, preferred-register: '' }
+# CHECK: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
# CHECK: body: |
# CHECK: bb.0:
# CHECK: %0:gr32 = MOV32r0 implicit-def $eflags
diff --git a/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir b/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
index 84d298dbd40700..aacf66c98cf5d3 100644
--- a/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
+++ b/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir
@@ -15,9 +15,9 @@
name: test
tracksRegLiveness: true
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '$esi' }
-# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '$edi' }
+# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '$esi', flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '$edi', flags: [ ] }
registers:
- { id: 0, class: gr32 }
- { id: 1, class: gr32, preferred-register: '$esi' }
diff --git a/llvm/test/CodeGen/MIR/X86/virtual-registers.mir b/llvm/test/CodeGen/MIR/X86/virtual-registers.mir
index e317746e08a18e..819f65638b67de 100644
--- a/llvm/test/CodeGen/MIR/X86/virtual-registers.mir
+++ b/llvm/test/CodeGen/MIR/X86/virtual-registers.mir
@@ -33,9 +33,9 @@
name: bar
tracksRegLiveness: true
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
-# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '' }
+# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gr32 }
- { id: 1, class: gr32 }
@@ -67,9 +67,9 @@ name: foo
tracksRegLiveness: true
# CHECK: name: foo
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
-# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '' }
+# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 2, class: gr32 }
- { id: 0, class: gr32 }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir
index 3b8455684f33d2..881ceac1d1f7f2 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir
@@ -26,9 +26,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -56,9 +56,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -86,9 +86,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir
index 4965b069715a11..c2800bef9713de 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir
@@ -26,9 +26,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -56,9 +56,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -86,9 +86,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir
index 77a94581b66fde..e45818af22a356 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir
@@ -28,9 +28,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -58,9 +58,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -88,9 +88,9 @@ alignment: 16
legalized: false
regBankSelected: false
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir
index 1d280e9e4bd11f..28c4eaea388414 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir
@@ -33,8 +33,8 @@ selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_mul_vec256
# CHECK: registers:
-# CHECK: - { id: 0, class: vecr, preferred-register: '' }
-# CHECK: - { id: 1, class: vecr, preferred-register: '' }
+# CHECK: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -56,8 +56,8 @@ selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_add_vec256
# CHECK: registers:
-# CHECK: - { id: 0, class: vecr, preferred-register: '' }
-# CHECK: - { id: 1, class: vecr, preferred-register: '' }
+# CHECK: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -79,8 +79,8 @@ selected: false
tracksRegLiveness: true
# CHECK-LABEL: name: test_sub_vec256
# CHECK: registers:
-# CHECK: - { id: 0, class: vecr, preferred-register: '' }
-# CHECK: - { id: 1, class: vecr, preferred-register: '' }
+# CHECK: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
+# CHECK: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -100,8 +100,8 @@ alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -122,8 +122,8 @@ alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir
index 2f8827c7ff9066..4a19a040b0ce8d 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir
@@ -33,8 +33,8 @@ alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -53,8 +53,8 @@ alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -73,8 +73,8 @@ alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -93,8 +93,8 @@ alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
+# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -115,8 +115,8 @@ alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir
index c69345ccf5a2ad..8eac3eaf361459 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir
@@ -14,11 +14,11 @@ alignment: 16
legalized: true
regBankSelected: false
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' }
-# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' }
+# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '', flags: [ ] }
+# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir b/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir
index 4ba8606df5dfc6..43c4105c883e1f 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir
@@ -25,12 +25,12 @@ alignment: 16
legalized: true
regBankSelected: true
# X32: registers:
-# X32-NEXT: - { id: 0, class: gr32, preferred-register: '' }
-# X32-NEXT: - { id: 1, class: gr32, preferred-register: '' }
+# X32-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
+# X32-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
#
# X32ABI: registers:
-# X32ABI-NEXT: - { id: 0, class: low32_addr_access, preferred-register: '' }
-# X32ABI-NEXT: - { id: 1, class: gr32, preferred-register: '' }
+# X32ABI-NEXT: - { id: 0, class: low32_addr_access, preferred-register: '', flags: [ ] }
+# X32ABI-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
@@ -60,8 +60,8 @@ alignment: 16
legalized: true
regBankSelected: true
# X32ALL: registers:
-# X32ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
-# X32ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
+# X32ALL-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
+# X32ALL-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir b/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir
index 4a1f63c9879552..d292bbfcaa98be 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir
@@ -25,8 +25,8 @@ alignment: 16
legalized: true
regBankSelected: true
# X64ALL: registers:
-# X64ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
-# X64ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
+# X64ALL-NEXT: - { id: 0, class: gr64, preferred-register: '', flags: [ ] }
+# X64ALL-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
#
registers:
- { id: 0, class: gpr, preferred-register: '' }
@@ -58,8 +58,8 @@ alignment: 16
legalized: true
regBankSelected: true
# X64ALL: registers:
-# X64ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
-# X64ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
+# X64ALL-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
+# X64ALL-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
#
registers:
- { id: 0, class: gpr, preferred-register: '' }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir
index 987f67bad15b32..32898be2e6f5e0 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir
@@ -32,19 +32,19 @@ alignment: 16
legalized: true
regBankSelected: true
# NOVL: registers:
-# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
+# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] }
+# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }
+# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
+# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] }
+# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }
+# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] }
#
# AVX512BWVL: registers:
-# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] }
+# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
+# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@@ -74,19 +74,19 @@ alignment: 16
legalized: true
regBankSelected: true
# NOVL: registers:
-# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
+# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] }
+# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }
+# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
+# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] }
+# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }
+# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] }
#
# AVX512BWVL: registers:
-# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] }
+# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
+# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@@ -116,19 +116,19 @@ alignment: 16
legalized: true
regBankSelected: true
# NOVL: registers:
-# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
+# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] }
+# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }
+# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] }
+# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
+# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] }
#
# AVX512BWVL: registers:
-# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] }
+# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
+# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@@ -158,19 +158,19 @@ alignment: 16
legalized: true
regBankSelected: true
# NOVL: registers:
-# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' }
+# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '', flags: [ ] }
+# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }
+# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] }
+# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
+# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] }
#
# AVX512BWVL: registers:
-# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '', flags: [ ] }
+# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
+# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir
index 3ee959294413dd..742cc4378e3ebd 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir
@@ -30,19 +30,19 @@ alignment: 16
legalized: true
regBankSelected: true
# AVX2: registers:
-# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
+# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
+# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }
+# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' }
+# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
+# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }
+# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] }
#
# AVX512BWVL: registers:
-# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
+# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
+# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@@ -70,19 +70,19 @@ alignment: 16
legalized: true
regBankSelected: true
# AVX2: registers:
-# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
+# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
+# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }
+# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' }
+# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
+# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }
+# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] }
#
# AVX512BWVL: registers:
-# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
+# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
+# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@@ -110,19 +110,19 @@ alignment: 16
legalized: true
regBankSelected: true
# AVX2: registers:
-# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
+# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
+# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }
+# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
+# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
+# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
+# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] }
#
# AVX512BWVL: registers:
-# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
+# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
+# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@@ -150,19 +150,19 @@ alignment: 16
legalized: true
regBankSelected: true
# AVX2: registers:
-# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
+# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
+# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }
+# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
+# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
+# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
+# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] }
#
# AVX512BWVL: registers:
-# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
+# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
+# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir b/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir
index 72a6ed15f63b5b..41e1b5bf22bf1d 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir
@@ -35,8 +35,8 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
@@ -61,8 +61,8 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
@@ -87,10 +87,10 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr16[[ABCD:(_abcd)?]], preferred-register: '' }
-# X32-NEXT: - { id: 1, class: gr8_abcd_l, preferred-register: '' }
-# X64-NEXT: - { id: 1, class: gr8, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: gr16[[ABCD:(_abcd)?]], preferred-register: '', flags: [ ] }
+# X32-NEXT: - { id: 1, class: gr8_abcd_l, preferred-register: '', flags: [ ] }
+# X64-NEXT: - { id: 1, class: gr8, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
@@ -120,9 +120,9 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
@@ -150,10 +150,10 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr32[[ABCD:(_abcd)?]], preferred-register: '' }
-# X32-NEXT: - { id: 1, class: gr8_abcd_l, preferred-register: '' }
-# X64-NEXT: - { id: 1, class: gr8, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: gr32[[ABCD:(_abcd)?]], preferred-register: '', flags: [ ] }
+# X32-NEXT: - { id: 1, class: gr8_abcd_l, preferred-register: '', flags: [ ] }
+# X64-NEXT: - { id: 1, class: gr8, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
@@ -183,10 +183,10 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: low32_addr_access_rbp, preferred-register: '' }
-# ALL-NEXT: - { id: 3, class: low32_addr_access_rbp, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: gr16, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: low32_addr_access_rbp, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 3, class: low32_addr_access_rbp, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr, preferred-register: '' }
- { id: 1, class: gpr, preferred-register: '' }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir
index 73af03b34ec77c..301d63b7f3643f 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir
@@ -18,12 +18,12 @@ alignment: 16
legalized: true
regBankSelected: true
# AVX: registers:
-# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' }
+# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
+# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
+# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@@ -50,12 +50,12 @@ alignment: 16
legalized: true
regBankSelected: true
# AVX: registers:
-# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' }
+# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
+# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '', flags: [ ] }
#
# AVX512VL: registers:
-# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
+# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir
index 5ddf58e6455576..cff8560a4ba45f 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir
@@ -27,8 +27,8 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@@ -53,8 +53,8 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@@ -79,8 +79,8 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
@@ -105,8 +105,8 @@ alignment: 16
legalized: true
regBankSelected: true
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
-# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-inc.mir b/llvm/test/CodeGen/X86/GlobalISel/select-inc.mir
index 45e2b47176b975..b834155d49f64c 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-inc.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-inc.mir
@@ -13,10 +13,10 @@ name: test_add_i8
legalized: true
regBankSelected: true
# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
-# INC-NEXT: - { id: 1, class: gpr, preferred-register: '' }
-# ADD-NEXT: - { id: 1, class: gpr, preferred-register: '' }
-# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '' }
+# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '', flags: [ ] }
+# INC-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
+# ADD-NEXT: - { id: 1, class: gpr, preferred-register: '', flags: [ ] }
+# ALL-NEXT: - { id: 2, class: gr8, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir
index f24a82899c62e8..86a83c417d63ee 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir
@@ -33,12 +33,12 @@ alignment: 16
legalized: true
regBankSelected: true
# NO_AVX512F: registers:
-# NO_AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 1, class: vr256, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 0, class: gr64, preferred-register: '', flags: [ ] }
+# NO_AVX512F-NEXT: - { id: 1, class: vr256, preferred-register: '', flags: [ ] }
#
# AVX512ALL: registers:
-# AVX512ALL-NEXT: - { id: 0, class: gr64, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 0, class: gr64, preferred-register: '', flags: [ ] }
+# AVX512ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: gpr }
- { id: 1, class: vecr }
@@ -106,12 +106,12 @@ alignment: 16
legalized: true
regBankSelected: true
# NO_AVX512F: registers:
-# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
+# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
#
# AVX512ALL: registers:
-# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
+# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: gpr }
@@ -146,12 +146,12 @@ alignment: 16
legalized: true
regBankSelected: true
# NO_AVX512F: registers:
-# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '' }
-# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '' }
+# NO_AVX512F-NEXT: - { id: 0, class: vr256, preferred-register: '', flags: [ ] }
+# NO_AVX512F-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
#
# AVX512ALL: registers:
-# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '' }
+# AVX512ALL-NEXT: - { id: 0, class: vr256x, preferred-register: '', flags: [ ] }
+# AVX512ALL-NEXT: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: vecr }
- { id: 1, class: gpr }
diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir
index 61f9eb9a728740..50f6fbd59cd999 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir
@@ -15,7 +15,7 @@ alignment: 16
legalized: false
regBankSelected: false
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' }
+# CHECK-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _, preferred-register: '' }
# CHECK: %0:_(p0) = G_GLOBAL_VALUE @g_int
diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir
index a2cf55dc2ba543..e7c5d9b3679419 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir
@@ -15,7 +15,7 @@ alignment: 16
legalized: false
regBankSelected: false
# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' }
+# CHECK-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
registers:
- { id: 0, class: _, preferred-register: '' }
# CHECK: %0:_(p0) = G_GLOBAL_VALUE @g_int
diff --git a/llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir b/llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir
index ae55990c1ad87a..8ba07c31dcce11 100644
--- a/llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir
+++ b/llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir
@@ -7,11 +7,11 @@
# Make sure that register hints are preserved in the cloned function.
# RESULT: registers:
-# RESULT-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
-# RESULT-NEXT: - { id: 1, class: vgpr_32, preferred-register: '' }
-# RESULT-NEXT: - { id: 2, class: vgpr_32, preferred-register: '%1' }
-# RESULT-NEXT: - { id: 3, class: vgpr_32, preferred-register: '%4' }
-# RESULT-NEXT: - { id: 4, class: vgpr_32, preferred-register: '%3' }
+# RESULT-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr0', flags: [ ] }
+# RESULT-NEXT: - { id: 1, class: vgpr_32, preferred-register: '', flags: [ ] }
+# RESULT-NEXT: - { id: 2, class: vgpr_32, preferred-register: '%1', flags: [ ] }
+# RESULT-NEXT: - { id: 3, class: vgpr_32, preferred-register: '%4', flags: [ ] }
+# RESULT-NEXT: - { id: 4, class: vgpr_32, preferred-register: '%3', flags: [ ] }
---
name: register_hints
tracksRegLiveness: true
>From 268209d3b99c78c23a700171034db63c14e5d15e Mon Sep 17 00:00:00 2001
From: Akshat Oke <76596238+optimisan at users.noreply.github.com>
Date: Mon, 14 Oct 2024 14:29:09 +0530
Subject: [PATCH 06/10] [MIR] Add missing noteNewVirtualRegister callbacks
(#111634)
The delegates' callback isn't invoked on parsing new virtual registers.
There are two places in the serialization where new virtual registers can be discovered: in register infos and in instructions.
---
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 1 +
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 1 +
2 files changed, 2 insertions(+)
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 5e7c93f329302e..45847b5830da65 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1786,6 +1786,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
MRI.setRegClassOrRegBank(Reg, static_cast<RegisterBank *>(nullptr));
MRI.setType(Reg, Ty);
+ MRI.noteNewVirtualRegister(Reg);
}
}
} else if (consumeIfPresent(MIToken::lparen)) {
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 0c8a3eb6c2d83d..10d3cdcf0c1ce1 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -705,6 +705,7 @@ bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
+ RegInfo.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
>From caa1eefdaff400ff9fb143d4354074cf82d2f4f3 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Mon, 14 Oct 2024 09:59:26 +0100
Subject: [PATCH 07/10] [GlobalISel] Add an assert for the DemandedElts APInt
size. (#112150)
Similar to the other implementations in DAG/ValueTracking, this adds an
assert that the size of the DemandedElts is what we expect it to be -
the size of a fixed length vector or APInt(1,1) otherwise. The
G_BUILDVECTOR is fixed as it was passing an original DemandedElts for
the scalar operands.
---
llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
index 35ee85b474d043..52f5d408c8eddd 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
@@ -148,6 +148,17 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
unsigned Opcode = MI.getOpcode();
LLT DstTy = MRI.getType(R);
+#ifndef NDEBUG
+ if (DstTy.isFixedVector()) {
+ assert(
+ DstTy.getNumElements() == DemandedElts.getBitWidth() &&
+ "DemandedElt width should equal the fixed vector number of elements");
+ } else {
+ assert(DemandedElts.getBitWidth() == 1 && DemandedElts == APInt(1, 1) &&
+ "DemandedElt width should be 1 for scalars or scalable vectors");
+ }
+#endif
+
// Handle the case where this is called on a register that does not have a
// type constraint (i.e. it has a register class constraint instead). This is
// unlikely to occur except by looking through copies but it is possible for
@@ -196,7 +207,7 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
if (!DemandedElts[i])
continue;
- computeKnownBitsImpl(MI.getOperand(i + 1).getReg(), Known2, DemandedElts,
+ computeKnownBitsImpl(MI.getOperand(i + 1).getReg(), Known2, APInt(1, 1),
Depth + 1);
// Known bits are the values that are shared by every demanded element.
>From b5b2d125b899ec3fe9e26c5fba9c8238e9fb909f Mon Sep 17 00:00:00 2001
From: Christian Kandeler <christian.kandeler at qt.io>
Date: Mon, 14 Oct 2024 11:00:02 +0200
Subject: [PATCH 08/10] [clangd] Let DefineOutline tweak handle member
functions (#95235)
... of class templates.
---
clang-tools-extra/clangd/AST.cpp | 7 ++-
.../clangd/refactor/tweaks/DefineOutline.cpp | 50 +++++++++++++++--
.../unittests/tweaks/DefineOutlineTests.cpp | 55 ++++++++++++++-----
clang-tools-extra/docs/ReleaseNotes.rst | 2 +
4 files changed, 94 insertions(+), 20 deletions(-)
diff --git a/clang-tools-extra/clangd/AST.cpp b/clang-tools-extra/clangd/AST.cpp
index 333fc10f17d7b4..f3eee1c6335f98 100644
--- a/clang-tools-extra/clangd/AST.cpp
+++ b/clang-tools-extra/clangd/AST.cpp
@@ -144,8 +144,13 @@ getQualification(ASTContext &Context, const DeclContext *DestContext,
// since we stored inner-most parent first.
std::string Result;
llvm::raw_string_ostream OS(Result);
- for (const auto *Parent : llvm::reverse(Parents))
+ for (const auto *Parent : llvm::reverse(Parents)) {
+ if (Parent != *Parents.rbegin() && Parent->isDependent() &&
+ Parent->getAsRecordDecl() &&
+ Parent->getAsRecordDecl()->getDescribedClassTemplate())
+ OS << "template ";
Parent->print(OS, Context.getPrintingPolicy());
+ }
return OS.str();
}
diff --git a/clang-tools-extra/clangd/refactor/tweaks/DefineOutline.cpp b/clang-tools-extra/clangd/refactor/tweaks/DefineOutline.cpp
index f43f2417df8fce..591a8b245260ea 100644
--- a/clang-tools-extra/clangd/refactor/tweaks/DefineOutline.cpp
+++ b/clang-tools-extra/clangd/refactor/tweaks/DefineOutline.cpp
@@ -128,7 +128,28 @@ getFunctionSourceAfterReplacements(const FunctionDecl *FD,
SM.getBufferData(SM.getMainFileID()), Replacements);
if (!QualifiedFunc)
return QualifiedFunc.takeError();
- return QualifiedFunc->substr(FuncBegin, FuncEnd - FuncBegin + 1);
+
+ std::string TemplatePrefix;
+ if (auto *MD = llvm::dyn_cast<CXXMethodDecl>(FD)) {
+ for (const CXXRecordDecl *Parent = MD->getParent(); Parent;
+ Parent =
+ llvm::dyn_cast_or_null<const CXXRecordDecl>(Parent->getParent())) {
+ if (const TemplateParameterList *Params =
+ Parent->getDescribedTemplateParams()) {
+ std::string S;
+ llvm::raw_string_ostream Stream(S);
+ Params->print(Stream, FD->getASTContext());
+ if (!S.empty())
+ *S.rbegin() = '\n'; // Replace space with newline
+ TemplatePrefix.insert(0, S);
+ }
+ }
+ }
+
+ auto Source = QualifiedFunc->substr(FuncBegin, FuncEnd - FuncBegin + 1);
+ if (!TemplatePrefix.empty())
+ Source.insert(0, TemplatePrefix);
+ return Source;
}
// Returns replacements to delete tokens with kind `Kind` in the range
@@ -212,9 +233,13 @@ getFunctionSourceCode(const FunctionDecl *FD, const DeclContext *TargetContext,
}
}
const NamedDecl *ND = Ref.Targets.front();
- const std::string Qualifier =
+ std::string Qualifier =
getQualification(AST, TargetContext,
SM.getLocForStartOfFile(SM.getMainFileID()), ND);
+ if (ND->getDeclContext()->isDependentContext() &&
+ llvm::isa<TypeDecl>(ND)) {
+ Qualifier.insert(0, "typename ");
+ }
if (auto Err = DeclarationCleanups.add(
tooling::Replacement(SM, Ref.NameLoc, 0, Qualifier)))
Errors = llvm::joinErrors(std::move(Errors), std::move(Err));
@@ -407,10 +432,23 @@ class DefineOutline : public Tweak {
return !SameFile;
}
- // Bail out in templated classes, as it is hard to spell the class name,
- // i.e if the template parameter is unnamed.
- if (MD->getParent()->isTemplated())
- return false;
+ for (const CXXRecordDecl *Parent = MD->getParent(); Parent;
+ Parent =
+ llvm::dyn_cast_or_null<const CXXRecordDecl>(Parent->getParent())) {
+ if (const TemplateParameterList *Params =
+ Parent->getDescribedTemplateParams()) {
+
+ // Class template member functions must be defined in the
+ // same file.
+ SameFile = true;
+
+ // Bail out if the template parameter is unnamed.
+ for (NamedDecl *P : *Params) {
+ if (!P->getIdentifier())
+ return false;
+ }
+ }
+ }
// The refactoring is meaningless for unnamed classes and namespaces,
// unless we're outlining in the same file
diff --git a/clang-tools-extra/clangd/unittests/tweaks/DefineOutlineTests.cpp b/clang-tools-extra/clangd/unittests/tweaks/DefineOutlineTests.cpp
index 906ff33db87344..6a9e90c3bfa70f 100644
--- a/clang-tools-extra/clangd/unittests/tweaks/DefineOutlineTests.cpp
+++ b/clang-tools-extra/clangd/unittests/tweaks/DefineOutlineTests.cpp
@@ -105,8 +105,8 @@ TEST_F(DefineOutlineTest, TriggersOnFunctionDecl) {
F^oo(const Foo&) = delete;
};)cpp");
- // Not available within templated classes, as it is hard to spell class name
- // out-of-line in such cases.
+ // Not available within templated classes with unnamed parameters, as it is
+ // hard to spell class name out-of-line in such cases.
EXPECT_UNAVAILABLE(R"cpp(
template <typename> struct Foo { void fo^o(){} };
)cpp");
@@ -154,7 +154,6 @@ TEST_F(DefineOutlineTest, FailsWithoutSource) {
}
TEST_F(DefineOutlineTest, ApplyTest) {
- llvm::StringMap<std::string> EditedFiles;
ExtraFiles["Test.cpp"] = "";
FileName = "Test.hpp";
@@ -229,17 +228,18 @@ TEST_F(DefineOutlineTest, ApplyTest) {
// Ctor initializer with attribute.
{
R"cpp(
- class Foo {
- F^oo(int z) __attribute__((weak)) : bar(2){}
+ template <typename T> class Foo {
+ F^oo(T z) __attribute__((weak)) : bar(2){}
int bar;
};)cpp",
R"cpp(
- class Foo {
- Foo(int z) __attribute__((weak)) ;
+ template <typename T> class Foo {
+ Foo(T z) __attribute__((weak)) ;
int bar;
- };)cpp",
- "Foo::Foo(int z) __attribute__((weak)) : bar(2){}\n",
- },
+ };template <typename T>
+Foo<T>::Foo(T z) __attribute__((weak)) : bar(2){}
+)cpp",
+ ""},
// Virt specifiers.
{
R"cpp(
@@ -369,7 +369,31 @@ TEST_F(DefineOutlineTest, ApplyTest) {
};)cpp",
" void A::foo(int) {}\n",
},
- // Destrctors
+ // Complex class template
+ {
+ R"cpp(
+ template <typename T, typename ...U> struct O1 {
+ template <class V, int A> struct O2 {
+ enum E { E1, E2 };
+ struct I {
+ E f^oo(T, U..., V, E) { return E1; }
+ };
+ };
+ };)cpp",
+ R"cpp(
+ template <typename T, typename ...U> struct O1 {
+ template <class V, int A> struct O2 {
+ enum E { E1, E2 };
+ struct I {
+ E foo(T, U..., V, E) ;
+ };
+ };
+ };template <typename T, typename ...U>
+template <class V, int A>
+typename O1<T, U...>::template O2<V, A>::E O1<T, U...>::template O2<V, A>::I::foo(T, U..., V, E) { return E1; }
+)cpp",
+ ""},
+ // Destructors
{
"class A { ~A^(){} };",
"class A { ~A(); };",
@@ -378,9 +402,14 @@ TEST_F(DefineOutlineTest, ApplyTest) {
};
for (const auto &Case : Cases) {
SCOPED_TRACE(Case.Test);
+ llvm::StringMap<std::string> EditedFiles;
EXPECT_EQ(apply(Case.Test, &EditedFiles), Case.ExpectedHeader);
- EXPECT_THAT(EditedFiles, testing::ElementsAre(FileWithContents(
- testPath("Test.cpp"), Case.ExpectedSource)));
+ if (Case.ExpectedSource.empty()) {
+ EXPECT_TRUE(EditedFiles.empty());
+ } else {
+ EXPECT_THAT(EditedFiles, testing::ElementsAre(FileWithContents(
+ testPath("Test.cpp"), Case.ExpectedSource)));
+ }
}
}
diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst
index 8655331dfc00e4..39b600f361e8c5 100644
--- a/clang-tools-extra/docs/ReleaseNotes.rst
+++ b/clang-tools-extra/docs/ReleaseNotes.rst
@@ -88,6 +88,8 @@ Objective-C
Miscellaneous
^^^^^^^^^^^^^
+- The DefineOutline tweak now handles member functions of class templates.
+
Improvements to clang-doc
-------------------------
>From 255787389a20d6c732a1a186c4e26d65640adc15 Mon Sep 17 00:00:00 2001
From: Jack Styles <jack.styles at arm.com>
Date: Mon, 14 Oct 2024 10:07:40 +0100
Subject: [PATCH 09/10] fixup! Add support for FEAT_PAuth_LR to libunwind
Formatting fixes
---
libunwind/src/DwarfInstructions.hpp | 15 +++++---
libunwind/src/DwarfParser.hpp | 23 ++++++------
libunwind/src/dwarf2.h | 57 ++++++++++++++---------------
3 files changed, 50 insertions(+), 45 deletions(-)
diff --git a/libunwind/src/DwarfInstructions.hpp b/libunwind/src/DwarfInstructions.hpp
index e7c467de80adb6..e7be0d6d5d6354 100644
--- a/libunwind/src/DwarfInstructions.hpp
+++ b/libunwind/src/DwarfInstructions.hpp
@@ -318,14 +318,19 @@ int DwarfInstructions<A, R>::stepWithDwarf(A &addressSpace, pint_t pc,
// We use the hint versions of the authentication instructions below to
// ensure they're assembled by the compiler even for targets with no
// FEAT_PAuth/FEAT_PAuth_LR support.
- if(isReturnAddressSignedWithPC(addressSpace, registers, cfa, prolog)) {
- register unsigned long long x15 __asm("x15") = prolog.ptrAuthDiversifier;
- if(cieInfo.addressesSignedWithBKey) {
+ if (isReturnAddressSignedWithPC(addressSpace, registers, cfa, prolog)) {
+ register unsigned long long x15 __asm("x15") =
+ prolog.ptrAuthDiversifier;
+ if (cieInfo.addressesSignedWithBKey) {
asm("hint 0x27\n\t" // pacm
- "hint 0xe" : "+r"(x17) : "r"(x16), "r"(x15)); // autib1716
+ "hint 0xe"
+ : "+r"(x17)
+ : "r"(x16), "r"(x15)); // autib1716
} else {
asm("hint 0x27\n\t" // pacm
- "hint 0xc" : "+r"(x17) : "r"(x16), "r"(x15)); // autia1716
+ "hint 0xc"
+ : "+r"(x17)
+ : "r"(x16), "r"(x15)); // autia1716
}
} else {
if (cieInfo.addressesSignedWithBKey)
diff --git a/libunwind/src/DwarfParser.hpp b/libunwind/src/DwarfParser.hpp
index b104d773ed4440..3b099af2eaed36 100644
--- a/libunwind/src/DwarfParser.hpp
+++ b/libunwind/src/DwarfParser.hpp
@@ -91,9 +91,9 @@ class CFI_Parser {
int64_t cfaExpression; // CFA = expression
uint32_t spExtraArgSize;
RegisterLocation savedRegisters[kMaxRegisterNumber + 1];
- #if defined(_LIBUNWIND_TARGET_AARCH64)
- pint_t ptrAuthDiversifier;
- #endif
+#if defined(_LIBUNWIND_TARGET_AARCH64)
+ pint_t ptrAuthDiversifier;
+#endif
enum class InitializeTime { kLazy, kNormal };
// When saving registers, this data structure is lazily initialized.
@@ -808,15 +808,16 @@ bool CFI_Parser<A>::parseFDEInstructions(A &addressSpace,
results->savedRegisters[UNW_AARCH64_RA_SIGN_STATE].value ^ 0x3;
results->setRegisterValue(UNW_AARCH64_RA_SIGN_STATE, value,
initialState);
- // When calucating the value of the PC, it is assumed that the CFI instruction
- // is placed before the signing instruction, however it is placed after. Because
- // of this, we need to take into account the CFI instruction is one instruction
- // call later than expected, and reduce the PC value by 4 bytes to compensate.
+ // When calucating the value of the PC, it is assumed that the CFI
+ // instruction is placed before the signing instruction, however it is
+ // placed after. Because of this, we need to take into account the CFI
+ // instruction is one instruction call later than expected, and reduce
+ // the PC value by 4 bytes to compensate.
results->ptrAuthDiversifier = fdeInfo.pcStart + codeOffset - 0x4;
- _LIBUNWIND_TRACE_DWARF("DW_CFA_AARCH64_negate_ra_state_with_pc(pc=0x%" PRIx64 ")\n",
- static_cast<uint64_t>(results->ptrAuthDiversifier));
- }
- break;
+ _LIBUNWIND_TRACE_DWARF(
+ "DW_CFA_AARCH64_negate_ra_state_with_pc(pc=0x%" PRIx64 ")\n",
+ static_cast<uint64_t>(results->ptrAuthDiversifier));
+ } break;
#endif
#else
diff --git a/libunwind/src/dwarf2.h b/libunwind/src/dwarf2.h
index 2ad3d3c464e80d..68ad882347203c 100644
--- a/libunwind/src/dwarf2.h
+++ b/libunwind/src/dwarf2.h
@@ -18,44 +18,43 @@
// DWARF unwind instructions
enum {
- DW_CFA_nop = 0x0,
- DW_CFA_set_loc = 0x1,
- DW_CFA_advance_loc1 = 0x2,
- DW_CFA_advance_loc2 = 0x3,
- DW_CFA_advance_loc4 = 0x4,
- DW_CFA_offset_extended = 0x5,
- DW_CFA_restore_extended = 0x6,
- DW_CFA_undefined = 0x7,
- DW_CFA_same_value = 0x8,
- DW_CFA_register = 0x9,
- DW_CFA_remember_state = 0xA,
- DW_CFA_restore_state = 0xB,
- DW_CFA_def_cfa = 0xC,
- DW_CFA_def_cfa_register = 0xD,
- DW_CFA_def_cfa_offset = 0xE,
- DW_CFA_def_cfa_expression = 0xF,
- DW_CFA_expression = 0x10,
+ DW_CFA_nop = 0x0,
+ DW_CFA_set_loc = 0x1,
+ DW_CFA_advance_loc1 = 0x2,
+ DW_CFA_advance_loc2 = 0x3,
+ DW_CFA_advance_loc4 = 0x4,
+ DW_CFA_offset_extended = 0x5,
+ DW_CFA_restore_extended = 0x6,
+ DW_CFA_undefined = 0x7,
+ DW_CFA_same_value = 0x8,
+ DW_CFA_register = 0x9,
+ DW_CFA_remember_state = 0xA,
+ DW_CFA_restore_state = 0xB,
+ DW_CFA_def_cfa = 0xC,
+ DW_CFA_def_cfa_register = 0xD,
+ DW_CFA_def_cfa_offset = 0xE,
+ DW_CFA_def_cfa_expression = 0xF,
+ DW_CFA_expression = 0x10,
DW_CFA_offset_extended_sf = 0x11,
- DW_CFA_def_cfa_sf = 0x12,
- DW_CFA_def_cfa_offset_sf = 0x13,
- DW_CFA_val_offset = 0x14,
- DW_CFA_val_offset_sf = 0x15,
- DW_CFA_val_expression = 0x16,
- DW_CFA_advance_loc = 0x40, // high 2 bits are 0x1, lower 6 bits are delta
- DW_CFA_offset = 0x80, // high 2 bits are 0x2, lower 6 bits are register
- DW_CFA_restore = 0xC0, // high 2 bits are 0x3, lower 6 bits are register
+ DW_CFA_def_cfa_sf = 0x12,
+ DW_CFA_def_cfa_offset_sf = 0x13,
+ DW_CFA_val_offset = 0x14,
+ DW_CFA_val_offset_sf = 0x15,
+ DW_CFA_val_expression = 0x16,
+ DW_CFA_advance_loc = 0x40, // high 2 bits are 0x1, lower 6 bits are delta
+ DW_CFA_offset = 0x80, // high 2 bits are 0x2, lower 6 bits are register
+ DW_CFA_restore = 0xC0, // high 2 bits are 0x3, lower 6 bits are register
// GNU extensions
- DW_CFA_GNU_window_save = 0x2D,
- DW_CFA_GNU_args_size = 0x2E,
+ DW_CFA_GNU_window_save = 0x2D,
+ DW_CFA_GNU_args_size = 0x2E,
DW_CFA_GNU_negative_offset_extended = 0x2F,
// AARCH64 extensions
DW_CFA_AARCH64_negate_ra_state_with_pc = 0x2C,
- DW_CFA_AARCH64_negate_ra_state = 0x2D
+ DW_CFA_AARCH64_negate_ra_state = 0x2D
};
-
// FSF exception handling Pointer-Encoding constants
// Used in CFI augmentation by GCC
enum {
>From 020a6be7f0c0c3e1d17b28d55ef2d7e872d85a8f Mon Sep 17 00:00:00 2001
From: Jack Styles <jack.styles at arm.com>
Date: Mon, 14 Oct 2024 10:08:36 +0100
Subject: [PATCH 10/10] fixup! [PAuthLR] Add support for FEAT_PAuth_LR's DWARF
frame instruction
Formatting Fixes
---
llvm/include/llvm/MC/MCDwarf.h | 1 -
llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp | 34 +++++++++----------
.../lib/Target/AArch64/AArch64PointerAuth.cpp | 6 ++--
3 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/llvm/include/llvm/MC/MCDwarf.h b/llvm/include/llvm/MC/MCDwarf.h
index 2ceea906ea57a7..1392336968e74a 100644
--- a/llvm/include/llvm/MC/MCDwarf.h
+++ b/llvm/include/llvm/MC/MCDwarf.h
@@ -649,7 +649,6 @@ class MCCFIInstruction {
return MCCFIInstruction(OpNegateRAStateWithPC, L, 0, INT64_C(0), Loc);
}
-
/// .cfi_restore says that the rule for Register is now the same as it
/// was at the beginning of the function, after all initial instructions added
/// by .cfi_startproc were executed.
diff --git a/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp b/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp
index 38e264f233e39b..96cb86ad4c3711 100644
--- a/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp
+++ b/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp
@@ -668,26 +668,26 @@ Error UnwindTable::parseRows(const CFIProgram &CFIP, UnwindRow &Row,
break;
case dwarf::DW_CFA_AARCH64_negate_ra_state_with_pc: {
- constexpr uint32_t AArch64DWARFPAuthRaState = 34;
- auto LRLoc = Row.getRegisterLocations().getRegisterLocation(
- AArch64DWARFPAuthRaState);
- if (LRLoc) {
- if (LRLoc->getLocation() == UnwindLocation::Constant) {
- // Toggle the constant value of bits[1:0] from 0 to 1 or 1 to 0.
- LRLoc->setConstant(LRLoc->getConstant() ^ 0x3);
- } else {
- return createStringError(
- errc::invalid_argument,
- "%s encountered when existing rule for this register is not "
- "a constant",
- CFIP.callFrameString(Inst.Opcode).str().c_str());
- }
+ constexpr uint32_t AArch64DWARFPAuthRaState = 34;
+ auto LRLoc = Row.getRegisterLocations().getRegisterLocation(
+ AArch64DWARFPAuthRaState);
+ if (LRLoc) {
+ if (LRLoc->getLocation() == UnwindLocation::Constant) {
+ // Toggle the constant value of bits[1:0] from 0 to 1 or 1 to 0.
+ LRLoc->setConstant(LRLoc->getConstant() ^ 0x3);
} else {
- Row.getRegisterLocations().setRegisterLocation(
- AArch64DWARFPAuthRaState, UnwindLocation::createIsConstant(0x3));
+ return createStringError(
+ errc::invalid_argument,
+ "%s encountered when existing rule for this register is not "
+ "a constant",
+ CFIP.callFrameString(Inst.Opcode).str().c_str());
}
- break;
+ } else {
+ Row.getRegisterLocations().setRegisterLocation(
+ AArch64DWARFPAuthRaState, UnwindLocation::createIsConstant(0x3));
}
+ break;
+ }
case dwarf::DW_CFA_undefined: {
llvm::Expected<uint64_t> RegNum = Inst.getOperandAsUnsigned(CFIP, 0);
diff --git a/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp b/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
index c3ad488fb8e4d1..2e5688cf60027a 100644
--- a/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
+++ b/llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
@@ -224,13 +224,15 @@ void AArch64PointerAuth::authenticateLR(
TII->get(UseBKey ? AArch64::AUTIBSPPCi : AArch64::AUTIASPPCi))
.addSym(PACSym)
.setMIFlag(MachineInstr::FrameDestroy);
- emitPACCFI(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameDestroy, EmitAsyncCFI);
+ emitPACCFI(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameDestroy,
+ EmitAsyncCFI);
} else {
BuildPACM(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameDestroy, PACSym);
BuildMI(MBB, MBBI, DL,
TII->get(UseBKey ? AArch64::AUTIBSP : AArch64::AUTIASP))
.setMIFlag(MachineInstr::FrameDestroy);
- emitPACCFI(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameDestroy, EmitAsyncCFI);
+ emitPACCFI(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameDestroy,
+ EmitAsyncCFI);
}
if (NeedsWinCFI) {
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